Non-volatile memory device and operating method

Abstract

An operating method of a nonvolatile memory device includes performing a read operation on adjacent memory cells connected to adjacent word lines adjacent to a target word line to determine adjacent data, classifying target memory cells connected to the target word line into groups according to the adjacent data, setting a read voltage level for each of the groups by searching for a read voltage level of a target memory cell in at least one of the groups, and performing a read operation on a target memory cell using the read voltage level set for each of the groups.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0060623, filed with the Korean Intellectual Property Office on May 20, 2020, the subject of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to storage devices, and more specifically, to non-volatile storage devices and methods of operating non-volatile storage devices. Background Technology

[0004] Storage devices are used to store data and can generally be divided into volatile storage devices and non-volatile storage devices. Flash memory devices are a type of non-volatile memory commonly used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computing devices, personal computers, and the like. Summary of the Invention

[0005] Embodiments of the present invention provide storage devices, storage systems, and / or methods of operating the storage devices that exhibit improved reliability and better overall read performance.

[0006] According to one aspect of the present invention, a method of operating a non-volatile memory device is provided, the method comprising: performing a read operation on adjacent memory cells connected to adjacent word lines adjacent to a target word line to determine adjacent data; classifying target memory cells connected to the target word line into groups based on the adjacent data; setting a read voltage level for each of the groups by searching for a read voltage level of a target memory cell in at least one of the groups; and performing a read operation on the target memory cell using the read voltage level set for each of the groups.

[0007] According to one aspect of the present invention, a non-volatile storage device is provided, comprising: a memory cell array including memory cells respectively connected to bit lines and word lines; and control logic configured to: perform a read operation on memory cells connected to a target word line and adjacent word lines adjacent to the target word line. The control logic sets a read voltage level for each of the plurality of groups by classifying target memory cells connected to the target word line into a plurality of groups based on adjacent data read from adjacent memory cells connected to the adjacent word lines; searches for the read voltage level of a target memory cell included in at least one of the plurality of groups; and performs the read operation on the target memory cell using the read voltage level set for the group to which the target memory cell belongs.

[0008] According to one aspect of the present invention, a non-volatile memory system is provided, comprising: a memory cell array including memory cells respectively connected to bit lines and word lines; and control logic configured to: perform a read operation on a target memory cell connected to a target word line among the word lines; perform a read operation on an adjacent memory cell storing adjacent data and connected to an adjacent word line adjacent to the target word line; set a read voltage level for each of the plurality of groups by classifying the target memory cell into groups among the plurality of groups according to the adjacent data; search for a read voltage level of a target memory cell included in at least one of the plurality of groups; and perform the read operation on the target memory cell using the read voltage level set for the corresponding group to which the target memory cell belongs. Attached Figure Description

[0009] Some embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a storage system according to an embodiment of the concept of the present invention;

[0011] Figure 2 This is further illustrated in one example. Figure 1 Block diagram of storage device 100;

[0012] Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The diagrams are graphical representations of various aspects of exemplary threshold voltage distributions of memory cells that may be used in certain embodiments of the inventive concept.

[0013] Figure 8 This is a flowchart outlining a method for operating a non-volatile storage device according to an embodiment of the present invention;

[0014] Figure 9 This is a flowchart outlining a method for setting read voltage levels for each group of memory cells according to an embodiment of the present invention;

[0015] Figure 10 and Figure 11 These are flowcharts illustrating certain read operations that can be performed in embodiments of the inventive concept;

[0016] Figure 12 This is a circuit diagram illustrating relevant portions of a memory cell array including word line groups according to an embodiment of the present invention;

[0017] Figure 13This is a block diagram illustrating a non-volatile memory system according to an embodiment of the concept of the present invention;

[0018] Figure 14 This is a flowchart illustrating a read operation that can be performed by an embodiment of the inventive concept;

[0019] Figure 15 and Figure 16 These are conceptual diagrams illustrating methods for assembling groups of storage units according to embodiments of the present invention; and

[0020] Figure 17 This is a cross-sectional view showing a memory device 400 having a chip-to-chip (C2C) structure. Detailed Implementation

[0021] Figure 1 This is a block diagram of a storage system according to an embodiment of the present invention. Here, the storage system typically includes a storage device 100 and a storage controller 200. The storage device 100 may include a storage cell array 110 and control logic 120.

[0022] The storage controller 200 can control read, program, and erase operations, as well as other operations, performed by the storage device 100. In this regard, the storage controller 200 can provide the storage device 100 with data (DATA), address signals (ADDR), command signals (CMD), and / or control signals (CTRL) differently to read data stored in the storage device 100, program (or write) data to the storage device 100, and erase data stored in the storage device 100. For example, data can be read from the storage device 100 during a read operation controlled by the storage controller 200 and performed in response to a read request received from an external host (not shown). Similarly, data can be written to the storage device 100 in response to a write request received from a host. Figure 1 During read and write operations performed by the storage system, data can be exchanged between the storage controller 200 and the storage device 100 (e.g., read data retrieved from the storage device 100 and / or write data to be written to the storage device 100 during a read operation).

[0023] The memory cell array 110 may include a plurality of memory cells. Hereinafter, it will be assumed that the memory cell array 110 includes an embodiment comprising a plurality of NAND flash memory cells. However, other embodiments of the inventive concept may additionally or optionally include one or more other types of memory cells, such as resistive random access memory (RAM) (RRAM), phase-change RAM (PRAM), and / or magnetoresistive RAM (MRAM).

[0024] Control logic 120 can control the execution of a read operation targeting a memory cell connected to a word line corresponding to the read address. The read operation can use one or more read voltage levels differently during the read period to determine the programming state (i.e., data value or bit value) of the read memory cell. Therefore, the read voltage level can be, for example, a default read voltage level defined during the packaging process of memory device 100. Here, the default read voltage level can be determined based on an initial (or modeled) distribution of the threshold voltages of the memory cell.

[0025] In some embodiments, control logic 120 may read data with respect to (or based on) a default read voltage level, and then perform error correction operations on the obtained read data. For example, control logic 120 may use algorithms such as Reed Solomon (RS) codes, Hamming codes, and Cyclic Redundancy Codes (CRC) to perform error checking and correction (ECC) encoding processes and corresponding ECC decoding processes.

[0026] In some embodiments, the ECC encoding process may include generating parity bits during a programming operation that correspond to write data to memory cells to be programmed into storage device 100. Subsequently, a corresponding ECC decoding process may be used to detect and / or correct (hereinafter referred to as "detect / correct") bit errors (hereinafter referred to as "errors") in read data retrieved from memory cell array 110 during a read operation. In this regard, control logic 120 may detect / correct errors by comparing one or more parity bits generated and stored when write data is programmed into storage device 100 with parity bits generated when read data is retrieved from storage device 100. This comparison operation may involve one or more logical operations (e.g., XOR operations) performed to detect errors.

[0027] exist Figure 1 In the example shown, control logic 120 includes a memory cell grouping unit 121, a read level (RL) setting unit 122, and a read controller 123. These various units can be implemented differently using software, hardware, and / or firmware, and can be flexibly differentiated according to function. For example, each of the aforementioned units can be functionally categorized (or differentiated) but still provided using a single processor package or multiple separate processor packages. Reference will be made below. Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A more detailed description of... Figure 1The storage unit grouping unit 121, RL setting unit 122, and exemplary functions (e.g., operations) of the read controller 123 of the described control logic 120 are described.

[0028] Figure 2 This is further illustrated in one example. Figure 1 Block diagram of storage device 100.

[0029] Reference Figure 2 The storage device 100 may include a memory cell array 110, control logic 120, a voltage generator 130, a row decoder 140, and a page buffer 150. Examples of the memory cell array 110 and control logic 120 have already been provided. Figure 1 The description is within the context of [the previous sentence]. However, the storage device 100 is not limited to [the previous sentence]. Figure 1 and Figure 2 As described herein, other embodiments of the inventive concept may include different or additional components, such as data input / output (I / O) units.

[0030] Reference Figure 2 The memory cell array 110 may include memory cells connected via word lines WL and bit lines BL, respectively. The memory cell array 110 may be connected to the row decoder 140 via word lines WL, serial select line SSL, and ground select line GSL, and may be connected to the page buffer 150 via bit lines BL. Each memory cell may store one or more bits, and each memory cell may be used as a single-level, multi-level, or triple-level cell.

[0031] Control logic 120 can respond to commands CMD, addresses ADDR, and / or control signals CTRL received from storage controller 200, providing various control signals required to write data to storage cell array 110, read data from storage cell 110, or erase data stored in storage cell array 110. In this way, control logic 120 can control the execution of various operations in storage device 100.

[0032] The voltage generator 130, row decoder 140, and / or page buffer 150 can be used to provide various control signals provided by the control logic 120, respectively and selectively. For example, the control logic 120 can provide the voltage control signal CTRL_vol to the voltage generator 130, the row address X-ADDR to the row decoder 140, and the column address Y-ADDR to the page buffer 150. However, the scope of the inventive concept is not limited thereto, and the control logic 120 can also provide other control signals to the voltage generator 130, row decoder 140, and page buffer 150.

[0033] However, in Figure 2 In the example shown, control logic 120 includes a read controller 123. During a read operation, read controller 123 can control voltage generator 130 and row decoder 140 such that a read voltage with a read voltage level corresponding to a default level is applied to the selected word line WL. Additionally, if the read operation fails, read controller 123 can control voltage generator 130 and row decoder 140 to apply an optimal read voltage level to the selected memory cell. In this context, the term "optimal" should be understood as a relative term representing the best possible read voltage level within a defined set of conditions.

[0034] Voltage generator 130 can generate various voltages used during programming, reading, and erasing operations in memory cell array 110 in response to a voltage control signal CTRL_vol provided by control logic 120. Voltage generator 130 can generate word line drive voltages VWL for driving word lines WL, such as programming voltage (or write voltage), read voltage, programming disable voltage, read disable voltage, erase verification voltage, or programming verification voltage. Additionally, voltage generator 130 can also generate a string select line drive voltage for driving the string select line SSL and a ground select line drive voltage for driving the ground select line GSL. Furthermore, voltage generator 130 can also generate an erase voltage to be supplied to memory cell array 110.

[0035] Row decoder 140 can select some word lines WL in response to row address X-ADDR received from control logic 120. During a read operation, row decoder 140 can apply a read voltage to the selected word lines WL and a read inhibit voltage to the unselected word lines WL. Additionally, during a programming operation, row decoder 140 can apply a programming voltage to the selected word lines WL and a read inhibit voltage to the unselected word lines WL. Furthermore, row decoder 140 can select some serial select lines SSL or some ground select lines GSL in response to row address X-ADDR received from control logic 120.

[0036] Page buffer 150 can be connected to memory cell array 110 via bit lines BL and can select some bit lines BL in response to column address Y-ADDR received from control logic 120. During a read operation, page buffer 150 can be used as a sense amplifier and can sense "read data" stored in memory cell array 110. However, during a programming operation, page buffer 150 can be used as a write driver to enable "write data" to be programmed (or stored) in memory cell array 110.

[0037] In some embodiments, the page buffer 150 may include at least one latch with a forced latch, wherein read data retrieved (e.g., sensed) from a “target memory cell” (e.g., a memory cell identified by a read request and / or received address ADDR) may be temporarily stored in the at least one latch. Therefore, the control logic 120 and / or the memory controller 200 may obtain read data differently from the page buffer 150, including “adjacent data” stored in “adjacent memory cells” (e.g., memory cells physically close to the target memory cell) and “target data” stored in the target memory cell. In this context, the read data may be categorized or grouped based on the target data and adjacent data obtained from the target memory cell and adjacent memory cells, respectively.

[0038] Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 (summarized below as " Figures 3 to 7 The figures ("") are conceptual diagrams illustrating various aspects of exemplary threshold voltage distributions of memory cells that can be used in certain embodiments of the inventive concept. Figures 3 to 7 In the example shown, it is assumed that a three-bit (or three-level) memory cell can have one of an erase state (E) or seven (7) possible programming states (e.g., P1, P2, P3, P4, P5, P6, and P7). Figures 3 to 7 In the diagram, the horizontal axis represents the threshold voltage level (Vth), and the vertical axis represents the number of memory cells.

[0039] Reference Figure 1 , Figure 2 and Figure 3 The initial distribution 30 of the threshold voltage of the memory cell MC connected to the word line WL may unexpectedly become the altered distribution 31 due to various factors, including, for example, memory cell leakage due to long data storage latency, memory cell wear, read interference (or read interruption), varying temperature, power and / or process conditions, etc.

[0040] The initial distribution 30 can be the distribution of memory cells immediately following the programming of the memory cells, or the distribution within a specific time period after programming. Here, the control logic 120 can determine the first to seventh default read voltage levels (e.g., RL1 to RL7) of the first to seventh programming states (P1 to P7) based on the valley between two adjacent programming states. For example, the control logic 120 can determine the first default read voltage level RL1 based on the valley detected between the erase state E and the first programming state P1; and so on, until the control logic circuit 120 determines the seventh default read voltage level RL7 based on the valley detected between the sixth programming state P6 and the seventh programming state P7.

[0041] The altered distribution 31 can be the distribution of memory cells after a specific period of time following the programming of the memory cells. As a result, the memory cells programmed into the erase state E and the first to seventh programming states P1 to P7 may have been migrated (or "spread"), resulting in the altered distribution 31.

[0042] For example, the "data retention time" of data stored in a memory cell MC can be the time after the final programming operation of the memory cell (typically measured with respect to a specific temperature). As the data retention time increases, charge loss in the memory cell may increase, and the rate of charge loss may differ between word lines WL. Due to various phenomena such as rearrangement, loss via channel regions, and movement through the charge storage layer, electrons trapped in the charge storage layer during programming operations may be lost over time. Therefore, the threshold voltage Vth of the memory cell may decrease, resulting in a possible decrease and expansion in the distribution of threshold voltage Vth according to the memory cell MC. Furthermore, in this respect, the decrease in threshold voltage Vth may differ between word lines WL.

[0043] The read interrupt mentioned above is a phenomenon where the distribution of adjacent memory cells connected to adjacent word lines WL unexpectedly changes based on the result of a read operation targeting a memory cell connected to a target (or selected) word line WL. For example, when programming state corresponding to a high threshold voltage Vth is written to a memory cell connected to a selected word line WL, the threshold voltage Vth of the memory cells connected to adjacent word lines WL may increase, and the amount of increase in threshold voltage Vth for each word line WL may vary depending on the distance from the memory cell to the selected word line WL.

[0044] Furthermore, the threshold voltage Vth of the memory cells programmed into erase state E and first programming state P1 may decrease, thus the valley between erase state E and first programming state P1 may shift in the negative direction. Therefore, when a read operation is performed using the first default read voltage level RL1, read errors may occur in some memory cells programmed into first programming state P1. In this case, a read error may correspond to a situation where the number of fault bits in the read data is greater than or equal to the reference number of fault bits that can be corrected by ECC operations supported by the memory system. In this case, the read error can be eliminated by changing the optimal read voltage for first programming state P1 to a first corrected read voltage level corresponding to the valley of the offset between erase state E and first programming state P1.

[0045] Although read errors have been described based on the initial distribution 30 and the modified distribution 31, and in the case of the same word line WL, the increased retention time may necessitate the use of one or more (potentially different) read voltage levels of the word line WL across different chips or blocks to read adjacent data from adjacent memory cells to account for temperature, voltage, and / or process differences. However, read errors can still occur even when reading memory cells from different chips or blocks using the predetermined default read voltage level.

[0046] Reference Figure 4 Control logic 120 can load the read result from the adjacent word line WL(n+1) in response to a read voltage level reset command, assuming that the adjacent word line WL(n+1) is the word line WL adjacent to the target word line WL(n). Therefore, control logic 120 can reread adjacent data from the adjacent memory cell connected to the adjacent word line WL(n+1) in response to a read voltage level reset command, but the inventive concept is not limited thereto.

[0047] In this way, control logic 120 can effectively “reset” the read voltage of the target word line WL(n) while taking into account adjacent data read from adjacent memory cells. Here, the adjacent data may have been pre-stored in the page buffer. That is, a competent page buffer may include multiple latches (more than the number of target data bits) capable of temporarily storing data read from memory cells connected to one or more bit lines BL. Therefore, some adjacent data read from adjacent memory cells(s) may be stored in at least one of the page buffer latches.

[0048] In some embodiments, the results of read operations on adjacent memory cells can be classified according to one or more read voltage levels, based on each of the erase state E and the first to seventh programming states P1 to P7. Control logic 120 can also group target data obtained from the target memory cell based on voltage distributions indicating read results from adjacent memory cells, and group target memory cells according to read interrupts associated with the target memory cell and adjacent memory cells. For example, adjacent memory cells in erase state E and the first to third programming states P1 to P3 with low read interrupt levels may include a first group of memory cells because the threshold voltage of these particular memory cells is relatively low. Conversely, adjacent memory cells in the fourth to seventh programming states P4 to P7 with high read interrupt levels may include a second group of memory cells because the threshold voltage of these particular memory cells is relatively high. In other words, when control logic 120 receives adjacent data (e.g., from a latch connected to the first bit line BL commonly connected to the target memory cell) resulting from read operations on adjacent memory cells, the grouping of target memory cells can be determined based on the read results of (one or more) adjacent memory cells.

[0049] Reference Figure 4 Although the target memory cell has been described by using voltage distribution that classifies the target memory cell into two groups based on the read results of adjacent memory cells, the scope of the present invention is not limited thereto, and the control logic 120 can classify the target memory cell into three or more groups based on the read results of adjacent memory cells.

[0050] Reference Figure 5 The read result of the target memory cell can be classified into erase state E and first to seventh programming states P1 to P7 based on the read voltage level. The memory device 100 can determine the programming state of the memory cell based on a preset number of read voltage levels, and the read voltage level can be a voltage level determined based on the corresponding valley value between adjacent programming states. Therefore, according to... Figure 5 For example, the read voltage level RL used to determine the fifth programming state P5 and the sixth programming state P6 in all target memory cells MC can be a pre-stored voltage level based on the valley between the fifth programming state P5 and the sixth programming state P6.

[0051] However, refer to Figure 6 Control logic 120 can set the read voltage level for each group of target memory cells connected to the target word line WL(n). In other words, control logic 120 can classify and set the read voltage level for each group of target memory cells based on the read interrupt level associated with the target memory cell and adjacent memory cells. For example, according to Figure 4In one embodiment, the first group may include target memory cells that share bit line BL with adjacent memory cells having a relatively low read interrupt level, and the second group may include target memory cells that share bit line BL with adjacent memory cells having a relatively high read interrupt level.

[0052] Control logic 120 can set the read voltage level for each group by searching for the read voltage level of at least one group of memory cells among the target memory cells classified into different groups. For example, control logic 120 can search for the read voltage level by distinguishing the read voltage level RL_GR1 of the first group from the read voltage level RL_GR2 of the second group, thereby resetting the new read voltage level from a predetermined default read voltage level, and can perform a read operation on the target memory cells based on the read voltage level set for each group. However, control logic 120 is not limited to this, and can reset the read voltage level of the second group by searching only the read voltage level of the second group.

[0053] When an adjacent memory cell is programmed with a high voltage value and the read interrupt level is high, the threshold voltage of the target memory cell MC can be increased. Therefore, control logic 120 can improve read accuracy by resetting the read voltage level of the target memory cell MC connected to the adjacent memory cell MC with a high read interrupt level.

[0054] Reference Figure 7 Control logic 120 can search for the read voltage level of the first group of the target memory cell group. Control logic 120 can count the number of memory cells MC corresponding to the first, second, third, and fourth peripheral voltage levels Vth_1 to Vth_4 around the preset default read voltage level RL of the first memory cell group. Then, control logic 120 can set one of the first, second, third, and fourth peripheral voltage levels Vth_1 to Vth_4 as the first read voltage level of the first memory cell group. In some embodiments, the first, second, third, and fourth peripheral voltage levels Vth_1 to Vth_4 can be any voltage level deviating upwards and downwards from the default read voltage level.

[0055] Control logic 120 can count the number of memory cells MC corresponding to the first, second, third, and fourth peripheral voltage levels Vth_1 to Vth_4, and select the peripheral voltage level of the memory cell MC with the lowest count as the read voltage level. Therefore, according to Figure 7In the illustrated embodiment, control logic 120 can count the number of target memory cells corresponding to each of the first, second, third, and fourth peripheral voltage levels Vth_1 to Vth_4 around the default read voltage RL. When the number of target memory cells counted at the second peripheral voltage level Vth_2 is determined to be less than the number of target memory cells MC counted at the first, third, and fourth peripheral voltage levels Vth_1, Vth_3, and Vth_4, control logic 120 can select (or set) the second peripheral voltage level Vth_2 as the read voltage level.

[0056] Notice, Figure 7 The illustrated embodiment assumes that the read voltage level setting can be effectively used to distinguish the sixth programming state P6 from the seventh programming state P7 of the first group. However, those skilled in the art will recognize that this particular example is merely one of many read voltage level settings and classifications of resulting reads that may occur in various embodiments of the inventive concept.

[0057] Figure 8 This is a flowchart outlining a method for operating a non-volatile memory device according to an embodiment of the present invention. Here, the non-volatile memory device according to an embodiment of the present invention can perform a method of setting one or more read voltage levels using control logic 120. However, other embodiments of the present invention may use, for example, an external memory controller to set one or more read voltage levels.

[0058] Reference Figure 1 , Figure 2 and Figure 8 The control logic 120 of the storage device 100 can perform a read operation (S100) on an adjacent memory cell (e.g., a memory cell connected to an adjacent word line WL, wherein the adjacent word line WL is proximate to the target word line WL connected to the target memory cell). For example, the control logic 120 can perform a read operation and control the page buffer 150 to store the read data (e.g., read data including target data and adjacent data) in the latch of the page buffer 150.

[0059] Then, control logic 120 can classify the target memory cell into a group of multiple groups based on the adjacent data obtained by reading adjacent memory cells (S200). In some embodiments, the target memory cell may be physically close to adjacent memory cells (e.g., memory cells in a memory cell array that share bit lines BL with adjacent memory cells). Control logic 120 can identify the read results of adjacent memory cells and then determine which group the target memory cell belongs to.

[0060] For example, when adjacent data read from an adjacent memory cell may have one of eight (8) possible states, including the erase state E, four (4) of the eight possible states can be designated as the first group, and the remaining four (4) of the eight possible states can be designated as the second group. In this case, when the read result of the adjacent memory cell is in a state indicating the first group, the control logic 120 can designate the target memory cell as the first group, or when the read result of the adjacent memory cell is in a state indicating the second group, the control logic 120 can designate the target memory cell MC as the second group.

[0061] Then, control logic 120 can set the read voltage level of each group according to the category (S300). Control logic 120 can search for the read voltage level of each group in all groups and set the found read voltage level as the new read voltage level, but it can only search for the read voltage level of certain groups and set the found read voltage level as the new read voltage level.

[0062] In some embodiments, the control logic 120 may not search for read voltage levels for certain groups that are determined to have read interrupt levels lower than other groups among the plurality of groups, but may instead search for read voltage levels only for the remaining groups that are determined to have relatively high read interrupt levels.

[0063] Control logic 120 can use (or be based on) the read voltage level set for the group to which the target memory cell belongs to perform a read operation on the target memory cell (S400). In this regard, general control logic, by performing a read operation on the target memory cell MC connected to the target word line WL with a consistent read voltage level, may not be able to reflect the appropriate level of the threshold voltage Vth according to a read interruption. However, when the read operation is performed based on the read voltage level set for each group according to the embodiments of the present invention, an accurate read operation that reflects the appropriate level of the read interruption can be performed appropriately.

[0064] In some embodiments of the present invention, when word lines WL are stacked in a three-dimensional arrangement, i.e., when word lines WL are stacked vertically on the substrate, the three-dimensional word lines WL can have different corresponding specifications depending on, for example, the degree of trenching (exemplary process variations) and the different degrees of interruption between adjacent word lines WL spanning the chip and / or block. Additionally, the voltage distribution varies from one another depending on the number of read cycles, write cycles, erase cycles, and / or data retention time.

[0065] As those skilled in the art will understand upon considering the foregoing, the storage devices (e.g., according to embodiments of the present invention) Figure 1The storage device 100 can reduce errors in reading data by adaptively setting the read voltage level, thereby improving data reliability by searching for an appropriate read voltage level based on the read interrupt level between adjacent word lines.

[0066] Figure 9 This is a flowchart outlining a method for setting a read voltage level for a group according to an embodiment of the present invention.

[0067] Reference Figure 1 , Figure 2 , Figure 8 and Figure 9 The storage device 100 can search for read voltage levels only for target memory cells corresponding to one or more adjacent memory cells that have been determined to have a greater impact on read interruption than other (one or more) adjacent memory cells. Therefore, the storage device 100 may not search for read voltage levels of adjacent memory cells determined to have a smaller impact on read interruption, and may (e.g.) maintain a previously stored default read voltage level, or (e.g.) set the read voltage level according to a predetermined offset value. Therefore, according to Figure 9 In the embodiments described, target memory cells that are identified as having a significant impact on read interruptions can be classified into the first group.

[0068] The storage device 100 can perform read operations on adjacent memory cells connected to (or associated with) adjacent word lines WL, and temporarily store adjacent data read from adjacent memory cells according to bit lines BL (e.g., in units of bit lines BL).

[0069] The control logic 120 of the storage device 100 can classify the target storage cell into a group of multiple groups by determining whether the target storage cell belongs to a first group (S210). For example, the control logic 120 can determine whether the impact of a read interrupt on the target storage cell is relatively large based on the adjacent data read from the adjacent storage cell, and classify the target storage cell corresponding to the adjacent data that has been determined to have a relatively large read interrupt impact into the first group.

[0070] If the control logic determines that the target memory cell does indeed belong to the first group (S210 = Yes), then the control logic 120 can search for the read voltage level of the target memory cell belonging to the first group (S310). For example, the control logic 120 can use information about... Figure 7 The method described in the embodiment searches for a read voltage level. Then, control logic 120 selects a read voltage level as a new read voltage level corresponding to the first group (S320) and performs a read operation on the target memory cell.

[0071] On the other hand, if control logic 120 determines that the target memory cell does not belong to the first group (e.g., the target memory cell corresponding to the adjacent memory cell is determined to have a relatively small read interrupt impact), control logic 120 can set the read voltage level of other groups based on a preset offset value (S330). In this regard, other groups can be groups with a lower read interrupt impact than the first group, and in this case, control logic 120 can set a new read voltage level based on a preset offset value.

[0072] According to embodiments of the present invention, even when the target memory cell is properly programmed, the captured charge may be lost over time, and the threshold voltage of the target memory cell may decrease. Therefore, control logic 120 can set a new read voltage level by applying a preset offset value to the read voltage levels of other groups (i.e., groups other than the first group in the aforementioned example). For example, control logic 120 can set a new read voltage level by subtracting the offset value from the default read voltage level of other groups. However, control logic 120 is not limited to this; it can set a new read voltage level by adding the offset value to the read voltage level.

[0073] Notice, Figure 9 The embodiments assume that only the members of a single group are determined (and possibly only the read voltage level of a single group is searched), but the inventive concept is not limited thereto, and the control logic 120 may search for multiple read voltage levels associated with multiple groups that are determined to have relatively large read interrupt levels.

[0074] Therefore, according to embodiments of the present invention, such as those concerning... Figure 9 In the described embodiment, control logic 120 can search for read voltage levels only for target memory cells that have been determined to have a relatively large read interrupt impact, and can set the read voltage level by effectively taking read interrupts into account, by searching for read voltage levels in certain groups rather than searching for read voltage levels in all groups.

[0075] Figure 10 and Figure 11 This is a flowchart illustrating the execution of a read operation according to an embodiment of the present invention. Figure 10 This shows that when a read error is correctable, Figure 1 The read operation performed in the storage system, and Figure 11 This shows what happens when a read error is uncorrectable. Figure 1 The read operation performed in the storage system 100.

[0076] Reference Figure 1 , Figure 2 and Figure 10 , Figure 1The storage system can determine whether one or more read errors occurring in the data read from the memory cell connected to the selected word line WL are correctable before searching for the read voltage level. That is, the storage controller 200 can provide the storage device 100 with a read command CMD_RD (S10) indicating a read operation for the nth address (ADDRn) of the target memory cell. In this regard, the storage device 100 can receive a preset default read voltage level, the command signal CMD_RD, and the nth address ADDRn from the storage controller 200, and the storage device 100 can perform a read operation for the nth address using the default read voltage level (S20).

[0077] When performing a read operation, the storage device 100 can send the obtained read data to the storage controller 200 (S30), wherein the read data can be arranged as a series of bits derived by reading various programming states of the target storage cell connected to the selected word line WL.

[0078] Then, the storage controller 200 can determine whether one or more errors detected in the read data can be corrected using ECC (S40). If it is determined that one or more errors can be corrected using ECC operation, the storage controller 200 can perform an ECC decoding operation to correct one or more errors and complete the read operation for the nth address ADDRn.

[0079] When the read operation for address n ADDRn is completed, the storage controller 200 can send another read command CMD_RD for address (n-1) (ADDRn-1) to the storage device 100 to perform the read operation for address (n-1) ADDRn-1 (S11). Then, the storage device 100 performs the read operation for address (n-1) ADDRn-1 (S21).

[0080] In this regard, regarding Figure 10 The described embodiment illustrates a read operation performed on each word line WL of the memory cell array, where the read operation can be completed without resetting the individual read voltage level because it has been determined that the read data can be corrected by ECC operation.

[0081] Reference Figure 1 , Figure 2 and Figure 11 , Figure 1 The storage system can determine again whether one or more read errors occurring in the data read from the memory cell connected to the selected word line WL are correctable before searching for the read voltage level.

[0082] Operations S10, S20, S30, and S40 can be related to previous statements. Figure 10 The corresponding operations are the same for similar representations described.

[0083] However, when the storage controller 200 determines that one or more errors in the read data cannot be corrected using ECC operation, it can send a data recovery command CMD_DR (S50) from the storage controller 200 to the control logic 120 of the storage device 100, indicating a data recovery operation for the nth address ADDRn.

[0084] Upon receiving the data recovery command CMD_RD, control logic 120 may request page buffer 150 to provide adjacent data previously read from adjacent word line WLn+1 in order to reset the read voltage level (S60). In response, page buffer 150 may provide read data, which includes adjacent data stored in a latch connected to at least one bit line BL, wherein the latch may be used to temporarily store data read (or sensed) from an adjacent memory cell connected to adjacent word line WLn+1. Therefore, page buffer 150 may send read data to control logic 120 in response to the request received from control logic 120, which includes at least adjacent data read from a memory cell connected to adjacent word line WLn+1 (S70).

[0085] Subsequently, the control logic 120 of the storage device 100 can group the target memory cells into groups based on the adjacent data provided by the page buffer 150 (S200). Then, the control logic 120 can set the read voltage level for each group (S300). Here, operations S200 and S300 can be related to... Figure 8 The corresponding operations are the same for similar representations described.

[0086] according to Figure 10 and Figure 11 In some embodiments, although the storage controller 200 receives read data from the storage device 100 and determines whether the read data includes one or more errors, the control logic 120 of the storage device 100 can also be used to determine whether one or more errors have occurred in the read data.

[0087] Figure 12 This is a circuit diagram illustrating a relevant portion of a memory cell array including word line groups according to an embodiment of the present invention.

[0088] Reference Figure 1 , Figure 2 and Figure 12Control logic 120 can set the read voltage level for the target word line WL to the read voltage level of all word lines WL included in the memory cell array. Although the degree of read interruption between adjacent word lines WL differs for each word line WL, the difference in the degree of read interruption between adjacent word lines WL may be small when they are located in the same memory cell array because word lines WL in the same memory cell array typically have the same read cycle or hold time. Therefore, by setting the read voltage level for the target word line WL, which is one of the word lines in the memory cell array, and setting the remaining word lines WL to the same read voltage level as the target word line WL, read errors can be effectively corrected.

[0089] According to another embodiment, the memory cell array may include word line groups 0 to n (e.g., WLG0 to WLGn), and control logic 120 may set a read voltage level for each of the word line groups 0 to n. Here, word lines WL may differ between the actual read voltage level of the lowest word line WL and the highest word line WL due to process, voltage, or temperature variations. Instead of setting the same read voltage level for all word lines WL, the read voltage level can be set more accurately by setting the read voltage level for each word line group comprising multiple word lines WL.

[0090] about Figures 1 to 12 The described embodiment may be an embodiment in which the storage cell grouping unit 121 and the RL setting unit 122 are used to classify the target storage cells into groups and set the read voltage level for each group by searching the read voltage level of the target storage cells in at least one group.

[0091] Figure 13 This is a block diagram illustrating a non-volatile storage system according to an embodiment of the concept of the present invention.

[0092] Reference Figure 13 The control logic 120a may include a read controller 123, and the storage controller 200a may include a storage cell grouping unit 210 and an RL setting unit 220. The control logic 120a of the storage device 100 can be used to control the execution of read operations, and the storage cell grouping unit 210 and RL setting unit 220 of the storage controller 200a can be used to group target storage cells and set a read voltage level for each group. Additionally, the above references... Figures 1 to 12 The given description can be applied to Figure 13 Examples of implementations.

[0093] Figure 14 This is a flowchart illustrating an embodiment of the present invention of performing a read operation in a storage system.

[0094] Here, the storage system according to an embodiment of the present invention can determine whether one or more errors detected in the data read from the storage cell connected to the word line WL are correctable before searching for the read voltage level. Again, operations S10, S20, S30, and S40 can be related to the previous... Figure 10 and Figure 11 The corresponding operations are the same for similar representations described.

[0095] However, when the storage controller 200a determines that one or more errors cannot be corrected using ECC operation, the storage controller 200a may request the page buffer 150 to provide adjacent data read from the storage cell connected to the adjacent word line WLn+1 to reset the read voltage level (S60). In response, the page buffer 150 sends read data to the storage controller 200a, which includes at least the adjacent data (S70).

[0096] Therefore, the storage controller 200a, having already received adjacent data, can group the target storage cells into groups based on the adjacent data (S200) and set the read voltage level for each group (S300). Again, operations S200 and S300 can be performed in accordance with previously referenced... Figure 8 The corresponding operations are the same for similar representations described.

[0097] In this way, although according to Figure 11 In one embodiment, control logic 120 can set the read voltage level for each group of target memory cells, but according to Figure 14 In one embodiment, the storage controller 200a can be configured to set the read voltage level.

[0098] Figure 15 and Figure 16 These are conceptual diagrams illustrating one or more groups of storage units according to embodiments of the present invention.

[0099] Here, the storage controller (200 or 200a) can group the target storage cells by matching the read results of adjacent storage cells, which have already been classified as logical "high" or logical "low," with the read results of the target storage cell. Using the read results of adjacent storage cells (i.e., at least a portion of adjacent data), the groups of adjacent storage cells can be classified as high or low based on the degree of interruption in the read operations of the adjacent storage cells. For example, adjacent storage cells with a threshold voltage greater than a reference voltage value can be classified as a group with high bits, while adjacent storage cells with a threshold voltage less than a reference voltage value can be classified as a group with low bits. (Refer to...) Figure 4 This indicates that adjacent memory cells in the first group GR1 can be classified as the group with the least significant bit, while adjacent memory cells in the second group GR2 can be classified as the group with the most significant bit.

[0100] In some embodiments, the storage controller (200 or 200a) may group adjacent storage cells based on read results of adjacent storage cells, but is not limited thereto, and may also group adjacent storage cells through an external storage controller. When adjacent storage cells are grouped through an external storage controller, the storage device may also receive the group indicated by the adjacent storage cells, but may also send data of the target storage cell to the external storage controller.

[0101] Figure 15 This illustrates a case where adjacent memory cells are classified into groups with higher bits based on adjacent data (e.g., the memory controller classifies the target memory cell into a second group GR2).

[0102] Therefore, in adjacent word lines WLn+1, the high and low bit values ​​can be arranged in bit line order, and the memory controller can group target memory cells by matching the target memory cell of the target word line WLn with the adjacent memory cells of adjacent word lines WLn+1 that share the same bit line with the target memory cell. For example, the memory controller can set the target memory cell corresponding to the remaining data that has not been erased into a second group GR2 by multiplying the bit value of the adjacent word line WLn+1 with the bit value of its corresponding target word line WLn. For example, the memory controller can search for the read voltage level of the second group GR2 by using the threshold voltage value corresponding to the target memory cell of the second group GR2.

[0103] Figure 16 This illustrates a case where adjacent memory cells are classified into groups with low-order bits based on adjacent data (e.g., the memory controller classifies the target memory cell into the first group GR1).

[0104] Therefore, the high and low bit values ​​of adjacent word lines WLn+1 can be inverted, and the memory controller can classify the target memory cells indicating the low logic bits into the first group GR1 by matching the target memory cell of the target word line WLn with the adjacent memory cells of the adjacent word line WLn+1 that share the same bit line as the target memory cell. For example, the memory controller can classify the target memory cells corresponding to the remaining data that has not been erased into the first group GR1 by multiplying the inverted bit value of the adjacent word line WLn+1 with the bit value of its corresponding target word line WLn. For example, the memory controller can search for the read voltage level of the first group GR1 by using the threshold voltage value corresponding to the target memory cells of the first group GR1.

[0105] according to Figure 15 and Figure 16In some embodiments, grouping target storage units does not always require using adjacent data stored in the page buffer latches inside storage device 100; instead, data provided by an external controller can be used.

[0106] Figure 17 This is a cross-sectional view of a relevant portion of a memory device 400 having a chip-to-chip (C2C) structure according to certain embodiments of the present invention. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper and lower chips by bonding. For example, the bonding method may include electrically connecting a bonding metal formed on the topmost metal layer of the upper chip to a bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method can be a Cu-Cu bonding, and the bonding metal can also be formed of aluminum or tungsten.

[0107] The peripheral circuit region PERI and cell region CELL of the storage device 40 can each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0108] The Peripheral Circuit Area (PERI) may include: a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In an example embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten, which has relatively high resistance, while the second metal layers 240a, 240b, and 240c may be formed of copper, which has relatively low resistance.

[0109] exist Figure 17 In the examples shown, although first metal layers 230a, 230b, and 230c and second metal layers 240a, 240b, and 240c are shown and described, they are not limited thereto, and one or more metal layers may be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like, having a lower resistance than the copper used to form the second metal layers 240a, 240b, and 240c.

[0110] An interlayer insulating layer 215 may be disposed on a first substrate 210 and cover a plurality of circuit elements 220a, 220b and 220c, first metal layers 230a, 230b and 230c and second metal layers 240a, 240b and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide or silicon nitride.

[0111] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be electrically connected to the upper bonding metals 371b and 372b in the cell area (CELL) by bonding, and the lower bonding metals 271b and 272b, as well as the upper bonding metals 371b and 372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 371b and 372b in the cell area (CELL) can be referred to as first metal pads, while the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0112] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 310 and a common source line 320. Multiple word lines 331 to 338 (i.e., 330) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 330, respectively, and the multiple word lines 330 may be positioned between the at least one string select line and the at least one ground select line.

[0113] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 310 and pass through multiple word lines 330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In an example embodiment, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0114] exist Figure 17In the example shown, the area with the channel structure CH, bit line 360c, etc., can be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 360c can be electrically connected to circuit element 220c, which provides page buffer 393 in the peripheral circuit area PERI. For example, bit line 360c can be connected to upper bonding metals 371c and 372c in the cell area CELL, and upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c, which are connected to the circuit element 220c of the page buffer 393.

[0115] In the word line bonding area (WLBA), multiple word lines 330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and can be connected to multiple cell contact plugs 341 to 347 (i.e., 340). The multiple word lines 330 and the multiple cell contact plugs 340 can be connected to each other in pads provided by at least a portion of the word lines 330 extending at different lengths along the second direction. A first metal layer 350b and a second metal layer 360b can be sequentially connected to the upper portion of the multiple cell contact plugs 340 connected to the multiple word lines 330. The multiple cell contact plugs 340 can be connected to the peripheral circuit region PERI in the word line bonding area (WLBA) via upper bonding metals 371b and 372b of the cell region CELL and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0116] Multiple unit contact plugs 340 may be electrically connected to circuit element 220b providing a row decoder 394 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 220b providing the row decoder 394 may differ from the operating voltage of circuit element 220c providing the page buffer 393. For example, the operating voltage of circuit element 220c providing the page buffer 393 may be greater than the operating voltage of circuit element 220b providing the row decoder 394.

[0117] A common source contact 380 can be disposed in the external pad bonding region PA. The common source contact 380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a can be sequentially stacked on top of the common source contact 380. For example, the region where the common source contact 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding region PA.

[0118] Input and output pads 205 and 305 can be set in the external pad bonding area PA. (See reference...) Figure 17A lower insulating film 201 covering the lower surface of the first substrate 210 can be formed below the first substrate 210, and first input / output pads 205 can be formed on the lower insulating film 201. The first input / output pads 205 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via first input / output contact plugs 203, and can be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film can be provided between the first input / output contact plugs 203 and the first substrate 210 to electrically separate the first input / output contact plugs 203 from the first substrate 210.

[0119] Reference Figure 17 An upper insulating film 301 covering the upper surface of the second substrate 310 can be formed on the second substrate 310, and a second input / output pad 305 can be disposed on the upper insulating film 301. The second input / output pad 305 can be connected to at least one of a plurality of circuit elements 220a, 220b and 220c disposed in the peripheral circuit region PERI via a second input / output contact plug 303.

[0120] In some embodiments, the second substrate 310 and the common source line 320 may not be located in the region where the second input / output contact plug 303 is provided. Furthermore, the second input / output pad 305 may not overlap with the word line 330 in the third direction (Z-axis direction). (Refer to...) Figure 17 The second input / output contact plug 303 can be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can pass through the interlayer insulating layer 315 of the cell region CELL to connect to the second input / output pad 305.

[0121] In some embodiments, the first input / output pad 205 and the second input / output pad 305 may be selectively formed. For example, the storage device 400 may include only the first input / output pad 205 disposed on the first substrate 210 or the second input / output pad 305 disposed on the second substrate 310. Alternatively, the storage device 400 may include both the first input / output pad 205 and the second input / output pad 305.

[0122] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern in the uppermost metal layer can be set as a dummy pattern or the uppermost metal layer can be absent.

[0123] In the external pad bonding area PA, the storage device 400 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit area PERI, which corresponds to an upper metal pattern 372a formed in the uppermost metal layer of the cell area CELL and has the same shape as the upper metal pattern 372a of the cell area CELL. In the peripheral circuit area PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 372a may be formed in the uppermost metal layer of the cell area CELL, which corresponds to the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI and has the same shape as the lower metal pattern of the peripheral circuit area PERI.

[0124] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL via Cu-Cu bonding.

[0125] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 392 can be formed in the uppermost metal layer of the cell region CELL. This upper metal pattern 392 corresponds to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 252 of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0126] In some embodiments, a reinforcing metal pattern having the same shape as the metal pattern can be formed in the uppermost metal layer of the other of the cell region CELL and the peripheral circuit region PERI, corresponding to the metal pattern formed in the uppermost metal layer of the cell region CELL and the peripheral circuit region PERI, and contacts may not be formed on the reinforcing metal pattern.

[0127] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a non-volatile storage device, the method comprising: Perform a read operation on the adjacent memory cell of the adjacent word line connected to the adjacent target word line to determine the adjacent data; The target storage units connected to the target word line are grouped according to the adjacent data; The read voltage level of each group is set by searching for the read voltage level of the target memory cell in at least one of the groups; as well as A read operation is performed on the target memory cell using the read voltage level set for each of the groups. The setting of the read voltage level for each group includes: The number of memory cells in the first group of the group corresponding to multiple peripheral voltage levels around a preset read voltage level is counted; and Based on the number of storage cells obtained from counting, one of the plurality of peripheral voltage levels is set as the first read voltage level of the first group.

2. The method according to claim 1, wherein, Grouping the target storage units includes: Based on the adjacent data, the adjacent storage units are grouped together; and The target storage unit is classified into a group corresponding to the group to which the corresponding adjacent storage unit belongs.

3. The method according to claim 1, wherein, Grouping the target storage units includes: Storing adjacent data read from adjacent memory cells connected to at least one bit line; and Based on the adjacent data, determine which group of the group the target storage cell that shares bit lines with the adjacent storage cell belongs to.

4. The method according to claim 1, wherein, Grouping the target storage units includes: The target storage units are classified into groups by matching the logical high or logical low states of adjacent data read from adjacent storage units with the data stored in the target storage units.

5. The method according to claim 4, wherein, Grouping the target storage units includes: Based on the threshold voltage distribution of the adjacent memory cells, the adjacent data of each adjacent memory cell is classified into a logic high state or a logic low state.

6. The method according to claim 4, wherein, Grouping the target storage units includes: By multiplying the programming state of the adjacent memory cell by the programming state of the target memory cell, the target memory cell is set as the first group as follows: the programming state of the adjacent memory cell of the target memory cell is in a logic high state.

7. The method according to claim 6, wherein, Grouping the target storage units includes: By multiplying the inverted value of the programming state of the adjacent memory cell by the programming state of the target memory cell, the target memory cells are classified into a second group as follows: the programming state of the adjacent memory cells of the target memory cell is a logic low state.

8. The method according to claim 1, wherein, Setting the read voltage level for each of the groups also includes: The peripheral voltage level of the memory cell with the smallest count among the plurality of peripheral voltage levels is set as the first read voltage level of the first group.

9. The method according to claim 1, wherein, Setting the read voltage level for each of the groups also includes: The second read voltage level of the second group is set based on a preset offset value of the storage cell belonging to the second group, which is different from the first group.

10. The method according to claim 1, wherein, The non-volatile storage device includes a memory cell array, and the method further includes: The read voltage level of the target word line is set to the read voltage level of the multiple word lines of the memory cell array.

11. The method according to claim 1, wherein, The non-volatile storage device includes a memory cell array, the memory cell array including word lines, and the method further includes: Set the read voltage level of the target word line to the read voltage level of the word line group including the target word line.

12. The method according to claim 1, further comprising: Determine whether errors in the data read from the target storage unit can be corrected using error checking and correction operations; as well as When it is determined that the error is uncorrectable, a read operation is performed on the adjacent storage unit.

13. A non-volatile storage device, comprising: A memory cell array, the memory cell array comprising memory cells respectively connected to bit lines and word lines; as well as Control logic, which is configured as follows: A read operation is performed on the memory cell connected to the target word line and the adjacent word line of the target word line. By classifying the target memory cells connected to the target word line into multiple groups based on the adjacent data read from the adjacent memory cells connected to the adjacent word line, a read voltage level is set for each of the multiple groups; Search for the read voltage level of the target memory cell included in at least one of the plurality of groups, and The read operation on the target memory cell is performed using the read voltage level set for the group to which the target memory cell belongs. The process of searching for the read voltage level of a target memory cell in at least one of the plurality of groups includes: the control logic counting the number of memory cells in the first group of the plurality of groups that correspond to a plurality of peripheral voltage levels around a preset read voltage level, and setting one of the plurality of peripheral voltage levels as the first read voltage level of the first group based on the number of memory cells obtained by counting.

14. The non-volatile storage device according to claim 13, wherein, The control logic classifies the adjacent storage units into groups among the plurality of groups based on the adjacent data, and In response to the group to which the adjacent storage units belong, the target storage unit is classified into at least one of the plurality of groups.

15. The non-volatile storage device according to claim 13, wherein, The control logic stores the adjacent data for each bit line, and determines, based on the adjacent data of the adjacent storage cells, which group among the plurality of groups the target storage cell that shares the bit line with the adjacent storage cell belongs to.

16. The non-volatile storage device according to claim 15, wherein, The control logic classifies the target storage unit into the multiple groups by comparing the programming state of the adjacent storage unit that will be reset to a logic high or logic low state with the programming state of the target storage unit.

17. The non-volatile storage device according to claim 13, wherein, The control logic is further configured to set the read voltage level of the target word line to the read voltage level of at least another word line.

18. A non-volatile memory system, comprising: A memory cell array, the memory cell array comprising memory cells respectively connected to bit lines and word lines; and control logic, which is configured as follows: Perform a read operation on the target memory cell connected to the target word line in the word line. Perform a read operation on an adjacent storage cell that stores adjacent data and is connected to an adjacent word line adjacent to the target word line. The read voltage level of each of the multiple groups is set by classifying the target storage unit into multiple groups based on the adjacent data. Search for the read voltage level of the target memory cell included in the plurality of groups, and The read operation is performed on the target memory cell using the read voltage level set for the group to which the target memory cell belongs among the plurality of groups. The process of searching for the read voltage level of the target storage cell included in the plurality of groups includes: the control logic counting the number of storage cells in the first group of the plurality of groups that correspond to a plurality of peripheral voltage levels around a preset read voltage level, and setting one of the plurality of peripheral voltage levels as the first read voltage level of the first group based on the number of storage cells obtained by counting.

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