Semiconductor memory device and operation method thereof, and semiconductor memory system

Abstract

A semiconductor memory device and an operation method thereof and a semiconductor memory system are provided. The semiconductor memory device may include a cache latch circuit and a sensing latch circuit. The cache latch circuit may store setting data. The sensing latch circuit may store sensing data.

Description

Technical Field

[0001] Various embodiments relate generally to a semiconductor memory device, an operating method thereof, and a semiconductor memory system, and more particularly, to a semiconductor memory device capable of performing a program operation for storing data, an operating method thereof, and a semiconductor memory system. Background Art

[0002] In general, there are two types of semiconductor memory devices: volatile memory devices and non-volatile memory devices. Both types are capable of performing data processing operations of storing data or outputting stored data using power applied thereto. In this case, the volatile memory device has the advantage of a fast data processing operation speed, but has the disadvantage of requiring continuous power supply to maintain the stored data. In addition, the non-volatile memory device has the advantage of not requiring continuous power supply to maintain the stored data, but has the disadvantage of a slow data processing speed.

[0003] Nowadays, as process and design technology continue to develop rapidly, the difference between the data processing speed of volatile memory devices and the data processing speed of non-volatile memory devices has been significantly reduced. Therefore, non-volatile memory devices, which have the advantage of not requiring power to retain stored data, have recently received attention.

[0004] A representative example of a nonvolatile memory device is a NAND-type flash memory device in which a plurality of memory cells are connected in series to form a string structure. The memory cell of the NAND-type flash memory device includes a floating gate. Therefore, the memory cell can store logic "high" data and logic "low" data by injecting electrons into the floating gate or releasing electrons from the floating gate by means of a Fowler-Nordheim tunneling method.

[0005] Nonvolatile memory devices including NAND-type flash memory devices perform a program operation to store data in memory cells and perform a read operation to output the data stored in the memory cells. In addition, nonvolatile memory devices perform an erase operation to erase data from memory cells before a program operation.

[0006] The memory cell of the nonvolatile memory device is a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) according to the number of distributions of data stored in one memory cell during a programming operation. SLC storage can represent 1 bit in two different states, MLC storage can represent 2 bits in four different states, TLC storage can represent 3 bits in eight different states, and QLC storage can represent 4 bits in 16 different states.

[0007] Unlike volatile memory devices, nonvolatile memory devices include page buffer circuits connected to memory cells. Typically, page buffer circuits include multiple latch circuits. Multiple latch circuits store input data to be stored in memory cells during a programming operation, or store setup data during a setup operation before a programming operation. In order to smoothly perform a programming operation, it is necessary to pre-drive a specific node based on a set value before the programming operation. The set value is the setup data. Therefore, multiple latch circuits store setup data during the setup operation and drive specific nodes based on the setup data before the programming operation, so that the programming operation can be smoothly performed.

[0008] In this case, the setup data is stored in a plurality of latch circuits according to a set setup-data-latch sequence. That is, the setup data is not fixed and is not stored in one of the plurality of latch circuits, but is latched by the plurality of latch circuits according to the set setup-data-latch sequence. The reason why the setup data needs to be latched by the plurality of latch circuits according to the set sequence is that the physical number of latch circuits is limited.

[0009] The data latch sequence may be slightly different depending on the circuit design or circuit operation. However, generally, unless the physical design of multiple latch circuits is changed significantly, the data latch sequence tends to be standardized in a particular manner. For this reason, the increase in the operating speed of the existing semiconductor memory device is limited due to the standardized data latch sequence. Summary of the invention

[0010] Various embodiments are directed to providing a semiconductor memory device capable of performing a set operation and a program operation by changing a set data latch sequence.

[0011] In addition, various embodiments are directed to providing a semiconductor memory system capable of controlling a setup operation time.

[0012] The objects of the present disclosure are not limited to the above objects, and other objects not described above may be clearly understood by those skilled in the art to which the present disclosure belongs from the following description.

[0013] In one embodiment, a semiconductor memory device may include: a memory cell array configured to store input data received from an external source; and a plurality of page buffer circuits coupled to the memory cell array through bit lines and configured to transmit the input data to the bit lines during a programming operation. Each of the plurality of page buffer circuits may include: a cache latch circuit coupled to a sensing node to which the input data is transmitted and configured to store setup data; and a sense latch circuit configured to store sense data sensed through the bit lines during a sensing operation. During a setup operation prior to the programming operation, the setup data stored in the cache latch circuit is transmitted to the sense latch circuit.

[0014] In one embodiment, a method for operating a semiconductor memory device may include the following steps: during a set operation before performing a programming operation, transferring set data from a cache latch circuit to a sense latch circuit and storing the set data in the sense latch circuit; driving a bit line by the set data stored in the sense latch circuit; and transferring the set data from the sense latch circuit to at least one of a plurality of data latch circuits during the programming operation.

[0015] In one embodiment, a semiconductor memory system may include: a host device configured to provide program timing information; and a semiconductor memory device configured to control a set operation time based on the program timing information.

[0016] In one embodiment, a semiconductor memory device may include: a memory cell array configured to store programming data; a first latch configured to generate setup data; a second latch configured to latch the setup data from the first latch during a setup operation; and a third latch configured to latch the setup data from the second latch during a programming operation that stores the programming data in the array after the setup operation. The second latch is also configured to latch the setup data from the third latch again after the programming operation for subsequent programming operations. A bit line is coupled to the array and driven by the setup data latched in the second latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0018] Figure 2 It shows that Figure 1 1. A block diagram of a configuration of multiple page buffer circuits of such multiple page buffer circuits.

[0019] Figure 3A and Figure 3B It shows that Figure 2 A circuit diagram of a first page buffer circuit is a configuration of such a first page buffer circuit.

[0020] Figure 4A and Figure 4B is a timing diagram illustrating some operations of a semiconductor memory device according to an embodiment.

[0021] Figure 5A and Figure 5B It shows that Figure 3A and Figure 3B A first page buffer circuit is a schematic diagram of a setup data latch sequence in such a first page buffer circuit.

[0022] Figure 6 is a block diagram showing a configuration of a semiconductor memory system according to an embodiment. DETAILED DESCRIPTION

[0023] The embodiments described below are merely examples of the structural and / or functional aspects of the present invention. However, the present invention is not limited to the embodiments described in the specification. That is, as those skilled in the art will recognize from this disclosure, the present invention can take many different forms and configurations. The present invention includes all such variations that fall within the scope of the claims. In addition, the purposes or effects set forth in this disclosure are not necessarily associated with each embodiment. Therefore, the scope of the claims is not limited thereto.

[0024] In addition, throughout the specification, references to "one embodiment" and the like do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments. The meanings of the terms described in this application should be understood as follows.

[0025] Terms such as "first" and "second" are used to distinguish one element from another element that otherwise has the same or similar name, and are not used to indicate any substantial changes in the elements themselves. Therefore, the present invention should not be limited by these terms in any way.

[0026] Elements described in the singular may include multiple instances of the element, unless otherwise explicitly stated or the context clearly indicates that only one is used. Terms such as "including" or "having" should be understood in an open sense to include the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the existence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0027] In each step, for ease of description, symbols (e.g., a, b, and c) may be used, but any such symbols do not necessarily indicate the order of the steps. The steps may be performed in any order consistent with the teachings herein, unless a specific order is indicated or the context clearly requires a specific order.

[0028] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in commonly used dictionaries should be interpreted in the context of the relevant technology and should not be interpreted in an ideal way or in an overly formal way unless explicitly defined in this application.

[0029] Figure 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0030] Reference Figure 1 , a semiconductor memory device may include a memory cell array 100 , a peripheral circuit 200 , and an operation control circuit 300 .

[0031] First, the memory cell array 100 can store data input or received from an external device. The memory cell array 100 may include a plurality of memory blocks BK1 to BKn (where n is a natural number). Each of the plurality of memory blocks BK1 to BKn may include a plurality of memory cells for storing input data. The plurality of memory cells may be respectively connected to a plurality of row lines RL1 to RLn and a plurality of bit lines BL1 to BLm (where m is a natural number) in a matrix form. As described below, the plurality of row lines RL1 to RLn may receive a set voltage from the row decoding circuit 220 according to a programming operation, a read operation, or an erase operation. In addition, the plurality of bit lines BL1 to BLm may receive a set voltage corresponding to the input and output data from the plurality of page buffer circuits 230 according to a programming operation, a read operation, or an erase operation.

[0032] The peripheral circuit 200 may control a program operation, a read operation, or an erase operation of a target memory cell in the memory cell array 100. The peripheral circuit 200 may include a voltage generation circuit 210, a row decoding circuit 220, a plurality of page buffer circuits 230, a column decoding circuit 240, and a data input / output (I / O) circuit 250.

[0033] First, the voltage generation circuit 210 may generate an internal voltage V_W for a program operation, a read operation, or an erase operation. The voltage generation circuit 210 may generate an internal voltage V_W having various voltage levels based on a voltage control signal CTR_V generated by the operation control circuit 300. For example, in addition to voltage levels for a program operation, a read operation, and an erase operation, the voltage generation circuit 210 may also generate an internal voltage V_W having a voltage level for a verification operation, a pass operation, etc.

[0034] The row decoding circuit 220 may selectively apply the internal voltage V_W generated by the voltage generating circuit 210 to the plurality of row lines RL1 to RLn. The row decoding circuit 220 may receive the internal voltage V_W from the voltage generating circuit 210, and may receive the row address signal ADD_R from the operation control circuit 300. In this case, the row address signal ADD_R may be a signal for selecting a corresponding row line among the plurality of row lines RL1 to RLn. Therefore, the row decoding circuit 220 may apply the set internal voltage V_W to each of the plurality of row lines RL1 to RLn based on the row address signal ADD_R. In addition, although not shown, the row decoding circuit 220 may also be connected to the drain selection line, the source selection line, and the common source line included in the memory cell array 100. Therefore, according to a programming operation, a read operation, or an erase operation, the row decoding circuit 220 may apply the set internal voltage V_W to each of the drain selection line, the source selection line, and the common source line.

[0035] For example, during a programming operation, the row decoding circuit 220 may apply a programming voltage (i.e., one of the internal voltages V_W) to a selected row line among the plurality of row lines RL1 to RLn, and may apply a programming pass voltage having a voltage level lower than the programming voltage to unselected row lines. In addition, during a verification operation, the row decoding circuit 220 may apply a verification voltage (i.e., one of the internal voltages V_W) to a selected row line, and may apply a verification pass voltage having a voltage level higher than the verification voltage to unselected row lines. In addition, during a read operation, the row decoding circuit 220 may apply a read voltage to a selected row line, and may apply a read pass voltage having a voltage level higher than the read voltage to unselected row lines. In addition, at the time of an erase operation, the row decoding circuit 220 may apply a ground voltage to a selected row line.

[0036] The plurality of page buffer circuits 230 may be coupled to the memory cell array 100 through the plurality of bit lines BL1 to BLm. The plurality of page buffer circuits 230 may transmit data to the plurality of bit lines BL1 to BLm during a programming operation, and receive data from the plurality of bit lines BL1 to BLn during a reading operation. Each of the plurality of page buffer circuits 230 may be configured with a plurality of latch circuits. Each latch circuit may perform a programming operation and a reading operation on input and output data based on an operation control signal CTR_OP generated by the operation control circuit 300.

[0037] The column decoding circuit 240 may control a transmission path of input and output data. The column decoding circuit 240 may receive data to be output to the outside from the plurality of page buffer circuits 230, and may receive data to be input to the inside from the data I / O circuit 250. In addition, the column decoding circuit 240 may receive a column address signal ADD_C from the operation control circuit 300, and may control a transmission path of input and output data. In this case, the column address signal ADD_C may be a signal for selecting a plurality of bit lines BL1 to BLm.

[0038] The data I / O circuit 250 may control input and output of external data DAT_OUT and internal data DAT_IN. The data I / O circuit 250 may perform an I / O operation of data based on an I / O control signal CTR_IO generated by the operation control circuit 300. Therefore, based on the I / O control signal CTR_IO, the data I / O circuit 250 may output external data DAT_OUT received from an external source as internal data DAT_IN during a program operation, and may output internal data DAT_IN received from the column decoder 240 as external data DAT_OUT during a read operation.

[0039] The operation control circuit 300 may control the voltage generation circuit 210, the row decoding circuit 220, the plurality of page buffer circuits 230, the column decoding circuit 240, and the data I / O circuit 250 included in the peripheral circuit 200. The operation control circuit 300 may generate a voltage control signal CTR_V for controlling the voltage generation circuit 210 based on a command signal CMD and an address signal ADD from the outside, may generate a row address signal ADD_R to be provided to the row decoding circuit 220, may generate an operation control signal CTR_OP for controlling the plurality of page buffer circuits 230, may generate a column address signal ADD_C to be provided to the column decoding circuit 240, and may generate an I / O control signal CTR_IO for controlling the data I / O circuit 250. The operation control circuit 300 may control the overall operation of the semiconductor memory device. The semiconductor memory device may perform a programming operation, a read operation, an erase operation, etc. through the operation control circuit 300.

[0040] Figure 2 It is shown Figure 1 1 is a block diagram of a configuration of a plurality of page buffer circuits 230.

[0041] Reference Figure 2 , each of the plurality of page buffer circuits 230 may store data input and output according to a program operation and a read operation based on an operation control signal CTR_OP. The plurality of page buffer circuits 230 may include first to m-th page buffer circuits 230_1 to 230_m respectively coupled to a plurality of bit lines BL1 to BLm. Hereinafter, the first page buffer circuit 230_1 coupled to the first bit line BL1 among the first to m-th page buffer circuits 230_1 to 230_m is described as a representative example.

[0042] Reference Figure 2 The first page buffer circuit 230_1 is coupled to the first bit line BL1 and may transmit input data to the first bit line BL1 during a program operation. The first page buffer circuit 230_1 may include a caching latch circuit 231 and a sensing latch circuit 232 .

[0043] First, the cache latch circuit 231 can store setup data. The cache latch circuit 231 can efficiently operate multiple latch circuits in the first page buffer circuit 230_1. Therefore, in addition to the setup data, the cache latch circuit 231 can also store input data received during a programming operation and output data output during a read operation.

[0044] The sensing latch circuit 232 may store sensing data for a sensing operation of data transmitted through the first bit line BL1. In this case, the sensing data may have a set logic level. Therefore, the logic level of the sensing data may be maintained or inverted based on the output data transmitted through the first bit line BL1 during a read operation.

[0045] The semiconductor memory device according to the embodiment may include a cache latch circuit 231 and a sense latch circuit 232 in each page buffer circuit. As described in more detail below, during a setup operation prior to a programming operation, the page buffer circuit may transfer setup data from the cache latch circuit 231 to the sense latch circuit 232. Therefore, the page buffer circuit may minimize the setup data latch sequence during the setup operation. Minimizing the setup data latch sequence during the setup operation improves the programming operation timing speed as well as the overall programming operation speed.

[0046] The first page buffer circuit 230_1 may further include a plurality of data latch circuits 233 and verification latch circuits 234 .

[0047] First, a plurality of data latch circuits 233 may store input data during a programming operation. The number of data latch circuits included in the plurality of data latch circuits 233 may vary according to the number of distributions of data stored in the memory cell (i.e., the number of states that the memory cell can represent). A semiconductor memory device according to an embodiment includes a plurality of data latch circuits 233. As described below, any one of the plurality of data latch circuits 233 may receive setting data from the sense latch circuit 232 during a programming operation and may store the received setting data.

[0048] The verification latch circuit 234 may store verification data during a verification operation performed during a programming operation. In this case, the verification data is used to determine whether the input data stored in the memory cell during the programming operation forms a desired data distribution. The number of verification latch circuits 234 may vary according to the number of verification operations performed during the programming operation. A semiconductor memory device according to an embodiment includes a verification latch circuit 234. As described below, the verification latch circuit 234 may be initialized during a programming operation.

[0049] Figure 3A and Figure 3B It is shown Figure 2 2 is a circuit diagram of a configuration of the first page buffer circuit 230_1.

[0050] Reference Figure 2 , Figure 3A and Figure 3B The first page buffer circuit 230_1 may include a cache latch circuit 231, a sensing latch circuit 232, a first data latch circuit 233_1, a second data latch circuit 233_2 and a third data latch circuit 233_3 as a plurality of data latch circuits 233, a first verification latch circuit 234_1 and a second verification latch circuit 234_2 as a verification latch circuit 234, a bit line connection circuit 235 and a data sensing circuit 236.

[0051] Can be based on Figure 1 The first page buffer circuit 230_1 may be controlled by the operation control signal CTR_OP generated by the operation control circuit 300. That is, a signal for controlling the first page buffer circuit 230_1 may be included in the operation control signal CTR_OP.

[0052] First, the cache latch circuit 231 is coupled to the sensing node SO and may store setting data. The cache latch circuit 231 may generate the setting data based on the first control signal HT_N and the second control signal LT_N.

[0053] More specifically, the cache latch circuit 231 may include a first PMOS transistor P1, a second PMOS transistor P2, and a first NMOS transistor N1 connected in series between a power supply voltage level VCCI and a ground voltage level VSS. In addition, the cache latch circuit 231 may include a third PMOS transistor P3, a fourth PMOS transistor P4, and a second NMOS transistor N2 connected in series between the power supply voltage level VCCI and the ground voltage level VSS. The gates of the first PMOS transistor P1 and the first NMOS transistor N1 may be commonly connected to a negative cache node QC_N, that is, a drain of the fourth PMOS transistor P4. The gates of the third PMOS transistor P3 and the second NMOS transistor N2 may be commonly connected to a positive cache node QC, that is, a drain of the second PMOS transistor P2. In this case, the second PMOS transistor P2 and the fourth PMOS transistor P4 may receive a first control signal HT_N and a second control signal LT_N through their gates, respectively, and may perform a turn-on / turn-off operation. Therefore, when the first control signal HT_N is enabled, a logic "high" level may be stored in the positive cache node QC. When the second control signal LT_N is enabled, a logic 'high' level may be stored in the negative cache node QC_N. Thus, the cache latch circuit 231 may store setting data based on the first control signal HT_N and the second control signal LT_N.

[0054] The cache latch circuit 231 may include a third NMOS transistor N3 located between the positive cache node QC and the ground voltage level VSS. The third NMOS transistor N3 may receive a cache reset signal CRST through its gate. Therefore, the cache latch circuit 231 may perform a reset operation on the positive cache node QC based on the cache reset signal CRST. In addition, the cache latch circuit 231 may include a fourth NMOS transistor N4 and a fifth NMOS transistor N5 connected in series between the negative cache node QC_N and the sensing node SO. The fourth NMOS transistor N4 may receive a first cache transfer signal TRANC through its gate. The fifth NMOS transistor N5 may receive a second cache transfer signal TRANPB through its gate. Therefore, the cache latch circuit 231 may transmit the setting data to the sensing node SO based on the first cache transfer signal TRANC and the second cache transfer signal TRANPB.

[0055] The sensing latch circuit 232 may store sensing data for a sensing operation of data transmitted through the first bit line BL1. The sensing latch circuit 232 may store the sensing data based on a sensing reset signal SRST and a sensing set signal SSET.

[0056] More specifically, the sensing latch circuit 232 may include a fifth PMOS transistor P5 and a sixth NMOS transistor N6 connected in series between the core voltage level VCORE and the ground voltage level VSS. In addition, the sensing latch circuit 232 may include a sixth PMOS transistor P6 and a seventh NMOS transistor N7 connected in series between the core voltage level VCORE and the ground voltage level VSS. The gates of the fifth PMOS transistor P5 and the sixth NMOS transistor N6 may be commonly connected to the negative sensing node QS_N, and the sixth PMOS transistor P6 and the seventh NMOS transistor N7 may be commonly connected to the negative sensing node QS_N. The gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 may be commonly connected to the positive sensing node QS, and the fifth PMOS transistor P5 and the sixth NMOS transistor N6 may be commonly connected to the positive sensing node QS.

[0057] The sensing latch circuit 232 may include an eighth NMOS transistor N8 and a ninth NMOS transistor N9 connected in series between the positive sensing node QS and the ground voltage level VSS. In this case, the eighth NMOS transistor N8 may receive a sensing reset signal SRST through its gate. The ninth NMOS transistor N9 may receive a page reset signal PBRST through its gate. In addition, the sensing latch circuit 232 may include a tenth NMOS transistor N10 located between the negative sensing node QS_N and the first common node COM1. In this case, the tenth NMOS transistor N10 may receive a sensing set signal SSET through its gate. Therefore, during a read operation, the sensing latch circuit 232 may store sensing data based on the sensing reset signal SRST and the sensing set signal SSET.

[0058] The sense latch circuit 232 of the semiconductor memory device according to the embodiment may receive the setup data from the cache latch circuit 231 during the setup operation before the program operation. Figure 4A Describe it in more detail.

[0059] The first data latch circuit 233_1, the second data latch circuit 233_2, and the third data latch circuit 233_3 (i.e., multiple data latch circuits 233) can store input data during a programming operation. For reference, the three data latch circuits of the first data latch circuit 233_1, the second data latch circuit 233_2, and the third data latch circuit 233_3 can correspond to SLC or MLC or TLC. Therefore, for example, assuming that data corresponding to TLC is input, the first data latch circuit 233_1 can receive data corresponding to the most significant bit (MSB). The second data latch circuit 233_2 can receive data corresponding to the middle significant bit (CSB). The third data latch circuit 233_3 can receive data corresponding to the least significant bit (LSB). In one embodiment, a programming operation corresponding to SLC is described as an example. Therefore, as described again below, the first data latch circuit 233_1 can store input data. The second data latch circuit 233_2 may store setting data from the sense latch circuit 232 during a program operation.

[0060] First, the first data latch circuit 233_1 may include a seventh PMOS transistor P7 and an eleventh NMOS transistor N11 connected in series between the core voltage level VCORE and the ground voltage level VSS. In addition, the first data latch circuit 233_1 may include an eighth PMOS transistor P8 and a twelfth NMOS transistor N12 connected in series between the core voltage level VCORE and the ground voltage level VSS. The gates of the seventh PMOS transistor P7 and the eleventh NMOS transistor N11 may be commonly connected to the first negative data node Q1_N. The gates of the eighth PMOS transistor P8 and the twelfth NMOS transistor N12 may be commonly connected to the first positive data node Q1.

[0061] The first data latch circuit 233_1 may include a thirteenth NMOS transistor N13 and a fourteenth NMOS transistor N14 connected in series between the sensing node SO and the ground voltage level VSS. The thirteenth NMOS transistor N13 may receive the first positive data transmission signal TRAN1 through its gate. The gate of the fourteenth NMOS transistor N14 may be connected to the first positive data node Q1. The first data latch circuit 233_1 may include a fifteenth NMOS transistor N15 and a sixteenth NMOS transistor N16 connected in series between the sensing node SO and the ground voltage level VSS. The fifteenth NMOS transistor N15 may receive the first negative data transmission signal TRAN1_N through its gate. The gate of the sixteenth NMOS transistor N16 may be connected to the first negative data node Q1_N.

[0062] The first data latch circuit 233_1 may include a 161th NMOS transistor N161 coupled between the first positive data node Q1 and the first common node COM1. The 161th NMOS transistor N161 may receive the first data reset signal RST1 through its gate. The first data latch circuit 233_1 may include a 17th NMOS transistor N17 coupled between the first negative data node Q1_N and the first common node COM1. The 17th NMOS transistor N17 may receive the first data setting signal SET1 through its gate.

[0063] Therefore, the first data latch circuit 233_1 may perform an initialization operation and a data transmission operation based on the first positive and negative data transmission signals TRAN1 and TRAN1_N and the first data reset and set signals RST1 and SET1 .

[0064] The first data latch circuit 233_1, the second data latch circuit 233_2, and the third data latch circuit 233_3 have similar internal configurations except for their input control signals; therefore, detailed descriptions of the second data latch circuit 233_2 and the third data latch circuit 233_3 are omitted. In this case, the second data latch circuit 233_2 has a second positive data node Q2 and a second negative data node Q2_N formed therein, and can perform an initialization operation and a data transmission operation based on the second positive data transmission signal TRAN2 and the second negative data transmission signal TRAN2_N and the second data reset signal RST2 and the second data setting signal SET2. In addition, the third data latch circuit 233_3 has a third positive data node Q3 and a third negative data node Q3_N formed therein, and can perform an initialization operation and a data transmission operation based on the third positive data transmission signal TRAN3 and the third negative data transmission signal TRAN3_N and the third data reset signal RST3 and the third data setting signal SET3.

[0065] The first verification latch circuit 234_1 and the second verification latch circuit 234_2 (i.e., the verification latch circuit 234) can store verification data during a verification operation performed during a programming operation. In this case, the first verification latch circuit 234_1 and the second verification latch circuit 234_2 can perform two verification operations during the programming operation to improve the retention characteristic of the memory cell during the programming operation.

[0066] First, the first verification latch circuit 234_1 may include a ninth PMOS transistor P9 and an eighteenth NMOS transistor N18 connected in series between the core voltage level VCORE and the ground voltage level VSS. In addition, the first verification latch circuit 234_1 may include a tenth PMOS transistor P10 and a nineteenth NMOS transistor N19 connected in series between the core voltage level VCORE and the ground voltage level VSS. The gates of the ninth PMOS transistor P9 and the eighteenth NMOS transistor N18 may be commonly connected to the first negative verification node QM_N. The gates of the tenth PMOS transistor P10 and the nineteenth NMOS transistor N19 may be commonly connected to the first positive verification node QM.

[0067] The first verification latch circuit 234_1 may include a twentieth NMOS transistor N20 and a twenty-first NMOS transistor N21 coupled in series between the sensing node SO and the ground voltage level VSS. The twentieth NMOS transistor N20 may receive the first verification transmission signal TRANM through a gate thereof.

[0068] The first verification latch circuit 234_1 may include a 22nd NMOS transistor N22 coupled between the first positive verification node QM and the third common node COM3. The 22nd NMOS transistor N22 may receive the first verification reset signal MRST through its gate. The first verification latch circuit 234_1 may include a 23rd NMOS transistor N23 coupled between the first negative verification node QM_N and the third common node COM3. The 23rd NMOS transistor N23 may receive the first verification set signal MSET through its gate.

[0069] Therefore, the first verification latch circuit 234_1 can perform an initialization operation and a data verification operation based on the first verification transmission signal TRANM and the first verification reset signal MRST and the first verification setting signal MSET. Except for their input control signals, the first verification latch circuit 234_1 and the second verification latch circuit 234_2 have similar internal configurations, so the detailed description of the second verification latch circuit 234_2 is omitted. In this case, the second verification latch circuit 234_2 has a second positive verification node QD and a second negative verification node QD_N formed therein, and can perform an initialization operation and a data verification operation based on the second verification transmission signal TRAND and the second verification reset signal DRST and the second verification setting signal DSET.

[0070] The twenty-fourth NMOS transistor N24 may be coupled between the ground voltage level VSS and the first common node COM1, to which the sensing latch circuit 232 and the first data latch circuit 233_1 are commonly coupled. In addition, the twenty-fifth NMOS transistor N25 may be coupled between the ground voltage level VSS and the second common node COM2, to which the second data latch circuit 233_2 and the third data latch circuit 233_3 are commonly coupled. In addition, the twenty-sixth NMOS transistor N26 may be coupled between the ground voltage level VSS and the third common node COM3, to which the first verification latch circuit 234_1 and the second verification latch circuit 234_2 are commonly coupled. The gates of the twenty-fourth NMOS transistor N24, the twenty-fifth NMOS transistor N25, and the twenty-sixth NMOS transistor N26 may be coupled to the sensing node SO. Therefore, the twenty-fourth NMOS transistor N24, the twenty-fifth NMOS transistor N25, and the twenty-sixth NMOS transistor N26 may form a current path coupled to the ground voltage level VSS based on the voltage level of the sensing node SO.

[0071] The bit line connection circuit 235 may transmit input data from the sensing node SO to the first bit line BL1 by selectively connecting the first bit line BL1. As described below, the input data transmitted through the sensing node SO may be transmitted to the current sensing node CSO through the data sensing circuit 236. Therefore, the bit line connection circuit 235 may transmit input data from the sensing node SO to the first bit line BL1 through the current sensing node CSO by connecting the first bit line BL1 and the current sensing node CSO based on the bit line selection signal SEL_BL.

[0072] More specifically, the bit line connection circuit 235 may include a 27th NMOS transistor N27 and a 28th NMOS transistor N28 connected in series between the first bit line BL1 and the ground voltage level VSS. The 27th NMOS transistor N27 may receive the bit line selection signal SEL_BL through its gate. The 28th NMOS transistor N28 may receive the bit line discharge signal BLDIS through its gate.

[0073] The bit line connection circuit 235 may include a twenty-ninth NMOS transistor N29 connected between the buffer voltage level VEXT_PB and the first bit line BL1. The twenty-ninth NMOS transistor N29 may receive the erase control voltage BL_BIAS through its gate. In addition, the bit line connection circuit 235 may include a thirtieth NMOS transistor N30 connected between the common node BLCM of the twenty-seventh NMOS transistor N27 and the twenty-eighth NMOS transistor N28 and the current sensing node CSO. The thirtieth NMOS transistor N30 may receive the bit line sensing signal PB_SENSE through its gate.

[0074] Therefore, the bit line coupling circuit 235 may transfer input data from the sensing node SO to the first bit line BL1 based on the bit line selection signal SEL_BL and the bit line sensing signal PB_SENSE.

[0075] During a program operation, the data sensing circuit 236 may transfer data from the sensing node SO to the bit line coupling circuit 235. During a read operation, the data sensing circuit 236 may sense data transferred through the first bit line BL1 and may transfer the sensed data to the sensing node SO.

[0076] More specifically, the data sensing circuit 236 may include an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, and a thirty-first NMOS transistor N31 connected in series between the core voltage stage VCORE and the current sensing node CSO. The gate of the eleventh PMOS transistor P11 may be connected to the positive sensing node QS. The twelfth PMOS transistor P12 may receive a precharge control signal SA_PRECH_N through its gate. The thirty-first NMOS transistor N31 may receive a sensing control signal SA_SENSE through its gate. The data sensing circuit 236 may include a thirty-second NMOS transistor N32 located between the drain of the eleventh PMOS transistor P11 and the current sensing node CSO. The thirty-second NMOS transistor N32 may receive a sense amplifier connection signal SA_CSOC through its gate.

[0077] The data sensing circuit 236 may include a 33rd NMOS transistor N33 and a 34th NMOS transistor N34 connected in series between the sensing node SO and the ground voltage level VSS. The 33rd NMOS transistor N33 may receive the sense amplifier discharge signal SA_DISCH through its gate. The gate of the 34th NMOS transistor N34 may be connected to the positive sensing node QS.

[0078] Therefore, during a program operation, the data sensing circuit 236 may transfer data from the sensing node SO to the bit line coupling circuit 235 based on the sensing control signal SA_SENSE and the sense amplifier coupling signal SA_CSOC. During a read operation, the data sensing circuit 236 may sense data transmitted through the first bit line BL1 and may transfer the sensed data to the sensing node SO.

[0079] The first page buffer circuit 230_1 may include a thirteenth PMOS transistor P13 for precharging the sensing node SO. The thirteenth PMOS transistor P13 may be coupled between the core voltage level VCORE and the sensing node SO, and may receive a precharge signal PRECHSO_N through its gate. Therefore, the thirteenth PMOS transistor P13 may precharge the sensing node SO to a voltage level corresponding to the core voltage level VCORE based on the precharge signal PRECHSO_N.

[0080] A semiconductor memory device according to an embodiment can improve the overall programming operation speed by changing the setup data latch sequence during the setup operation and the programming operation. Figure 4A and Figure 4B Describes the setup data latch sequence during setup and programming operations.

[0081] Figure 4A and Figure 4B is a timing diagram illustrating some operations of a semiconductor memory device according to an embodiment. Figure 4A is a timing diagram corresponding to the setting operation. Figure 4B is a timing diagram corresponding to a program operation. For reference, it is assumed that the first setting data has been stored in the cache latch circuit 231 based on the first control signal HT_N and the second control signal LT_N and the bit line selection signal SEL_BL maintains a logic “high” state.

[0082] Reference Figure 4A , during the setup operation, the semiconductor memory device may precharge the sensing node SO based on the precharge signal PRECHSO_N. In this case, the precharge signal PRECHSO_N may be a pulse signal enabled as a logic "low" level. Therefore, the sensing node SO may be precharged to a voltage level corresponding to the level of the core voltage level VCORE based on the precharge signal PRECHSO_N.

[0083] The sense setting signal SSET of the sense latch circuit 232 may be enabled. Therefore, the negative sense node QS_N may be initialized to a logic 'low' level based on the sense setting signal SSET. The positive sense node QS may be initialized to a logic 'high' level.

[0084] The first cache transfer signal TRANC and the second cache transfer signal TRAMPB of the cache latch circuit 231 may be sequentially enabled. Therefore, the setting data stored in the cache latch circuit 231 may be transferred to the sensing node SO. In addition, the setting data transferred to the sensing node SO may be applied to the gate of the twenty-fourth NMOS transistor N24.

[0085] The sensing reset signal SRST of the sensing latch circuit 232 may be enabled. In this case, since the setting data transmitted through the sensing node SO is applied to the gate of the twenty-fourth NMOS transistor N24, the logic level of the positive sensing node QS may be determined based on the setting data. Therefore, the sensing latch circuit 232 may store the setting data in the positive sensing node QS.

[0086] During a set operation prior to a program operation, the semiconductor memory device according to an embodiment may transfer the set data from the cache latch circuit 231 to the sense latch circuit 232, and store the transferred set data in the sense latch circuit 232. Therefore, when the set data is transferred from the cache latch circuit 231 to the sense latch circuit 232, a set data latch sequence may be minimized.

[0087] Reference Figure 4B In the semiconductor memory device according to the embodiment, during the program operation, the bit line sense signal PB_SENSE of the bit line connection circuit 235 may be slowly enabled, and the sense amplifier connection signal SA_CSOC and the sense amplifier discharge signal SA_DISCH of the data sensing circuit 236 may be enabled. Therefore, the setting data stored in the sense latch circuit 232 may be transferred to the first bit line BL1 through the current sensing node CSO. Before the program pulse is applied, the first bit line BL1 may be driven by the setting data.

[0088] During a programming operation, an incremental step pulse program (ISPP) method may be used to apply a programming pulse to a specific word line WL. Using the ISPP method, the voltage level of the programming pulse gradually increases. Although not shown in the drawings, a verification operation may be performed on input data stored during the programming operation between operations of applying programming pulses to the word line WL.

[0089] During a program operation, a first verification reset signal MRST of the first verification latch circuit 234_1 may be enabled, and a second verification set signal DSET of the second verification latch circuit 234_2 may be enabled. The first verification latch circuit 234_1 and the second verification latch circuit 234_2 may perform an initialization operation based on the first verification reset signal MRST and the second verification set signal DSET, respectively.

[0090] During the programming operation, the second data reset signal RST2 of the second data latch circuit 233_2 may be enabled. Therefore, the second data latch circuit 233_2 may be initialized based on the second data reset signal RST2. Thereafter, when the precharge signal PRECHSO_N is enabled, the sense node SO may be precharged. When the sense amplifier discharge signal SA_DISCH is enabled, the setting data stored in the sense latch circuit 232 may be transferred to the sense node SO. Thereafter, the second data setting signal SET2 of the second data latch circuit 233_2 may be enabled. Therefore, the setting data may be stored in the second data latch circuit 233_2.

[0091] During a program operation, the semiconductor memory device according to an embodiment may initialize the first verification latch circuit 234_1 and the second verification latch circuit 234_2 and may latch the set data from the sense latch circuit 232 in the second data latch circuit 233_2 .

[0092] Figure 5A and Figure 5B It shows Figure 3A and Figure 3B Schematic diagram of the setup data latch sequence in the first page buffer circuit 230_1. Figure 5A The set data latch sequence in is denoted as “first set data latch sequence”, and Figure 5B The setting data latch sequence in is represented as a “second setting data latch sequence.” The semiconductor memory device according to the embodiment may latch the setting data according to the first setting data latch sequence and the second setting data latch sequence having different latch sequences of the setting data.

[0093] Reference Figure 3A , Figure 3B and Figure 5AAs described above, the setting data based on the first setting data latch sequence may be stored in the positive cache node QC of the cache latch circuit 231 during the setting operation before the initial program operation. Thereafter, the setting data stored in the positive cache node QC may be transferred to the positive sensing node QS of the sensing latch circuit 232. The first bit line BL1 may be driven by the setting data stored in the positive sensing node QS. During the programming operation, the setting data stored in the positive sensing node QS of the sensing latch circuit 232 may be transferred to the second positive data node Q2 of the second data latch circuit 233_2. After the programming operation, the setting data stored in the second positive data node Q2 may be transferred to the positive sensing node QS of the sensing latch circuit 232 for the next programming operation. The sensing data transferred to the positive sensing node QS may be used to drive the first bit line BL1 for the next programming operation. Then, the next programming operation may be performed.

[0094] According to the first setting data latch sequence, an initial programming operation may be performed after the setting data is transmitted to the positive sensing node QS of the sensing latch circuit 232. Figure 5A As shown, a set operation time based on the first set data latch sequence may be defined as “T1.” After the set operation time “T1,” an initial program operation may be performed.

[0095] Reference Figure 3A , Figure 3B and Figure 5B As shown, the setting data may be stored in the positive cache node QC of the cache latch circuit 231 during the setting operation before the initial programming operation. Thereafter, the setting data stored in the positive cache node QC may be transferred to the second positive data node Q2 of the second data latch circuit 233_2. Thereafter, the setting data stored in the second positive data node Q2 may be transferred to the positive sensing node QS of the sensing latch circuit 232. The first bit line BL1 may be driven by the setting data stored in the positive sensing node QS. During the programming operation, the setting data stored in the sensing latch circuit 232 may be transferred to the second positive data node Q2 of the second data latch circuit 233_2. After the programming operation, for the next programming operation, the setting data stored in the second positive data node Q2 may be transferred to the positive sensing node QS of the sensing latch circuit 232. The sensing data transferred to the positive sensing node QS may be used to drive the first bit line BL1 for the next programming operation. In addition, the next programming operation may be performed.

[0096] In the second setting data latch sequence, the initial programming operation may be performed after the setting data is transferred to the positive sensing node QS of the sensing latch circuit 232. Figure 5BAs shown, a set operation time based on the second set data latch sequence may be defined as “T2.” After the set operation time “T2,” an initial program operation may be performed.

[0097] As from Figure 5A and Figure 5B As can be seen, the initial programming operation timing based on the first setting data latch sequence and the initial programming operation timing based on the second setting data latch sequence can be different. In other words, in the first setting data latch sequence, since the setting operation time is "T1", the initial programming operation can be performed relatively quickly. In the second setting data latch sequence, since the setting operation time is "T2" which is longer than "T1", the initial programming operation can be performed relatively slowly. Therefore, the first setting data latch sequence can be applied to a semiconductor memory system that meets the condition that the initial programming operation is relatively fast. The second setting data latch sequence can be applied to a semiconductor memory system that meets the condition that the initial programming operation is relatively slow. In the following, a semiconductor memory system to which the first setting data latch sequence and the second setting data latch sequence are applied is described.

[0098] Figure 6 is a block diagram showing a configuration of a semiconductor memory system according to an embodiment.

[0099] Reference Figure 6 , the semiconductor memory system may include a host device 1000 and a semiconductor memory device 2000 .

[0100] First, the host device 1000 may store data in the semiconductor memory device 2000 or receive data stored in the semiconductor memory device 2000. The host device 1000 may exchange data DAT_OUT or data stored in the semiconductor memory device 2000 with the semiconductor memory device 2000. The host device 1000 may provide program timing information INF_PT to the semiconductor memory device 2000. The program timing information INF_PT may be related to the program operation timing of the semiconductor memory device 2000.

[0101] The semiconductor memory device 2000 may store the data DAT_OUT provided by the host device 1000 or output the stored data as DAT_OUT. The semiconductor memory device 2000 may include Figure 1The operation control circuit 300 may perform a program operation and a read operation. In this case, the operation control circuit 300 may control the setting operation time and the programming operation timing based on the programming timing information INF_PT provided by the host device 1000. In other words, the operation control circuit 300 may change the setting data latch sequence to the first setting data latch sequence or the second setting data latch sequence based on the programming timing information INF_PT. The first setting data latch sequence and the second setting data latch sequence may have different setting operation times, as has been described with reference to Figure 5A and Figure 5B Just as described.

[0102] First, the semiconductor memory device 2000 may perform a set operation with a first set data latch sequence based on the program timing information INF_PT. In other words, the semiconductor memory device 2000 may store the set data in the positive cache node QC of the cache latch circuit 231, and may transmit the set data from the positive cache node QC to the positive sense node QS of the sense latch circuit 232. In addition, after driving the first bit line BL1 with the set data, the semiconductor memory device 2000 may perform a program operation. In addition, during the program operation, the semiconductor memory device 2000 may transmit the set data from the positive sense node QS of the sense latch circuit 232 to the second positive data node Q2 of the second data latch circuit 233_2.

[0103] The semiconductor memory device 2000 may perform a set operation in a second set data latch sequence based on the program timing information INF_PT. In other words, the semiconductor memory device 2000 may store the set data in the positive cache node QC of the cache latch circuit 231, may transfer the set data from the positive cache node QC to the second positive data node Q2 of the second data latch circuit 233_2, and may transfer the set data from the second positive data node Q2 to the positive sense node QS of the sense latch circuit 232. In addition, after driving the first bit line BL1 with the set data, the semiconductor memory device 2000 may perform a program operation. In the second set data latch sequence, unlike the first set data latch sequence, during the set operation, the set data may be stored in the second positive data node Q2 of the second data latch circuit 233_2.

[0104] As a result, if the host device 1000 wants a relatively fast programming timing, the semiconductor memory device 2000 can perform a setup operation with a first setup data latch sequence. In addition, if the host device 1000 wants a relatively slow programming timing, the semiconductor memory device 2000 can perform a setup operation with a second setup data latch sequence. Therefore, the semiconductor memory device 2000 can control the setup operation time based on the programming timing information INF_PT. In this case, controlling the setup operation time can mean that the programming timing is controlled.

[0105] The semiconductor memory system according to the embodiment may control the setup operation time and the program timing based on the program timing information INF_PT provided by the host device 1000. Therefore, the semiconductor memory system may improve the system compatibility between the host device 1000 and the semiconductor memory device 2000.

[0106] The effect of the embodiment is that it can improve the overall program operation speed by changing the set data latch sequence during the set operation and the program operation.

[0107] The embodiment has an effect in that it can improve the compatibility of the system by setting the operation time and programming the operation timing based on the system operation control.

[0108] Effects of the present disclosure are not limited to the above effects; based on the above description, those skilled in the art to which the present disclosure belongs may understand other effects not described above.

[0109] While various embodiments have been shown and described, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

[0110] CROSS-REFERENCE TO RELATED APPLICATIONS

[0111] This application claims the benefit of Korean Application No. 10-2020-0070566, filed on June 10, 2020, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a memory cell array configured to store input data received from an external source; as well as a plurality of page buffer circuits coupled to the memory cell array through bit lines and configured to transfer the input data to the bit lines during a programming operation, Wherein, each of the plurality of page buffer circuits comprises: a cache latch circuit coupled to a sensing node to which the input data is transmitted and configured to store setting data or to store the input data to be stored in the memory cell array; and a sense latch circuit configured to store sense data sensed through the bit line during a sense operation, During a setting operation prior to the programming operation, the setting data stored in the cache latch circuit is transferred to the sensing latch circuit.

2. The semiconductor memory device according to claim 1, The semiconductor memory device further includes a plurality of data latch circuits configured to store the input data during the programming operation, in, At least one of the plurality of data latch circuits stores the setting data from the sense latch circuit during the programming operation.

3. The semiconductor memory device according to claim 1, The semiconductor memory device further includes a verification latch circuit configured to store verification data during a verification operation of the program operation, in, The verify latch circuit is initialized during the programming operation.

4. The semiconductor memory device according to claim 1, further comprising: a bit line connection circuit configured to transfer the input data from the sense node to the bit line by selectively connecting the bit line; as well as A data sensing circuit is configured to transfer data from the sense node to the bit line coupling circuit during the program operation and sense data from the bit line during a read operation.

5. A method for operating a semiconductor memory device, the method comprising the following steps: During a set operation before performing a programming operation, transferring set data from a cache latch circuit to a sense latch circuit and storing the set data in the sense latch circuit; driving a bit line by the setting data stored in the sense latch circuit; as well as transferring the setting data from the sense latch circuit to at least one of a plurality of data latch circuits during the programming operation, The cache latch circuit is configured to store the setting data or to store input data to be stored in a memory cell array of the semiconductor memory device.

6. The operating method according to claim 5, further comprising the following steps: After the program operation, the setting data is transferred from the at least one of the plurality of data latch circuits to the sense latch circuit for a next program operation.

7. The operating method according to claim 6, further comprising the following steps: After the bit line is driven by the setting data stored in the sense latch circuit for the next program operation, the next program operation is performed.

8. A semiconductor memory system, the semiconductor memory system comprising: a host device configured to provide programming timing information; a semiconductor memory device configured to control a set operation time for a set operation based on the program timing information; as well as a cache latch circuit configured to store setting data or to store input data to be stored in a memory cell array of the semiconductor memory device, The semiconductor memory device is further configured to transfer the setting data stored in the cache latch circuit to the sense latch circuit during the setting operation.

9. The semiconductor memory system according to claim 8, wherein: The semiconductor memory device controls the set operation time by changing a set data latch sequence based on the program timing information.

10. The semiconductor memory system according to claim 9, wherein: The setting data latch sequence includes a first setting data latch sequence and a second setting data latch sequence having different setting operation times.

11. The semiconductor memory system according to claim 10, wherein: Based on the first setting data latch sequence, the semiconductor memory device is further configured to: storing the setting data in the cache latch circuit, transferring the setting data from the cache latch circuit to the sense latch circuit, and The bit lines are then driven by the set data.

12. The semiconductor memory system according to claim 11, wherein: The semiconductor memory device is also configured to transfer the setting data from the sense latch circuit to at least one of a plurality of data latch circuits during a program operation.

13. The semiconductor memory system according to claim 10, wherein: Based on the second setting data latch sequence, the semiconductor memory device is further configured to: storing the setting data in the cache latch circuit, transferring the setting data from the cache latch circuit to at least one of a plurality of data latch circuits, transferring the setting data from the at least one of the plurality of data latch circuits to the sense latch circuit, and The bit lines are then driven by the set data.

14. A semiconductor memory device, the semiconductor memory device comprising: a memory cell array configured to store programming data; a first latch configured to generate setup data or store the programming data; a second latch configured to latch the set data from the first latch during a set operation; as well as a third latch configured to latch the set data from the second latch during a program operation that stores the program data in the memory cell array after the set operation, wherein the second latch is further configured to latch the setting data from the third latch again after the programming operation for a subsequent programming operation, and Wherein, a bit line is coupled to the memory cell array and is driven by the setting data latched in the second latch.

15. The semiconductor memory device according to claim 14, in, The third latch is further configured to latch the setting data from the first latch during the setting operation, The second latch latches the setting data from the first latch via the third latch during the setting operation.

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