Floating-gate devices in high voltage applications

Abstract

The present invention relates to floating gate devices in high voltage applications. The present disclosure relates to semiconductor structures, and more particularly to floating gate devices and methods of manufacturing the same. The structure comprises: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor located above the gate electrode and electrically connected to the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to floating gate devices and methods of manufacturing the same. Background Art

[0002] High voltage semiconductor devices are used in a variety of applications. These applications include, for example, nonvolatile memory devices. Electronic devices utilizing nonvolatile memory require greater nonvolatile data storage capacity while decreasing in size.

[0003] Nonvolatile memory cells can be formed using a "double poly" structure, in which the control gate and floating gate are formed in separate polycrystalline silicon (also called polysilicon) layers. However, the double poly process is expensive because of the additional manufacturing steps required to form multiple polysilicon layers. Alternatively, memory cells can be manufactured by providing a very thick gate oxide, for example, In comparison, the gate oxide thickness is approximately However, making thicker gate oxides is also a time-consuming and expensive process.

[0004] In another type of nonvolatile memory cell, the gate of a transistor used as a floating gate is coupled to a capacitor used as a control gate. These memory cells occupy a very large semiconductor surface area because the capacitor must be implemented in the semiconductor substrate and laid out to the side of the transistor. Nonvolatile memory cells with capacitors also require minimum spacing requirements, which increases the occupied semiconductor area. Summary of the invention

[0005] In one aspect of the present disclosure, a structure includes a gate structure including a gate dielectric material and a gate electrode; and a vertically stacked capacitor located above and electrically connected to the gate electrode.

[0006] In one aspect of the present disclosure, a structure includes: a substrate; a floating gate structure located on the substrate and including a gate dielectric material and a gate electrode; and a vertically stacked capacitor located above the floating gate structure and having a footprint that is the same as or smaller than that of the floating gate structure.

[0007] In one aspect of the present disclosure, a method includes forming a gate structure on a substrate; and forming a capacitor vertically above and electrically connected to the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0009] Figure 1 A gate structure and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0010] Figure 2 A voltage divider stacked on a gate structure and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0011] Figure 3 Shown are representations of floating gate voltage (fg) and input control gate (Cg) according to aspects of the present disclosure.

[0012] Figure 4 A top view of a voltage divider stacked on a gate structure according to aspects of the present disclosure is shown.

[0013] Figures 5 to 7 A diagram comparing a voltage divider stacked on a gate structure with a conventional gate electrode is shown. DETAILED DESCRIPTION

[0014] The present disclosure relates to semiconductor structures, and more specifically to floating gate devices and methods of manufacturing. More specifically, the present disclosure relates to floating gate devices used in high voltage applications, such as 25V+. In an embodiment, the floating gate device includes a gate structure with a vertically stacked capacitor on top of the gate structure. Advantageously, the present disclosure allows high voltage applications, such as 25V+ devices, to be implemented at the gate stack without modifying the gate dielectric of the gate stack. The floating gate device also does not increase the footprint, and further reduces the complexity of the gate manufacturing process.

[0015] In an embodiment, a voltage divider (e.g., a back-end of line (BEOL) capacitor) is stacked vertically on top of a gate electrode of a field effect transistor (FET) formed on a substrate. Preferably, the BEOL capacitor is formed within the footprint of the gate electrode, although it is also contemplated that the BEOL capacitor may extend beyond the footprint of the gate electrode. In an implementation, the BEOL capacitor (i.e., the voltage divider) may control the voltage applied to the gate electrode of the FET by capacitive coupling to the gate electrode. For example, by coupling a connection of the BEOL capacitor directly to the gate electrode of the FET, and in an embodiment, maintaining some floating connections, the voltage applied to the gate electrode of the FET may be controlled.

[0016] The floating gate devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the floating gate devices of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned by a photolithography process on top of the wafer. Specifically, the manufacture of floating gate devices uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) etching the film selectively to the mask.

[0017] Figure 1 The gate structure and the corresponding manufacturing process according to aspects of the present disclosure are shown. More specifically, Figure 1 The illustrated structure 10 includes a gate structure 12 formed on a substrate 14. In an embodiment, the substrate 14 may be any suitable semiconductor material. For example, the substrate 14 may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In addition, the substrate 14 may represent a single semiconductor material such as bulk silicon. Alternatively, the substrate may include semiconductor-on-insulator (SOI) technology as is known in the art, and thus further explanation is not required to fully appreciate the present disclosure.

[0018] Still refer to Figure 1 , the gate structure 12 includes a gate dielectric material 16 and a gate electrode 18. In an embodiment, the gate dielectric material 16 may be a high-k gate dielectric material, such as HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations thereof. The gate dielectric material 16 may have a thickness of about or greater; however, other thicknesses are contemplated herein. The gate electrode 18 may be, for example, a polysilicon material.

[0019] In an embodiment, the gate dielectric material 16 and the gate electrode 18 are formed by conventional deposition, lithography, and etching processes. For example, the gate dielectric material 16 can be deposited by a conventional atomic layer deposition (ALD) process or a plasma enhanced chemical vapor deposition (PECVD) process as an example. The gate electrode 18 can be formed by depositing a polysilicon material on the gate dielectric material 16 using a CVD deposition process. After the deposition process, conventional lithography and etching processes are used to pattern the materials of the gate dielectric material 16 and the gate electrode 18, so that the present disclosure can be fully understood without further explanation. The sidewall spacer 20 is formed on the gate structure 12 by a conventional deposition process, and then an anisotropic etching process is performed. The sidewall spacer 20 can be, for example, a nitride material.

[0020] Figure 1 Also shown are source and drain regions 22 formed by a conventional ion implantation process or elevated source and drain regions 22 formed by a doped epitaxial growth process. For example, in an epitaxial growth process, epitaxial regions (source / drain regions) are formed by selectively growing semiconductor material on substrate 14. Although not shown, substrate 14 may include a well formed by introducing a dopant (via, for example, ion implantation that introduces a concentration of the dopant into substrate 14). Among other suitable examples, the P-well is doped with a p-type dopant, such as boron (B); the N-well is doped with an n-type dopant, such as arsenic (As), phosphorus (P), and Sb.

[0021] Figure 2 1 shows a voltage divider 24 vertically stacked on the gate structure 12 and a corresponding manufacturing process. More specifically, the voltage divider 24 is a BEOL capacitor vertically stacked on the gate structure 12. Figure 2 As shown, the BEOL capacitor 24 does not increase the footprint of the device (e.g., gate structure 12) because it is positioned vertically above the gate structure 12; that is, the BEOL capacitor 24 can have the same or smaller footprint than the gate structure 12. In one non-limiting exemplary embodiment, the BEOL capacitor 24 can be a metal-oxide-metal (MOM) capacitor or an alternating polarity metal-oxide-metal (APMOM) capacitor. In the latter case, the wiring 28 located on the same wiring level will alternate between positive and negative.

[0022] Depending on the design parameters, the BEOL capacitor 24 may include one or more layers of wiring 28. For example, an increase in the number of layers of wiring 28 will increase the capacitance; while a decrease in the number of layers of wiring 28 will decrease the capacitance. In addition, the spacing between wirings 28 on the same level or layer or on different levels or the size of wirings 28 may be adjusted to increase or decrease the capacitance density. For example, using five metal layers when an 8V voltage is applied will result in a capacitive coupling of 1:4, thereby extending an existing 20V high voltage (HV) gate oxide to a 25V HV application. Similarly, using three metal layers when a 12V voltage is applied will result in a capacitive coupling of 1:1.67, thereby extending an existing 20V high voltage (HV) gate oxide to a 32V HV application. A more detailed example is provided below.

[0023] The BEOL capacitor 24 is coupled to the gate electrode 18 of the gate structure 12 through a wiring or interconnect structure 26. For example, at least one or more wirings 28 of the BEOL capacitor 24 are directly connected to the gate electrode 18 through the wiring or interconnect structure 26. In this way, when a voltage is applied, the gate structure 12 becomes a floating node (e.g., a floating gate device). In addition, one or more layers of wiring 28 can be optionally separated by a nitride layer 30. The BEOL capacitor 24 and the wiring or via structure 26 are formed in a dielectric material 32. In an embodiment, the dielectric material 32 is an inter-level dielectric material, which includes, for example, SiO2. In addition, for example, the ratio of the thickness of the gate dielectric material 16 to the thickness of the back-end process dielectric material (e.g., dielectric material 32) can be 1:1 to 1:4.

[0024] The BEOL capacitor 24 (e.g., wiring structures and interconnect structures) can be formed to have the same or smaller footprint than the gate structure 12 using conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed over the layer of dielectric material 32 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to form one or more trenches in the dielectric material 32 through the openings in the resist. After the resist is removed using a conventional oxygen ashing process or other known stripper, the conductive material can be deposited by any conventional deposition process, such as a chemical vapor deposition (CVD) process. Prior to forming the next layer, any residual material on the surface of the insulator material can be removed by a conventional chemical mechanical polishing (CMP) process, and then the nitride material 30 can be optionally deposited. This process can continue to form the desired number of layers of wiring 28. Thus, although Figure 2 Three layers of wiring 28 are shown, although any number of wiring layers are contemplated herein depending on design parameters (eg, coupling capacitance, desired voltage at the gate oxide, etc.).

[0025] In an embodiment, Figure 3 As shown, the floating gate voltage (fg) is controlled by capacitive coupling with the interconnect structure 26 and the input control gate (Cg). The coupling ratio can be designed by appropriate selection of the BEOL capacitor 24 (MOM or APMOM) (e.g., the pitch, number and size of the different wirings), where the initial charge in the floating gate voltage is drained by the final annealing (e.g., 400° C.) in the BEOL structure. For example, the capacitive coupling is controlled by various terminals (e.g., wiring 28) without any effective charge transfer from the gate structure 12 (e.g., floating gate) to the substrate 14 or wiring 28 in contact with the gate electrode (e.g., polysilicon) 18 through the dielectric (i.e., tunneling). In this way, the V of the device is modulated by the amount of charge accumulated in the floating gate 12 by means of capacitive coupling. th Furthermore, by controlling the voltage division through precise capacitive coupling using the BEOL capacitors 24, higher input voltages (eg, 25V / 30V) can now be achieved.

[0026] Figure 4 A top view of a voltage divider stacked on a gate structure according to aspects of the present disclosure is shown. The voltage divider 24 (e.g., a BEOL capacitor) includes a plurality of wirings 28 configured as fingers. The BEOL capacitor 24 is also shown as being vertically stacked on the gate structure 12, e.g., stacked above the gate electrode, and having the same or smaller footprint than the gate structure 12. In addition, the BEOL capacitor 24 includes two degrees of freedom: (i) the spacing between horizontal metal lines and the thickness of the metal lines themselves; and (ii) the number of metal layers.

[0027] Table 1 below provides examples of different applications for implementing the BEOL capacitors described herein, such as input voltages of 25V and 30V.

[0028] Table 1

[0029]

[0030] Figures 5 to 7 A graph comparing the examples in Table 1 (eg, gate dielectric thickness is The gate device is combined with the BEOL capacitor described in the present disclosure). More specifically, in Figure 5 In the graph shown, the X-axis represents input voltage (V) and the Y-axis represents floating gate voltage (V). As shown in the graph, each of the examples "B" and "C" shown in Table 1 and the conventional device "A" provide a floating gate voltage of approximately 20 V. This indicates that the size and utilization of the capacitor layout shown in the above examples will produce the desired gate voltage at the HV transistor (e.g., the gate oxide 16 of the device 12).

[0031] Figure 6 and7 , respectively, a graph in which the X-axis represents the input voltage (V) and the Y-axis represents the drain current (A / μm). Figure 6 As shown in the graph of , each of the examples "B" and "C" shown in Table 1 and the conventional device "A" have similar switching characteristics. Figure 7 As shown, each of the examples "B" and "C" shown in Table 1 and the conventional device "A" have similar drain currents. Therefore, this indicates that the Idsat of the examples "B" and "C" has almost no change relative to the conventional device "A".

[0032] The floating gate device can be utilized in system-on-chip (SoC) technology. It should be understood by those skilled in the art that SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, SoC consumes much less power and occupies much less area than multi-chip designs with equivalent functions. As a result, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.

[0033] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0034] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a floating gate structure including a gate dielectric material and a gate electrode; an inter-level dielectric material located above the floating gate structure; a vertically stacked capacitor located in the inter-level dielectric material and located above the gate electrode and electrically connected to the gate electrode, wherein the vertically stacked capacitor comprises a plurality of vertically stacked wiring layers, the plurality of wiring layers being separated by a nitride material layer between two adjacent wiring layers, each of the plurality of wiring layers comprising a plurality of fingers separated by the inter-level dielectric material; an interconnect structure disposed in the inter-level dielectric material and connecting the vertically stacked capacitor to the floating gate structure; as well as The raised source region and drain region are located on the side of the floating gate structure and on the semiconductor substrate; a sidewall spacer disposed on the sidewall of the floating gate structure and separating the floating gate structure from the raised source and drain regions, wherein the plurality of wiring layers of the vertically stacked capacitor and the interconnect structure connecting a lowermost wiring layer of the plurality of wiring layers to the gate electrode are confined within an edge of the gate electrode.

2. The semiconductor structure according to claim 1, wherein: The thickness of the gate dielectric material is or greater, and a ratio of a thickness of the gate dielectric material to a thickness of a back-end-of-line dielectric material is 1:1 to 1:

4.

3. The semiconductor structure according to claim 1, wherein: The vertically stacked capacitor includes a control gate voltage and a floating gate voltage applied through the vertically stacked capacitor.

4. The semiconductor structure according to claim 3, wherein: The vertically stacked capacitors provide capacitive coupling controlled by various wiring of the vertically stacked capacitors, which causes charge transfer from the floating gate structure to the substrate or terminal in contact with the gate electrode.

5. The semiconductor structure according to claim 1, wherein: The vertically stacked capacitors are metal-oxide-metal MOM capacitors.

6. The semiconductor structure according to claim 1, wherein: The vertically stacked capacitors are alternating polarity metal-oxide-metal APMOM capacitors, which include wiring on the same wiring level that alternates between positive and negative.

7. A semiconductor structure comprising: Semiconductor substrate; a floating gate structure located on the semiconductor substrate and comprising a gate dielectric material and a gate electrode; an inter-level dielectric material located above the floating gate structure; a vertically stacked capacitor located in the inter-level dielectric material and above the floating gate structure and confined within an edge of the gate electrode, wherein the vertically stacked capacitor comprises a plurality of vertically stacked wiring layers, the plurality of wiring layers being separated by a nitride material layer between two adjacent wiring layers, each of the plurality of wiring layers comprising a plurality of fingers separated by the inter-level dielectric material; an elevated source region and a drain region, located on the semiconductor substrate and adjacent to the floating gate structure; a sidewall spacer located on the sidewalls of the floating gate structure and separating the floating gate structure from the elevated source and drain regions; as well as An interconnect structure is located in the inter-level dielectric material and connects a lowermost wiring layer of the plurality of wiring layers of the vertically stacked capacitor to the floating gate structure.

8. The semiconductor structure according to claim 7, wherein: The thickness of the gate dielectric material is or greater, and a ratio of a thickness of the gate dielectric material to a thickness of a back-end-of-line dielectric material is 1:1 to 1:

4.

9. The semiconductor structure according to claim 7, wherein: The vertically stacked capacitor includes a control gate voltage and a floating gate voltage applied through the vertically stacked capacitor.

10. The semiconductor structure according to claim 7, wherein: The vertically stacked capacitors provide capacitive coupling controlled by various wiring of the vertically stacked capacitors, which causes charge transfer from the floating gate structure to the substrate or terminal in contact with the gate electrode.

11. The semiconductor structure according to claim 7, wherein: The vertically stacked capacitors are metal-oxide-metal capacitors.

12. The structure according to claim 7, wherein: The vertically stacked capacitors are alternating polarity metal-oxide-metal capacitors that include wiring on the same wiring level that alternates between positive and negative.

13. A method for manufacturing a semiconductor structure, comprising: forming a floating gate structure on a semiconductor substrate; forming an inter-level dielectric material above the floating gate structure; forming a capacitor to be located vertically above and electrically connected to the floating gate structure, wherein the capacitor comprises a plurality of wiring layers stacked vertically, the plurality of wiring layers being separated by a nitride material layer between two adjacent wiring layers, each of the plurality of wiring layers comprising a plurality of fingers separated by the inter-level dielectric material; forming an interconnect structure in the inter-level dielectric material, the interconnect structure connecting a lowermost wiring layer of the plurality of wiring layers of the capacitor to the floating gate structure; forming a raised source region and a drain region, which are located on the side of the floating gate structure and on the semiconductor substrate; The plurality of wiring layers and the interconnect structure of the capacitor are confined within an edge of a gate electrode of the floating gate structure.

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