An adaptive control circuit and a control method

Abstract

The present invention provides an adaptive control circuit and a control method, which are applied to a synchronous rectification circuit. The control method includes: detecting the drain-source voltage after the minimum conduction time of the synchronous rectifier tube in the synchronous rectification circuit ends within the current switching period, and adjusting the minimum conduction time of the synchronous rectifier tube in the next switching period according to the detected drain-source voltage of the synchronous rectifier tube. So that the synchronous rectifier tube adopts a small minimum conduction time when the duration of the interference signal is small; and adopts a long minimum conduction time when the duration of the interference signal is long.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and more particularly, to an adaptive control circuit and a control method. Background Art

[0002] Synchronous rectification is a method that uses a power MOSFET with a low on-resistance to replace a rectifier diode to reduce rectification losses. The power MOSFET belongs to a voltage-controlled device, and its volt-ampere characteristic is linear when it is conducting. When using a power MOSFET as a rectifier, it is required that the gate voltage must be synchronized with the phase of the rectified voltage to complete the rectification function.

[0003] In most existing designs, when the synchronous rectification chip detects that the drain-source voltage of the synchronous rectification MOSFET is negative, the MOSFET is turned on, and when the synchronous rectification chip detects that the current in the channel of the synchronous rectification MOSFET is close to 0, the MOSFET is turned off. In practical applications, due to the presence of large interference signals during the switching operation, it is easy to cause misoperation.

[0004] As Figure 1a shown, when the circuit is operating at heavy load, the interference signal caused by the switching operation has a long duration, which will cause the waveform of the drain-source voltage Vdsen of the synchronous rectification to resonate to V ON-MIN after the minimum conduction time T OFF_TH ends, resulting in the premature turn-off of the synchronous rectification controller; as Figure 1b shown, when the circuit is operating at light load, the interference signal caused by the switching operation has a short duration, and the minimum conduction time T ON-MIN is longer than the time for the secondary side to freewheel to zero, which will cause the drain-source voltage Vdsen of the synchronous rectification to be greater than 0V after T ON-MIN ends, resulting in the late turn-off of the synchronous rectification controller, causing a negative current, which may cause abnormal operation or circuit damage. Summary of the Invention

[0005] In view of this, the present invention proposes an adaptive control circuit and a control method to solve the existing problems.

[0006] According to a first aspect of the present invention, an adaptive control method is proposed, which is applied to a synchronous rectification circuit, and is characterized in that it includes: detecting the drain-source voltage of the synchronous rectification tube after the end of the minimum conduction time of the synchronous rectification circuit in the current switching cycle, and adjusting the minimum conduction time of the synchronous rectification tube in the next switching cycle according to the detected drain-source voltage of the synchronous rectification tube.

[0007] Preferably, adjusting the minimum conduction time of the next switching cycle of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum conduction time of the next switching cycle.

[0008] Preferably, adjusting the minimum conduction time of the next switching cycle of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, decreasing the minimum conduction time of the next switching cycle.

[0009] Preferably, adjusting the minimum conduction time of the next switching cycle of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum conduction time of the next switching cycle.

[0010] Preferably, when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjusting the minimum conduction time of the next switching cycle to increase the second time from the minimum conduction time of the current switching cycle; and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum conduction time of the next switching cycle to decrease the second time from the minimum conduction time of the current switching cycle.

[0011] Preferably, detecting the drain-source voltage at the end of the first time delay from the end time of the minimum conduction time of the synchronous rectifier tube within the current switching cycle.

[0012] Preferably, the first time is set to be not less than the sum of the logic delay time inside the chip, the drive pull-down time, and the turn-off time of the synchronous rectifier tube.

[0013] Preferably, the first time is set to be not less than the sum of the logic delay time inside the chip, the drive pull-down time, the turn-off time of the synchronous rectifier tube, and the charging time of the parasitic capacitance of the synchronous rectifier tube.

[0014] Preferably, the first threshold voltage is determined by the threshold voltage at which the body diode of the synchronous rectifier tube conducts.

[0015] Preferably, the first threshold voltage is set to be less than zero.

[0016] Preferably, the second threshold voltage is significantly greater than the drain-source voltage at the turn-off moment of the synchronous rectifier tube.

[0017] According to a second aspect of the present invention, an adaptive control circuit is provided, which is applied to a synchronous rectification circuit and is characterized by comprising: a voltage detection circuit configured to detect the drain-source voltage of the synchronous rectifier tube after the end of the minimum conduction time within the current switching cycle of the synchronous rectification circuit; and an adjustment circuit configured to adjust the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the drain-source voltage of the synchronous rectifier tube.

[0018] Preferably, adjusting the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is not greater than a first threshold voltage, increasing the minimum conduction time of the next switching cycle.

[0019] Preferably, adjusting the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is not less than a second threshold voltage, decreasing the minimum conduction time of the next switching cycle.

[0020] Preferably, adjusting the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the drain-source voltage of the synchronous rectifier tube includes: when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum conduction time of the next switching cycle.

[0021] Preferably, when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjusting the minimum conduction time of the next switching cycle to increase a second time based on the minimum conduction time of the current switching cycle; and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum conduction time of the next switching cycle to decrease a second time based on the minimum conduction time of the current switching cycle.

[0022] Preferably, the adjustment circuit includes: a comparison circuit that inputs the drain-source voltage of the synchronous rectifier tube and a reference voltage and outputs a comparison signal; a logic circuit that receives the comparison signal and outputs a counting instruction; and a minimum conduction time generation circuit that receives the counting instruction and outputs a signal representing the minimum conduction time of the synchronous rectifier tube in the next switching cycle.

[0023] Preferably, the logic circuit outputs the counting instruction according to the comparison signal at the end of a first time delay starting from the end moment of the minimum conduction time of the current switching cycle.

[0024] Preferably, the comparison circuit includes: a first comparison circuit, whose positive input terminal receives a first threshold voltage, negative input terminal receives the drain-source voltage of the synchronous rectifier tube, and outputs a first comparison signal; and a second comparison circuit, whose positive input terminal receives the drain-source voltage of the synchronous rectifier tube, negative input terminal receives a second threshold voltage, and outputs a second comparison signal.

[0025] Preferably, the logic circuit includes: an exclusive OR gate, whose input terminals receive the first comparison signal and the second comparison signal; an inverter, whose input terminal receives a first time signal; and a trigger circuit, whose D terminal receives the output signal of the exclusive OR gate, reset terminal receives the minimum conduction time signal of the current switching cycle, and clock terminal receives the output signal of the inverter.

[0026] Preferably, the minimum conduction time generation circuit includes: an up-down counter, which receives the first comparison signal and the output signal of the trigger circuit, and outputs a numerical signal; a digital-to-analog conversion circuit, which receives the numerical signal and outputs an analog signal corresponding to the numerical signal after digital-to-analog conversion, wherein the up-down counter receives the first comparison signal and the output signal of the trigger as the counting instruction.

[0027] Preferably, the first time is set to be not less than the sum of the logic delay time inside the chip, the drive pull-down time and the turn-off time of the synchronous rectifier tube.

[0028] Preferably, the first time is set to be not less than the sum of the logic delay time inside the chip, the drive pull-down time, the turn-off time of the synchronous rectifier tube and the charging time of the parasitic capacitance of the synchronous rectifier tube.

[0029] Preferably, the first threshold voltage is determined by the threshold voltage at which the body diode of the synchronous rectifier tube conducts.

[0030] Preferably, the first threshold voltage is set to be less than zero.

[0031] Preferably, the second threshold voltage is significantly greater than the drain-source voltage at the turn-off moment of the synchronous rectifier tube.

[0032] Preferably, the second threshold voltage is set to be greater than zero.

[0033] The present invention provides an adaptive control circuit and a control method, which are applied to a synchronous rectification circuit. The control method includes: detecting the drain-source voltage after the minimum conduction time of the synchronous rectifier in the current switching period ends, and adjusting the minimum conduction time of the synchronous rectifier in the next switching period according to the detected drain-source voltage of the synchronous rectifier. Thus, when the duration of the interference signal is small, the synchronous rectifier adopts a small minimum conduction time; when the duration of the interference signal is long, the synchronous rectifier adopts a long minimum conduction time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0035] Figure 1a is the working waveform of the synchronous rectification circuit in the prior art under heavy load;

[0036] Figure 1b is the working waveform of the synchronous rectification circuit in the prior art under light load;

[0037] Figure 2 is the block diagram of the adaptive control circuit according to the embodiment of the present invention;

[0038] Figure 3 is the circuit structure diagram of the adjustment circuit according to the embodiment of the present invention;

[0039] Figure 4a is the first working waveform of the adaptive control circuit according to the embodiment of the present invention;

[0040] Figure 4b is the second working waveform of the adaptive control circuit according to the embodiment of the present invention;

[0041] Figure 5 is the flowchart of the adaptive control method according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The following is a description of the present invention based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. In order to avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0043] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0044] Meanwhile, it should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one component or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or when an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means there are no intermediate elements between the two.

[0045] Unless the context clearly requires otherwise, the words such as "comprising", "including" and the like in the whole specification and claims shall be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0046] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] Figure 2 It is a block diagram of the adaptive control circuit according to an embodiment of the present invention. As Figure 2 shown, the adaptive control circuit 20 includes a voltage detection circuit 21 and an adjustment circuit 22. In the present invention, the adaptive control circuit 20 is applied to a synchronous rectification circuit. Among them, the voltage detection circuit 21 is used to detect the drain-source voltage Vds after the end of the minimum conduction time of the synchronous rectification tube M2 in the synchronous rectification circuit during the current switching cycle. It should be understood that any circuit capable of detecting the drain-source voltage is within the protection scope of the present invention. The adjustment circuit 22 is used to adjust the minimum conduction time of the synchronous rectification tube M2 in the next switching cycle according to the drain-source voltage Vds of the synchronous rectification tube M2. The synchronous rectification circuit described in the present invention can be any type of rectification circuit such as a full-wave rectification circuit, a full-bridge rectification circuit, a half-wave rectification circuit, a voltage-doubling rectification circuit, etc., and the present invention does not limit this.

[0048] Specifically, the voltage detection circuit 21 is used to detect the drain-source voltage Vds starting from the end of the minimum conduction time of the synchronous rectification tube M2 in the synchronous rectification circuit during the current switching cycle and delaying for a first time T AThe drain-source voltage Vds at the end moment. When the drain-source voltage Vds of the synchronous rectifier tube M2 detected by the voltage detection circuit 21 is not greater than the first threshold voltage V1, increase the minimum conduction time of the synchronous rectifier tube M2 in the next switching cycle; when the drain-source voltage Vds of the synchronous rectifier tube M2 detected by the voltage detection circuit 21 is not less than the second threshold voltage V2, decrease the minimum conduction time of the synchronous rectifier tube M2 in the next switching cycle; when the drain-source voltage of the synchronous rectifier tube detected by the voltage detection circuit 21 is greater than the first threshold voltage V1 and less than the second threshold voltage V2, do not change the minimum conduction time of the synchronous rectifier tube M2 in the next switching cycle. Further, when the detected drain-source voltage of the synchronous rectifier tube M2 is not greater than the first threshold voltage V1, adjust the minimum conduction time of the next switching cycle to be the minimum conduction time of the current switching cycle plus the second time T B ; and when the detected drain-source voltage of the synchronous rectifier tube M2 is not less than the second threshold voltage V2, adjust the minimum conduction time of the next switching cycle to be the minimum conduction time of the current switching cycle minus the second time T B .

[0049] In the present invention, the first time T A is the sampling delay time of the voltage Vds after the minimum conduction time of the synchronous rectifier tube. In this embodiment, the first time T A is set to be not less than the sum of the logic delay time inside the chip, the driving pull-down time, and the turn-off time of the synchronous rectifier tube. If it is necessary to consider that after the synchronous rectifier tube is turned off, the leakage inductance energy charges the parasitic capacitance Cds of the synchronous rectifier tube and makes it rise, then the first time T A is set to be not less than the sum of the logic delay time inside the chip, the driving pull-down time, the turn-off time of the synchronous rectifier tube, and the charging time of the parasitic capacitance of the synchronous rectifier tube. The second time T B is the adjustment amount of the minimum conduction time of the synchronous rectifier tube, and its value is greater than zero and can be set according to the parameters of the synchronous rectification circuit. In this implementation, the second time T BIt can be set to 400 - 600 ns, preferably set to 500 ns. The first threshold voltage V1 is determined by the threshold voltage at which the body diode of the synchronous rectifier conducts. In this embodiment, when the threshold voltage at which the body diode conducts is positive, the first threshold voltage V1 is set to be less than the threshold voltage at which the body diode conducts and less than zero; when the threshold voltage at which the body diode conducts is negative, the first threshold voltage V1 is set to be greater than the threshold voltage at which the body diode conducts and less than zero. For example, this value is generally set to -200 mV to -500 mV, preferably set to -300 mV. The second threshold voltage V2 is set to be significantly greater than the drain-source voltage at the turn-off moment of the synchronous rectifier, and the second threshold voltage V2 is set to be greater than 0. In this implementation, this value is generally set to 2V.

[0050] Figure 3 is the circuit structure diagram of the adjustment circuit according to the embodiment of the present invention. As Figure 3 shown, the adjustment circuit 22 includes a comparison circuit 31, a logic circuit 32, and a minimum conduction time generation circuit 33. The comparison circuit 31 is configured to receive the drain-source voltage Vds of the synchronous rectifier M2 and a reference voltage, and output a comparison signal. The logic circuit 32 is configured to receive the comparison signal and output a counting instruction. The logic circuit 32 is configured to output the counting instruction according to the comparison signal after delaying for a first time when the minimum conduction time of the current cycle ends. The minimum conduction time generation circuit 33 receives the counting instruction and outputs a signal characterizing the minimum conduction time of the next switching cycle of the synchronous rectifier according to the counting instruction.

[0051] Specifically, the comparison circuit 31 includes a first comparison circuit CMP1 and a second comparison circuit CMP2. The positive input terminal of the first comparison circuit CMP1 receives the first threshold voltage V1, the negative input terminal receives the drain-source voltage Vds of the synchronous rectifier, and outputs a first comparison signal Vc1; the positive input terminal of the second comparison circuit CMP2 receives the drain-source voltage Vds of the synchronous rectifier, the negative input terminal receives the second threshold voltage V2, and outputs a second comparison signal Vc2. When the drain-source voltage Vds is less than the first threshold voltage V1, the output first comparison signal Vc1 is at a high level; otherwise, the output first comparison signal Vc1 is at a low level. When the drain-source voltage Vds is greater than the second threshold voltage V2, the output second comparison signal Vc2 is at a high level; otherwise, the output second comparison signal Vc2 is at a low level.

[0052] The logic circuit 32 includes an exclusive OR gate U1, an inverter U2, and a trigger circuit U3. The input terminals of the exclusive OR gate U1 receive the first comparison signal Vc1 and the second comparison signal Vc2; the input terminal of the inverter U2 receives the first time signal V characterizing the first time TATA , the first time signal V TA is valid from the end of the minimum conduction time to the end of the first time TA; the D terminal of the trigger circuit U3 receives the output signal of the exclusive-OR gate U1, and the reset terminal reset receives the minimum conduction time signal V of the current switching cycle TON-MIN(N) , and the clock terminal clk receives the output signal of the inverter U2. When the drain-source voltage Vds is less than the first threshold voltage V1 or when the drain-source voltage Vds is greater than the second threshold voltage V2, the output signal of the exclusive-OR gate U1 is high level; when the drain-source voltage Vds is greater than the first threshold voltage V1 and less than the second threshold voltage V2, the output signal of the exclusive-OR gate U1 is low level. When the D terminal of the flip-flop receives a high level, its reset terminal reset is at a low level, and the clock terminal clk is at a rising edge, the output signal of the trigger circuit is high level; when the D terminal of the flip-flop receives a low level, the output signal of the trigger circuit is low level.

[0053] The minimum conduction time generation circuit 33 includes an up-down counter U4 and a digital-to-analog conversion circuit U5. Among them, the up-down counter U4 receives the first comparison signal VC1 and the output signal of the trigger circuit U3, and outputs a numerical signal. The digital-to-analog conversion circuit U5 receives the numerical signal, and after digital-to-analog conversion, outputs an analog signal corresponding to the numerical signal. Among them, the up-down counter receives the first comparison signal and the output signal of the flip-flop as the counting instruction, and the analog signal represents the minimum conduction time of the synchronous rectifier in the next switching cycle. When the first comparison signal Vc1 received by the up-down counter U4 is high level and the output signal of the trigger circuit U3 is also high level, the counting instruction is 1, and the up-down counter U4 increments by 1; when the first comparison signal Vc1 is low level and the output signal of the trigger circuit U3 is high level, the counting instruction is 0, and the up-down counter U4 decrements by 1; when the first comparison signal CMP1 is low level and the output signal of the trigger circuit is also low level, the up-down counter U4 neither increments nor decrements. Among them, the numerical signal output by the up-down counter U4 is a binary numerical signal, and from small to large, they are (0,0,0) < (1,0,0) < (1,1,0) < (1,1,1). If the numerical signal output by the up-down counter U4 is (0,0,0), after being converted by the digital-to-analog conversion circuit U5, the output analog signal voltage is the smallest, and its corresponding T ON-MIN is the smallest; if the numerical signal output by the up-down counter U4 is (1,1,1), after being converted by the digital-to-analog conversion circuit U5, the output analog signal voltage is the largest, and its corresponding T ON-MINis the largest. The present invention adopts a scheme of a D flip-flop cascaded with an up-down counter. Of course, in other embodiments, a pure digital scheme can also be used, which is not limited herein.

[0054] Figure 4a is the first working waveform of the adaptive control circuit according to the embodiment of the present invention. As Figure 4a shown, when the synchronous rectification circuit operates at light load, the minimum on-time of the current switching cycle is much greater than the duration of the interference signal.

[0055] The moment t1 is the end moment of the minimum on-time of the synchronous rectification tube M2 within the current switching cycle; the moment t2 is the moment after delaying the first time T after the end of the minimum on-time of the synchronous rectification tube M2 within the current switching cycle. Detect the drain-source voltage Vds of the synchronous rectification tube M2 at the moment t2. If the drain-source voltage Vds is greater than the second threshold voltage V2, the first comparison signal Vc1 output by the first comparison circuit is at a low level, the second comparison signal output by the second comparison circuit is at a high level, and the exclusive-OR gate U1 outputs a high level. During the time period from t1 to t2, the minimum on-time signal V A is at a low level, that is, the reset terminal reset of the trigger circuit is zero. The first time signal V TON-MIN(N) is a pulse, then the output signal V TA of the inverter U2 is at a low level, and at the moment t2, V U2 rises to a high level, which is a rising edge. At the moment t2, the D terminal of the flip-flop U3 receives the output signal of the exclusive-OR gate, that is, a high level, the set terminal reset is zero, and the clock terminal clk receives the output signal V U2 of the inverter U2 as a rising edge, then the output signal V U2 of the flip-flop U3 is at a high level; the up-down counter U4 receives the first comparison signal Vc1 and the output signal V U3 of the flip-flop U3, and outputs a low level V U3 , that is, the up-down counter decrements by 1, then the minimum on-time of the next switching cycle is reduced. U4

[0056] In the next switching cycle, detect the drain-source voltage Vds at the moment t4 after delaying the first time T after the end (moment t3) of the adjusted minimum on-time T ON-MIN(N+1) . If the drain-source voltage Vds is greater than the first threshold voltage V1 and less than the second threshold voltage V2, the first comparison signal Vc1 output by the first comparison circuit CMP1 is at a low level, the second comparison signal output by the second comparison circuit is at a low level, and the exclusive-OR gate U1 outputs a low level. During the time period from t3 to t4, the minimum on-time signal V A TON-MIN(N+1)is at a low level; at time t4, the output signal V of the inverter U2 U2 rises to a high level, which is a rising edge; at time t4, the D terminal of the flip-flop U3 receives the output signal of the exclusive-OR gate U1, which is a low level, then the output V of the flip-flop U3 is at a low level. The first comparison signal Vc1 received by the up / down counter and the output signal V of the flip-flop U3 are both at a low level, then the up / down counter neither increases nor decreases, and does not change the minimum conduction time of the next next switching period.

[0057] Figure 4b is the second working waveform of the adaptive control circuit according to the embodiment of the present invention. As Figure 4b shown, when the synchronous rectification circuit works in heavy load, the minimum conduction time of the current switching period is less than the interference signal duration.

[0058] Time t1 is the end time of the minimum conduction time of the synchronous rectifier M2 within the current switching period; time t2 is the time after delaying the first time T after the end of the minimum conduction time of the synchronous rectifier M2 within the current switching period. A At time t2, the drain-source voltage Vds of the synchronous rectifier M2 is detected. If the drain-source voltage Vds is less than the first threshold voltage V1, the first comparison signal Vc1 output by the first comparison circuit is at a high level, the second comparison signal output by the second comparison circuit is at a low level, and the exclusive-OR gate U1 outputs a high level. During the time t1 - t2, the minimum conduction time signal V TON-MIN(N) is at a low level, that is, the reset terminal reset of the trigger circuit is zero. The first time signal V TA is a pulse, then the output signal V of the inverter U2 U2 is at a low level, and at time t2, V U2 rises to a high level, which is a rising edge. At time t2, the D terminal of the flip-flop U3 receives the output signal of the exclusive-OR gate, which is a high level, the set terminal reset is zero, and the clock terminal clk receives the output signal V of the inverter U2 U2 as a rising edge, then the output signal V of the flip-flop U3 U3 is at a high level; the up / down counter U4 receives the first comparison signal Vc1 and the output signal V of the flip-flop U3 U3 and outputs a high level V U4 , that is, the up / down counter increments by 1, then increases the minimum conduction time of the next switching period.

[0059] In the next switching period, it is detected that after the adjusted minimum conduction time ends, it is delayed by the first time T AThe drain-source voltage Vds after that, where the drain-source voltage Vds is greater than the first threshold voltage V1 and less than the second threshold voltage V2. As described above, the minimum conduction time of the next-next switching period is not changed.

[0060] The present invention also discloses a synchronous rectification control method, which is applied to a synchronous rectification circuit and includes: detecting the drain-source voltage after the end of the minimum conduction time of the synchronous rectification tube in the current switching period, and adjusting the minimum conduction time of the synchronous rectification tube in the next switching period according to the detected drain-source voltage of the synchronous rectification tube.

[0061] Figure 5 It is a flowchart of the adaptive control method according to an embodiment of the present invention and includes:

[0062] Step 51: Detect the drain-source voltage Vds at a moment after the end of the minimum conduction time of the synchronous rectification tube in the current switching period and after a first delay time;

[0063] Step 52: Determine the magnitudes of the drain-source voltage Vds, the first threshold voltage, and the second threshold voltage;

[0064] Step 53a: If the drain-source voltage Vds is not greater than the first threshold voltage, increase the minimum conduction time of the next switching period; specifically, adjust the minimum conduction time of the next switching period to be the minimum conduction time of the current switching period plus a second time;

[0065] Step 53b: If the drain-source voltage Vds is not less than the second threshold voltage, decrease the minimum conduction time of the next switching period; specifically, adjust the minimum conduction time of the next switching period to be the minimum conduction time of the current switching period minus a second time;

[0066] Step 53c: If the drain-source voltage Vds is greater than the first threshold voltage and less than the second threshold voltage, do not change the minimum conduction time of the next switching period.

[0067] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art in the relevant technical field can make good use of the present invention and its modifications based on it. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. An adaptive control method, applied to a synchronous rectification circuit, characterized in that, Including: Detecting the drain-source voltage after the minimum conduction time of the synchronous rectifier tube in the synchronous rectifier circuit ends within the current switching cycle, and Adjusting the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the comparison result of the detected drain-source voltage of the synchronous rectifier tube with the first threshold voltage and the second threshold voltage; When the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum conduction time of the next switching cycle; when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, decreasing the minimum conduction time of the next switching cycle; when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum conduction time of the next switching cycle; Wherein, the first threshold voltage is determined by the threshold voltage at which the body diode of the synchronous rectifier tube conducts, and the second threshold voltage is significantly greater than the drain-source voltage at the turn-off moment of the synchronous rectifier tube.

2. The method according to claim 1, wherein When the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjusting the minimum conduction time of the next switching cycle to increase the second time compared to the minimum conduction time of the current switching cycle; And When the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum conduction time of the next switching cycle to decrease the second time compared to the minimum conduction time of the current switching cycle.

3. The method according to claim 1, wherein Detecting the drain-source voltage at the end of the first time delay from the end of the minimum conduction time of the synchronous rectifier tube within the current switching cycle.

4. The method according to claim 3, characterized in that, The first time is set to be not less than the sum of the internal logic delay time of the chip, the drive pull-down time, and the turn-off time of the synchronous rectifier tube.

5. The method according to claim 3, characterized in that, The first time is set to be not less than the sum of the internal logic delay time of the chip, the drive pull-down time, the turn-off time of the synchronous rectifier tube, and the charging time of the parasitic capacitance of the synchronous rectifier tube.

6. The method according to claim 1, characterized in that, The first threshold voltage is set to be less than zero.

7. An adaptive control circuit is applied to a synchronous rectification circuit, and is characterized in that, Including: A voltage detection circuit configured to detect the drain-source voltage after the minimum conduction time of the synchronous rectifier tube in the synchronous rectifier circuit ends within the current switching cycle; And An adjustment circuit configured to adjust the minimum conduction time of the synchronous rectifier tube in the next switching cycle according to the comparison result of the drain-source voltage of the synchronous rectifier tube with the first threshold voltage and the second threshold voltage; When the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum conduction time of the next switching cycle; when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, decreasing the minimum conduction time of the next switching cycle; when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum conduction time of the next switching cycle; Wherein, the first threshold voltage is determined by the threshold voltage at which the body diode of the synchronous rectifier tube conducts, and the second threshold voltage is significantly greater than the drain-source voltage at the turn-off moment of the synchronous rectifier tube.

8. The adaptive control circuit according to claim 7, wherein When the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjust the minimum conduction time of the next switching cycle to increase by a second time based on the minimum conduction time of the current switching cycle; And When the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjust the minimum conduction time of the next switching cycle to decrease by a second time based on the minimum conduction time of the current switching cycle.

9. The adaptive control circuit according to claim 7, wherein The adjustment circuit includes: A comparison circuit that inputs the drain-source voltage of the synchronous rectifier tube, the first threshold voltage, and the second threshold voltage, and outputs a comparison signal; A logic circuit that receives the comparison signal and outputs a counting instruction; and A minimum conduction time generation circuit that receives the counting instruction and outputs a signal representing the minimum conduction time of the next switching cycle of the synchronous rectifier tube.

10. The adaptive control circuit according to claim 9, characterized in that, The logic circuit starts from the end of the minimum conduction time of the current switching cycle, and after a first delay time, outputs the counting instruction according to the comparison signal.

11. The adaptive control circuit according to claim 9, characterized in that, The comparison circuit includes: A first comparison circuit whose positive input terminal receives the first threshold voltage, negative input terminal receives the drain-source voltage of the synchronous rectifier tube, and outputs a first comparison signal; and A second comparison circuit whose positive input terminal receives the drain-source voltage of the synchronous rectifier tube, negative input terminal receives the second threshold voltage, and outputs a second comparison signal.

12. The adaptive control circuit according to claim 11, wherein The logic circuit includes: An exclusive-OR gate whose input terminals receive the first comparison signal and the second comparison signal; An inverter whose input terminal receives a first time signal; and A trigger circuit whose D terminal receives the output signal of the exclusive-OR gate, reset terminal receives the minimum conduction time signal of the current switching cycle, and clock terminal receives the output signal of the inverter.

13. The adaptive control circuit according to claim 12, wherein The minimum conduction time generation circuit includes: An up-down counter that receives the first comparison signal and the output signal of the trigger circuit, and outputs a numerical signal; A digital-to-analog conversion circuit that receives the numerical signal and outputs an analog signal corresponding to the numerical signal after digital-to-analog conversion, wherein the up-down counter receives the first comparison signal and the output signal of the trigger circuit as the counting instruction.

14. The adaptive control circuit according to claim 10, characterized in that, The first time is set to be not less than the sum of the internal logic delay time of the chip, the drive pull-down time, and the turn-off time of the synchronous rectifier tube.

15. The adaptive control circuit according to claim 10, characterized in that, The first time is set to be not less than the sum of the internal logic delay time of the chip, the drive pull-down time, the turn-off time of the synchronous rectifier tube, and the charging time of the parasitic capacitance of the synchronous rectifier tube.

16. The adaptive control circuit according to claim 7, wherein The first threshold voltage is set to be less than zero.

17. The adaptive control circuit according to claim 7, wherein The second threshold voltage is set to be greater than zero.

Images