Σ-Δ Modulation Module and Analog-to-Digital Converter

Abstract

The present invention provides a Σ-Δ modulation module and an analog-to-digital converter, comprising: a first-stage modulator, a second-stage modulator, and an interconnection gain coefficient adjustment unit connected between the first-stage and second-stage modulators; the multi-bit quantizer in the second-stage modulator includes: a fully differential analog-to-digital conversion unit that generates a differential-form reference signal, a differential input comparison unit that compares the differential input signal with each reference signal to obtain a corresponding digital signal, a thermometer coding unit that encodes the digital signal output by the differential input comparison unit into a thermometer code, and a reverse gain coefficient embedding unit that converts the thermometer code into a multi-bit quantizer level code normalized between the positive and negative values of the reverse gain coefficient. The present invention solves the constraint that the gain coefficient is a power of 2, can use any gain coefficient, and has higher flexibility; it avoids using an intermediate rising quantizer and does not require additional digital hardware circuits to set the reverse gain coefficient, simplifies the circuit structure, and reduces the design difficulty.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to a Σ-Δ modulation module and an analog-to-digital converter. Background Art

[0002] In recent years, Σ-Δ ADCs have been increasingly widely used in the field of manufacturing related high-precision instruments. A Σ-Δ ADC includes a first-order modulation unit, a second-order modulation unit, or a modulator of more orders. For stability considerations, a high-order modulation unit is generally formed by cascading multiple low-order modulation units (a first-order modulation unit or a second-order modulation unit) because a low-order modulation unit is absolutely stable. The cascading of multiple low-order modulation units requires a corresponding digital noise cancellation circuit (Digital Noise Cancellation, DNS) to combine the digital outputs of single-stage modulators and send them to the next stage for processing. After combining the digital outputs of each stage via the digital noise cancellation circuit, quantization noise is shaped to the desired order. The design focus of the digital noise cancellation circuit lies in matching the gain coefficient in the analog domain of the modulator so as to completely eliminate unwanted terms before the signal enters the next-stage circuit for further signal processing; the selection of the gain coefficient in the modulator in the analog domain directly affects the setting of the reverse gain coefficient in the digital noise cancellation circuit.

[0003] In the prior art, the gain coefficient of the modulator is usually designed as a power of 2, so that the reverse gain coefficient can be easily implemented in digital hardware because multiplying by 2 is a simple digital operation; if the reverse gain coefficient is not a power of 2, the digital noise cancellation circuit requires a digital multiplier in the form of a multiplier-accumulator (MAC), and the circuit structure becomes complex. If complex hardware structure design is to be avoided, the flexibility will be greatly limited. If the gain coefficient of the modulator is odd, the design problem of the digital noise cancellation circuit will become more complex and more restrictive. And it is reasonable to set the gain coefficient of the modulator to be odd. In most cases, an intermediate-rising quantizer is used in the noise shaping modulator, so that the number of comparators in the quantizer is odd. The intermediate-rising quantizer has no threshold level under the common mode. If it is a 1-bit quantizer, it provides an inherent linear quantizer; in the case of a multi-bit quantizer, the threshold levels (even numbers) are symmetric about the common mode.

[0004] Therefore, how to overcome problems such as the gain coefficient of the modulator being a power of 2, the quantizer needing to use an intermediate-rising quantizer when the gain coefficient is set to be odd, and the complex structure of the digital noise cancellation circuit has become one of the problems that need to be urgently solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a Σ-Δ modulation module and an analog-to-digital converter, which are used to solve the problems of many constraint conditions of the modulator and complex structure of the digital noise cancellation circuit in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a Σ-Δ modulation module, and the Σ-Δ modulation module at least includes:

[0007] A first-stage modulator, a second-stage modulator, and an interconnection gain coefficient adjustment unit connected between the first-stage modulator and the second-stage modulator; wherein, the multi-bit quantizer in the second-stage modulator includes: a fully differential analog-to-digital conversion unit, a differential input comparison unit, a thermometer coding unit, and a reverse gain coefficient embedding unit;

[0008] The fully differential analog-to-digital conversion unit generates a differential-form reference signal corresponding to the number of comparators in the differential input comparison unit;

[0009] The differential input comparison unit is connected to the output end of the fully differential analog-to-digital conversion unit and receives a differential input signal, and is used to compare the differential input signal with each reference signal to obtain a corresponding digital signal;

[0010] The thermometer coding unit is connected to the output end of the differential input comparison unit, and is used to encode the digital signal output by the differential input comparison unit into a thermometer code;

[0011] The reverse gain coefficient embedding unit is connected to the output end of the thermometer coding unit, and is used to convert the thermometer code into a code of the multi-bit quantizer level normalized between the positive and negative values of the reverse gain coefficient based on a normalization factor; the normalization factor is equal to the number of comparators in the differential input comparison unit.

[0012] Optionally, the reverse gain coefficient satisfies:

[0013] D = 1 / (A*B*C)

[0014] Wherein, D is the reverse gain coefficient, A is the first-order input gain coefficient in the first-stage modulator, B is the second-order input gain coefficient in the first-stage modulator, C is the interconnection gain coefficient in the interconnection gain coefficient adjustment unit, the denominator of the second-order input gain coefficient B is the value corresponding to the number of comparators in the differential input comparison unit, and the denominator of the first-order input gain coefficient A is the numerator of the second-order input gain coefficient B.

[0015] More optionally, the fully differential analog-to-digital conversion unit includes a first resistor string and a second resistor string; the first and second ends of the first resistor string and the second resistor string are cross-coupled and connected to a first voltage and a second voltage, and the first voltage and the second voltage are differential signals; the first resistor string and the second resistor string divide the voltage to output corresponding differential reference signals.

[0016] More optionally, the differential input comparison unit includes a plurality of comparators, and each comparator respectively compares the differential input signal with each reference signal and outputs a comparison result; each comparator includes a first comparison module, a second comparison module, first, second, third, and fourth switches, and a latch.

[0017] The positive input terminal of the first comparison module is connected to the positive signal of the differential input signal via the first switch, and the negative input terminal is connected to the corresponding positive reference signal via the second switch; the positive input terminal of the second comparison module is connected to the negative signal of the differential input signal via the third switch, and the negative input terminal is connected to the corresponding negative reference signal via the fourth switch; the control terminals of each switch are connected to a sampling signal; each input terminal of the first comparison module and the second comparison module is respectively connected to a common voltage via a capacitor.

[0018] The latch is connected to the output terminals of the first comparison module and the second comparison module, and latches the comparison results of the first comparison module and the second comparison module.

[0019] More optionally, the number of comparators is set to be odd.

[0020] More optionally, the multi-bit quantizer is a 3-bit quantizer, and the thermometer encoding unit includes eight three-input AND gates.

[0021] The input terminals of the first three-input AND gate are respectively connected to the first bit, the second bit reverse signal and the high level output by the differential input comparison unit, and output the first bit signal of the temperature code; the input terminals of the second three-input AND gate are respectively connected to the second bit, the third bit reverse signal and the first bit forward signal output by the differential input comparison unit, and output the second bit signal of the temperature code; the input terminals of the third three-input AND gate are respectively connected to the third bit reverse signal output by the differential input comparison unit and the first and second bit forward signals, and output the third bit signal of the temperature code; the input terminals of the fourth three-input AND gate are respectively connected to the fourth bit reverse signal output by the differential input comparison unit and the second and third bit forward signals, and output the fourth bit signal of the temperature code; the input terminals of the fifth three-input AND gate are respectively connected to the fifth bit reverse signal output by the differential input comparison unit and the third and fourth bit forward signals, and output the fifth bit signal of the temperature code; the input terminals of the sixth three-input AND gate are respectively connected to the sixth bit reverse signal output by the differential input comparison unit and the fourth and fifth bit forward signals, and output the sixth bit signal of the temperature code; the input terminals of the seventh three-input AND gate are respectively connected to the seventh bit reverse signal output by the differential input comparison unit and the fifth and sixth bit forward signals, and output the seventh bit signal of the temperature code; the input terminals of the eighth three-input AND gate are respectively connected to the sixth and seventh bit forward signals output by the differential input comparison unit and the high level, and output the eighth bit signal of the temperature code.

[0022] More optionally, the reverse gain coefficient embedding unit is one of a two's complement encoding unit, a Gray code encoding unit, a sign-magnitude code encoding unit, an offset binary code encoding unit, and a one's complement encoding unit.

[0023] More optionally, the multi-bit quantizer is a 3-bit quantizer, the reverse gain coefficient embedding unit is a two's complement encoding unit, and the two's complement encoding unit includes three four-input OR gates, an eight-input OR gate, and a buffer;

[0024] The input terminals of the first four-input OR gate are respectively connected to the first, second, third, and fourth bit signals of the temperature code, and output the fifth bit signal of the two's complement; the input terminals of the second four-input OR gate are respectively connected to the third, fourth, seventh, and eighth bit signals of the temperature code, and output the fourth bit signal of the two's complement; the input terminals of the third four-input OR gate are respectively connected to the second, fourth, sixth, and eighth bit signals of the temperature code, and output the third bit signal of the two's complement; the input terminals of the eight-input OR gate are respectively connected to the eight bit signals of the temperature code, and output the second bit signal of the two's complement; the buffer receives a low level and outputs the first bit signal of the two's complement.

[0025] More optionally, the first-stage modulator includes a first input gain coefficient adjustment unit, a first feedback gain coefficient adjustment unit, a first adder, a first integrator, a second input gain coefficient adjustment unit, a second feedback gain coefficient adjustment unit, a second adder, a second integrator, and a single-bit quantizer;

[0026] The input analog signal is connected to the first adder via the first input gain coefficient adjustment unit, the output signal of the single-bit quantizer is connected to the first adder via the first feedback gain coefficient adjustment unit, and the first integrator is connected to the output end of the first adder; the output end of the first integrator is connected to the second adder via the second input gain coefficient adjustment unit, the output signal of the single-bit quantizer is connected to the second adder via the second feedback gain coefficient adjustment unit, and the second integrator is connected to the output end of the second adder; the single-bit quantizer is connected to the output end of the second integrator;

[0027] Wherein, the denominator of the second-order input gain coefficient is the value corresponding to the number of comparators in the multi-bit quantizer, and the denominator of the first-order input gain coefficient is the numerator of the second-order input gain coefficient.

[0028] More optionally, the second-stage modulator includes a third feedback gain coefficient adjustment unit, a third adder, a third integrator, a fourth feedback gain coefficient adjustment unit, a fourth adder, a fourth integrator, and a multi-bit quantizer;

[0029] The output end of the interconnection gain coefficient adjustment unit is connected to the third adder, the output signal of the multi-bit quantizer is connected to the third adder via the third feedback gain coefficient adjustment unit, and the third integrator is connected to the output end of the third adder; the output end of the third integrator is connected to the fourth adder, the output signal of the multi-bit quantizer is connected to the fourth adder via the fourth feedback gain coefficient adjustment unit, and the fourth integrator is connected to the output end of the fourth adder; the multi-bit quantizer is connected to the output end of the fourth integrator.

[0030] To achieve the above and other related purposes, the present invention also provides a Σ-Δ analog-to-digital converter, which at least includes:

[0031] The above Σ-Δ modulation module, digital noise cancellation module, and digital low-pass decimation filter module;

[0032] The Σ-Δ modulation module integrates the input analog signal and converts it into a digital quantity;

[0033] The digital noise cancellation module is connected to the output end of the modulation module and is used to shape the quantization noise in the output signal of the modulation module;

[0034] The digital low-pass decimation filter module is connected to the output end of the digital noise cancellation module, and performs low-pass filtering on the digital signal output by the digital noise cancellation module to filter out the quantization noise in the digital signal output by the digital noise cancellation module.

[0035] Optionally, the digital noise cancellation module includes a delay unit, a gain coefficient adjustment unit, a first adder unit, a differential unit, and a second adder unit;

[0036] The delay unit receives the digital quantity output by the first-stage modulator in the Σ-Δ modulation module and performs a delay.

[0037] The gain coefficient adjustment unit is connected to the output end of the delay unit and adjusts the gain of the signal output by the delay unit.

[0038] The first adder unit receives the digital quantity output by the second-stage modulator in the Σ-Δ modulation module and is connected to the output end of the gain coefficient adjustment unit to perform an addition operation.

[0039] The differential unit is connected to the output end of the first adder unit and performs a differential operation on the output signal of the first adder unit.

[0040] The second adder unit is connected to the output ends of the delay unit and the differential unit, adds the two, and outputs the result.

[0041] As described above, the Σ-Δ modulation module, analog-to-digital converter, and method for setting the reverse gain coefficient of the present invention have the following beneficial effects:

[0042] 1. The Σ-Δ analog-to-digital converter of the present invention solves the constraint that the gain coefficient is a power of 2, and can use any gain coefficient, including even and odd numbers, with higher flexibility.

[0043] 2. The Σ-Δ analog-to-digital converter of the present invention matches each-order gain coefficient with the normalization factor of the quantizer, avoids using an intermediate rising quantizer, and does not require an additional digital hardware circuit to set the reverse gain coefficient, simplifies the circuit structure, and reduces the design difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It shows a schematic circuit diagram of the Σ-Δ modulation module of the present invention.

[0045] Figure 2 It shows a schematic circuit diagram of the multi-bit quantizer of the present invention.

[0046] Figure 3 It shows a schematic circuit diagram of the fully differential analog-to-digital conversion unit of the present invention.

[0047] Figure 4 It shows a schematic circuit diagram of the comparator of the present invention.

[0048] Figure 5 It shows a schematic circuit diagram of the temperature encoding unit of the present invention.

[0049] Figure 6 It shows a schematic circuit diagram of the reverse gain coefficient embedding unit of the present invention.

[0050] Figure 7 It shows a schematic circuit diagram of the Σ-Δ analog-to-digital converter of the present invention.

[0051] Figure 8 It shows a schematic circuit diagram of the digital noise cancellation module of the present invention.

[0052] Description of component numbers

[0053] 1 Σ-Δ modulation module 11 First-stage modulator

[0054] 111 First input gain coefficient adjustment unit 112 First feedback gain coefficient adjustment unit

[0055] 113 First adder 114 First integrator

[0056] 115 Second input gain coefficient adjustment unit 116 Second feedback gain coefficient adjustment unit

[0057] 117 Second adder 118 Second integrator

[0058] 119 Single-bit quantizer 12 Interconnection gain coefficient adjustment unit

[0059] 13 Second-stage modulator 131 Third feedback gain coefficient adjustment unit

[0060] 132 Third adder 133 Third integrator

[0061] 134 Fourth feedback gain coefficient adjustment unit 135 Fourth adder

[0062] 136 Fourth integrator 137 Multibit quantizer

[0063] 137a Fully differential analog-to-digital conversion unit 137b Differential input comparison unit

[0064] 137c Temperature encoding unit 137d Reverse gain coefficient embedding unit

[0065] 2 Digital noise cancellation module 21 Delay unit

[0066] 22 Gain coefficient adjustment unit 23 First adder unit

[0067] 24 Second adder unit 25 Differentiator unit

[0068] 3 Digital low-pass decimation filter module Detailed implementation manners

[0069] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] Please refer to Figures 1 to 8 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0071] Embodiment 1

[0072] As Figure 1 shown, this embodiment provides a Σ-Δ modulation module 1, and the Σ-Δ modulation module 1 includes:

[0073] A two-stage fourth-order structure, wherein the second-stage modulator 13 is cascaded after the first-stage modulator 11 through an interconnected gain coefficient adjustment unit 12.

[0074] As Figure 1 shown, the first-stage modulator 11 receives an input analog signal X(z) and outputs the signal to the second-stage modulator 13. In this embodiment, the first-stage modulator 11 includes a first input gain coefficient adjustment unit 111, a first feedback gain coefficient adjustment unit 112, a first adder 113, a first integrator 114, a second input gain coefficient adjustment unit 115, a second feedback gain coefficient adjustment unit 116, a second adder 117, a second integrator 118, and a single-bit quantizer 119.

[0075] Specifically, the input analog signal X(z) is connected to the first input end of the first adder 113 via the first input gain coefficient adjustment unit 111, and the output signal of the single-bit quantizer 119 is connected to the second input end of the first adder 113 via the first feedback gain coefficient adjustment unit 112; the first integrator 114 (in the present invention, the transfer functions of all integrators satisfy: ) Connect to the output terminal of the first adder 113. The first input gain coefficient adjustment unit 111, the first feedback gain coefficient adjustment unit 112, the first adder 113, and the first integrator 114 constitute a first-order modulation structure.

[0076] Specifically, the output terminal of the first integrator 114 is connected to the first input terminal of the second adder 117 via the second input gain coefficient adjustment unit 115, and the output signal of the single-bit quantizer 119 is connected to the second input terminal of the second adder 117 via the second feedback gain coefficient adjustment unit 116; the second integrator 118 is connected to the output terminal of the second adder 117. The second input gain coefficient adjustment unit 115, the second feedback gain coefficient adjustment unit 116, the second adder 117, and the second integrator 118 constitute a second-order modulation structure.

[0077] It should be noted that in this embodiment, the denominator of the second-order input gain coefficient B (the coefficient preset by the second input gain coefficient adjustment unit 115) is the value corresponding to the number of comparators of the multi-bit quantizer in the second-stage modulator 13, and the denominator of the first-order input gain coefficient A (the coefficient preset by the first input gain coefficient adjustment unit 111) is the numerator of the second-order input gain coefficient B. The numerators of the first-order input gain coefficient A and the second-order input gain coefficient B can be set according to actual needs, and the first-order input gain coefficient A and the second-order input gain coefficient B can be even or odd. In this embodiment, the first-order feedback gain coefficient (the coefficient preset by the first feedback gain coefficient adjustment unit 112) is the negative of the first-order input gain coefficient -A, and the second-order feedback gain coefficient (the coefficient preset by the second feedback gain coefficient adjustment unit 116) is -2 times the first-order input gain coefficient A and the second-order input gain coefficient B -2AB, which can be set based on needs in actual use and is not limited to this embodiment. As an example, the first-order input gain coefficient A is set to 1 / 4, the second-order input gain coefficient B is set to 4 / 7, the first-order feedback gain coefficient -A is set to -1 / 4, and the second-order feedback gain coefficient -2AB is set to -2 / 7.

[0078] Specifically, the single-bit quantizer 119 is connected to the output end of the second integrator 118. The single-bit quantizer 119 includes an analog-to-digital conversion unit and a digital-to-analog conversion unit (not shown in the figure). The analog-to-digital conversion unit converts the output signal of the second-order modulation unit 112 into a digital signal Y1(z). The digital signal Y1(z) is consistent with the coding type corresponding to the second-stage modulator 13. In this embodiment, the digital signal Y1(z) is a two's complement. The digital-to-analog conversion unit generates a feedback signal based on the output signal of the analog-to-digital conversion unit and feeds it back to the first feedback gain coefficient adjustment unit 112 and the second input gain coefficient adjustment unit 115. The specific structure is not described in detail here.

[0079] As Figure 1 shown, the interconnection gain coefficient adjustment unit 12 is connected between the first-stage modulator 11 and the second-stage modulator 12.

[0080] Specifically, the input end of the interconnection gain coefficient adjustment unit 12 is connected to the output end of the second integrator 118 to adjust the gain of the output signal of the second integrator 118. The adjustment multiple is the interconnection gain coefficient. In this embodiment, the interconnection gain coefficient C is set to 1 / 2. In actual use, the interconnection gain coefficient C can be set according to actual needs, and this embodiment is not limiting.

[0081] As Figure 1 shown, the second-stage modulator 13 is cascaded after the first-stage modulator 11 via the interconnection gain coefficient adjustment unit 12. In this embodiment, the second-stage modulator 13 includes a third feedback gain coefficient adjustment unit 131, a third adder 132, a third integrator 133, a fourth feedback gain coefficient adjustment unit 134, a fourth adder 135, a fourth integrator 136, and a multi-bit quantizer 137.

[0082] Specifically, the output end of the interconnection gain coefficient adjustment unit 12 is connected to the first input end of the third adder 132. The output signal of the multi-bit quantizer 137 is connected to the second input end of the third adder 132 via the third feedback gain coefficient adjustment unit 131. The third integrator 133 is connected to the output end of the third adder 132. The third feedback gain coefficient adjustment unit 131, the third adder 132, and the third integrator 133 form a third-order modulation structure.

[0083] Specifically, the output terminal of the third integrator 133 is connected to the first input terminal of the fourth adder 135, and the output signal of the multi-bit quantizer 137 is connected to the fourth adder 135 via the fourth feedback gain coefficient adjustment unit 134; the fourth integrator 136 is connected to the output terminal of the fourth adder 135. The fourth feedback gain coefficient adjustment unit 134, the fourth adder 135, and the fourth integrator 136 constitute a fourth-order modulation structure.

[0084] It should be noted that the third-order input gain coefficient is the interconnection gain coefficient C, and the fourth-order input gain coefficient can be set according to actual needs and can be even or odd. In this embodiment, the fourth-order input gain coefficient is set to 1. In actual use, it can be set according to needs. When the fourth-order input gain coefficient is not set to 1, a corresponding input gain coefficient adjustment module needs to be added, which will not be elaborated here one by one. As an example, the third-order feedback gain coefficient (the coefficient preset by the third feedback gain coefficient adjustment unit 131) is set to -1, and the fourth-order feedback gain coefficient (the coefficient preset by the fourth feedback gain coefficient adjustment unit 134) is set to -2.

[0085] Specifically, the multi-bit quantizer 137 is connected to the output terminal of the fourth integrator 136. In this embodiment, the multi-bit quantizer 137 is a 3-bit quantizer and uses a flash analog-to-digital converter (flash-ADC); in actual use, it can be set to a quantizer with more bits according to needs, and any analog-to-digital converter that can implement the functions of the present invention is applicable. For example Figure 2As shown, by way of example, the multi-bit quantizer 137 includes a fully differential analog-to-digital conversion unit 137a, a differential input comparison unit 137b, a thermometer encoding unit 137c, and a reverse gain coefficient embedding unit 137d. The fully differential analog-to-digital conversion unit 137a generates a set of differential reference signals RDAC_P<7:1> and RDAC_N<7:1> corresponding to the number of comparators in the differential input comparison unit 137b as the reference signals for the differential input comparison unit 137b. The differential input comparison unit 137b is connected to the output of the fully differential analog-to-digital conversion unit 137a (receiving the reference signals) and the output of the fourth-order modulation unit 122 (receiving the differential input signals INP and INN), and is configured to compare the differential input signals INP and INN with the respective reference signals RDAC_P<7:1> and RDAC_N<7:1> to obtain corresponding digital signals QP<7:1> and QN<7:1>. The thermometer encoding unit 137c is connected to the output of the differential input comparison unit 137b and is configured to encode the digital signals QP<7:1> and QN<7:1> output by the differential input comparison unit into a thermometer code TH_CODE<8:1> (also referred to as One of N Code). The reverse gain coefficient embedding unit 137d is connected to the output of the thermometer encoding unit 137c and is configured to convert the thermometer code TH_CODE<8:1> into a code of the quantizer level normalized between the positive and negative values of the reverse gain coefficient based on a normalization factor (in this embodiment, a two's complement Y2_TCC<5:1>); the normalization factor is equal to the number of comparators in the differential input comparison unit.

[0086] It should be noted that, in this embodiment, the reverse gain coefficient D satisfies the following relationship: D = 1 / (A*B*C), where D is the reverse gain coefficient, A is the first-order input gain coefficient, B is the second-order input gain coefficient, and C is the interconnection gain coefficient. In actual use, the reverse gain coefficient D can be determined based on any method and embedded into the multi-bit quantizer 137 through the reverse gain coefficient embedding unit 137d. By way of example, the reverse gain coefficient D = 1 / ((1 / 4)*(4 / 7)*(1 / 2)) = 14, and the positive and negative values of the reverse gain coefficient D are -14 and 14. Divide -14 to 14 into 7 equal parts (normalization factor) to obtain the normalized values 14, 10, 6, 2, -2, -6, -10, -14.

[0087] More specifically, as Figure 3As shown, in this embodiment, the fully differential analog-to-digital conversion unit 137a includes a first resistor string and a second resistor string. The head and tail ends of the first resistor string and the second resistor string are cross-coupled and connected to a first voltage VP and a second voltage VN, and the first voltage VP and the second voltage VN are differential signals. The first resistor string and the second resistor string divide the voltage to output corresponding differential reference signals, denoted as RDAC_P<7:1> and RDAC_N<7:1> respectively. The number of resistors can be set as needed.

[0088] More specifically, the differential input comparison unit 137b includes a plurality of comparators. In this embodiment, the multi-bit quantizer 137 is set as a 3-bit quantizer, and the number of comparators is set to 7 (an odd number). Each comparator compares the differential input signals INP and INN with each reference signal respectively and outputs comparison results QP<7:1> and QN<7:1>. As Figure 4 shown, as an example, each comparator includes a first comparison module CP1, a second comparison module CP2, a first, second, third, fourth switch, and a latch LATCH. The positive input terminal of the first comparison module CP1 is connected to the positive signal INP of the differential input signal via the first switch K1, and the negative input terminal is connected to the corresponding positive reference signal (one of RDAC_P<7:1>, taking RDAC_P<1> as an example in the figure) via the second switch K2; the positive input terminal of the second comparison module CP2 is connected to the negative signal INN of the differential input signal via the third switch K3, and the negative input terminal is connected to the corresponding negative reference signal (one of RDAC_N<7:1>, taking RDAC_N<1> as an example in the figure) via the fourth switch K4; the control terminals of each switch (K1, K2, K3, and K4) are connected to the sampling signal SAMPLE; each input terminal of the first comparison module CP1 and the second comparison module CP2 is connected to the common voltage VCM via a capacitor. The latch LATCH is connected to the output terminals of the first comparison module CP1 and the second comparison module CP2, latches and outputs the comparison results QP and QN of the first comparison module CP1 and the second comparison module CP2, and the latch LATCH is also connected to the enable signal REGEN.

[0089] It should be noted that the number of comparators in the differential input comparison unit 137b can be set to an odd number or an even number, not limited to this embodiment.

[0090] More specifically, in this embodiment, the multi-bit quantizer 137 is set as a 3-bit quantizer, and the temperature encoding unit 137c encodes the 7-bit digital signal output by the differential input comparison unit 137b into an 8-bit temperature code TH_CODE<8:1>. As Figure 5As shown, the temperature encoding unit 137c includes eight three-input AND gates; the input terminals of the first three-input AND gate AND1 are respectively connected to the first-bit inverted signal QN<1>, the second-bit inverted signal QN<2> output by the differential input comparison unit, and the high-level VDD, and output the first-bit signal TH_CODE<1> of the temperature code; the input terminals of the second three-input AND gate AND2 are respectively connected to the second-bit inverted signal QN<2>, the third-bit inverted signal QN<3> output by the differential input comparison unit, and the first-bit positive signal QP<1>, and output the second-bit signal TH_CODE<2> of the temperature code; the input terminals of the third three-input AND gate AND3 are respectively connected to the third-bit inverted signal QN<3>, the first-bit positive signal QP<1>, and the second-bit positive signal QP<2> output by the differential input comparison unit, and output the third-bit signal TH_CODE<3> of the temperature code; the input terminals of the fourth three-input AND gate AND4 are respectively connected to the fourth-bit inverted signal QN<4>, the second-bit positive signal QP<2>, and the third-bit positive signal QP<3> output by the differential input comparison unit, and output the fourth-bit signal TH_CODE<4> of the temperature code; the input terminals of the fifth three-input AND gate AND5 are respectively connected to the fifth-bit inverted signal QN<5>, the third-bit positive signal QP<3>, and the fourth-bit positive signal QP<4> output by the differential input comparison unit, and output the fifth-bit signal TH_CODE<5> of the temperature code; the input terminals of the sixth three-input AND gate AND6 are respectively connected to the sixth-bit inverted signal QN<6>, the fourth-bit positive signal QP<4>, and the fifth-bit positive signal QP<5> output by the differential input comparison unit, and output the sixth-bit signal TH_CODE<6> of the temperature code; the input terminals of the seventh three-input AND gate AND7 are respectively connected to the seventh-bit inverted signal QN<7>, the fifth-bit positive signal QP<5>, and the sixth-bit positive signal QP<6> output by the differential input comparison unit, and output the seventh-bit signal TH_CODE<7> of the temperature code; the input terminals of the eighth three-input AND gate AND8 are respectively connected to the sixth-bit positive signal QP<6>, the seventh-bit positive signal QP<7>, and the high-level VDD output by the differential input comparison unit, and output the eighth-bit signal TH_CODE<8> of the temperature code.

[0091] It should be noted that the correspondence between the 7-bit digital signal encoding output by the differential input comparison unit 137b and the 8-bit temperature code can be set as needed, not limited to this embodiment. When obtaining different correspondences, the circuit connection relationship can be adjusted adaptively, which will not be elaborated here one by one.

[0092] More specifically, in this embodiment, the multi-bit quantizer 137 is set as a 3-bit quantizer, and the reverse gain coefficient embedding unit 137d is set as a two's complement coding unit, which converts the 8-bit temperature code TH_CODE<8:1> into a 5-bit two's complement Y2_TCC<5:1>. The two's complement Y2_TCC<5:1> corresponds to the quantizer levels normalized between the positive and negative values of the reverse gain coefficient. As Figure 6 shown, the two's complement coding unit includes a buffer BUFFER, an eight-input OR gate OR1, and three four-input OR gates; the buffer BUFFER receives the low level VSS and outputs the first bit signal Y2_TCC<1> of the two's complement; the input terminals of the eight-input OR gate OR1 are respectively connected to the eight-bit signals TH_CODE<8:1> of the temperature code and output the second bit signal Y2_TCC<2> of the two's complement; the input terminals of the first four-input OR gate OR2 are respectively connected to the second bit signal TH_CODE<2>, the fourth bit signal TH_CODE<4>, the sixth bit signal TH_CODE<6>, and the eighth bit signal TH_CODE<8> of the temperature code and output the third bit signal Y2_TCC<3> of the two's complement; the input terminals of the second four-input OR gate OR3 are respectively connected to the third bit signal TH_CODE<3>, the fourth bit signal TH_CODE<4>, the seventh bit signal TH_CODE<7>, and the eighth bit signal TH_CODE<8> of the temperature code and output the fourth bit signal Y2_TCC<4> of the two's complement; the input terminals of the third four-input OR gate OR4 are respectively connected to the first bit signal TH_CODE<1>, the second bit signal TH_CODE<2>, the third bit signal TH_CODE<3>, and the fourth bit signal TH_CODE<4> of the temperature code and output the fifth bit signal Y2_TCC<5> of the two's complement.

[0093] It should be noted that the correspondence between the temperature code TH_CODE<8:1> and the two's complement Y2_TCC<5:1> can be set as needed, not limited to this embodiment. When obtaining different correspondences, the circuit connection relationship can be adjusted adaptively, which will not be elaborated here one by one. Further, the reverse gain coefficient embedding unit 137d can adopt one of, but not limited to, a two's complement coding unit, a Gray code coding unit, a sign-magnitude code coding unit, an offset binary code coding unit, and a one's complement coding unit, which will not be elaborated here one by one.

[0094] The following table shows an example of the output signals of each unit in the multi-bit quantizer 137:

[0095] QP(7b) QN(7b) TH-CODE(8b) ND(-14 to 14) Y2_TCC(5b) 1111111 0000000 10000000 14 01110 1111110 1000000 01000000 10 01010 1111100 1100000 00100000 6 00110 1111000 1110000 00010000 2 00010 1110000 1111000 00001000 -2 11110 1100000 1111100 00000100 -6 11010 1000000 1111110 00000010 -10 10110 0000000 1111111 00000001 -14 10010

[0096] First, convert the output signal of the fourth integrator 136 into a temperature code, and then encode the temperature code into a two's complement corresponding to the level of the normalized multi-bit quantizer 137, so as to realize the embedding of the reverse gain coefficient.

[0097] In the Σ-Δ modulation module of this embodiment, the input gain coefficient is not limited to a power of 2 and can be set to any value, which has greater flexibility and does not require the use of an intermediate thread quantizer.

[0098] Embodiment 2

[0099] As Figure 7 shown, this embodiment provides a Σ-Δ analog-to-digital converter, and the Σ-Δ analog-to-digital converter includes:

[0100] A Σ-Δ modulation module 1, a digital noise cancellation module 2, and a digital low-pass decimation filter module 3.

[0101] As Figure 7 shown, the Σ-Δ modulation module 1 receives an input analog signal X(z) and converts it into a digital quantity.

[0102] Specifically, in this embodiment, the frequency of the analog signal X(z) is less than 24 KHz. The frequency of the output signal of the Σ-Δ modulation module 1 is 3.072 MHz, and the digital quantities Y1(z) output by the first-stage modulator 11 and the digital quantity Y2(z) output by the first-stage modulator 11 are only 5-bit two's complements.

[0103] Specifically, the Σ-Δ modulation module 1 is a two-stage fourth-order modulation structure. For the specific circuit structure and principle, refer to Embodiment 1 and will not be elaborated here one by one.

[0104] As Figure 7 shown, the digital noise cancellation module 2 is connected to the output end of the Σ-Δ modulation module 1 and is used to shape the quantization noise in the output signal of the Σ-Δ modulation module 1.

[0105] Specifically, as Figure 8 shown, the digital noise cancellation module 2 includes a delay unit 21, a gain coefficient adjustment unit 22, a first addition unit 23, a differential unit 24, and a second addition unit 25.

[0106] More specifically, the delay unit 21 receives the digital quantity Y1(z) output by the first-stage modulator 11 and delays it. In this embodiment, the delay unit 21 includes two cascaded delay blocks, and each delay block satisfies the transfer function: z -1 .

[0107] More specifically, the gain coefficient adjustment unit 22 is connected to the output end of the delay unit 21, and performs gain adjustment on the signal output by the delay unit 21. In this embodiment, the gain coefficient set by the gain coefficient adjustment unit 22 is -1. In actual use, the gain coefficient of the gain coefficient adjustment unit 22 can be set as needed, which will not be elaborated here one by one.

[0108] More specifically, the first adder unit 23 receives the digital quantity Y2(z) output by the second-stage modulator 13 in the Σ-Δ modulation module 1, and is connected to the output end of the gain coefficient adjustment unit 22 to perform an addition operation.

[0109] It should be noted that since the reverse gain coefficient D is embedded in the multi-bit quantizer 137, it is equivalent to performing reverse gain coefficient adjustment on the digital quantity Y2(z) output by the second-stage modulator 13 received by the first adder unit 23. There is no need to set a reverse gain coefficient adjustment unit in the digital noise cancellation module 2 (digital domain), which simplifies the structure and reduces the design difficulty.

[0110] More specifically, the differentiator unit 24 is connected to the output end of the first adder unit 23, and performs a differentiation operation on the output signal of the first adder unit 23 to achieve shaping of the quantization noise. In this embodiment, the differentiator unit 24 includes two cascaded differentiator blocks, and each differentiator block satisfies the transfer function: 1 - z -1 .

[0111] More specifically, the second adder unit 25 is connected to the output ends of the delay unit 21 and the differentiator unit 24, adds the two and outputs the signal YOUT(z). In this embodiment, the output signal YOUT(z) is 9 bits and the frequency is 3.072 MHz.

[0112] As Figure 7 shown, the digital low-pass decimation filter module 3 is connected to the output end of the digital noise cancellation module 2, and performs low-pass filtering on the digital signal output by the digital noise cancellation module 2 to filter out the quantization noise in the digital signal output by the digital noise cancellation module 2, and outputs the signal OUT-ADC. In this embodiment, the output signal OUT-ADC is 24 bits and the frequency is 48 KHz.

[0113] Specifically, any circuit structure that can remove the shaped quantization noise of the digital noise cancellation module 2 is applicable to the digital low-pass decimation filter module 3 of the present invention, which will not be elaborated here one by one.

[0114] In summary, the present invention provides a Σ-Δ modulation module and an analog-to-digital converter, including: a first-stage modulator, a second-stage modulator, and an interconnection gain coefficient adjustment unit connected between the first-stage modulator and the second-stage modulator; wherein, the multi-bit quantizer in the second-stage modulator includes: a fully differential analog-to-digital conversion unit, a differential input comparison unit, a thermometer coding unit, and a reverse gain coefficient embedding unit; the fully differential analog-to-digital conversion unit generates a differential-form reference signal corresponding to the number of comparators in the differential input comparison unit; the differential input comparison unit is connected to the output end of the fully differential analog-to-digital conversion unit and receives a differential input signal, and is used to compare the differential input signal with each reference signal to obtain a corresponding digital signal; the thermometer coding unit is connected to the output end of the differential input comparison unit and is used to encode the digital signal output by the differential input comparison unit into a thermometer code; the reverse gain coefficient embedding unit is connected to the output end of the thermometer coding unit and is used to convert the thermometer code into a code of the multi-bit quantizer level normalized between the positive and negative values of the reverse gain coefficient. The Σ-Δ analog-to-digital converter of the present invention solves the constraint that the gain coefficient is a power of 2, and any gain coefficient can be used, including even and odd numbers, with higher flexibility; matches the gain coefficients of each order with the normalization factor of the quantizer, avoids using an intermediate rising quantizer, and does not require additional digital hardware circuits to set the reverse gain coefficient, simplifies the circuit structure, and reduces the design difficulty. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0115] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A Σ-Δ modulation module, characterized in that, The Σ-Δ modulation module at least includes: A first-stage modulator, a second-stage modulator, and an interconnection gain coefficient adjustment unit connected between the first-stage modulator and the second-stage modulator. The interconnection gain coefficient adjustment unit is used for gain adjustment. Among them, the second-stage modulator includes a third feedback gain coefficient adjustment unit, a third adder, a third integrator, a fourth feedback gain coefficient adjustment unit, a fourth adder, a fourth integrator, and a multi-bit quantizer. The output end of the interconnection gain coefficient adjustment unit is connected to the third adder. The output signal of the multi-bit quantizer is connected to the third adder via the third feedback gain coefficient adjustment unit. The third integrator is connected to the output end of the third adder. The output end of the third integrator is connected to the fourth adder. The output signal of the multi-bit quantizer is connected to the fourth adder via the fourth feedback gain coefficient adjustment unit. The fourth integrator is connected to the output end of the fourth adder. The multi-bit quantizer is connected to the output end of the fourth integrator. The multi-bit quantizer includes: a fully differential analog-to-digital conversion unit, a differential input comparison unit, a thermometer coding unit, and a reverse gain coefficient embedding unit. The fully differential analog-to-digital conversion unit generates a differential-form reference signal corresponding to the number of comparators in the differential input comparison unit. The differential input comparison unit is connected to the output end of the fully differential analog-to-digital conversion unit and receives a differential input signal, and is used for comparing the differential input signal with each reference signal to obtain a corresponding digital signal. The thermometer coding unit is connected to the output end of the differential input comparison unit and is used for encoding the digital signal output by the differential input comparison unit into a thermometer code. The reverse gain coefficient embedding unit is connected to the output end of the thermometer coding unit and is used for converting the thermometer code into a code of the multi-bit quantizer level normalized between the positive and negative values of the reverse gain coefficient based on a normalization factor. The normalization factor is equal to the number of comparators in the differential input comparison unit. Among them, the reverse gain coefficient embedding unit is one of a two's complement coding unit, a Gray code coding unit, a sign-magnitude code coding unit, an offset binary code coding unit, and a one's complement coding unit.

2. The Σ-Δ modulation module according to claim 1, wherein: The reverse gain coefficient satisfies: D = 1 / (A*B*C) Where D is the reverse gain coefficient, A is the first-order input gain coefficient in the first-stage modulator, B is the second-order input gain coefficient in the first-stage modulator, C is the interconnection gain coefficient in the interconnection gain coefficient adjustment unit. The denominator of the second-order input gain coefficient B is the value corresponding to the number of comparators in the differential input comparison unit, and the denominator of the first-order input gain coefficient A is the numerator of the second-order input gain coefficient B.

3. The Σ-Δ modulation module according to claim 1 or 2, characterized in that: The fully differential analog-to-digital conversion unit includes a first resistor string and a second resistor string; the first resistor string and the second resistor string are cross-coupled at their head and tail ends and connected to a first voltage and a second voltage, and the first voltage and the second voltage are differential signals; the first resistor string and the second resistor string divide the voltage to output corresponding differential reference signals.

4. The Σ-Δ modulation module according to claim 1 or 2, characterized in that: The differential input comparison unit includes a plurality of comparators, and each comparator compares the differential input signal with each reference signal respectively and outputs a comparison result; each comparator includes a first comparison module, a second comparison module, a first, a second, a third, a fourth switch and a latch. The positive input terminal of the first comparison module is connected to the positive signal of the differential input signal via the first switch, and the negative input terminal is connected to the corresponding positive reference signal via the second switch; the positive input terminal of the second comparison module is connected to the negative signal of the differential input signal via the third switch, and the negative input terminal is connected to the corresponding negative reference signal via the fourth switch; the control terminals of each switch are connected to the sampling signal; each input terminal of the first comparison module and the second comparison module is connected to a common voltage via a capacitor respectively. The latch is connected to the output terminals of the first comparison module and the second comparison module to latch the comparison results of the first comparison module and the second comparison module.

5. The Σ-Δ modulation module according to claim 4, wherein: The number of the comparators is set to be odd.

6. The Σ-Δ modulation module according to claim 1 or 2, characterized in that: The multi-bit quantizer is a 3-bit quantizer, and the thermometer encoding unit includes eight three-input AND gates. The input terminals of the first three-input AND gate are respectively connected to the first bit, the second bit negative signal and the high level output by the differential input comparison unit, and output the first bit signal of the thermometer code; the input terminals of the second three-input AND gate are respectively connected to the second bit, the third bit negative signal and the first bit positive signal output by the differential input comparison unit, and output the second bit signal of the thermometer code; the input terminals of the third three-input AND gate are respectively connected to the third bit negative signal and the first and second bit positive signals output by the differential input comparison unit, and output the third bit signal of the thermometer code; the input terminals of the fourth three-input AND gate are respectively connected to the fourth bit negative signal and the second and third bit positive signals output by the differential input comparison unit, and output the fourth bit signal of the thermometer code; the input terminals of the fifth three-input AND gate are respectively connected to the fifth bit negative signal and the third and fourth bit positive signals output by the differential input comparison unit, and output the fifth bit signal of the thermometer code; the input terminals of the sixth three-input AND gate are respectively connected to the sixth bit negative signal and the fourth and fifth bit positive signals output by the differential input comparison unit, and output the sixth bit signal of the thermometer code; The input terminals of the seventh three-input AND gate are respectively connected to the seventh bit negative signal and the fifth and sixth bit positive signals output by the differential input comparison unit, and output the seventh bit signal of the thermometer code; the input terminals of the eighth three-input AND gate are respectively connected to the sixth and seventh bit positive signals and the high level output by the differential input comparison unit, and output the eighth bit signal of the thermometer code.

7. The Σ-Δ modulation module according to claim 1 or 2, characterized in that: The multi-bit quantizer is a 3-bit quantizer, the reverse gain coefficient embedding unit is a two's complement coding unit, and the two's complement coding unit includes three four-input OR gates, one eight-input OR gate, and one buffer; The input terminals of the first four-input OR gate are respectively connected to the first, second, third, and fourth bit signals of the temperature code, and output the fifth bit signal of the two's complement; the input terminals of the second four-input OR gate are respectively connected to the third, fourth, seventh, and eighth bit signals of the temperature code, and output the fourth bit signal of the two's complement; the input terminals of the third four-input OR gate are respectively connected to the second, fourth, sixth, and eighth bit signals of the temperature code, and output the third bit signal of the two's complement; the input terminals of the eight-input OR gate are respectively connected to the eight bit signals of the temperature code, and output the second bit signal of the two's complement; the buffer receives a low level and outputs the first bit signal of the two's complement.

8. The Σ-Δ modulation module according to claim 1 or 2, characterized in that: The first-stage modulator includes a first input gain coefficient adjustment unit, a first feedback gain coefficient adjustment unit, a first adder, a first integrator, a second input gain coefficient adjustment unit, a second feedback gain coefficient adjustment unit, a second adder, a second integrator, and a single-bit quantizer; The input analog signal is connected to the first adder via the first input gain coefficient adjustment unit, the output signal of the single-bit quantizer is connected to the first adder via the first feedback gain coefficient adjustment unit, and the first integrator is connected to the output terminal of the first adder; the output terminal of the first integrator is connected to the second adder via the second input gain coefficient adjustment unit, the output signal of the single-bit quantizer is connected to the second adder via the second feedback gain coefficient adjustment unit, and the second integrator is connected to the output terminal of the second adder; the single-bit quantizer is connected to the output terminal of the second integrator; Among them, the denominator of the second-order input gain coefficient is the value corresponding to the number of comparators in the multi-bit quantizer, and the denominator of the first-order input gain coefficient is the numerator of the second-order input gain coefficient.

9. A Σ-Δ analog-to-digital converter, characterized in that, The Σ-Δ analog-to-digital converter at least includes: The Σ-Δ modulation module, digital noise cancellation module, and digital low-pass decimation filter module as described in any one of claims 1 to 8; The Σ-Δ modulation module integrates the input analog signal and converts it into a digital quantity; The digital noise cancellation module is connected to the output terminal of the Σ-Δ modulation module and is used to shape the quantization noise in the output signal of the Σ-Δ modulation module; The digital low-pass decimation filter module is connected to the output terminal of the digital noise cancellation module and performs low-pass filtering on the digital signal output by the digital noise cancellation module to filter out the quantization noise in the digital signal output by the digital noise cancellation module.

10. The Σ-Δ analog-to-digital converter according to claim 9, characterized in that: The digital noise cancellation module includes a delay unit, a gain coefficient adjustment unit, a first adder unit, a differential unit, and a second adder unit; The delay unit receives the digital quantity output by the first-stage modulator in the Σ-Δ modulation module and performs a delay; The gain coefficient adjustment unit is connected to the output end of the delay unit and adjusts the gain of the signal output by the delay unit; The first addition unit receives the digital quantity output by the second-stage modulator in the Σ-Δ modulation module and is connected to the output end of the gain coefficient adjustment unit to perform an addition operation; The differential unit is connected to the output end of the first addition unit and performs a differential operation on the output signal of the first addition unit; The second addition unit is connected to the output ends of the delay unit and the differential unit, adds the two, and outputs the result.

Images