Method for improving warping of printed circuit board and anti-warping printed circuit board

Abstract

The present invention provides a method for improving the warping of a printed circuit board and an anti-warping printed circuit board. The anti-warping printed circuit board includes a plurality of working plates, the plurality of working plates include a plurality of working plate surface layers that are symmetrical in pairs, the working plates include a process frame and a plurality of plate groups, each plate group includes a plate group frame and at least two unit plates, at least one process frame has a frame optimization structure, or at least one plate group frame has a frame optimization structure, or at least one process frame and at least one plate group frame both have frame optimization structures, so that the difference in residual copper rate between the two symmetrical working plate surface layers is less than or equal to 10%. Based on the characteristics of the printed circuit board itself and the characteristics that affect the warping, the present invention eliminates the stress inside the board by optimizing the frame structure, does not extend the delivery time, does not increase the cost, is not affected by the machine model space, and is not affected by the machine component layout or the parts layout, and solves the PCB warping from the root.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit boards, and in particular to a method for improving warping of printed circuit boards and an anti-warping printed circuit board. Background Art

[0002] Printed Circuit Board, or PCB for short, is one of the important components of the electronics industry. Almost every electronic device, from electronic watches and calculators to computers, communication electronic equipment, and military weapon systems, as long as there are electronic components such as integrated circuits, must use PCBs to make electrical connections between the various components. Figure 1 As shown in the figure, the main components of PCB are copper clad laminates, which are composed of copper foil 1, glass fiber cloth, epoxy resin and filler. The glass fiber cloth, epoxy resin and filler form an intermediate layer 2, and the intermediate layer 2 is filled between two layers of copper foil 1. Most PCB production requires a lamination process. During the lamination process, the semi-cured sheet is softened, flows and fills the pattern, and finally solidifies to bond two or more copper clad laminates (also called core boards) together. After the lamination is completed, the temperature of the PCB drops, and the epoxy resin with a relatively large thermal expansion coefficient (CTE) has been solidified and is restricted by the glass fiber cloth and copper foil to shrink. There is tensile stress inside the PCB. At the same time, due to the uneven residual copper rate inside the PCB (the residual copper rate refers to the ratio of the area with copper on the board plane to the area of ​​the entire board), there is a large copper surface in some positions to form a high temperature zone, resulting in compressive stress in the area with high residual copper rate inside the PCB, and tensile stress in the area with low residual copper rate, which causes the PCB to bend.

[0003] Since some electronic components on the PCB surface are rigidly connected to the PCB, when the PCB is deformed, the electronic components may be disconnected from the PCB surface, thus affecting the use.

[0004] In the prior art, the following solutions are used to improve PCB warping:

[0005] Solution 1: After PCB production, add a press-bake process at the supplier end to eliminate the stress inside the board to improve PCB warping;

[0006] Solution 2: Use special fixtures or PIN pins to fix the PCB to improve PCB warping;

[0007] Solution three: Improve PCB warping by optimizing PCB layout, such as symmetrical layout, optimizing the connection bridge and small board placement, etc.

[0008] Among the above solutions to improve PCB warping, Solution 1 increases the PCB production process, which easily leads to extended delivery time and increased costs, and there is incomplete release of internal stress, which cannot completely eliminate PCB warping; Solution 2 increases costs due to the addition of special fixtures or PIN pin fixation, and some models are affected by space and cannot be equipped with PIN pins; Solution 3 is affected by the layout of mechanical components or parts, and it is impossible to arrange it completely evenly and symmetrically, resulting in structural stress in the PCB, and it cannot completely eliminate PCB warping. Summary of the invention

[0009] In view of this, the present invention first provides a method for improving the warping of a printed circuit board.

[0010] The method for improving the warping of a printed circuit board provided by the present invention comprises the steps of:

[0011] Calculate the residual copper rate of each working board surface;

[0012] Determine the difference in residual copper rate of the surface layers of multiple symmetrical working boards;

[0013] The frame structure is optimized for the two layers of the symmetrical working board whose residual copper rate difference on the surface layer is greater than 10%.

[0014] Preferably, in the above-mentioned method for improving warping of printed circuit boards, when optimizing the frame structure of two layers of symmetrical working board surface layers whose residual copper rate difference is greater than 10%, the structure of the working board process frames on the two layers is optimized.

[0015] Preferably, in the above-mentioned method for improving the warping of printed circuit boards, when the structural optimization of the working board process borders on the two layers is performed, the steps include: optimizing the working board process border of the layer with a high residual copper rate into a plurality of spaced copper strips.

[0016] Preferably, in the above-mentioned method for improving the warping of printed circuit boards, when the structure of the working board process borders on the two layers is optimized, the step of optimizing the working board process borders of the layer with a low residual copper rate into a plurality of spaced-apart square non-functional pads is also included.

[0017] Preferably, in the above method for improving warping of printed circuit boards, when optimizing the structure of two layers of symmetrical working boards whose surface copper residual rate difference is greater than 10%, the board assembly frames on the two layers are optimized structurally.

[0018] Preferably, in the above method for improving the warping of printed circuit boards, when the structure of the board assembly frame on the two layers is optimized, the step of optimizing the surface mount track frame of the board assembly frame on the two layers includes a plurality of spaced copper strips.

[0019] Preferably, in the above-mentioned method for improving the warping of printed circuit boards, when the structure of the board assembly frame on the two layers is optimized, it also includes the step of: CNC forming a plurality of spaced openings on the non-surface mount track frame of the board assembly frame on the two layers to cut the substrate.

[0020] Preferably, in the above method for improving the warping of a printed circuit board, when performing structural optimization, the intervals on the upper and lower layers of the same working board are staggered with each other.

[0021] Furthermore, the present invention also provides an anti-bending and warping printed circuit board, comprising multiple working boards, the multiple working boards comprising multiple symmetrical working board surface layers, the working boards comprising process frames and multiple board groups, each of the board groups comprising a board group frame and at least two unit boards, at least one of the process frames having a frame optimization structure, or at least one of the board group frames having a frame optimization structure, or at least one of the process frames and at least one of the board group frames both having a frame optimization structure, so that the difference in residual copper rate between the two symmetrical working board surface layers is less than or equal to 10%.

[0022] Preferably, in the above-mentioned anti-bending and warping printed circuit board, the two symmetrical working board surface layers are divided into a layer with a high residual copper rate and a layer with a low residual copper rate, and the frame optimization structure on the process frame includes a plurality of copper bars spaced apart on the layer with a high residual copper rate, each of the copper bars has a length of 12mm-24mm, and the spacing between two adjacent copper bars is 0.5mm-1.0mm.

[0023] Preferably, in the above-mentioned anti-bending and warping printed circuit board, the frame optimization structure on the process frame also includes a plurality of square non-functional pads spaced apart on a layer with a low residual copper rate, each of the square non-functional pads having a side length of 1.5mm-2.8mm, and the spacing between two adjacent square non-functional pads is 0.45mm-0.8mm.

[0024] Preferably, in the above-mentioned anti-bending and warping printed circuit board, the board group frame is divided into a surface mount track frame and a non-surface mount track frame, and the frame optimization structure of the board group frame includes a plurality of copper bars spaced apart on the surface mount track frame, each of the copper bars has a length of 12mm-24mm, and the spacing between two adjacent copper bars is 0.5mm-1.0mm.

[0025] Preferably, in the above-mentioned anti-bending and warping printed circuit board, the frame optimization structure of the board group frame also includes a plurality of openings formed by CNC on the non-surface mount rail frame, the plurality of openings are spaced apart and the substrate is cut, the spacing between two adjacent openings is 12mm-24mm, and the width of the opening is 0.8mm or 1.0mm.

[0026] The above-mentioned method for improving the warping of printed circuit boards and the anti-warping printed circuit board are based on the characteristics of the printed circuit board itself and the characteristics that affect the warping. Starting from the root cause of the warping of the PCB, the frame structure of the two layers of the symmetrical working board with a difference in residual copper rate greater than 10% is optimized. The stress in the board is eliminated by optimizing the frame structure, which will not extend the delivery time or increase the cost; and it is not affected by the model space, nor is it affected by the layout of the machine components or the layout of the parts, thus solving the problem of PCB warping from the root.

[0027] The advantages and features of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show the embodiments of the present invention and their descriptions, and are used to explain the principles of the present invention. In the drawings,

[0029] Figure 1 This is a schematic diagram of the structure of a core board of a commonly used PCB;

[0030] Figure 2 A schematic diagram of the composition of a bending and warping prevention printed circuit board according to an exemplary embodiment of the present invention;

[0031] Figure 3 for Figure 2 AA section view in;

[0032] Figure 4 A block diagram of a method for improving warping of a printed circuit board according to an exemplary embodiment of the present invention;

[0033] Figure 5 A simplified schematic diagram of a warping-resistant printed circuit board according to an exemplary embodiment of the present invention;

[0034] Figure 6 is a schematic diagram of the structure of a layer with a high residual copper rate according to an exemplary embodiment of the present invention;

[0035] Figure 7 is a schematic structural diagram of a layer with a low residual copper rate according to an exemplary embodiment of the present invention;

[0036] Figure 8 A schematic diagram of the structure of a working plate according to an exemplary embodiment of the present invention;

[0037] Fig. 9 is a schematic structural diagram of a plate assembly according to an exemplary embodiment of the present invention;

[0038] Fig.10 FIG. 4 is a schematic structural diagram of a working plate according to another exemplary embodiment of the present invention.

[0039] Explanation of numbers in the figure: 1. Copper foil; 2. Middle layer; 101. Core board; 102. First layer of copper foil; 103. Second layer of copper foil; 10. Process frame; 20. Board group; 210. Board group frame; 211. Surface mount track frame; 212. Non-surface mount track frame; 220. Unit board; 30. Frame optimization structure; 31. Copper bar; 32. Square non-functional pad; 33. Opening; 34. Spacing of the upper layer; 35. Spacing of the lower layer. DETAILED DESCRIPTION

[0040] In the following description, a large amount of details are provided so that the present invention can be thoroughly understood. However, it will be appreciated by those skilled in the art that the following description only exemplarily illustrates a preferred embodiment of the present invention, and the present invention can be implemented without one or more such details. In addition, in order to avoid confusion with the present invention, some technical features well known in the art are not described in detail.

[0041] Combination Figure 2 and Figure 3 As shown, the anti-bending and warping printed circuit board of one embodiment of the present invention includes a plurality of working plates in the thickness direction, and the plurality of working plates are specifically a first layer of copper foil 102, a second layer of copper foil 103 and a multilayer core plate 101 disposed between the first layer of copper foil 102 and the second layer of copper foil 103 (the structure of the core plate 101 can be seen in Figure 1 ), the first layer of copper foil 102 forms a working board surface layer, the second layer of copper foil 103 also forms a working board surface layer, and the upper and lower surfaces of each core board 101 also form working board surface layers respectively, so that the multi-layer working board includes a plurality of two symmetrical working board surface layers, the first layer of copper foil 102 corresponds to L1, the second layer of copper foil 103 corresponds to LN, from the first layer of copper foil 102 downwards, they are L2, L3, L4..., from the second layer of copper foil 103 upwards, they are LN-1, LN-2, LN-3..., L1 and LN are symmetrical working board surface layers, L2 and LN-1 are symmetrical working board surface layers, L3 and LN-2 are symmetrical working board surface layers, L4 and LN-3 are symmetrical working board surface layers... Each working panel includes a process frame 10 and multiple panel groups 20 (the process frame 10 and multiple panel groups 20 as a whole constitute a working panel, and the working panel is also called a Working Panel). Each panel group 20 (the panel group 20 is also called a Shipping Panel) includes a panel group frame 210 and at least two unit panels 220 (the unit panel 220 is also called a PCS).

[0042] For the above printed circuit board, in order to improve the warping, Figure 4 As shown, one embodiment of the present invention provides the following method:

[0043] S10, calculate the residual copper rate of each working board surface, which is marked as X1, X2...Xn-1, Xn in sequence. Here, each working board surface refers to Figure 2 Correspondingly, for L1, L2, L3, L4..., LN-3, LN-2, LN-1, LN, the residual copper rates X1, X2, X3, X4..., Xn-3, Xn-2, Xn-1, Xn are calculated one by one for L1, L2, L3, L4..., LN, LN-1, LN-2, LN-3... respectively. It should be noted that the residual copper rate of each layer of the working board is calculated by calculating the percentage of the copper area of ​​the graphic to the area of ​​the region in a certain area, corresponding to Figure 5 The residual copper rate of this area is the square pattern area divided by (X*Y) multiplied by 100%.

[0044] S20, determining the difference between the residual copper rates of the surface layers of a plurality of symmetrical working boards, that is, determining the difference between X1 and Xn, the difference between X2 and Xn-1, the difference between X3 and Xn-2, and so on.

[0045] S30, for the two layers of the symmetrical working board whose residual copper rate difference is greater than 10%, the frame structure is optimized. If the difference between X1 and Xn is greater than 10%, the frame structure of L1 and LN is optimized. If the difference between X2 and Xn-1 is greater than 10%, the frame structure of L2 and LN-1 is optimized... and so on.

[0046] The above S30 includes: optimizing the structure of the work board process frame 10 on the two layers. The structural optimization of the work board process frame 10 includes: optimizing the work board process frame 10 of the layer with high residual copper rate into a plurality of spaced copper strips 31, such as Figure 6 As shown, the length of the copper strip 31 is determined according to the formula ΔL=Δt*Δα*L, and the formula ΔL=Δt*Δα*L is described in detail later. Further, since the square non-functional pads have the following advantages: uniform spacing, good epoxy resin fluidity and easy PCB production, the structural optimization of the work board process frame 10 also includes: optimizing the work board process frame 10 of the layer with low residual copper rate into a plurality of spaced square non-functional pads 32, such as Figure 7 As shown, the side length of the square non-functional pad 32 is determined according to the formula ΔL=Δt*Δα*L. The formula ΔL=Δt*Δα*L will be described in detail below.

[0047] The above S30 further includes: structural optimization of the board group frame 210 on the two layers. The structural optimization of the board group frame 210 includes the following steps: optimizing the surface mount track frame 211 (surface mount track frame is referred to as SMT track frame) of the board group frame 210 on the two layers with multiple spaced copper strips 31; further, the structural optimization of the board group frame 210 also includes the following: CNC forming multiple spaced openings 33 on the non-surface mount track frame 212 (non-surface mount track frame is referred to as non-SMT track frame) of the board group frame 210 on the two layers to cut the substrate, such as Fig. 9 shown.

[0048] During the production process of the core board 101, the operator needs to touch the frame of the working panel to collect / release the board or hold the board, so the spacing between the upper and lower layers of the same core board 101 cannot completely overlap. If the spacing between the upper and lower layers of the same core board 101 overlaps, the core board 101 is easy to break at the spacing. Figure 8 and Fig.10 As shown, when optimizing the structure, the intervals on the upper and lower layers of the same working board are staggered, that is, the intervals 34 of the upper layer and the intervals 35 of the lower layer are staggered, so that the working board (mainly the core board 101) can be prevented from being damaged during the manufacturing process. It should be noted that since the first copper foil 102 and the second copper foil 103 have only one working board surface layer, the upper and lower layers of the same working board here actually refer to the upper and lower layers of the core board 101. Figure 8 In the embodiment, the upper layer of the core board 101 adopts a plurality of spaced-apart square non-functional pads optimization method, and the lower layer adopts a plurality of spaced-apart copper strips optimization method. Fig.10 In the embodiment, both the upper and lower layers of the core board 101 adopt an optimized method of multiple spaced copper strips.

[0049] In order to make the difference in residual copper rate between the surface layers of two symmetrical working boards less than or equal to 10%, the anti-bending and warping printed circuit board of one embodiment of the present invention has a frame optimization structure 30 on both the process frame 10 and the board assembly frame 210, such as Figure 1 As shown, for a single working panel, the Working Panel includes a process frame 10 and four panel groups 20, and the Shipping Panel includes a panel group frame 210 and two PCSs. After calculation, the difference between X2 and Xn-1 is greater than 10%, and the residual copper rate of L2 is greater than LN-1. L2 corresponds to a layer with a high residual copper rate, and LN-1 corresponds to a layer with a low residual copper rate. Figure 6As shown, the frame optimization structure 30 on the process frame 10 includes a plurality of copper bars 31 spaced apart on L2, each copper bar 31 has a length of 12 mm, and a spacing L between two adjacent copper bars 31 is 0.5 mm; in an embodiment not shown, each copper bar 31 has a length of 24 mm, and a spacing L between two adjacent copper bars 31 is 1 mm; in another embodiment not shown, each copper bar 31 has a length of 18 mm, and a spacing L between two adjacent copper bars 31 is 0.75 mm.

[0050] like Figure 7 As shown, the frame optimization structure 30 on the process frame 10 also includes a plurality of square non-functional pads 32 spaced apart on LN-1, each square non-functional pad 32 has a side length of 1.5 mm, and the spacing L between two adjacent square non-functional pads 32 is 0.45 mm. In one embodiment not shown, the side length of each square non-functional pad 32 is 2.8 mm, and the spacing L between two adjacent square non-functional pads 32 is 0.8 mm. In another embodiment not shown, the side length of each square non-functional pad 32 is 2.15 mm, and the spacing L between two adjacent square non-functional pads 32 is 0.65 mm.

[0051] like Fig. 9 As shown, the board assembly frame 210 is divided into a surface mount track frame 211 and a non-surface mount track frame 212, and the frame optimization structure 30 of the board assembly frame 210 includes a plurality of copper bars 31 spaced apart on the surface mount track frame 211, each copper bar 31 has a length of 12 mm, and a spacing L between two adjacent copper bars 31 is 0.5 mm; in an embodiment not shown, each copper bar 31 has a length of 24 mm, and a spacing L between two adjacent copper bars 31 is 1 mm; in another embodiment not shown, each copper bar 31 has a length of 18 mm, and a spacing L between two adjacent copper bars 31 is 0.75 mm.

[0052] Further, the frame optimization structure 30 of the board assembly frame 210 also includes a plurality of openings 33 formed by numerical control molding (i.e., CNC molding) on ​​the non-surface mount rail frame 212, the plurality of openings 33 are spaced apart and cut the substrate, the spacing between two adjacent openings 33 is 12 mm, and the width of the opening 33 is 0.8 mm; in an embodiment not shown, the spacing between the openings 33 is 24 mm, and the width of the opening 33 is 1.0 mm; in another embodiment not shown, the spacing between the openings 33 is 18 mm, and the width of the opening 33 is 1.0 mm. It should be understood that the width of the opening 33 is determined by the molding tool.

[0053] The theoretical calculation of the warping deformation of the printed circuit board during the pressing process is as follows:

[0054] ΔL=Δt*Δα*L

[0055] Δt: temperature change; Δα: coefficient of thermal expansion (also called CTE), Δα=α epoxy resin-α glass fiber cloth-α copper foil, where the CTE value of epoxy resin is 200-400ppm / ℃, the CTE value of copper is 17ppm / ℃, and the CTE value of glass fiber cloth is: 6-7ppm / ℃; L: PCB length.

[0056] For a conventional PCB with a length of 300 mm, if the maximum PCB pressing temperature is 210 degrees, the room temperature of the PCB production workshop (i.e., the surface temperature of the PCB) is 22 degrees, the CTE value of the epoxy resin is 400, and the CTE value of the glass fiber cloth is 7. If no structural optimization is performed, then:

[0057] ΔL=Δt*Δα*L=(210-22)℃*(400+17+7)x10 -6 / ℃*300mm

[0058] =23.9mm

[0059] From the above theoretical calculation, it can be seen that when the PCB length is 300mm with full copper surface, the PCB will become 23.9mm longer after expansion. Considering the most serious situation, assuming that all the deformation is converted into PCB board warping, the maximum warping degree of the PCB is 23.9mm. In other words, if the structure is not optimized, the maximum warping deformation of the PCB is 23.9mm.

[0060] The PCB optimized by the method of the above embodiment of the present invention uses a copper strip 31 with a length of 12 mm based on the frame optimization structure 30, and the longest full copper surface is 12 mm.

[0061] ΔL=Δt*Δα*L=(210-22)℃*(400+17+7)x10 -6 / ℃*12mm

[0062] =0.956mm

[0063] Based on the frame optimization structure 30, a copper strip 31 with a length of 24 mm is used, and the longest full copper surface is 24 mm. When CTE = 200,

[0064] ΔL=Δt*Δα*L=(210-22)℃*200x10 -6 / ℃*24mm

[0065] =0.902mm

[0066] It can be seen that the maximum warping deformation of the PCB optimized by the method of the above embodiment of the present invention can be controlled within 1 mm, and the warping deformation will not affect the electronic components on the surface of the PCB.

[0067] It should be noted that when optimizing the structure, if the warping deformation is to be controlled to 1 mm, L1 = ΔL / Δt / Δα = 1mm / ((210-22)℃*(400+17+7)x10 -6 / ℃)=12.55mm. Similarly: when CTE=200ppm, L1=23.75mm, so the length of the copper strip 31 can be determined.

[0068] Furthermore, the PCB optimized by the method of the above embodiment of the present invention uses a square non-functional pad 32 with a side length of 1.5 m based on the frame optimization structure 30.

[0069] ΔL=Δt*Δα*L=(210-22)℃*(400+17+7)x10 -6 / ℃*1.5mm

[0070] =0.12mm

[0071] Based on the frame optimization structure 30, a square non-functional pad 32 with a side length of 2.8 mm is used. When CTE=200,

[0072] ΔL=Δt*Δα*L=(210-22)℃*(400+17+7)x10 -6 / ℃*2.8mm

[0073] =0.11mm

[0074] It can be seen that for the PCB optimized by the method of the above embodiment of the present invention, the maximum warping deformation of large parts areas such as double rate synchronous dynamic random access memory (DDR) / central processing unit (CPU) / graphics processing unit (GPU) can be controlled within 0.12mm, and the maximum warping deformation is not greater than the SMT tin thickness (SMT tin thickness is generally 0.12mm), thereby ensuring the weldability of large parts areas such as DDR / CPU / GPU.

[0075] It should be noted that when optimizing the structure, if the thickness of the SMT steel mesh is 0.12mm, that is, the thickness of the SMT tin is 0.12mm, in order to ensure good weldability of large parts such as DDR / CPU / GPU, the deformation of the corresponding area should be less than 0.12mm, based on the following calculation:

[0076] L2=ΔL / Δt / Δα=0.12mm / ((210-22)℃*(400+17+7)x10 -6 / ℃)=1.5mm

[0077] Similarly, when CTE=200 ppm, L2=2.85 mm, so the side length of the square non-functional pad 32 can be determined.

[0078] It should be noted that if the frame optimization structure 30 on the process frame 10 can make the difference in residual copper rate between the surface layers of two symmetrical working boards less than or equal to 10%, the frame optimization structure 30 can be set only on the process frame 10; similarly, if the frame optimization structure 30 on the board group frame 210 can make the difference in residual copper rate between the surface layers of two symmetrical working boards less than or equal to 10%, the frame optimization structure 30 can be set only on the board group frame 210.

[0079] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the directional words "upward" and "downward" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside" and "outside" refer to the inside and outside relative to the contours of each component itself.

[0080] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between one or more components or features shown in the figure and other components or features. It should be understood that spatially relative terms include not only the orientation of the components as described in the figure, but also different orientations in use or operation. For example, if the components in the accompanying drawings are inverted as a whole, the components "above other components or features" or "above other components or features" will include the situation where the components are "below other components or structures" or "below other components or structures". Therefore, the exemplary term "above" may include both "above" and "below". In addition, these components or features may also be positioned at other different angles (e.g., rotated 90 degrees or other angles), and this article is intended to include all of these situations.

[0081] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, parts, components and / or combinations thereof.

[0082] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0083] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for improving warping of a printed circuit board, characterized in that: include: Calculate the residual copper rate of each working board surface; Determine the difference in residual copper rate of the surface layers of multiple symmetrical working boards; Optimize the frame structure for the two layers of the symmetrical working board with a residual copper rate difference greater than 10%; Among them, when optimizing the frame structure of two layers of symmetrical working board with a residual copper rate difference greater than 10%, the structural optimization of the working board process frame on the two layers is performed; Among them, when the working board process frame on the two layers is structurally optimized, it includes: optimizing the working board process frame of the layer with a high residual copper rate into a plurality of spaced copper bars, each of which has a length of 12mm-24mm, and a spacing between two adjacent copper bars of 0.5mm-1.0mm; optimizing the working board process frame of the layer with a low residual copper rate into a plurality of spaced square non-functional pads, each of which has a side length of 1.5mm-2.8mm, and a spacing between two adjacent square non-functional pads of 0.45mm-0.8mm.

2. The method for improving warping of a printed circuit board according to claim 1, characterized in that: When performing structural optimization on two layers of a symmetrical working board whose surface residual copper rate difference is greater than 10%, structural optimization is performed on the board group frames on the two layers.

3. The method for improving warping of a printed circuit board according to claim 2, characterized in that: When the structure of the board assembly frame on the two layers is optimized, it includes: optimizing the surface mounting track frame of the board assembly frame on the two layers with multiple spaced copper strips.

4. The method for improving warping of a printed circuit board according to claim 3, characterized in that: When the structure of the board assembly frame on the two layers is optimized, the method further includes: numerically controlling a plurality of openings distributed at intervals on the non-surface mounted track frame of the board assembly frame on the two layers to cut the substrate.

5. The method for improving warping of a printed circuit board according to claim 1, 3 or 4, characterized in that: When the structure is optimized, the intervals on the upper and lower working plate surface layers of the same working plate are staggered.

6. A warping-proof printed circuit board, comprising a plurality of working plates, the plurality of working plates comprising a plurality of two-by-two symmetrical working plate surface layers, the working plates comprising a process frame and a plurality of plate groups, each of the plate groups comprising a plate group frame and at least two unit plates, characterized in that: At least one of the process frames has a frame optimization structure, or at least one of the board group frames has a frame optimization structure, or at least one of the process frames and at least one of the board group frames both have frame optimization structures, so that the difference in residual copper rate between the two symmetrical working board surface layers is less than or equal to 10%; The two symmetrical working board surface layers are divided into a layer with a high residual copper rate and a layer with a low residual copper rate, and the frame optimization structure on the process frame includes a plurality of copper bars arranged at intervals on the layer with a high residual copper rate, each of the copper bars has a length of 12 mm to 24 mm, and the spacing between two adjacent copper bars is 0.5 mm to 1.0 mm; Among them, the frame optimization structure on the process frame also includes a plurality of square non-functional pads spaced apart on a layer with a low residual copper rate, each of the square non-functional pads has a side length of 1.5mm-2.8mm, and the spacing between two adjacent square non-functional pads is 0.45mm-0.8mm.

7. The anti-bending printed circuit board according to claim 6, characterized in that: The board group frame is divided into a surface mount track frame and a non-surface mount track frame. The frame optimization structure of the board group frame includes a plurality of copper bars spaced apart on the surface mount track frame, each of the copper bars has a length of 12 mm-24 mm, and a spacing between two adjacent copper bars is 0.5 mm-1.0 mm.

8. The anti-bending printed circuit board according to claim 7, characterized in that: The frame optimization structure of the panel group frame also includes a plurality of openings formed by CNC on the non-surface mount rail frame, the plurality of openings are spaced apart and cut the substrate, the spacing between two adjacent openings is 12mm-24mm, and the width of the openings is 0.8mm or 1.0mm.

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