Display device and method of manufacturing the same

Abstract

The present disclosure relates to a display device including a light-emitting element and a method for manufacturing the display device. A display device according to an embodiment of the present invention includes pixels arranged in a display area. Each pixel includes: a first electrode; a first insulating layer, disposed on the first electrode and including an opening, the opening being used to divide each unit and simultaneously expose different areas of the first electrode; a light-emitting element, each of the light-emitting elements being located within a unit divided by any one of the openings, and including a first end electrically connected to the first electrode and a second end protruding above the first insulating layer; and a second electrode, disposed on the light-emitting element and electrically connected to the second end of the light-emitting element.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting element has been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements each having a small size corresponding to a range from nanometers to micrometers and forming a light source of various light-emitting devices including pixels of a display device using the ultra-small light-emitting elements has been developed. Summary of the invention

[0003] Technical issues

[0004] Embodiments of the present disclosure relate to a display device having a pixel including a light emitting element and a method of manufacturing the same.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure may include a pixel disposed in a display area. The pixel may include: a first electrode; a first insulating layer disposed on the first electrode and including an opening formed to expose different regions of the first electrode and define a corresponding unit; light-emitting elements, each disposed in a unit defined by one of the openings, and including a first end electrically connected to the first electrode and a second end protruding upward from the first insulating layer; and a second electrode disposed on the light-emitting element and electrically connected to the second end of the light-emitting element.

[0007] In an implementation, each of the openings may have a width smaller than a length of each of the light emitting elements.

[0008] In an embodiment, each of the light emitting elements may be arranged in a vertical direction or a diagonal direction with respect to the first electrode and the second electrode.

[0009] In an embodiment, the first end of the light emitting element may be in direct contact with the first electrode.

[0010] In an embodiment, the second end of the light emitting element may be in direct contact with the second electrode.

[0011] In an embodiment, each of the openings may have a polygonal shape, a circular shape, an elliptical shape, or a shape corresponding to a combination thereof in a plan view, and the openings may be disposed adjacent to each other in an emission region of a pixel.

[0012] In an implementation, the display device may further include a first contact electrode embedded in the corresponding opening and in contact with the first end of the light emitting element and the first electrode.

[0013] In an implementation, the display device may further include an insulating pattern embedded in the corresponding opening to cover the first contact electrode and a region of the first end of the light emitting element.

[0014] In an implementation, the insulating pattern may include an organic insulating material.

[0015] In an implementation, the display device may further include a second insulating layer interposed between the first insulating layer and the second electrode and surrounding a side wall of the light emitting element.

[0016] In an implementation, the second insulating layer may include an organic insulating material, and a portion of the second insulating layer may be introduced into the opening.

[0017] In an embodiment, the pixel further includes at least one intermediate electrode spaced apart from the first electrode and the second electrode and electrically connected between the first electrode and the second electrode via at least one of the light emitting elements.

[0018] In an embodiment, the pixel may include a plurality of intermediate electrodes, and the plurality of intermediate electrodes may be alternately disposed on a layer on which the first electrode is disposed and a layer on which the second electrode is disposed.

[0019] In an embodiment, the light emitting element may include a rod-type light emitting element or a core-shell light emitting element.

[0020] According to an embodiment, a method for manufacturing a display device may include: forming a first electrode on a base layer; forming a first insulating layer on the first electrode; forming an alignment electrode on the first insulating layer that overlaps with the first electrode and includes a first opening; using the alignment electrode as a mask, forming a second opening in the first insulating layer that overlaps with the first opening; providing a light-emitting element on the base layer, and aligning the light-emitting element in a unit formed by the first opening and the second opening by applying an alignment signal to the first electrode and the alignment electrode; electrically connecting a first end of the light-emitting element to the first electrode; and forming a second electrode on a second end of the light-emitting element so that the second electrode is electrically connected to the second end of the light-emitting element.

[0021] In an embodiment, electrically connecting the first end of the light emitting element to the first electrode may include: after aligning the light emitting element, forming a conductive layer covering the alignment electrode and the light emitting element; forming an organic insulating layer on the conductive layer; and etching the conductive layer and the organic insulating layer so that the conductive layer and the organic insulating layer maintain a predetermined height or less only in the second opening.

[0022] In an embodiment, when the conductive layer is etched, the alignment electrode may be removed together with the conductive layer.

[0023] In an embodiment, the method may further include: after removing the alignment electrode, forming a second insulating layer covering the first insulating layer and the light emitting element; and partially etching the second insulating layer in a thickness direction so that a second end of the light emitting element is exposed.

[0024] In an embodiment, the method may further include dividing a lower electrode pattern including the first electrode into a first electrode and at least one intermediate electrode after aligning the light emitting element and before forming the second electrode.

[0025] In an embodiment, forming the second electrode may include forming the second electrode and at least one intermediate electrode on different ones of the light emitting elements, respectively.

[0026] Beneficial Effects

[0027] In the display device and the method of manufacturing the display device according to various embodiments of the present disclosure, a plurality of light emitting elements can be reliably connected between the first electrode and the second electrode of each pixel, and the light efficiency of each pixel can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 4a and Figure 4b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure.

[0033] Figure 6a to Figure 6g are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0034] Figure 7 is a plan view showing a pixel according to an embodiment of the present disclosure.

[0035] Figure 8 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure, and shows, for example, Figure 7An embodiment of the cross section corresponding to line II'.

[0036] Figure 9a to Figure 9m are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Figure 7 and Figure 8 Embodiments of the present invention provide a method for displaying a pixel of a display device.

[0037] Fig.10 1 is a plan view showing a pixel according to an embodiment of the present disclosure, and is a detailed view showing the pixel immediately after the opening is formed in the first insulating layer (eg Figure 9d A plan view of the emissive area of ​​a pixel (shown in FIG. 1 ).

[0038] Fig.11 is a plan view showing a pixel according to an embodiment of the present disclosure.

[0039] Fig.12 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure, and shows, for example, Fig.11 An embodiment of the cross section corresponding to line II-II'.

[0040] Figures 13a to 13i are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.11 and Fig.12 Embodiments of the present invention provide a method for displaying a pixel of a display device.

[0041] Fig.14 is a plan view showing a pixel according to an embodiment of the present disclosure.

[0042] Fig.15 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure, and shows, for example, Fig.14 Implementation of the cross section corresponding to line III-III'.

[0043] Figures 16a to 16e are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.14 and Fig.15 Embodiments of the present invention provide a method for displaying a pixel of a display device.

[0044] Figures 17a to 17d are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.14 and Fig.15 Embodiments of the present invention provide a method for displaying a pixel of a display device. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, and the embodiments of the present disclosure may be variously modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0046] In order to clearly explain the present disclosure, some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings. In addition, the size, ratio, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that in all the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and repeated explanations will be omitted.

[0047] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It should also be understood that, when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. In addition, when a first component or part is disposed on a second component or part, the first component or part may not only be directly on the second component or part, but also a third component or part may be between them. In addition, the terms "position", "direction", etc. used in the following description are defined as relative terms, and it should be noted that they may be changed to opposite positions or directions according to the viewing angle or direction. In addition, the singular form may include the plural form, as long as it is not specifically mentioned in the sentence.

[0048] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view each showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0049] refer to Figure 1a and Figure 1b, the light emitting element LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer 11 (also referred to as a “first semiconductor layer”), a second conductive type semiconductor layer 13 (also referred to as a “second semiconductor layer”), and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may include the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 continuously stacked in a longitudinal direction.

[0050] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0051] In an embodiment, one of the first and second conductive type semiconductor layers 11 and 13 may be disposed on a first end of the light emitting element LD. The other of the first and second conductive type semiconductor layers 11 and 13 may be disposed on a second end of the light emitting element LD.

[0052] In an embodiment, the light emitting element LD may be a rod-type light emitting element (also referred to as a "rod-type light emitting diode") manufactured in the form of a rod by an etching scheme or the like. In this specification, the term "rod-type" includes a rod-like shape and a bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), such as a cylindrical shape and a prism shape, and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0053] In an embodiment, the light emitting element LD may have a small size in the range from nanometer level to micrometer level. For example, each light emitting element LD may have a diameter D (or width) and / or a length L in the range from nanometer level to micrometer level. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., display devices) that use a light emitting device using the light emitting element LD as a light source.

[0054] The first conductive type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first conductive type semiconductor layer 11 may include an N-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive type semiconductor layer 11 is not limited thereto, and the first conductive type semiconductor layer 11 may be formed of various other materials.

[0055] The active layer 12 may be disposed on the first conductive type semiconductor layer 11 and have a single quantum well structure or a multiple quantum well (MQW) structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0056] If a voltage equal to or greater than the threshold voltage is applied between opposite ends of the light emitting element LD, the light emitting element LD can emit light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0057] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a P-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0058] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround predetermined regions of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 disposed on the respective opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, may expose both base sides of a cylinder (at Figure 1a and Figure 1b In the embodiment, the top surface and the bottom surface of the light emitting element LD are covered instead of covering the two base sides.

[0059] In an embodiment, the insulating film INF may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N4 ), aluminum oxide (Al 2 O 3 ) and titanium oxide (TiO 2 ) at least one insulating material, but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0060] In an embodiment, in addition to the first conductive type semiconductor layer 11, the active layer 12, the second conductive type semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include additional other components. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive type semiconductor layer 11, the active layer 12 and / or the second conductive type semiconductor layer 13.

[0061] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0062] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed of a transparent electrode material, such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or alloy thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), alone or in combination. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0063] In an embodiment, the insulating film INF may at least partially surround the peripheral surfaces of the electrode layers 14 and 15, or may not surround the peripheral surfaces thereof. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different conductivity types, and, for example, may expose at least one region of each of the electrode layers 14 and 15. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0064] If the insulating film INF is disposed on the surface of the light emitting element LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode (e.g., the first electrode or the second electrode of the pixel) not shown. Therefore, the electrical stability of the light emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connection (conecting) or connection (connection)" can comprehensively refer to physical and / or electrical connection (conecting) or connection (or connection). In addition, the term "connection (conecting) or connection (connection)" can comprehensively refer to direct and / or indirect connection (conecting) or connection (connection) and integral or non-integral connection (conecting) or connection (connection).

[0065] In addition, by forming the insulating film INF on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on the surface of each light emitting element LD, even in the case where a plurality of light emitting elements LD are arranged adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0066] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, each light emitting element LD may be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed in the solution rather than unevenly aggregated.

[0067] In a non-limiting embodiment related hereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as Teflon TM or Cytop TM ) or corresponding materials.

[0068] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in display devices, but also in various devices that require light sources. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices (such as lighting devices) that require light sources.

[0069] Figure 4a and Figure 4b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element LD according to an embodiment of the present disclosure. Figure 4a and Figure 4b Shows that with Figures 1a to 3b The structure of the light emitting element LD shown in the figure is different from that of the light emitting element LD, and for example, a light emitting element LD having a core-shell structure is shown. In other words, the type, structure and / or shape of the light emitting element LD according to the embodiment of the present disclosure may be changed in various ways. Figure 4a and Figure 4b In the description of the embodiments of the present invention, the same reference numerals are used to represent Figures 1a to 3b Components similar or identical (or corresponding) to those of the embodiments of the present invention, and their detailed description will be omitted.

[0070] refer to Figure 4a and Figure 4b , the light emitting element LD according to an embodiment of the present disclosure may include a first conductive type semiconductor layer 11, a second conductive type semiconductor layer 13, and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. In an embodiment, the first conductive type semiconductor layer 11 may be disposed in a central region of the light emitting element LD, and the active layer 12 may be disposed on a surface of the first conductive type semiconductor layer 11 to surround at least one region of the first conductive type semiconductor layer 11. The second conductive type semiconductor layer 13 may be disposed on a surface of the active layer 12 to surround at least one region of the active layer 12.

[0071] The light emitting element LD may further include an electrode layer 14 and / or an insulating film INF, the electrode layer 14 being configured to surround at least one region of the second conductive type semiconductor layer 13, and the insulating film INF being disposed on the outermost surface of the light emitting element LD. For example, the light emitting element LD may further include an electrode layer 14 disposed on the surface of the second conductive type semiconductor layer 13 to surround a region of the second conductive type semiconductor layer 13, and an insulating film INF disposed on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14. In an embodiment, the insulating film INF may be disposed only on a portion of the surface of the light emitting element LD, so that a region of the first conductive type semiconductor layer 11 and a region of the second conductive type semiconductor layer 13 and / or the electrode layer 14 are exposed.

[0072] The light emitting element LD according to the aforementioned embodiment may be a core-shell light emitting element (also referred to as a "core-shell light emitting diode") manufactured by a growth scheme or the like. For example, the light emitting element LD may have a core-shell structure including a first conductive type semiconductor layer 11, an active layer 12, a second conductive type semiconductor layer 13, an electrode layer 14, and an insulating film INF that are continuously arranged in a direction from the center to the periphery. Here, the electrode layer 14 and the insulating film INF may be selectively included in the light emitting element LD. In an embodiment, the light emitting element LD may not include at least one of the electrode layer 14 and the insulating film INF.

[0073] In an embodiment, the light emitting element LD may have a polygonal pyramid shape extending in one direction. For example, at least one region of the light emitting element LD may have a hexagonal pyramid shape. However, the shape of the light emitting element LD may be changed in various ways.

[0074] If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end relative to the longitudinal direction. In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 (or an electrode layer disposed on either side of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13) is disposed on one end of the light emitting element LD. The other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 (or an electrode layer disposed on the other side of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13) may be disposed on the other end of the light emitting element LD.

[0075] In an embodiment of the present disclosure, the light emitting element LD may be a light emitting diode having a core-shell structure and having an ultra-small size, one end of which protrudes in a polygonal pyramid shape (e.g., a hexagonal pyramid shape). In an embodiment, the light emitting element LD may have a small size ranging from nanometer to micrometer, for example, having a width W and / or a length L corresponding to the nanometer or micrometer level. Here, the size and shape of the light emitting element LD may be changed according to the design conditions of various devices (e.g., display devices) that employ the light emitting element LD as a light source.

[0076] In an embodiment, the opposite ends of the first conductive type semiconductor layer 11 may have a shape that protrudes in the longitudinal direction of the light emitting element LD. The shapes of the opposite ends of the first conductive type semiconductor layer 11 that protrude outward may be different from each other. For example, the first end of the opposite ends of the first conductive type semiconductor layer 11, which is disposed at an upper position, may have a conical shape whose width decreases upward to form a vertex. In addition, the second end of the opposite ends of the first conductive type semiconductor layer 11, which is disposed at a lower position, may have a prism shape (e.g., a hexagonal prism shape) having a constant width, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first conductive type semiconductor layer 11 may have a polygonal or stepped cross-section whose width gradually decreases. The shapes of the opposite ends of the first conductive type semiconductor layer 11 may be changed in various ways according to the embodiment, and are not limited to the shapes of the aforementioned embodiments.

[0077] In an embodiment, the first conductive type semiconductor layer 11 may be disposed in the core of the light emitting element LD, that is, in the central (or middle) portion of the light emitting element LD. In addition, the light emitting element LD may have a shape corresponding to the shape of the first conductive type semiconductor layer 11. For example, if the first conductive type semiconductor layer 11 has a hexagonal pyramid shape at at least one end thereof, the light emitting element LD may have a hexagonal pyramid shape at at least one end thereof.

[0078] The active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the first conductive type semiconductor layer 11. For example, the active layer 12 may be disposed and / or formed in a shape surrounding a region of the first conductive type semiconductor layer 11 except for one end (e.g., one end disposed at a lower position) of the first conductive type semiconductor layer 11 relative to the longitudinal direction of the light emitting element LD.

[0079] The second conductive type semiconductor layer 13 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the active layer 12, and include a semiconductor layer having a different type from that of the first conductive type semiconductor layer 11. For example, in the case where the first conductive type semiconductor layer 11 includes at least one N-type semiconductor layer, the second conductive type semiconductor layer 13 may have at least one P-type semiconductor layer.

[0080] In an embodiment, the light emitting element LD may include an electrode layer 14 surrounding an outer peripheral surface of the second conductive type semiconductor layer 13. The electrode layer 14 may be an ohmic contact electrode electrically connected to the second conductive type semiconductor layer 13, but the present disclosure is not limited thereto.

[0081] As described above, the light emitting element LD may have a core-shell structure in which opposite ends protrude outward, and may include a first conductive type semiconductor layer 11 disposed in a central portion thereof, an active layer 12 surrounding the first conductive type semiconductor layer 11, a second conductive type semiconductor layer 13 surrounding the active layer 12, and an electrode layer 14 surrounding the second conductive type semiconductor layer 13. The first conductive type semiconductor layer 11 may be disposed on a first end of the light emitting element LD, and the electrode layer 14 may be disposed on a second end of the light emitting element LD.

[0082] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on a surface thereof. The insulating film INF may include a transparent insulating material. However, the insulating film INF may be selectively disposed and / or formed on the light emitting element LD. For example, in an embodiment, the insulating film INF may not be disposed on the surface of the light emitting element LD.

[0083] In an embodiment, the insulating film INF may be provided to cover a portion of the peripheral surface of the first conductive type semiconductor layer 11 and a portion of the peripheral surface of the electrode layer 14. In an embodiment, after first forming the insulating film INF to cover the entire peripheral surface of the electrode layer 14 included in the light emitting element LD, the insulating film INF may be partially removed to expose a region of the electrode layer 14 for electrical connection to an unillustrated electrode (e.g., a first electrode of a pixel).

[0084] The light emitting device including the above-mentioned light emitting element LD can be used in various devices requiring a light source. For example, the light emitting device can also be used in various electronic devices requiring a light source, such as a display device or a lighting device.

[0085] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 5 A display device (specifically, a display panel PNL provided in the display device) is shown as a display device that can be used according to Figures 1a to 4b The light emitting element LD of the embodiment is an example of a device as a light source. For example, each pixel PXL of the display panel PNL may have at least one light emitting element LD.

[0086] For the sake of explanation, Figure 5The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may also be provided in the display panel PNL.

[0087] refer to Figure 5 , the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area except the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0088] In an embodiment, the display area DA may be disposed in a central area of ​​the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of ​​the display panel PNL in a manner surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0089] The base layer BSL may form a substrate of the display panel PNL. In an embodiment, the base layer BSL may be a rigid substrate or a rigid film or a flexible substrate or a flexible film, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0090] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent, translucent, opaque, or reflective substrate.

[0091] One area on the base layer BSL may be defined as a display area DA in which the pixels PXL are disposed, and another area thereof may be defined as a non-display area NDA. For example, the base layer BSL may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0092] In an embodiment, a pixel PXL (also referred to as a "sub-pixel") may be disposed in each pixel region of the display area DA. In an embodiment, the pixel PXL may be arranged in the display area DA in a stripe or PenTile arrangement, but the present disclosure is not limited thereto. For example, the pixel PXL may be arranged in the display area DA in various known arrangements. In addition, each pixel PXL may be a white pixel or a pixel configured to emit light of a specific color (e.g., red, green, or blue). In the case where each pixel PXL is a pixel configured to emit light of a specific color, pixels PXL emitting light of different colors may be combined adjacent to each other to form each pixel unit (also referred to as a "unit pixel") configured to generate light of various colors.

[0093] Each pixel PXL may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power source (e.g., a first power source (or a first power source) and a second power source (or a second power source)). In an embodiment, each of the pixels PXL may include a Figures 1a to 3b At least one light emitting element LD of any one of the embodiments of the present invention, for example, at least one ultra-small rod-type light emitting element LD having a small size corresponding to the nanometer level or the micrometer level. In an embodiment, each of the pixels PXL may include a Figure 4a and Figure 4b The at least one light emitting element LD of the embodiment of the present invention has, for example, at least one ultra-small core-shell light emitting element LD having a small size corresponding to the nanometer level or micrometer level. In addition, different types of light emitting elements LD may be used as the light source of the pixel PXL.

[0094] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL that can be applied to the display device according to the present disclosure is not particularly limited. For example, each pixel PXL may have the same structure as a pixel for a passive or active light-emitting display device, which has various known structures and / or can operate with various known driving schemes.

[0095] Figure 6a to Figure 6g are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figure 6a to Figure 6g 1 and 2 show different embodiments of the pixel PXL applicable to an active display device. However, the types of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied are not limited thereto. In the embodiments, Figure 6a to Figure 6g Each pixel PXL shown in FIG. 1 may be set to Figure 5 The pixels PXL may have substantially the same or similar structures.

[0096] refer to Figure 6a The pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further selectively include a pixel circuit PXC configured to drive the light source unit LSU.

[0097] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD connected between a first power source VDD and a second power source VSS. For example, the light source unit LSU may include a first electrode ET1 (also referred to as a "first pixel electrode") connected to the first power source VDD via a pixel circuit PXC and a first power line PL1, a second electrode ET2 connected to the second power source VSS via a second power line PL2, and a plurality of light emitting elements LD connected in parallel to each other between the first electrode ET1 and the second electrode ET2 in the same direction. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0098] In an embodiment, each of the light emitting elements LD may include a P-type terminal connected to the first power supply VDD through the first electrode ET1 and / or the pixel circuit PXC and an N-type terminal connected to the second power supply VSS through the second electrode ET2. In an embodiment, the light emitting element LD may be connected in parallel between the first electrode ET1 and the second electrode ET2 in the forward direction. In this way, each of the light emitting elements LD connected between the first power supply VDD and the second power supply VSS in the forward direction may form an effective light source. A group of effective light sources may form a light source unit LSU of the pixel PXL.

[0099] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, during at least one emission cycle of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0100] In an embodiment, a first end (e.g., a P-type end) of the light emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through one electrode of the light source unit LSU of each pixel PXL (e.g., a first electrode ET1 (also referred to as a "first pixel electrode" or a "first alignment electrode") of each pixel PXL), and connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. A second end (e.g., an N-type end) of the light emitting element LD may be commonly connected to the second power supply VSS through another electrode of the light source unit LSU (e.g., a second electrode ET2 (also referred to as a "second pixel electrode" or a "second alignment electrode") of each pixel PXL) and the second power line PL2.

[0101] The light emitting element LD of the light source unit LSU may emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply the light source unit LSU with a driving current corresponding to the grayscale value of the data of the corresponding frame. The driving current supplied to the light source unit LSU may be divided into a portion flowing to the light emitting element LD connected in the forward direction. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current applied thereto, so that the light source unit LSU may emit light having a brightness corresponding to the driving current.

[0102] In an embodiment, the light source unit LSU may further include at least one ineffective light source in addition to the light emitting elements LD forming each effective light source. For example, at least one reverse light emitting element LDrv may be further connected between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0103] Each reverse light-emitting element LDrv, together with the light-emitting element LD forming an effective light source, can be connected in parallel with each other between the first electrode ET1 and the second electrode ET2, and can be connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to the direction of the light-emitting element LD. For example, the N-type end of the reverse light-emitting element LDrv can be connected to the first power supply VDD via the first electrode ET1 and the pixel circuit PXC. The P-type end of the reverse light-emitting element LDrv can be connected to the second power supply VSS via the second electrode ET2. Even when a predetermined driving voltage (for example, a driving voltage in the forward direction) is applied between the first electrode ET1 and the second electrode ET2, the reverse light-emitting element LDrv remains deactivated. Therefore, current does not substantially flow through the reverse light-emitting element LDrv.

[0104] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0105] The first transistor T1 (also referred to as a "driving transistor") is connected between the first power source VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0106] The second transistor T2 (also referred to as a "switching transistor") may be connected between the data line Dj and the first node N1. A gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0107] During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0108] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode thereof is connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0109] Despite Figure 6a The transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0110] For example, Figure 6b As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj in each frame period into the pixel PXL may be a high-level voltage (also referred to as a “gate high voltage”). Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate high voltage. Figure 6a The voltage level of the embodiment is opposite to the voltage level. For example, in Figure 6bIn an embodiment, as the grayscale value to be represented increases, a data signal with a higher voltage may be provided.

[0111] In an embodiment, the interconnection position between the pixel circuit PXC and the light source unit LSU may be changed. Figure 6b As shown in , in the case where both the first transistor T1 and the second transistor T2 forming the pixel circuit PXC are N-type transistors, the pixel circuit PXC may be connected between the light source unit LSU and the second power supply VSS, and the storage capacitor Cst may be connected between the first node N1 and the second power supply VSS. However, the present disclosure is not limited thereto. For example, in an embodiment, even in the case where the pixel circuit PXC is formed by an N-type transistor, the pixel circuit PXC may be connected between the first power supply VDD and the light source unit LSU.

[0112] In addition to the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) that vary according to the transistor types, Figure 6b The pixel PXL shown in FIG. 1 is similar in configuration and operation to the Figure 6a The pixels PXL are basically similar. Therefore, Figure 6b A detailed description of the pixel PXL.

[0113] The structure of the pixel circuit PXC is not limited to Figure 6a and Figure 6b For example, the configuration of the pixel circuit PXC may be similar to Figure 6c and Figure 6d In other words, the pixel circuit PXC may be formed of a well-known pixel circuit, which may have various structures and / or be operated by various driving schemes.

[0114] refer to Figure 6c , the pixel circuit PXC may also be connected to the control line CLi and the sensing line SENj. For example, the pixel circuit PXC of the pixel PXL disposed on the i-th row and the j-th column of the display area DA may be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. The pixel circuit PXC may further include a third transistor T3.

[0115] The third transistor T3 is connected between the first transistor T1 and the sensing line SENj. For example, the first electrode of the third transistor T3 may be connected to one electrode (e.g., the source electrode) of the first transistor T1 connected to the first electrode ET1, and the second electrode of the third transistor T3 may be connected to the sensing line SENj. In the case where the sensing line SENj is omitted, the second electrode of the third transistor T3 may be connected to the data line Dj.

[0116] In an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLi. In the case where the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 may be turned on by a control signal having a gate-on voltage (e.g., a high level voltage) provided to the control line CLi during a predetermined sensing period, and thus electrically connects the sensing line SENj to the first transistor T1.

[0117] In an embodiment, the sensing period may be a period for extracting characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL disposed in the display area DA. During the sensing period, the first transistor T1 may be turned on by providing a predetermined reference voltage capable of turning on the first transistor T1 to the first node N1 via the data line Dj and the second transistor T2 or by connecting each pixel PXL to a current source, etc. In addition, the third transistor T3 may be turned on by providing a control signal having a gate-on voltage to the third transistor T3, so that the first transistor T1 may be connected to the sensing line SENj. Therefore, characteristic information of each pixel PXL including the threshold voltage of the first transistor T1, etc. may be extracted through the sensing line SENj. The extracted characteristic information may be used to convert image data to compensate for characteristic deviations between the pixels PXL.

[0118] although Figure 6c The embodiment in which all of the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors is shown, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. Figure 6c An embodiment is shown in which the light source unit LSU is connected between the pixel circuit PXC and the second power source VSS, but the light source unit LSU may be connected between the first power source VDD and the pixel circuit PXC.

[0119] refer to Figure 6d , the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged on the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to the third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0120] The first transistor T1 is connected between the first power source VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to the first electrode ET1 of the light source unit LSU (e.g., the first pixel electrode of the corresponding pixel PXL) through the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control the driving current to be provided to the light source unit LSU in response to the voltage of the first node N1.

[0121] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the data line Dj may be transmitted to the first transistor T1.

[0122] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the third transistor T3 can be turned on to connect the first transistor T1 in a diode form.

[0123] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 can be the lowest voltage of the data signal or less.

[0124] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having a gate cut-off voltage (for example, a high level voltage) is provided to the emission control line Ei, the fifth transistor T5 can be turned off, and the fifth transistor T5 can be turned on in other cases.

[0125] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having the gate-off voltage is provided to the emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0126] The seventh transistor T7 is connected between the first electrode ET1 of the light source unit LSU (for example, the first pixel electrode of the corresponding pixel PXL) and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage (the subsequent horizontal pixel column), for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode ET1 of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode ET1 of the light source unit LSU may be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 may be connected to the scan line of the corresponding horizontal line, that is, the i-th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode ET1 of the light source unit LSU.

[0127] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0128] Despite Figure 6d The transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0129] although Figures 6a to 6d 1 shows an embodiment in which all effective light sources (ie, light emitting elements LD) constituting each light source unit LSU are connected in parallel to each other, but the present disclosure is not limited thereto. Figure 6e to Figure 6g As shown in , the light source unit LSU of each pixel PXL may be configured to include a series connection structure. Figure 6e to Figure 6g In the following description of the implementation method of Figures 6a to 6d Detailed explanation of components similar or identical to those of the embodiments (e.g., pixel circuit PXC).

[0130] refer to Figure 6e , the light source unit LSU may include at least two light emitting elements connected in series to each other. For example, the light source unit LSU may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3 which are connected in series between a first power supply VDD and a second power supply VSS in a forward direction and thus form each effective light source. Hereinafter, in the case of specifying a specific light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, the corresponding light emitting element will be referred to as "first light emitting element LD1", "second light emitting element LD2", or "third light emitting element LD3". The term "light emitting element (light emitting element) LD" or "light emitting elements (light emitting elements) LD" will be used to arbitrarily specify at least one light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, or to collectively specify the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3.

[0131] The P-type end of the first light emitting element LD1 may be connected to the first power source VDD through the first electrode ET1 of the light source unit LSU, etc. The N-type end of the first light emitting element LD1 may be connected to the P-type end of the second light emitting element LD2 through the first intermediate electrode IET1. The P-type end of the second light emitting element LD2 may be connected to the N-type end of the first light emitting element LD1. The N-type end of the second light emitting element LD2 may be connected to the P-type end of the third light emitting element LD3 through the second intermediate electrode IET2. The P-type end of the third light emitting element LD3 may be connected to the N-type end of the second light emitting element LD2. The N-type end of the third light emitting element LD3 may be connected to the second power source VSS through the second electrode ET2 of the light source unit LSU and the second power line PL2. In this way, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be continuously connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0132] Despite Figure 6e , the light emitting elements LD are connected to form a three-stage series structure, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light emitting elements LD may be connected to form a two-stage series structure, or four or more light emitting elements LD may be connected to form a four-stage or more series structure.

[0133] Assuming that the same brightness is expressed using light emitting elements LD having the same conditions (e.g., the same size and / or number), in the light source unit LSU having a structure in which the light emitting elements LD are connected in series, the voltage applied between the first electrode ET1 and the second electrode ET2 can be increased, and the amount of driving current flowing to the light source unit LSU can be reduced, compared to the light source unit LSU having a structure in which the light emitting elements LD are connected in parallel. Therefore, in the case where the series connection structure of the light emitting elements LD is used for the light source unit LSU forming each pixel PXL, when the display device is driven, the panel current flowing through the display panel PNL can be reduced.

[0134] In an embodiment, at least one series stage may include a plurality of light emitting elements LD connected in parallel to each other. In this case, the light source unit LSU may be formed by a series / parallel combination structure. For example, the light source unit LSU may be as follows: Figure 6f Configured as shown in the embodiment.

[0135] refer to Figure 6f , at least one series connection stage forming the light source unit LSU may include a plurality of light emitting elements LD connected in parallel with each other in the forward direction. For example, the light source unit LSU may include a plurality of first light emitting elements LD1 arranged in a first series connection stage (also referred to as a "first stage" or a "first row"), at least one second light emitting element LD2 arranged in a second series connection stage (also referred to as a "second stage" or a "second row") after the first series connection stage, and at least one third light emitting element LD3 arranged in a third series connection stage (also referred to as a "third stage" or a "third row") after the second series connection stage.

[0136] Despite Figure 6f , a light source unit LSU is shown which is formed by light emitting elements LD arranged in three series stages, but the present disclosure is not limited thereto. Figure 6g As shown in , the light source unit LSU may include a plurality of light emitting elements LD disposed in only two series stages. For example, the light source unit LSU may include at least one first light emitting element LD1 disposed in the first series stage and having a P-type terminal and an N-type terminal connected to the first electrode ET1 and the intermediate electrode IET, respectively, and at least one second light emitting element LD2 disposed in the second series stage and having a P-type terminal and an N-type terminal connected to the intermediate electrode IET and the second electrode ET2, respectively.

[0137] In addition, the number of series stages forming the light source unit LSU may be changed in various ways. For example, the light source unit LSU may include a plurality of light emitting elements LD distributed in four or more series stages. In addition, the number of light emitting elements LD connected in the forward direction in each series stage may be changed in various ways. In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD distributed in four or more series stages. Figure 5 The number of light-emitting elements LD included in the pixels PXL in the DA) may be the same or similar to each other. For example, in the step of providing the light-emitting element LD to each pixel PXL, the light-emitting element LD may be aligned in such a way that the light-emitting element ink (or also referred to as "light-emitting element solution") including the light-emitting element LD is controlled to be uniformly applied to the emission area of ​​each pixel PXL, and the electric field is controlled to be applied to each pixel PXL under uniform conditions. In this way, the light-emitting element LD can be relatively uniformly provided to each pixel PXL and aligned in each pixel PXL.

[0138] In an embodiment, if Figure 6f and Figure 6g As shown in , each pixel PXL may further include at least one reverse light emitting element LDrv disposed in at least one series stage. For example, at least one of the plurality of series stages may further include at least one reverse light emitting element LDrv connected in a direction opposite to that of the light emitting element LD.

[0139] Even in the case where the reverse light emitting element LDrv is connected to at least one series stage, in the case where at least one effective light source (e.g., the first light emitting element LD1, the second light emitting element LD2, and / or the third light emitting element LD3) connected to the series stage in the forward direction is provided, the driving current of the pixel PXL can continuously flow through the series stage. Therefore, the light source unit LSU can emit light at a brightness corresponding to the driving current.

[0140] As described in the foregoing embodiments, each light source unit LSU may include a plurality of light emitting elements LD connected between a first power source VDD and a second power source VSS in a forward direction and forming a corresponding effective light source. In addition, the connection structure between the light emitting elements LD may be changed in various ways according to the embodiments. For example, the light emitting elements LD may be connected to each other only in series or in parallel or in a series / parallel combination structure.

[0141] As described above, the pixel PXL may include a pixel circuit PXC and / or a light source unit LSU that may have various structures. The structure of the pixel PXL that may be applied to the present disclosure is not limited to Figure 6a to Figure 6g , and each pixel PXL may have various known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0142] Figure 7 is a plan view showing a pixel PXL according to an embodiment of the present disclosure. In the embodiment, Figure 7 Each pixel PXL shown in FIG. 1 may be Figure 5 to Figure 6g Any one of the pixels PXL shown in . For example, Figure 7 Each pixel PXL shown in FIG. 1 may be Figures 6a to 6d As shown in the embodiment of FIG. 1 , the pixel PXL includes a light source unit LSU having a parallel structure. In the embodiment, Figure 7 The structure of each pixel PXL is illustrated focusing on the light source unit LSU. In an embodiment, each pixel PXL may further selectively include a circuit element connected to the light source unit LSU (eg, a plurality of circuit elements forming each pixel circuit PXC).

[0143] also, Figure 7 An embodiment in which each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj) through a first contact hole CH1 and a second contact hole CH2 is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ET1 and the second electrode ET2 of each pixel PXL may be directly connected to a predetermined power line and / or a signal line without using, for example, a contact hole and / or an intermediate line.

[0144] refer to Figures 5 to 7 , a plurality of pixels PXL may be regularly arranged in the display area DA. For example, a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and a third pixel PXL3 configured to emit light of a third color may be continuously arranged in the display area DA in the first direction DR1. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 adjacent to each other may be combined to form a pixel unit capable of emitting light of various colors. Although Figure 7 An embodiment in which the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 are continuously disposed in the first direction DR1 (eg, the row direction) is shown, but the arrangement structure of the pixels PXL disposed in the display area DA may be changed in various ways.

[0145] In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a red pixel, a green pixel, and a blue pixel, respectively, but the present disclosure is not limited thereto. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light emitting element LD that emits light of different colors, so that the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may emit light of different colors. The color of light emitted from each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be changed in various ways according to the embodiment.

[0146] In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be predetermined color pixels configured to emit light of the same color. Color conversion layers and / or color filters having different colors may be disposed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, so that light of different colors may be controlled to be emitted from the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 to the outside of the display panel PNL. The number and / or type of pixels PXL forming each pixel unit may be changed in various ways according to an embodiment.

[0147] In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures. For the sake of explanation, the structure of the first pixel PXL1 will be focused on. Figure 7 Let's describe the structure of each pixel PXL.

[0148] In this specification, in order to specify a specific pixel among the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, the corresponding pixel will be referred to as "the first pixel PXL1", "the second pixel PXL2", or "the third pixel PXL3". The term "pixel PXL" or "pixels PXL" will be used to arbitrarily specify at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 or to collectively specify the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0149] Each pixel PXL may include first and second electrodes ET1 and ET2, each of which is disposed to overlap a corresponding emission area EMA, and a plurality of light emitting elements LD electrically connected between the first and second electrodes ET1 and ET2. The first and second electrodes ET1 and ET2 and the light emitting elements LD may form a light source unit LSU of each pixel PXL.

[0150] The emission area EMA of each pixel PXL may be an area in which an effective light source (i.e., a light emitting element LD) of the light source unit LSU for forming the pixel PXL is disposed. The first electrode ET1 and the second electrode ET2 electrically connected to the light emitting element LD may be further disposed in the emission area EMA. In an embodiment, each emission area EMA may be an area surrounded by an opaque dam (also referred to as a "pixel defining layer") not shown. For example, in the display area DA, a mesh dam (not shown) including a plurality of openings may be formed to correspond to the emission area EMA of each pixel PXL. The dam may define each emission area EMA and prevent light from leaking between the pixels PXL.

[0151] The first electrode ET1 may be a planar electrode having a shape and / or size corresponding to the shape and / or size of each emission area EMA. Here, the present disclosure is not limited thereto. The first electrode ET1 may have a predetermined shape regardless of the shape of the emission area EMA.

[0152] In an embodiment, the first electrode ET1 may be a rectangular planar electrode having a width in the first direction DR1 (or in the second direction DR2) and a length in the second direction DR2 (or in the first direction DR1). In an embodiment, the first electrode ET1 may be a flat plate electrode having a polygonal shape other than a rectangular shape, a circular or elliptical flat plate electrode, or a flat plate electrode including a combination of a boundary of a linear line and a curve. In an embodiment, the first electrode ET1 may be a mesh electrode including a plurality of openings. In other words, the shape and / or structure of the first electrode ET1 may be changed in various ways according to the embodiment.

[0153] In an embodiment, the first electrode ET1 may have a separate pattern for each of the pixels PXL. The first electrode ET1 may be electrically connected to a first electrode line ETL1 (also referred to as a "first alignment line" or a "first connection line"), and may be electrically connected to the pixel circuit PXC and / or the first power supply VDD through the first electrode line ETL1 and / or the first contact hole CH1. In an embodiment, the first electrode ET1 and the first electrode line ETL1 may be connected to each other integrally or non-integrally. In the case where the first electrode ET1 and the first electrode line ETL1 are connected to each other integrally, the first electrode ET1 and the first electrode line ETL1 may be considered as different regions of a single electrode, line or pattern.

[0154] The second electrode ET2 may be disposed in each emission region EMA and overlap each first electrode ET1. In an embodiment, the second electrode ET2 may be disposed on a layer different from that of the corresponding first electrode ET1 at a position spaced apart from the first electrode ET1. For example, the second electrode ET2 may be disposed on a layer different from that of the first electrode ET1, and the light emitting element LD disposed in each emission region EMA is interposed therebetween. For example, the first electrode ET1 may be disposed below the light emitting element LD, and the second electrode ET2 may be disposed above the light emitting element LD.

[0155] In an embodiment, the second electrode ET2 may be a planar electrode having a shape and / or size corresponding to the shape and / or size of the corresponding first electrode ET1. For example, the first electrode ET1 and the second electrode ET2 of each pixel PXL may have shapes and / or sizes corresponding to each other at least in the emission area EMA and overlap each other. Here, the present disclosure is not limited thereto. The second electrode ET2 may have a predetermined shape regardless of the shape of the emission area EMA.

[0156] In an embodiment, the second electrode ET2 may be a flat plate electrode having a polygonal shape including a rectangular shape, a circular or elliptical flat plate electrode, or a flat plate electrode including a combination of a boundary of a linear line and a curve. In an embodiment, the second electrode ET2 may be a mesh electrode including a plurality of openings. In other words, the shape and / or structure of the second electrode ET2 may be changed in various ways according to the embodiment.

[0157] In an embodiment, the second electrode ET2 may be electrically connected to a second electrode line ETL2 (also referred to as a "second alignment line" or a "second connection line"), and may be electrically connected to a second power supply VSS through the second electrode line ETL2 and / or the second contact hole CH2. In an embodiment, the second electrode ET2 and the second electrode line ETL2 may be connected to each other integrally or non-integrally. In the case where the second electrode ET2 and the second electrode line ETL2 are connected to each other integrally, the second electrode ET2 and the second electrode line ETL2 may be considered as different regions of a single electrode, line, or pattern.

[0158] In an embodiment, the second electrodes ET2 of the pixels PXL may be connected to each other integrally or non-integrally. For example, the second electrodes ET2 of the pixels PXL may be electrically connected to each other through the second electrode line ETL2 connected thereto.

[0159] The first electrode line ETL1 may be connected between the first power line PL1 and the first electrode ET1. The first electrode line ETL1 may receive a voltage of a first power source VDD (or a first drive signal, such as a scan signal, a data signal, or a predetermined other control signal) provided from the first power line PL1 during a period in which the display device is driven, and transmit the voltage of the first power source VDD to the first electrode ET1. In an embodiment, the first electrode line ETL1 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through a first contact hole CH1. For example, the first electrode line ETL1 may be electrically connected to a predetermined circuit element disposed thereunder through the first contact hole CH1, and connected to the first power line PL1 through the circuit element. For example, each pixel PXL may also include a pixel circuit PXC connected between the first electrode line ETL1 and the first power source VDD. In an embodiment, the pixel circuit PXC may be disposed under each light source unit LSU and electrically connected to the first electrode line ETL1 of the light source unit LSU through the first contact hole CH1. In an embodiment, the first electrode line ETL1 may be connected to a signal line provided with a predetermined first driving signal via the first contact hole CH1 or the like. In an embodiment, the first electrode line ETL1 may be directly connected to the first power line PL1 or the predetermined signal line without using the first contact hole CH1 and / or the circuit element. In this case, the first electrode line ETL1 may be connected to the first power line PL1 or the predetermined signal line in an integral or non-integrated manner.

[0160] In an embodiment, the first electrode line ETL1 connected to each first electrode ET1 of the pixel PXL may first be manufactured to be commonly connected to the first electrodes ET1 of the plurality of pixels PXL, and may be provided with a first alignment signal (or a first alignment voltage) in the step of aligning the light emitting element LD. Thereafter, the first electrode line ETL1 between the pixels PXL may be disconnected so that the pixels PXL may be manufactured to be individually operable. For example, the first electrode lines ETL1 of the pixels PXL may be separated from each other between adjacent pixels PXL.

[0161] The second electrode line ETL2 may be connected between the second power line PL2 and the second electrode ET2. The second electrode line ETL2 may receive the voltage of the second power supply VSS (or a second drive signal, such as a scan signal, a data signal, or a predetermined other control signal) during a period in which the display device is driven, and transmit the voltage of the second power supply VSS to the second electrode ET2. In an embodiment, the second electrode line ETL2 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through a second contact hole CH2. For example, the second electrode line ETL2 may be connected to a second power line PL2 disposed thereunder through a second contact hole CH2. In an embodiment, the second electrode line ETL2 may be directly connected to the second power line PL2 or a predetermined signal line without using, for example, a second contact hole CH2 and / or a circuit element. In this case, the second electrode line ETL2 may be connected to the second power line PL2 or a predetermined signal line in one piece or in a non-one piece.

[0162] In the step of aligning the light emitting element LD, the second electrode line ETL2 may be provided with a predetermined second alignment signal (or second alignment voltage). During a period of actually driving the display device, the second electrode line ETL2 may be provided with a voltage of a second power source VSS or a predetermined second driving signal.

[0163] For example, the first electrode line ETL1 and the second electrode line ETL2 may be alignment lines, which are provided with a predetermined alignment signal to be applied to each light source unit LSU in the step of aligning the light emitting element LD in each pixel PXL to manufacture the display device, and the alignment lines are arranged on a path along which an alignment current corresponding to the alignment signal flows. In addition, the first electrode line ETL1 and the second electrode line ETL2 may be connecting lines, which are provided with a predetermined driving voltage to be applied to each light source unit LSU in the step of driving the display device (for example, when the display device is used), and the connecting lines are arranged on a path along which a driving current of each pixel PXL flows.

[0164] The first insulating layer INS1 and the light emitting element LD may be disposed between the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may include a plurality of openings OPN (also referred to as "through holes" or "alignment holes"), which define corresponding cells in the emission area EMA of each pixel PXL. Each light emitting element LD may be disposed in any one of the openings OPN. Although Figure 7An embodiment in which only one light emitting element LD is disposed in each opening OPN is shown, but the present disclosure is not limited thereto. For example, a plurality of light emitting elements LD may be disposed in at least one opening OPN, or no light emitting element LD may be disposed in the opening OPN.

[0165] The first insulating layer INS1 may be disposed on the first electrode ET1 of each pixel PXL and include a plurality of openings OPN that expose various different regions of the first electrode ET1 and define various units. In an embodiment, the first insulating layer INS1 may be formed on the entire surface of the display area DA, but the present disclosure is not limited thereto. For example, in an embodiment, each first insulating layer INS1 may be individually formed in the emission area EMA of each pixel PXL. In other words, in an embodiment, the first insulating layer INS1 may be formed in the form of an individual pattern individually provided for each of the pixels PXL.

[0166] In an embodiment, each opening OPN may be formed to have a width (or diameter) that is the same as or greater than the width (or diameter) of each light emitting element LD and less than the length of each light emitting element LD. In this case, each light emitting element LD may be disposed to stand vertically or diagonally in any one opening OPN so that the light emitting element LD is arranged in a vertical direction or a diagonal direction relative to the first electrode ET1 and the second electrode ET2.

[0167] In an embodiment, the opening OPN may have various shapes and / or arrangement structures. For example, in a plan view, the openings OPN may each have a polygonal shape, a circular shape, an elliptical shape, or a combination thereof, and may be arranged adjacent to each other in the emission area EMA of each pixel PXL. For example, in a plan view, the openings OPN may each have a hexagonal shape, and may be arranged adjacent to each other in the emission area EMA of each pixel PXL. For example, the first insulating layer INS1 may have a honeycomb structure including a plurality of hexagonal cells defined by the openings OPN in each emission area EMA. At least one light emitting element LD may be arranged in at least some of these cells. If the openings OPN are densely arranged adjacent to each other in each emission area EMA, limited space may be used more efficiently. For example, when the openings OPN are densely arranged, space that can accommodate a greater number of light emitting elements LD may be ensured compared to the surface area of ​​the emission area EMA.

[0168] Each of the light emitting elements LD may be disposed in a cell defined by any one of the openings OPN. In an embodiment, each of the light emitting elements LD may include a first end EP1 electrically connected to the first electrode ET1 and a second end EP2 protruding upward from the first insulating layer INS1. In an embodiment, the second electrode ET2 may be disposed above the light emitting element LD. The second electrode ET2 may be electrically connected to the second end EP2 of the light emitting element LD protruding upward from the first insulating layer INS1.

[0169] In an embodiment, each light emitting element LD may be a light emitting element having a core-shell structure. Figure 4a and Figure 4b As shown in , each light emitting element LD may be a core-shell light emitting element having a polygonal pyramid (eg, a hexagonal pyramid) shape.

[0170] In addition, each light emitting element LD may include a first end EP1 and a second end EP2, the first end EP1 being arranged to face the first electrode ET1, and the second end EP2 being located at a position opposite to the first end EP1 and arranged to face the second electrode ET2. In an embodiment, the first end EP1 may be a P-type end, and the second end EP2 may be an N-type end, but the present disclosure is not limited thereto. For example, in an embodiment, the first end EP1 may be an N-type end, and the second end EP2 may be a P-type end.

[0171] In the pixel PXL and the display device including the pixel PXL according to the aforementioned embodiment, a plurality of openings OPN may be formed in the first insulating layer INS1, and the light emitting element LD may be disposed to stand between the first electrode ET1 and the second electrode ET2 by using the openings OPN. Therefore, a process limitation occurring when the light emitting element LD is horizontally aligned may be overcome, and the light emitting element LD may be reliably connected between the first electrode ET1 and the second electrode ET2.

[0172] Figure 8 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 In an embodiment, Figure 8 Only one transistor (eg, first transistor T1 ) and storage capacitor Cst among circuit elements disposed in each pixel region of the circuit element layer PCL are representatively shown. In an embodiment, transistors forming each pixel circuit PXC may have substantially the same or similar structures, but the present disclosure is not limited thereto.

[0173] refer to Figures 5 to 8According to an embodiment of the present disclosure, the pixel PXL and the display device including the pixel PXL may include a display element layer DPL, and the display element layer DPL includes a plurality of light-emitting elements LD arranged in the emission area EMA of each pixel PXL. The pixel PXL and the display device including the pixel PXL may also selectively include at least one of a circuit element layer PCL (also referred to as a "pixel circuit layer") and a covering layer CVL. For example, the pixel PXL and the display device including the pixel PXL may include a circuit element layer PCL, a display element layer DPL, and a covering layer CVL sequentially arranged on one surface of the base layer BSL. In an embodiment, the circuit element layer PCL and / or the covering layer CVL may be omitted.

[0174] The circuit element layer PCL may include at least one circuit element electrically connected to the light emitting element LD of the corresponding pixel PXL. For example, the circuit element layer PCL may include at least one circuit element forming the pixel circuit PXC of each pixel PXL.

[0175] For example, the circuit element layer PCL may include a plurality of transistors and storage capacitors Cst disposed in each pixel region and forming a corresponding pixel circuit PXC, and also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, the term "pixel region" may comprehensively refer to a region in which components for constituting each pixel PXL are disposed and / or formed. For example, each pixel region may include an emission region EMA, in which the first electrode ET1 and the second electrode ET2 of the light source unit LSU forming the corresponding pixel PXL and a plurality of light emitting elements LD connected between the first electrode ET1 and the second electrode ET2 are disposed. Each pixel region may also selectively include a pixel circuit region, in which a circuit element electrically connected to the light emitting element LD (e.g., a plurality of transistors and at least one capacitor forming each pixel circuit PXC) is disposed. For example, when each pixel PXL includes a light source unit LSU and a pixel circuit PXC connected thereto, each pixel region may include an emission region EMA and a pixel circuit region.

[0176] Here, in the case where the pixel circuit PXC is omitted and each light source unit LSU is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the circuit element layer PCL may be omitted. For the sake of explanation, Figure 8A transistor (e.g., first transistor T1) connected to each first electrode ET1 and a power line (e.g., second power line PL2) connected to each second electrode ET2 among the circuit elements and lines provided in the circuit element layer PCL are representatively shown. Here, the plane / cross-sectional structure of the circuit element layer PCL may be changed in various ways. The position and cross-sectional structure of each of the transistors including the first transistor T1 may be changed in various ways according to the embodiment.

[0177] In addition, the circuit element layer PCL may include a plurality of insulating layers disposed between the respective electrodes and / or lines. In an embodiment, the circuit element layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer BSL. In some embodiments, the circuit element layer PCL may further include at least one light shielding pattern (not shown) disposed under at least some of the transistors.

[0178] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least a double layer. In the case where the buffer layer BFL is formed of a multilayer, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0179] The first transistor T1 may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE1 and TE2. Figure 8 The embodiment in which the first transistor T1 includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in the first transistor T1 may be integrated with the corresponding semiconductor layer SCL.

[0180] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0181] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0182] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap a region of the semiconductor layer SCL.

[0183] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD is interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on respective different ends of the semiconductor layer SCL, and the gate insulating layer GI and the interlayer insulating layer ILD are interposed therebetween. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of the semiconductor layer SCL through respective contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0184] At least one transistor disposed in the pixel circuit PXC may be electrically connected to a first electrode ET1 or a second electrode ET2 of at least one corresponding pixel PXL. For example, any one (e.g., a drain electrode) of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 may be electrically connected to the first electrode ET1 of the corresponding pixel PXL through a first contact hole CH1 passing through the passivation layer PSV and / or a first electrode line ETL1 disposed on the passivation layer PSV.

[0185] The storage capacitor Cst may include a first capacitor electrode CET1 and a second capacitor electrode CET2 that overlap each other. In an embodiment, each of the first capacitor electrode CET1 and the second capacitor electrode CET2 may be formed of a single layer or multiple layers. In addition, at least one of the first capacitor electrode CET1 and the second capacitor electrode CET2 may be disposed on the same layer as at least one electrode of the first transistor T1 or a layer of the semiconductor layer SCL.

[0186] For example, the first capacitor electrode CET1 may be formed of a multilayer electrode including a lower electrode LE disposed on the same layer as that of the semiconductor layer SCL of the first transistor T1 and an upper electrode UE disposed on the same layer as that of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. The second capacitor electrode CET2 may be formed of a single-layer electrode disposed on the same layer as that of the gate electrode GE of the first transistor T1 and overlapping the lower electrode LE and the upper electrode UE of the first capacitor electrode CET1.

[0187] Here, the present disclosure is not limited thereto. The structure and / or position of each of the first capacitor electrode CET1 and the second capacitor electrode CET2 may be changed in various ways. For example, in an embodiment, any one of the first capacitor electrode CET1 and the second capacitor electrode CET2 may include at least one conductive pattern layer disposed on a layer different from a layer forming an electrode of the first transistor T1 (e.g., a gate electrode GE and a first transistor electrode TE1 and a second transistor electrode TE2) and a semiconductor layer SCL.

[0188] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be arranged on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be arranged on the same layer as the layer of the gate electrode GE of the first transistor T1. The data line Dj of each pixel PXL may be arranged on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1. In addition, the first power line PL1 and / or the second power line PL2 may be arranged on the same layer as the gate electrode GE of the first transistor T1 or the first transistor electrode TE1 and the second transistor electrode TE2. For example, the second power line PL2 for providing the voltage of the second power supply VSS may be arranged on the same layer as the layer of the gate electrode GE of the first transistor T1, and is electrically connected to the second electrode ET2 and / or the second electrode line ETL2 of the light source unit LSU through the bridge pattern BRP arranged on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and through the second contact hole CH2 at least passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2 and the like may be changed in various ways.

[0189] The display element layer DPL may include a light source unit LSU for each of the pixels PXL. For example, the display element layer DPL may include a first electrode ET1 and a second electrode ET2, a first insulating layer INS1 and a light emitting element LD, the first electrode ET1 and the second electrode ET2 being arranged in the emission area EMA of each pixel PXL and overlapping each other, the first insulating layer INS1 and the light emitting element LD being arranged between the first electrode ET1 and the second electrode ET2. In addition, the display element layer DPL may further include at least one contact electrode configured to more reliably connect the light emitting element LD to the first electrode ET1 or the second electrode ET2. For example, the display element layer DPL may further include a plurality of first contact electrodes CE1, the plurality of first contact electrodes CE1 being in contact with the corresponding first end EP1 of the light emitting element LD and the first electrode ET1. In addition, the display element layer DPL may further selectively include at least one insulating layer and / or insulating pattern. For example, the display element layer DPL may further include a plurality of insulating patterns INP embedded in the corresponding openings OPN, a second insulating layer INS2 inserted between the first insulating layer INS1 and the second electrode ET2, and at least one of a third insulating layer INS3 arranged on the second electrode ET2 to cover the second electrode ET2.

[0190] The first electrode ET1 may be disposed on one surface of the base layer BSL. For example, the first electrode ET1 may be disposed on one surface of the base layer BSL on which the circuit element layer PCL is formed.

[0191] The first electrode ET1 may include at least one conductive material. For example, the first electrode ET1 may include at least one metal among various metal materials, at least one material among conductive oxides and conductive polymers, the various metal materials include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or their alloys, and the conductive oxides include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO 2), a conductive polymer such as PEDOT, but the present disclosure is not limited thereto. For example, the first electrode ET1 may include other conductive materials, including carbon nanotubes, graphene, and the like. In other words, the first electrode ET1 may include at least one of various conductive materials to have conductivity, and its constituent materials are not particularly limited. In other words, the first electrode ET1 may be a reflective electrode, a transparent electrode, or an opaque electrode, and its material or properties are not particularly limited as long as it can provide satisfactory conductivity. For example, the constituent materials, structure, thickness, and the like of the first electrode ET1 may be determined by comprehensively considering contrast, light efficiency, and the like. For example, when the first electrode ET1 is formed by a reflective electrode including at least one reflective electrode layer, the light output efficiency of the pixel PXL may be improved.

[0192] In an embodiment, the first electrode ET1 may be formed of a single layer or multiple layers. For example, the first electrode ET1 may include a reflective electrode layer having a reflective conductive material. In addition, the first electrode ET1 may also selectively include at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0193] In an embodiment, the reflective electrode layer of the first electrode ET1 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials, and the various metal materials include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or their alloys, but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. In the case where the first electrode ET1 includes the reflective electrode layer, the light emitted from the light emitting element LD can travel more effectively in the direction of displaying the image (e.g., the forward direction).

[0194] In addition, the transparent electrode layer of the first electrode ET1 can be formed of various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, the first electrode ET1 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ET1 is formed of a multilayer having at least two layers, the voltage drop caused by signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting element LD.

[0195] In addition, if the first electrode ET1 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ET1 can be prevented from being damaged due to defects caused in the process of manufacturing the pixel PXL. However, the conductive capping layer can be selectively included in the first electrode ET1, and the conductive capping layer can be omitted in some embodiments. In addition, the conductive capping layer can be considered as a component of the first electrode ET1 or a separate component disposed on the first electrode ET1.

[0196] The first insulating layer INS1 may be disposed on the first electrode ET1. For example, the first insulating layer INS1 may be formed to cover a predetermined region of the first electrode ET1 and include a plurality of openings OPN exposing other predetermined regions of the first electrode ET1. The openings OPN may expose different predetermined regions of the first electrode ET1 and define corresponding cells for accommodating corresponding light emitting elements LD.

[0197] The first insulating layer INS1 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or organic insulating material. For example, the first insulating layer INS1 may include various known types of inorganic insulating materials and / or organic insulating materials, and the constituent material of the first insulating layer INS1 is not particularly limited.

[0198] In an implementation, the first insulating layer INS1 may include at least one organic layer. In this case, an upper surface of the first insulating layer INS1 may be substantially flat.

[0199] A plurality of light emitting elements LD may be provided to each pixel region (specifically, an emission region EMA of each pixel PXL in which the first insulating layer INS1 is formed) and aligned in each pixel region. For example, a plurality of light emitting elements LD may be provided to each emission region EMA by an inkjet scheme, a slit coating scheme, or the like. Thereafter, by applying a predetermined alignment signal (or alignment voltage) to the first electrode ET1 and an alignment electrode (not shown) provided on the first insulating layer INS1, the light emitting element LD may be aligned in the vertical direction or the diagonal direction in each opening OPN. In an embodiment, the alignment electrode may be formed on the first insulating layer INS1 before aligning the light emitting element LD, and then removed after the alignment of the light emitting element LD is completed.

[0200] Each of the light emitting elements LD may include a first end EP1 electrically connected to the first electrode ET1 and a second end EP2 electrically connected to the second electrode ET2. In an embodiment, the first end EP1 of the light emitting element LD may be in direct contact with the first electrode ET1 and thus electrically connected to the first electrode ET1. However, the present disclosure is not limited thereto. For example, the first end EP1 of at least one of the light emitting elements LD may be electrically connected to the first electrode ET1 through the first contact electrode CE1, rather than being in direct contact with the first electrode ET1.

[0201] Likewise, the second end EP2 of the light emitting element LD may be in direct contact with the second electrode ET2 and thus electrically connected to the second electrode ET2. However, the present disclosure is not limited thereto. For example, the second end EP2 of at least one of the light emitting elements LD may be electrically connected to the second electrode ET2 via at least one electrode (e.g., a second contact electrode not shown) rather than in direct contact with the second electrode ET2.

[0202] The first contact electrode CE1 may be embedded in the corresponding opening OPN and contact the first electrode ET1 of each pixel PXL and the first end EP1 of the light emitting element LD. If the first contact electrode CE1 is formed, the first end EP1 of the light emitting element LD may be more reliably connected to the first electrode ET1.

[0203] The first contact electrode CE1 may include at least one conductive material that is the same as or different from that of the first electrode ET1, and its constituent material is not particularly limited. In addition, each of the first contact electrodes CE1 may be formed of a single layer or multiple layers, and its structure may be variously changed.

[0204] In an implementation, the first contact electrode CE1 may be formed of a transparent electrode including a transparent conductive material. In this case, light emitted from the corresponding first end EP1 of the light emitting element LD may pass through the first contact electrode CE1.

[0205] The insulating pattern INP may be included in each opening OPN to cover each predetermined area of ​​the first end EP1 of the light emitting element LD and the first contact electrode CE1. For example, the insulating pattern INP may be formed in the opening OPN in which the light emitting element LD and the first contact electrode CE1 are formed, so that the insulating pattern INP may at least partially surround the first end EP1 of the light emitting element LD. If the insulating pattern INP is formed, the first end EP1 of the light emitting element LD may be prevented or mitigated from being damaged during a subsequent process after the light emitting element LD is aligned.

[0206] In an embodiment, each of the insulating patterns INP may include at least one organic insulating material and be formed of a single layer or multiple layers. For example, each of the insulating patterns INP may include at least one organic layer. In this case, during the process of forming the insulating pattern INP, the organic insulating material may be smoothly introduced into each of the openings OPN, thereby preventing the first end EP1 of the light emitting element LD from being damaged during subsequent processes.

[0207] The second insulating layer INS2 may be disposed between the first insulating layer INS1 and the second electrode ET2 and surround the exposed sidewall of the light emitting element LD. If the second insulating layer INS2 is formed, a short circuit defect between the first electrode ET1 and the second electrode ET2 may be effectively prevented and the light emitting element LD may be more reliably supported.

[0208] In an embodiment, the second insulating layer INS2 may include at least one organic insulating material and be formed of a single layer or a plurality of layers. For example, the second insulating layer INS2 may include at least one organic layer. In this case, during the process of forming the second insulating layer INS2, the organic insulating material may be smoothly introduced into each of the openings OPN. For example, a portion of the second insulating layer INS2 may be introduced into the openings OPN to surround the light emitting element LD and completely fill the space formed in the openings OPN. Therefore, the electrical stability between the first electrode ET1 and the second electrode ET2 may be ensured, and the light emitting element LD may be reliably supported.

[0209] The second electrode ET2 may be disposed on the light emitting element LD to cover an upper portion of the light emitting element LD. For example, the second electrode ET2 may be disposed on the light emitting element LD to completely cover the second end EP2 of the light emitting element LD that is exposed upward from the first insulating layer INS1 and the second insulating layer INS2. In addition, the second electrode ET2 may be electrically connected to the second power line PL2 through the bridge pattern BRP and / or the second contact hole CH2 that passes through the passivation layer PSV, the first insulating layer INS1, and the second insulating layer INS2. Therefore, the voltage of the second power supply VSS may be applied to the second end EP2 of the light emitting element LD.

[0210] The second electrode ET2 may include at least one conductive material. For example, the second electrode ET2 may include at least one conductive material that is the same as or different from the conductive material of the first electrode ET1, and may be formed of a single layer or multiple layers.

[0211] In an embodiment, the second electrode ET2 may be formed of a transparent electrode including at least one transparent conductive material to allow light to pass through the second electrode ET2. For example, in the case where the display panel PNL is a front-emitting display panel PNL that emits light in an upward direction of the second electrode ET2, the second electrode ET2 may be substantially transparent. Here, the term "substantially transparent" may mean that light is allowed to be transmitted to meet a predetermined degree or greater of transmittance.

[0212] In an embodiment, the second electrode ET2 may include at least one opaque conductive material and be formed to be substantially transparent by having a mesh structure having a plurality of holes that allow light to pass through or having a very small thickness. In other words, in order to allow light emitted from the light emitting element LD to pass through the second electrode ET2, the constituent material, structure and / or thickness of the second electrode ET2 may be adjusted accordingly.

[0213] The third insulating layer INS3 may be disposed on the second electrode ET2. For example, the third insulating layer INS3 may be formed on the entire surface of the display area DA to cover the second electrode ET2 of the pixel PXL.

[0214] The third insulating layer INS3 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or organic insulating material. For example, the third insulating layer INS3 may include various known organic / inorganic insulating materials, including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ) etc. The constituent material of the third insulating layer INS3 is not particularly limited.

[0215] In an embodiment, the third insulating layer INS3 may include a thin film encapsulation layer having a multi-layer structure. For example, the third insulating layer INS3 may be formed of a thin film encapsulation layer having a multi-layer structure including at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. Here, the constituent material and / or structure of the third insulating layer INS3 may be changed in various ways.

[0216] The cover layer CVL may be selectively disposed on the third insulating layer INS3. In an embodiment, the cover layer CVL may include an overcoat layer OC, a window, etc., and may also include various other functional films and the like.

[0217] In accordance with Figure 7 and Figure 8In the pixel PXL of the embodiment and the display device including the pixel PXL, a plurality of openings OPN are formed in the first insulating layer INS1, thereby defining a plurality of cells for accommodating the light emitting element LD. Therefore, the light emitting element LD can be aligned between the first electrode ET1 and the second electrode ET2 to stand vertically or diagonally. In this case, the process limitation that occurs when the light emitting element LD is aligned horizontally can be overcome, and the light emitting element LD can be more reliably connected between the first electrode ET1 and the second electrode ET2.

[0218] For example, in the case where the light emitting element LD is arranged horizontally and the first end EP1 and the second end EP2 of the light emitting element LD are subsequently connected to the first electrode ET1 and the second electrode ET2 through respective contact electrodes, a spacing distance is required for reliably preventing a short circuit from occurring between the first electrode ET1 and the second electrode ET2, taking into account the process distribution when the contact electrodes are formed. Therefore, the reduction in the length of the light emitting element LD is limited. In addition, if the length of the light emitting element LD increases, it may be difficult to evenly disperse the light emitting element LD in the light emitting element ink, making it difficult to evenly distribute the light emitting element LD in each emission area EMA. However, as shown in the embodiment of the present disclosure, if the first electrode ET1 and the second electrode ET2 are arranged on different layers, and the light emitting element LD is connected to stand vertically or diagonally between the first electrode ET1 and the second electrode ET2, the process limitations that occur when the light emitting element LD is arranged horizontally can be overcome, and the light emitting element LD can be reliably connected between the first electrode ET1 and the second electrode ET2.

[0219] In addition, in the pixel PXL and the display device including the pixel PXL according to the aforementioned embodiment, the light efficiency (e.g., light output rate) of each pixel PXL can be enhanced. In detail, the light emitting element LD can emit light from its opposite end relative to the longitudinal direction, that is, from the first end EP1 and the second end EP2. Therefore, if the light emitting element LD is arranged horizontally, the light emitting element LD emits light laterally relative to each pixel PXL, so that the efficiency of the light emitted in the front direction can be reduced. In addition, in the structure in which the light emitting element LD is arranged horizontally, a separate structure such as a reflective wall (or a dyke pattern) can be formed around the light emitting element LD to guide the light emitted laterally in the front direction, so that additional space and process can be required. However, as shown in the embodiment of the present disclosure, if the light emitting element LD is connected to stand vertically or diagonally, even if an additional structure for enhancing the output rate is not formed, the amount of light emitted in the front direction of each pixel PXL (e.g., the image display surface of the display panel PNL) can be increased. Therefore, the light efficiency of each pixel PXL can be improved.

[0220] Figure 9a to Figure 9mare cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Figure 7 and Figure 8 An embodiment of the method of a display device of a pixel PXL. Fig.10 1 is a plan view showing a pixel PXL according to an embodiment of the present disclosure, and shows in detail immediately after an opening OPN is formed in the first insulating layer INS1 (eg, Figure 9d ) is a plan view of the emission area EMA of the pixel PXL.

[0221] refer to Figures 7 to 9a , a circuit element layer PCL is formed on one surface of the base layer BSL, and a first electrode ET1 is formed on the base layer BSL on which the circuit element layer PCL is formed. Here, in some embodiments, when the circuit element layer PCL is omitted, the first electrode ET1 may be directly formed on one surface of the base layer BSL (or the base layer BSL on which the buffer layer BFL is formed).

[0222] In an embodiment, the first electrode ET1 may be formed by a process and / or a patterning process of forming a conductive layer including at least one conductive material, and may be formed by various types of known processes. In an embodiment, the first electrode ET1 may be formed of a single layer or multiple layers. For example, the first electrode ET1 may be formed of a conductive pattern having a single-layer structure or a conductive pattern having a multi-layer structure including a first reflective electrode and a first conductive capping layer.

[0223] refer to Figure 9b A first insulating layer INS1 is formed on the first electrode ET1. The first insulating layer INS1 may be formed on the entire surface of the display area DA including the first electrode ET1 of the pixel PXL, or may be formed in the form of a separate pattern in the emission area EMA of each of the pixels PXL.

[0224] In an embodiment, the first insulating layer INS1 may be formed, for example, by coating at least one organic insulating layer including at least one organic insulating material. In this case, the first insulating layer INS1 may be formed so that its surface is substantially flat. Here, the material and / or method of forming the first insulating layer INS1 is not limited thereto. In other words, the first insulating layer INS1 may be formed by a deposition process of an insulating layer including at least one inorganic insulating material and / or an organic insulating material, and the first insulating layer INS1 may be formed by various types of known processes.

[0225] refer to Fig.9c, an alignment electrode ALE including a plurality of first openings OPN1 is formed on the first insulating layer INS1. In an embodiment, the alignment electrode ALE may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes.

[0226] In an embodiment, the alignment electrode ALE may be formed by forming a conductive layer on the entire surface of the display area DA so that the conductive layer overlaps with the first electrode ET1 of the pixel PXL and then patterning the conductive layer so that a plurality of first openings OPN1 are included in a region overlapping with the first electrode ET1. In other words, the alignment electrode ALE may overlap with the first electrode ET1 of each pixel PXL and be formed to include a plurality of first openings OPN1 in a region overlapping with each first electrode ET1. In an embodiment, each first opening OPN1 may be formed to have a width (or diameter) that is the same as or greater than the width (or diameter) of each of the light emitting elements LD and less than the length of each of the light emitting elements LD.

[0227] refer to Figure 9d and Fig.10 By etching the first insulating layer INS1 using the alignment electrode ALE as a mask, a plurality of second openings OPN2 overlapping the first openings OPN1 may be formed in the first insulating layer INS1. A pair of the first openings OPN1 and the second openings OPN2 corresponding to each other may form an integrated opening OPN.

[0228] Hereinafter, to specify a specific opening of the first opening OPN1 and the second opening OPN2, the corresponding opening will be referred to as "first opening OPN1" or "second opening OPN2". The term "opening OPN" or "openings OPN" will be used to arbitrarily specify at least one of the first opening OPN1 and the second opening OPN2 or to specify the first opening OPN1 and the second opening OPN2 together.

[0229] In an embodiment, the second opening OPN2 may be formed in the first insulating layer INS1 by a vertical dry etching process using the alignment electrode ALE as a mask. However, the scheme of etching the first insulating layer INS1 is not limited thereto. In addition, the second opening OPN2 may be formed in the first insulating layer INS1 by various other etching schemes.

[0230] A plurality of cells for accommodating the light emitting elements LD may be defined by forming a plurality of openings OPN overlapping the corresponding first electrodes ET1 in the first insulating layer INS1 and the alignment electrode ALE. The openings OPN may expose different predetermined regions of the first electrode ET1 and may be disposed adjacent to each other on the first electrode ET1.

[0231] refer to Fig.9e , a plurality of light emitting elements LD are provided on a base layer BSL, and a plurality of cells are defined on each first electrode ET1 on the base layer BSL. Thereafter, an alignment signal may be applied to the first electrode ET1 and the alignment electrode ALE. For example, an AC type alignment signal may be applied to any one of the first electrode ET1 and the alignment electrode ALE, and a reference voltage having a reference potential (e.g., a ground potential) may be provided to the other electrode. Thus, an electric field may be formed between the first electrode ET1 and the alignment electrode ALE, and the light emitting element LD may be aligned in at least some of the openings OPN.

[0232] In an embodiment, the light emitting element ink in which a plurality of light emitting elements LD are dispersed is applied to the base layer BSL by an inkjet printing scheme, a slit coating scheme, etc., and the light emitting element LD may be supplied to each emission area EMA. However, the scheme for providing the light emitting element LD is not limited thereto, and the light emitting element LD may be provided to a predetermined area of ​​the base layer BSL in various other ways.

[0233] In an embodiment, each of the light emitting elements LD may be aligned to stand vertically or diagonally in any one opening OPN. In an embodiment, the first end EP1 of the light emitting element LD may be in direct contact with a portion of the first electrode ET1 exposed by the corresponding opening OPN and electrically connected to the first electrode ET1. However, the present disclosure is not limited thereto. In an embodiment, the first end EP1 of at least one light emitting element LD may not be in full contact with the first electrode ET1.

[0234] refer to Figure 9f After aligning the light emitting element LD in the opening OPN, a conductive layer CTL for covering the alignment electrode ALE and the light emitting element LD may be formed. In an embodiment, the conductive layer CTL may be formed by applying a transparent conductive material to one surface of the base layer BSL on which the alignment electrode ALE and the light emitting element LD are disposed through a sputtering scheme, etc. However, the material and / or scheme for forming the conductive layer CTL is not limited thereto.

[0235] refer to Figure 9g An insulating layer including an organic insulating material, that is, an organic insulating layer INL is formed on the conductive layer CTL. The organic insulating layer INL may be introduced into the opening OPN and filled into an inner space of the opening OPN.

[0236] refer to Figure 9h , the organic insulating layer INL can be etched so that the organic insulating layer INL maintains a predetermined height or less only in the opening OPN. For example, the insulating pattern INP embedded in each opening OPN can be formed by etching the organic insulating layer INL to a predetermined thickness through a semi-ashing process. Here, the organic insulating layer INL penetrates into the opening OPN, so that when the organic insulating layer INL is etched in the thickness direction, a predetermined area of ​​the organic insulating layer INL that has deeply penetrated into the opening OPN can be retained, and only other areas of the organic insulating layer INL can be selectively removed. In other words, the predetermined area of ​​the organic insulating layer INL that has deeply penetrated into the opening OPN can surround a predetermined area of ​​the light emitting element LD (e.g., the first end EP1 and / or the peripheral area of ​​the first end EP1), instead of being removed.

[0237] refer to Figure 9i , the first contact electrode CE1 may be formed in the corresponding opening OPN by etching the conductive layer CTL so that the conductive layer CTL only retains a predetermined height or less in the opening OPN. In the step of etching the conductive layer CTL, the alignment electrode ALE may be removed together with the conductive layer CTL. In an embodiment, the conductive layer CTL and the alignment electrode ALE may be etched and / or removed simultaneously or sequentially. In an embodiment, although the conductive layer CTL and the alignment electrode ALE may be etched and / or removed by a wet etching process, the present disclosure is not limited thereto. In an embodiment, the first contact electrode CE1 may be embedded in the opening OPN so that the first contact electrode CE1 contacts the first end EP1 and the first electrode ET1 of the light emitting element LD.

[0238] The first contact electrode CE1 electrically connecting the first end EP1 of the light emitting element LD to the first electrode ET1 may be Figure 9f to Figure 9i The above process is formed. Therefore, the first end EP1 of the light emitting element LD can be reliably connected to the first electrode ET1. In the process of etching the conductive layer CTL and the alignment electrode ALE, the first end EP1 of the light emitting element LD and / or its peripheral area can be surrounded and protected by the insulating pattern INP. Therefore, the light emitting element LD can be prevented from being damaged during subsequent processes, and the connection between the light emitting element LD and the first electrode ET1 can be reliably maintained.

[0239] refer to Figure 9j and Figure 9k After removing the alignment electrode ALE, a second insulating layer INS2 is formed on the first insulating layer INS1 and the light emitting element LD. Figure 9jAs shown in , the second insulating layer INS2 may be formed to have a thickness sufficient to completely cover the first insulating layer INS1 and the light emitting element LD. Figure 9k As shown in FIG, the second insulating layer INS2 may be partially etched in the thickness direction to expose the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be etched by a predetermined distance through a half-ashing process to expose the second end EP2 of the light emitting element LD.

[0240] After forming the second insulating layer INS2, a second contact hole CH2 is formed through at least the second insulating layer INS2. For example, the second contact hole CH2 may be formed to pass through the passivation layer PSV, the first insulating layer INS1, and the second insulating layer INS2 and expose the bridge pattern BRP. Figure 9a to Figure 9m In the embodiment, after forming the second insulating layer INS2, the second contact hole CH2 passing through the passivation layer PSV, the first insulating layer INS1 and the second insulating layer INS2 is formed at once, but the present disclosure is not limited thereto. For example, in order to form the second contact hole CH2, the passivation layer PSV, the first insulating layer INS1 and the second insulating layer INS2 may be opened sequentially.

[0241] In an embodiment, the second insulating layer INS2 may be at least one organic insulating layer coated with an organic insulating material. In the case where the second insulating layer INS2 is formed of an organic insulating layer, the second insulating layer INS2 may be smoothly introduced into the opening OPN during the process of forming the second insulating layer INS2. Therefore, the second insulating layer INS2 may fill the space formed in the opening OPN (e.g., the space formed in the upper region of the opening OPN) and stably surround the side wall of the light emitting element LD. In addition, due to the formation of the second insulating layer INS2, the first electrode ET1, the first contact electrode CE1, etc. may be effectively prevented from being short-circuited with the second electrode ET2 formed during a subsequent process.

[0242] refer to Figure 9l , a second electrode ET2 is formed on the light emitting element LD so that the second electrode ET2 is electrically connected to the second end EP2 of the light emitting element LD. For example, the second electrode ET2 may be formed on the second end EP2 of the light emitting element LD so that the second electrode ET2 is in direct contact with the second end EP2 of the light emitting element LD exposed upward from the second insulating layer INS2. However, the present disclosure is not limited thereto. For example, in an embodiment, a second contact electrode (not shown) may be formed on the second end EP2 of the light emitting element LD, and thereafter the second electrode ET2 may be formed on the second contact electrode so that the second electrode ET2 is connected to the second contact electrode.

[0243] refer to Figure 9m, a third insulating layer INS3 is formed on one surface of the base layer BSL on which the second electrode ET2 is formed. In an embodiment, the third insulating layer INS3 may be formed in the entire area of ​​the display area DA. In an embodiment, the third insulating layer INS3 may be a thin film encapsulation layer having at least one organic / inorganic insulating layer, but the present disclosure is not limited thereto.

[0244] Thereafter, as needed, a third insulating layer INS3 may be formed on one surface of the base layer BSL on which the third insulating layer INS3 is formed. Figure 8 In other words, in an embodiment, the cover layer CVL may be further selectively formed after the third insulating layer INS3 is formed.

[0245] Through the above process, the pixel PXL according to the embodiment of the present disclosure and the display device including the pixel PXL can be manufactured. Figure 7 and Figure 8 A pixel PXL according to an embodiment and a display panel PNL including the pixel PXL.

[0246] Fig.11 is a plan view showing a pixel PXL according to an embodiment of the present disclosure, and shows, for example Figure 7 Modifications to the implementation methods. Fig.12 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and shows, for example, Fig.11 The embodiment of the cross section corresponding to the line II-II'. Fig.11 and Fig.12 In the description of the embodiments of the present invention, the same reference numerals will be used to represent the same Figure 7 and Figure 8 The components of the embodiments are similar or identical to those of the embodiments, and their detailed description will be omitted.

[0247] refer to Fig.11 and Fig.12 , the light emitting element LD may be a rod-type light emitting element. For example, each light emitting element LD may be a rod-type light emitting element, such as Figure 2a and Figure 2b As shown in , it includes a first conductive type semiconductor layer 11, an active layer 12, a second conductive type semiconductor layer 13 and an electrode layer 14 stacked in sequence, and also includes an insulating film INF disposed on the surface thereof. In addition, the light emitting element LD may be a light emitting element LD having various structures, shapes and / or types. In an embodiment, the light emitting element LD may be a light emitting element of substantially the same type, but the present disclosure is not limited thereto. For example, in an embodiment, a combination of a core-shell light emitting element LD and a rod-type light emitting element LD may form a light source unit LSU for each pixel PXL.

[0248] In an embodiment, the first end EP1 of the light emitting element LD disposed to face the first electrode ET1 and electrically connected to the first electrode ET1 may be a P-type end (eg, each having a Figure 2b The second end EP2 of the light emitting element LD, which is disposed to face the second electrode ET2 and electrically connected to the second electrode ET2, may be an N-type end (for example, each having a Figure 2b However, this may vary depending on the connection position of the light source unit LSU and / or the connection direction of the light emitting element LD.

[0249] Figures 13a to 13i are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.11 and Fig.12 An embodiment of the method of a display device of a pixel PXL. Figures 13a to 13i Corresponding to Figure 9e to Figure 9l . In accordance with Figures 13a to 13i In the description of the method of manufacturing a display device according to the embodiment of the present invention, the same reference numerals are used to represent the same method as the previous embodiment (for example, Figure 9a to Figure 9m ) are similar or identical components to the components of the embodiment, and their detailed description will be omitted.

[0250] In the method of manufacturing a display device including a pixel PXL according to the present embodiment, the processes before providing the light emitting element LD may be substantially the same as those of the aforementioned embodiment. Figures 9a to 9d , the first electrode ET1 may be formed on one surface of the base layer BSL on which the circuit element layer PCL is formed, and a first insulating layer INS1 and an alignment electrode ALE each including a plurality of openings OPN may be formed on the first electrode ET1 .

[0251] refer to Fig.13a A plurality of light emitting elements LD are provided on a base layer BSL on which a first electrode ET1, a first insulating layer INS1, an alignment electrode ALE, etc. are formed, and the light emitting elements LD are aligned in the opening OPN. In an embodiment, each of the light emitting elements LD may be a rod-type light emitting element including a first end EP1 contacting the first electrode ET1 and a second end EP2 facing the first end EP1.

[0252] refer to Fig.13b and Fig.13c , the conductive layer CTL and the organic insulating layer INL may be continuously formed to cover the alignment electrode ALE and the light emitting element LD.

[0253] refer to Fig.13d and Fig.13e, the first contact electrode CE1 and the insulating pattern INP may be formed by selectively etching the conductive layer CTL and the organic insulating layer INL. The alignment electrode ALE is removed.

[0254] refer to Fig.13f and Figure 13g After forming the second insulating layer INS2 to completely cover the first insulating layer INS1 and the light emitting element LD, the second insulating layer INS2 is partially etched in the thickness direction so that the second end EP2 of the light emitting element LD is exposed.

[0255] refer to Fig.13h and Fig.13i A second electrode ET2 is formed on the light emitting element LD so that the second electrode ET2 is electrically connected to the second end EP2 of the light emitting element LD. A third insulating layer INS3 is formed on one surface of the base layer BSL on which the second electrode ET2 is formed.

[0256] Thereafter, as needed, a third insulating layer INS3 may be formed on one surface of the base layer BSL on which the third insulating layer INS3 is formed. Fig.12 In other words, the cover layer CVL may be further selectively formed after the third insulating layer INS3 is formed.

[0257] Through the above process, the pixel PXL according to the embodiment of the present disclosure and the display device including the pixel PXL can be manufactured. Fig.11 and Fig.12 A pixel PXL according to an embodiment and a display panel PNL including the pixel PXL.

[0258] In addition to the type and / or shape of the light emitting element LD, Figures 13a to 13i The method of manufacturing a display device according to an embodiment of the present invention may be Figure 9a to Figure 9m The method of manufacturing a display device according to the embodiment of the present invention is substantially the same. Therefore, detailed description thereof will be omitted.

[0259] Fig.14 is a plan view showing a pixel PXL according to an embodiment of the present disclosure, and shows, for example Fig.11 Modifications to the implementation methods. Fig.15 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Fig.14 Although Fig.14 and Fig.15 The pixel PXL (eg, Fig.11 and Fig.12However, the type of the light emitting element LD according to the present disclosure is not limited thereto. For example, at least some of the rod-type light emitting elements LD according to the present embodiment may be Figure 7 and Figure 8 The core-shell light-emitting element LD disclosed in the embodiment is replaced. Fig.14 and Fig.15 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the aforementioned embodiments, and their detailed description will be omitted.

[0260] refer to Fig.14 and Fig.15 , each pixel PXL may further include at least one intermediate electrode that is spaced apart from the first electrode ET1 and the second electrode ET2 and is electrically connected between the first electrode ET1 and the second electrode ET2 via at least one light emitting element LD. For example, the pixel PXL may include a plurality of intermediate electrodes alternately disposed on a layer on which the first electrode ET1 is disposed and a layer on which the second electrode ET2 is disposed. For example, the pixel PXL may include first to fourth intermediate electrodes IET1 to IET4 that are continuously connected between the first electrode ET1 and the second electrode ET2.

[0261] The first intermediate electrode IET1 together with the second electrode ET2 may be disposed on the second insulating layer INS2 and disposed to partially overlap with the first electrode ET1. The first intermediate electrode IET1 may be electrically connected to the first electrode ET1 through at least one light emitting element LD. At least one light emitting element LD may be connected between the first electrode ET1 and the first intermediate electrode IET1 in the forward direction. For example, at least one light emitting element LD may include a first end EP1 and a second end EP2 connected to the first electrode ET1 and the first intermediate electrode IET1, respectively. The first end EP1 and the second end EP2 may be a P-type end and an N-type end, respectively. In other words, among the light emitting elements LD aligned between the first electrode ET1 and the first intermediate electrode IET1, each light emitting element LD whose P-type end is connected to the first electrode ET1 and whose N-type end is connected to the first intermediate electrode IET1 may form an effective light source of a corresponding series stage (e.g., a first series stage).

[0262] The second intermediate electrode IET2 may be disposed on the passivation layer PSV together with the first electrode ET1, and is disposed to partially overlap with the first intermediate electrode IET1. The second intermediate electrode IET2 may be electrically connected to the first intermediate electrode IET1 through at least one light emitting element LD. At least one light emitting element LD may be connected between the first intermediate electrode IET1 and the second intermediate electrode IET2 in the forward direction. For example, at least one light emitting element LD may include a second end EP2' and a first end EP1' respectively connected to the first intermediate electrode IET1 and the second intermediate electrode IET2. The second end EP2' and the first end EP1' may be a P-type end and an N-type end, respectively. In other words, among the light emitting elements LD aligned between the first intermediate electrode IET1 and the second intermediate electrode IET2, each light emitting element LD whose P-type end is connected to the first intermediate electrode IET1 and whose N-type end is connected to the second intermediate electrode IET2 may form an effective light source of a corresponding series stage (e.g., a second series stage).

[0263] The third intermediate electrode IET3 together with the second electrode ET2 may be disposed on the second insulating layer INS2 and disposed to partially overlap with the second intermediate electrode IET2. The third intermediate electrode IET3 may be electrically connected to the second intermediate electrode IET2 through at least one light emitting element LD. At least one light emitting element LD may be connected between the second intermediate electrode IET2 and the third intermediate electrode IET3 in the forward direction. For example, at least one light emitting element LD may include a first end EP1 and a second end EP2 connected to the second intermediate electrode IET2 and the third intermediate electrode IET3, respectively. The first end EP1 and the second end EP2 may be a P-type end and an N-type end, respectively. In other words, among the light emitting elements LD aligned between the second intermediate electrode IET2 and the third intermediate electrode IET3, each light emitting element LD whose P-type end is connected to the second intermediate electrode IET2 and whose N-type end is connected to the third intermediate electrode IET3 may form an effective light source of a corresponding series stage (e.g., a third series stage).

[0264] The fourth intermediate electrode IET4 may be disposed on the passivation layer PSV together with the first electrode ET1, and is disposed to partially overlap the third intermediate electrode IET3. The fourth intermediate electrode IET4 may be electrically connected to the third intermediate electrode IET3 through at least one light emitting element LD. At least one light emitting element LD may be connected between the third intermediate electrode IET3 and the fourth intermediate electrode IET4 in the forward direction. For example, at least one light emitting element LD may include a second end EP2' and a first end EP1' connected to the third intermediate electrode IET3 and the fourth intermediate electrode IET4, respectively. The second end EP2' and the first end EP1' may be a P-type end and an N-type end, respectively. In other words, among the light emitting elements LD aligned between the third intermediate electrode IET3 and the fourth intermediate electrode IET4, each light emitting element LD whose P-type end is connected to the third intermediate electrode IET3 and whose N-type end is connected to the fourth intermediate electrode IET4 may form an effective light source of a corresponding series stage (e.g., a fourth series stage).

[0265] The fourth intermediate electrode IET4 may also be arranged to partially overlap with the second electrode ET2. The fourth intermediate electrode IET4 may be electrically connected to the second electrode ET2 through at least one light emitting element LD. At least one light emitting element LD may be connected between the fourth intermediate electrode IET4 and the second electrode ET2 in the forward direction. For example, at least one light emitting element LD may include a first end EP1 and a second end EP2 connected to the fourth intermediate electrode IET4 and the second electrode ET2, respectively. The first end EP1 and the second end EP2 may be a P-type end and an N-type end, respectively. In other words, among the light emitting elements LD aligned between the fourth intermediate electrode IET4 and the second electrode ET2, each light emitting element LD whose P-type end is connected to the fourth intermediate electrode IET4 and whose N-type end is connected to the second electrode ET2 may form an effective light source of a corresponding series stage (e.g., a fifth series stage).

[0266] In an embodiment, in the step of aligning the light emitting element LD, each of the first to fourth intermediate electrodes IET1 to IET4 may be electrically connected to the first electrode ET1 or the second electrode ET2, and a predetermined alignment signal may be provided. After completing the alignment of the light emitting element LD, each of the first to fourth intermediate electrodes IET1 to IET4 may be separated in the form of a separate electrode. In an embodiment, during the process of depositing the insulating pattern INP and / or the second insulating layer INS2 after the electrode separation process, the area between the first electrode ET1 and at least one intermediate electrode disposed on the same layer as the first electrode ET1 may be filled with an insulating material introduced therein. For example, the insulating pattern INP and / or the second insulating layer INS2 may be inserted between the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4.

[0267] According to the aforementioned embodiments, the plurality of light emitting elements LD forming each light source unit LSU may be connected in a series / parallel combination structure.

[0268] Figures 16a to 16e are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.14 and Fig.15 In accordance with an embodiment of the present invention, a method for displaying a pixel PXL of a display device is provided. Figures 16a to 16e In description of the method of manufacturing a display device according to the embodiment of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiment, and a detailed description thereof will be omitted.

[0269] refer to Figures 9a to 9d as well as Figure 14 to Figure 16a In the method for manufacturing a display device including a pixel PXL according to the present embodiment, the process before providing the light emitting element LD may be the same as that of the reference Figures 9a to 9d The processes of the described embodiments are substantially the same or similar. For example, a lower electrode pattern ETP including a first electrode ET1 and at least one intermediate electrode may be formed on one surface of the base layer BSL on which the circuit element layer PCL is formed. For example, a lower electrode pattern ETP including a first electrode ET1, a second intermediate electrode IET2, and a fourth intermediate electrode IET4 as a whole may be formed on one surface of the base layer BSL. Thereafter, a first insulating layer INS1 and an alignment electrode ALE each including a plurality of openings OPN may be formed on the lower electrode pattern ETP.

[0270] refer to Fig.16b In the region corresponding to the space between the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4, the alignment electrode ALE, the first insulating layer INS1, and the lower electrode pattern ETP may be patterned by various patterning processes including a photo process. In an embodiment, the alignment electrode ALE, the first insulating layer INS1, and the lower electrode pattern ETP may be patterned simultaneously or sequentially. Thus, the lower electrode pattern ETP may be divided into the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4.

[0271] refer to Fig.16c and Fig.16d After forming the conductive layer CTL, the conductive layer CTL is removed between the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4. Therefore, the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4 can be prevented from being short-circuited with each other.

[0272] Thereafter, as shown in the above-described embodiment, the first contact electrode CE1 and the insulating pattern INP are formed by forming an organic insulating layer INL on the conductive layer CTL and selectively etching the conductive layer CTL and the organic insulating layer INL. During the process of depositing the organic insulating layer INL to form the insulating pattern INP, an organic insulating material may be introduced between the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4, so that the insulating pattern INP may also be formed therebetween. After forming the second insulating layer INS2 to completely cover the first insulating layer INS1 and the light emitting element LD, the second insulating layer INS2 is partially etched in the thickness direction so that the second ends EP2 and EP2' of the light emitting element LD are exposed.

[0273] refer to Fig.16e At least one intermediate electrode and a second electrode ET2 are formed on some different light emitting elements LD among the light emitting elements LD. For example, the first intermediate electrode IET1, the third intermediate electrode IET3 and the second electrode ET2 may be formed on some different light emitting elements LD among the light emitting elements LD, respectively.

[0274] Subsequently, as required, a third insulating layer INS3 and / or an outer coating layer OC may be formed, thereby manufacturing a semiconductor device including the semiconductor device according to the present invention. Fig.14 and Fig.15 A display panel PNL of a pixel PXL according to an embodiment.

[0275] Figures 17a to 17d are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.14 and Fig.15 In accordance with an embodiment of the present invention, a method for displaying a pixel PXL of a display device is provided. Figures 17a to 17d In description of the method of manufacturing a display device according to the embodiment of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiment, and a detailed description thereof will be omitted.

[0276] refer to Figures 17a to 17d After forming the first contact electrode CE1 and the insulating pattern INP on the lower electrode pattern ETP, the first insulating layer INS1 and the lower electrode pattern ETP are continuously patterned, whereby the lower electrode pattern ETP can be divided into the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4. Thereafter, the second insulating layer INS2 is formed, and the first intermediate electrode IET1, the third intermediate electrode IET3, and the second electrode ET2 are formed on the second insulating layer INS2. During the process of forming the second insulating layer INS2, an organic insulating material is introduced into the space between the first electrode ET1, the second intermediate electrode IET2, and the fourth intermediate electrode IET4, so that a predetermined area of ​​the second insulating layer INS2 can also be disposed between them.

[0277] like Figures 16a to 16e implementation and Figures 17a to 17d As shown in the embodiment, the steps of performing the process of separating the lower electrode pattern ETP may be changed in various ways according to the embodiment.

[0278] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0279] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device comprising pixels, wherein the pixels are arranged in a display area, in, The pixels include: a first electrode; a first insulating layer disposed on the first electrode and comprising openings formed to expose different regions of the first electrode and define corresponding cells; light emitting elements, each disposed in the cell defined by one of the openings and including a first end electrically connected to the first electrode and a second end protruding upward from the first insulating layer; a second electrode disposed on the light emitting element and electrically connected to the second end of the light emitting element; and a second insulating layer surrounding the sidewall of the light emitting element; The second electrode covers the opening and a portion of the second insulating layer disposed between the openings.

2. The display device according to claim 1, wherein: Each of the openings has a width smaller than a length of each of the light emitting elements.

3. The display device according to claim 2, wherein: Each of the light emitting elements is arranged in a vertical direction or a diagonal direction with respect to the first electrode and the second electrode.

4. The display device according to claim 1, wherein: The first end of the light emitting element is in direct contact with the first electrode.

5. The display device according to claim 1, wherein: The second end of the light emitting element is in direct contact with the second electrode.

6. The display device according to claim 1, wherein: In a plan view, each of the openings has a polygonal shape, a circular shape, an elliptical shape, or a shape corresponding to a combination thereof, and the openings are disposed adjacent to each other in an emission region of the pixel. 7 . The display device according to claim 1 , further comprising a first contact electrode embedded in the corresponding opening and in contact with the first end of the light emitting element and the first electrode. 8 . The display device of claim 7 , further comprising an insulating pattern embedded in the corresponding opening to cover a region of the first contact electrode and the first end of the light emitting element.

9. The display device according to claim 8, wherein: The insulating pattern includes an organic insulating material.

10. The display device according to claim 1, wherein: The second insulating layer is interposed between the first insulating layer and the second electrode.

11. The display device according to claim 10, wherein: The second insulating layer includes an organic insulating material, and a portion of the second insulating layer is introduced into the opening.

12. The display device according to claim 1, wherein: The pixel further includes at least one intermediate electrode that is spaced apart from the first electrode and the second electrode and is electrically connected between the first electrode and the second electrode via at least one of the light emitting elements.

13. The display device according to claim 12, in, The pixel includes a plurality of intermediate electrodes, and The plurality of intermediate electrodes are alternately arranged on a layer on which the first electrode is arranged and a layer on which the second electrode is arranged.

14. The display device according to claim 1, wherein: The light-emitting element includes a rod-type light-emitting element or a core-shell light-emitting element.

15. A method for manufacturing a display device, comprising: forming a first electrode on the base layer; forming a first insulating layer on the first electrode; forming an alignment electrode on the first insulating layer, the alignment electrode overlapping the first electrode and including a first opening; using the alignment electrode as a mask, forming a second opening in the first insulating layer that overlaps the first opening; providing a light emitting element on the base layer, and aligning the light emitting element in a cell formed by the first opening and the second opening by applying an alignment signal to the first electrode and the alignment electrode; electrically connecting a first end of the light emitting element to the first electrode; as well as A second electrode is formed on the second end of the light emitting element so that the second electrode is electrically connected to the second end of the light emitting element.

16. The method according to claim 15, wherein: Electrically connecting the first end of the light emitting element to the first electrode comprises: After aligning the light emitting element, forming a conductive layer covering the alignment electrode and the light emitting element; forming an organic insulating layer on the conductive layer; and The conductive layer and the organic insulating layer are etched so that the conductive layer and the organic insulating layer maintain a predetermined height or less only in the second opening.

17. The method according to claim 16, wherein: When etching the conductive layer, the alignment electrode is removed together with the conductive layer.

18. The method according to claim 17, further comprising: After removing the alignment electrode, forming a second insulating layer covering the first insulating layer and the light emitting element; as well as The second insulating layer is partially etched in a thickness direction so that the second end of the light emitting element is exposed. 19 . The method of claim 15 , further comprising dividing a lower electrode pattern including the first electrode into the first electrode and at least one intermediate electrode after aligning the light emitting element and before forming the second electrode.

20. The method according to claim 15, wherein: Forming the second electrode includes forming the second electrode and at least one intermediate electrode on different light emitting elements among the light emitting elements, respectively.

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