Time-of-flight sensor pixel circuit, structure and time-of-flight sensor

Abstract

A time-of-flight sensor pixel circuit, structure and time-of-flight sensor, including a row a and b column pixel units; in the M-th row and N-th column pixel units, a photoelectric conversion element receives a modulated light wave to generate charges; a first charge storage transfer circuit to a fourth charge storage transfer circuit selectively modulate charges corresponding to four phases of the modulated light wave according to four charge modulation signals to generate four integrated charge signals, and output the four integrated charge signals according to four control selection signals; a charge readout circuit outputs a third photoelectric signal and a second photoelectric signal according to a third integrated charge signal and a second integrated charge signal, respectively; the charge readout circuit also outputs a first photoelectric signal and a fourth photoelectric signal of the M-th row and N+1 column pixel unit according to the first integrated charge signal and the fourth integrated charge signal outputted from the M-th row and N+1 column; therefore, the left and right adjacent pixel units share the charge readout circuit, saving area and improving the photosensitivity of the pixels.

Description

Technical Field

[0001] The present application belongs to the field of sensors, and in particular, relates to a time-of-flight sensor pixel circuit, structure and a time-of-flight sensor. Background Art

[0002] The time-of-flight sensor is an important part of a distance measurement device that can capture the three-dimensional (3D) distance information of a target object and obtain a 3D image. It is widely used in the fields of behavior analysis, monitoring, autonomous driving, artificial intelligence, machine vision perception, and image 3D enhancement. With the continuous advancement of semiconductor manufacturing technology, time-of-flight sensors are developing in the direction of low power consumption, high integration, and smaller size. In many application fields, sensor chips used to collect 3D data are becoming increasingly miniaturized.

[0003] The time-of-flight sensor uses the time-of-flight method to measure the travel time of the light pulse from the light source to the target object after reflection and then to the sensor receiving end, thereby determining the distance information of the target object. The time-of-flight sensor can obtain the travel time of light by direct methods or indirect methods. The indirect method refers to recording the phase difference of the light pulse from the emission to the reception time period, and then calculating the travel time of light.

[0004] A time-of-flight sensor generally includes a light source transmitting module and a light source sensing module. The light source transmitting module is used to transmit a sine wave or a pulse square wave of a specific frequency; the light source sensing module records the phase difference between the light emission and light reception time periods, and then calculates the distance information of the measured object.

[0005] The light source sensing module generally includes a photosensitive pixel module and a photoelectric signal processing system module. The photosensitive pixel uses an indirect method to obtain time data, which requires collecting four phase signals of the sinusoidal continuous light wave: 0 degrees, 90 degrees, 180 degrees and 270 degrees, and then inferring the time information.

[0006] In the prior art, a pixel unit usually includes multiple transistor devices to realize the acquisition of photoelectric phase signals, and the operation steps that need to be completed include photoelectric charge signal modulation, photoelectric charge signal storage, and photoelectric charge signal conversion to photoelectric signal output; the acquisition of four photoelectric phase signals requires four groups of circuit transistor device modules for photoelectric charge signal modulation, photoelectric charge signal storage, and photoelectric charge signal conversion to photoelectric signal. Too many circuit transistor devices will occupy too much pixel area, which will bring difficulties to the improvement of pixel photosensitivity and the miniaturization of sensor size. Summary of the invention

[0007] The purpose of the present application is to provide a time-of-flight sensor pixel circuit, structure and time-of-flight sensor, aiming to solve the defects of poor pixel photosensitivity and large sensor size in traditional time-of-flight sensors.

[0008] The embodiment of the present application provides a time-of-flight sensor pixel circuit, including a row a and b column pixel units, the M-th row and N-th column pixel units including: a photoelectric conversion element, configured to receive a modulated light wave to generate an electric charge; the modulated light wave is sent by a light source transmitting circuit and reflected to the photoelectric conversion element by a target object; a first charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the first phase of the modulated light wave according to a first charge modulation signal to generate a first integrated charge signal, and output the first integrated charge signal according to a first control selection signal; a second charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the second phase of the modulated light wave according to a second charge modulation signal to generate a second integrated charge signal, and output the second integrated charge signal according to a second control selection signal; and a third charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the second phase of the modulated light wave according to a second charge modulation signal to generate a second integrated charge signal, and output the second integrated charge signal according to a second control selection signal. a charge storage transfer circuit connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the third phase of the modulated light wave according to a third charge modulation signal to generate a third integrated charge signal, and output the third integrated charge signal according to a third control selection signal; a fourth charge storage transfer circuit connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the fourth phase of the modulated light wave according to a fourth charge modulation signal to generate a fourth integrated charge signal, and output the fourth integrated charge signal according to a fourth control selection signal; a charge readout circuit connected to the output end of the third charge storage transfer circuit and the output end of the second charge storage transfer circuit, configured to output a third photoelectric signal according to the third integrated charge signal to obtain a third calculation signal, and output a second photoelectric signal according to the second integrated charge signal to obtain a second calculation signal;

[0009] Wherein, the charge readout circuit of the pixel unit of the Mth row and the Nth column is also connected to the output end of the first charge storage transfer circuit of the pixel unit of the Mth row and the N+1th column and the output end of the fourth charge storage transfer circuit of the pixel unit of the Mth row and the N+1th column, and is configured to output the first photoelectric signal of the pixel unit of the Mth row and the N+1th column according to the first integrated charge signal outputted from the Mth row and the N+1th column, so as to obtain the first calculation signal of the pixel unit of the Mth row and the N+1th column, and to output the fourth photoelectric signal of the pixel unit of the Mth row and the N+1th column according to the fourth integrated charge signal outputted from the pixel unit of the Mth row and the N+1th column, so as to obtain the fourth calculation signal of the pixel unit of the Mth row and the N+1th column;

[0010] Wherein, the flight time is obtained based on the first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal corresponding to each pixel unit; a and b are both natural numbers, M is a natural number less than or equal to a, and N is a natural number less than b.

[0011] An embodiment of the present application also provides a structure of the above-mentioned time-of-flight sensor pixel circuit, wherein the photoelectric conversion element of the M-th row and N-th column pixel unit is located in the middle position of the M-th row and N-th column pixel unit, the charge readout circuit of the M-th row and N-th column pixel unit is located on the right side of the photoelectric conversion element of the M-th row and N-th column pixel unit, the output end of the first charge storage transfer circuit of the M-th row and N+1-th column pixel unit, the output end of the fourth charge storage transfer circuit of the M-th row and N+1-th column pixel unit, the output end of the third charge storage transfer circuit of the M-th row and N-th column pixel unit and the output end of the second charge storage transfer circuit of the M-th row and N-th column pixel unit are connected to the input end of the charge readout circuit of the M-th row and N-th column pixel unit.

[0012] An embodiment of the present application further provides a time-of-flight sensor, the time-of-flight sensor comprising the above-mentioned time-of-flight sensor pixel circuit; and / or the time-of-flight sensor comprising the structure of the above-mentioned time-of-flight sensor pixel circuit.

[0013] The embodiment of the present application also provides a control method for the above-mentioned time-of-flight sensor pixel circuit, and the control method comprises the following steps:

[0014] Obtaining the first integrated charge signal, the second integrated charge signal, the third integrated charge signal, and the fourth integrated charge signal based on global exposure;

[0015] The photoelectric signals corresponding to each integrated charge signal are read line by line in a rolling manner.

[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the four charge storage and transfer circuits respectively modulate the charges corresponding to the four phases of the modulated light wave to generate four integrated charge signals, the left and right adjacent pixel units share the charge readout circuit, which can effectively save area, thereby increasing the photosensitivity area of ​​the pixel photoelectric conversion element and improving the pixel photosensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of a structure of a pixel unit in a time-of-flight sensor pixel circuit provided in an embodiment of the present application;

[0019] Figure 2 Another structural schematic diagram of a pixel unit in a time-of-flight sensor pixel circuit provided by an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a structure of a charge readout circuit in a time-of-flight sensor pixel circuit provided in an embodiment of the present application;

[0021] Figure 4 An example circuit diagram of a pixel unit in a time-of-flight sensor pixel circuit provided in an embodiment of the present application;

[0022] Figure 5 An example diagram of a layout of a time-of-flight sensor pixel circuit provided in an embodiment of the present application;

[0023] Figure 6 An example diagram of a layout of a time-of-flight sensor pixel circuit provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of photoelectric signal reading of a time-of-flight sensor pixel circuit provided in an embodiment of the present application.

[0025] Figure 8 This is a control timing diagram of a time-of-flight sensor pixel circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0028] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0030] Figure 1 The schematic diagram of the structure of the pixel unit in the time-of-flight sensor pixel circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0031] The above-mentioned time-of-flight sensor pixel circuit includes a row and b column pixel units, and the Mth row and Nth column pixel units include a photoelectric conversion element 10, a first charge storage transfer circuit 11, a second charge storage transfer circuit 12, a third charge storage transfer circuit 13, a fourth charge storage transfer circuit 14 and a charge readout circuit 20. Wherein, a and b are both natural numbers, M is a natural number less than or equal to a, and N is a natural number less than b.

[0032] The photoelectric conversion element 10 is configured to receive modulated light waves to generate charges; the modulated light waves are sent by the light source transmitting circuit and reflected by the target object to the photoelectric conversion element 10 .

[0033] The first charge storage transfer circuit 11 is connected to the photoelectric conversion element 10, and is configured to selectively modulate the charge corresponding to the first phase of the modulated light wave according to the first charge modulation signal to generate a first integrated charge signal, and output the first integrated charge signal according to the first control selection signal.

[0034] The second charge storage transfer circuit 12 is connected to the photoelectric conversion element 10, and is configured to selectively modulate the charge corresponding to the second phase of the modulated light wave according to the second charge modulation signal to generate a second integrated charge signal, and output the second integrated charge signal according to the second control selection signal.

[0035] The third charge storage transfer circuit 13 is connected to the photoelectric conversion element 10, and is configured to selectively modulate the charge corresponding to the third phase of the modulated light wave according to the third charge modulation signal to generate a third integrated charge signal, and output the third integrated charge signal according to the third control selection signal.

[0036] The fourth charge storage transfer circuit 14 is connected to the photoelectric conversion element 10, and is configured to selectively modulate the charge corresponding to the fourth phase of the modulated light wave according to the fourth charge modulation signal to generate a fourth integrated charge signal, and output the fourth integrated charge signal according to the fourth control selection signal.

[0037] The charge readout circuit 20 is connected to the output end of the third charge storage transfer circuit 13 and the output end of the second charge storage transfer circuit 12, and is configured to output a third photoelectric signal based on the third integrated charge signal to obtain a third calculation signal, and to output a second photoelectric signal based on the second integrated charge signal to obtain a second calculation signal.

[0038] The charge readout circuit 20 of the pixel unit in the Mth row and the Nth column is also connected to the output end of the first charge storage transfer circuit 11 of the pixel unit in the Mth row and the N+1th column and the output end of the fourth charge storage transfer circuit 14 of the pixel unit in the Mth row and the N+1th column, and is configured to output the first photoelectric signal of the pixel unit in the Mth row and the N+1th column according to the first integrated charge signal output from the Mth row and the N+1th column to obtain the first calculation signal of the pixel unit in the Mth row and the N+1th column, and to output the fourth photoelectric signal of the pixel unit in the Mth row and the N+1th column according to the fourth integrated charge signal output from the pixel unit in the Mth row and the N+1th column to obtain the fourth calculation signal of the pixel unit in the Mth row and the N+1th column.

[0039] The flight time is acquired based on the first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal corresponding to each pixel unit.

[0040] It is worth emphasizing that, in one implementation, the first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal are acquired based on a pixel-frame operation.

[0041] In a specific implementation, the input end of the first charge storage transfer circuit 11 and the input end of the second charge storage transfer circuit 12 are connected to the same end of the photoelectric conversion element 10 through the first switch circuit, and the input end of the third charge storage transfer circuit 13 and the input end of the fourth charge storage transfer circuit 14 are connected to the same end of the photoelectric conversion element 10 through the second switch circuit. The first switch circuit is configured to transfer charge according to the first switch control signal, and is configured to transfer charge according to the second switch control signal.

[0042] By configuring the first switch circuit and the second switch circuit, crosstalk between charges corresponding to different phases is prevented.

[0043] The first phase, the second phase, the third phase and the fourth phase are respectively one of 0 degrees, 90 degrees, 180 degrees and 270 degrees; the modulated light source period is composed of four period intervals, and each period interval corresponds one-to-one to the first phase, the second phase, the third phase and the fourth phase to obtain the charge corresponding to each phase.

[0044] The modulated light source period is composed of four period intervals, and each period interval corresponds to the first phase, the second phase, the third phase and the fourth phase one by one to obtain the charge corresponding to each phase. Among them, the sizes of the four period intervals can be the same, and the first phase, the second phase, the third phase and the fourth phase are respectively located at the middle values ​​of the four period intervals. For example, the first phase, the second phase, the third phase and the fourth phase are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, and the four period intervals are (-45 degrees, 45 degrees), (45 degrees, 135 degrees), (135 degrees, 225 degrees), (225 degrees, 315 degrees).

[0045] It is worth noting that the first phase, the second phase, the third phase and the fourth phase can be arranged in sequence, and the phase difference between every two adjacent phases in the first phase, the second phase, the third phase and the fourth phase is 90 degrees.

[0046] By making the phase difference between every two adjacent phases in the first phase, the second phase, the third phase and the fourth phase 90 degrees, photoelectric signals of four phases with a phase difference of 90 degrees can be obtained, which facilitates the calculation of time information and thus improves the calculation efficiency of time information.

[0047] like Figure 2 As shown, the pixel unit in the Mth row and the Nth column further includes an anti-charge crosstalk circuit 30 .

[0048] The anti-blooming circuit 30 is connected to the photoelectric conversion element 10, the first charge storage transfer circuit 11, the second charge storage transfer circuit 12, the third charge storage transfer circuit 13 and the fourth charge storage transfer circuit 14. The anti-blooming circuit 30 is configured to clear the charge in the photoelectric conversion element 10 according to the anti-blooming control signal.

[0049] The anti-charge crosstalk circuit 30 allows the charge in the photoelectric conversion element 1011 to be cleared each time the time information is measured, thereby improving the accuracy of obtaining the time information.

[0050] like Figure 3As shown, the charge readout circuit 20 of the pixel unit of the Mth row and the Nth column includes a first charge readout circuit 21 and a second charge readout circuit 22 .

[0051] The first charge readout circuit 21 is connected to the output end of the second charge storage transfer circuit 12 of the M-th row and N-th column pixel unit and the output end of the first charge storage transfer circuit 11 of the M-th row and N+1-th column pixel unit, and is configured to output the second photoelectric signal of the M-th row and N-th column pixel unit according to the second integrated charge signal of the M-th row and N-th column pixel unit to obtain the second calculation signal of the M-th row and N-th column pixel unit, and to output the first photoelectric signal of the M-th row and N+1-th column pixel unit according to the first integrated charge signal of the M-th row and N+1-th column pixel unit to obtain the first calculation signal of the M-th row and N+1-th column pixel unit.

[0052] The second charge readout circuit 22 is connected to the output end of the third charge storage transfer circuit 13 of the M-th row and N-th column pixel unit and the output end of the fourth charge storage transfer circuit 14 of the M-th row and N+1-th column pixel unit, and is configured to output the third photoelectric signal of the M-th row and N-th column pixel unit according to the third integrated charge signal of the M-th row and N-th column pixel unit to obtain the third calculation signal of the M-th row and N-th column pixel unit, and to output the fourth photoelectric signal of the M-th row and N+1-th column pixel unit according to the fourth integrated charge signal of the M-th row and N+1-th column pixel unit to obtain the fourth calculation signal of the M-th row and N+1-th column pixel unit.

[0053] The charge readout circuit 20 includes two charge readout components, which increases the speed of charge readout and thus increases the speed of acquiring time information.

[0054] In a specific implementation, the anti-charge crosstalk control signal, the first charge modulation signal, the second charge modulation signal, the third charge modulation signal, the fourth charge modulation signal, the first control selection signal, the second control selection signal, the third control selection signal and the fourth control selection signal can be output by the control logic.

[0055] An embodiment of the present invention further provides a control method for the above-mentioned time-of-flight sensor pixel circuit, characterized in that the control method includes step 101 and step 102.

[0056] Step 101: obtaining the first integrated charge signal, the second integrated charge signal, the third integrated charge signal and the fourth integrated charge signal based on a global exposure method;

[0057] Step 102: Read the photoelectric signals corresponding to each integrated charge signal line by line in a rolling manner.

[0058] Figure 4An exemplary circuit structure of a time-of-flight sensor pixel circuit provided by an embodiment of the present invention is shown. For the sake of convenience, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0059] The first charge storage transfer circuit 11 includes a first charge transfer transistor 104 , a first charge storage device 108 , and a first charge selection transistor 112 .

[0060] The source of the first charge transfer transistor 104 is connected to the charge input terminal of the first charge storage transfer circuit 11, the drain of the first charge transfer transistor 104 is connected to the source of the first charge storage device 108, the drain of the first charge storage device 108 is connected to the source of the first charge selection transistor 112, and the drain of the first charge selection transistor 112 is connected to the first integrated charge signal output terminal of the first charge storage transfer circuit 11.

[0061] The gate of the first charge transfer transistor 104 is connected to the first charge modulation signal control line, and the gate of the first charge selection transistor 112 is connected to the first control selection signal control line;

[0062] The gate of the first charge storage device 108 is connected to a first voltage; wherein the first voltage may be a voltage of any value specified according to actual needs, or may indicate that the second end of the first charge storage device 108 is grounded.

[0063] and / or;

[0064] The second charge storage transfer circuit 12 includes a second charge transfer transistor 105 , a second charge storage device 109 , and a second charge selection transistor 113 .

[0065] The source of the second charge transfer transistor 105 is connected to the charge input terminal of the second charge storage transfer circuit 12, the drain of the second charge transfer transistor 105 is connected to the source of the second charge storage device 109, the drain of the second charge storage device 109 is connected to the source of the second charge selection transistor 113, and the drain of the second charge selection transistor 113 is connected to the second integrated charge signal output terminal of the second charge storage transfer circuit 12.

[0066] The gate of the second charge transfer transistor 105 is connected to the second charge modulation signal control line, and the gate of the second charge selection transistor 113 is connected to the second control selection signal control line;

[0067] The gate of the second charge storage device 109 is connected to a second voltage; wherein the second voltage may be a voltage of any value specified according to actual needs, or may indicate that the second end of the second charge storage device 109 is grounded.

[0068] and / or;

[0069] The third charge storage transfer circuit 13 includes a third charge transfer transistor 106 , a third charge storage device 110 , and a third charge selection transistor 114 .

[0070] The source of the third charge transfer transistor 106 is connected to the charge input terminal of the third charge storage transfer circuit 13, the drain of the third charge transfer transistor 106 is connected to the source of the third charge storage device 110, the drain of the third charge storage device 110 is connected to the source of the third charge selection transistor 114, and the drain of the third charge selection transistor 114 is connected to the third integrated charge signal output terminal of the third charge storage transfer circuit 13.

[0071] The gate of the third charge transfer transistor 106 is connected to the third charge modulation signal control line, and the gate of the third charge selection transistor 114 is connected to the third control selection signal control line;

[0072] The gate of the third charge storage device 110 is connected to a third voltage; wherein the third voltage may be a voltage of any value specified according to actual needs, or may indicate that the second end of the third charge storage device 110 is grounded.

[0073] and / or;

[0074] The fourth charge storage transfer circuit 14 includes a fourth charge transfer transistor 107 , a fourth charge storage device 111 , and a fourth charge selection transistor 115 .

[0075] The source of the fourth charge transfer transistor 107 is connected to the charge input terminal of the fourth charge storage transfer circuit 14, the drain of the fourth charge transfer transistor 107 is connected to the source of the fourth charge storage device 111, the drain of the fourth charge storage device 111 is connected to the source of the fourth charge selection transistor 115, and the drain of the fourth charge selection transistor 115 is connected to the fourth integrated charge signal output terminal of the fourth charge storage transfer circuit 14.

[0076] The gate of the fourth charge transfer transistor 107 is connected to the fourth charge modulation signal control line, and the gate of the fourth charge selection transistor 115 is connected to the fourth control selection signal control line;

[0077] The gate of the fourth charge storage device 111 is connected to a fourth voltage, wherein the fourth voltage may be a voltage of any value specified according to actual needs, or may indicate that the second terminal of the fourth charge storage device 111 is grounded.

[0078] The first charge readout circuit 21 includes a first reset transistor 116, a first source follower transistor 118, and a first pixel selection transistor 120;

[0079] The drain of the first reset transistor 116 is connected to the first power supply, the drain of the first source follower transistor 118 is connected to the second power supply, and the first power supply is the same as or different from the second power supply; the source of the first reset transistor 116 and the gate of the first source follower transistor 118 are commonly connected to the integrated charge signal input terminal, the source of the first source follower transistor 118 is connected to the drain of the first pixel selection transistor 120, and the source of the first pixel selection transistor 120 is connected to the photoelectric signal output terminal PO1 (or PO2);

[0080] The gate of the first reset transistor 116 is connected to the first reset control line to serve as a first reset control signal input terminal of the first charge output circuit and a second reset control signal input terminal of the first charge output circuit.

[0081] The floating diffusion active region serves as the integrated charge input terminal.

[0082] and / or;

[0083] The second charge readout circuit 20 includes a second reset transistor 117, a second source follower transistor 119, and a second pixel selection transistor 121;

[0084] The drain of the second reset transistor 117 is connected to the first power supply, the drain of the second source follower transistor 119 is connected to the second power supply, and the first power supply is the same as or different from the second power supply; the source of the second reset transistor 117 and the gate of the second source follower transistor 119 are commonly connected to the induced charge input terminal, the source of the second source follower transistor 119 is connected to the drain of the second pixel selection transistor 121, and the source of the second pixel selection transistor 121 is connected to the photoelectric signal output terminal PO2 (or PO1);

[0085] The gate of the second reset transistor 117 is connected to the second reset control line to serve as a third reset control signal input terminal of the second charge output circuit and a fourth reset control signal input terminal of the second charge output circuit.

[0086] The floating diffusion active region serves as the integrated charge input terminal.

[0087] The anti-charge crosstalk circuit 30 includes a first charge release transistor 122 and a second charge release transistor 123;

[0088] The source of the first charge release transistor 122 and the source of the second charge release transistor 123 are connected to the output end of the photoelectric conversion element 101, the drain of the first charge release transistor 122 and the drain of the second charge release transistor 123 are connected to the control power supply, and the gate of the first charge release transistor 122 and the gate of the second charge release transistor 123 are connected to the anti-charge crosstalk control signal. The voltage of the power supply is less than or equal to the voltage of the first power supply and greater than 0V.

[0089] The photoelectric conversion element 101 includes but is not limited to a pinned photodiode, a polysilicon gate photodiode, and a current-assisted photodiode; the charge storage device includes but is not limited to a MOS transistor capacitor, a polysilicon gate-insulator-polysilicon gate capacitor, and a metal-insulator-metal capacitor.

[0090] The first switch circuit includes a first switch transistor 102. The source of the first switch transistor 102 is connected to the charge input terminal of the first switch circuit, the drain of the first switch transistor 102 is connected to the charge output terminal of the first switch circuit, and the gate of the first switch transistor 102 is connected to the control line of the first switch circuit.

[0091] The second switch circuit includes a second switch transistor 103. The source of the second switch transistor 103 is connected to the charge input terminal of the second switch circuit, the drain of the second switch transistor 103 is connected to the charge output terminal of the second switch circuit, and the gate of the second switch transistor 103 is connected to the control line of the second switch circuit.

[0092] Figure 5 An example layout structure of a pixel unit in a time-of-flight sensor pixel circuit provided by an embodiment of the present invention is shown. Figure 6 An example layout structure of a time-of-flight sensor pixel circuit provided by an embodiment of the present invention is shown. Figure 7 FIG. 1 shows a schematic diagram of phase signal reading of a time-of-flight sensor pixel circuit provided by an embodiment of the present invention. Figure 8 The timing control schematic diagram of the time-of-flight sensor pixel circuit provided by the embodiment of the present invention is shown. For the convenience of explanation, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0093] In the layout of the pixel circuit of the time-of-flight sensor, the photoelectric conversion element 10 of the pixel unit in the Mth row and Nth column is located in the middle position of the pixel unit in the Mth row and Nth column, the charge readout circuit 20 of the pixel unit in the Mth row and Nth column is located on the right side of the photoelectric conversion element 10 of the pixel unit in the Mth row and Nth column, and the output end of the first charge storage transfer circuit 11 of the pixel unit in the Mth row and N+1 column, the output end of the fourth charge storage transfer circuit 14 of the pixel unit in the Mth row and N+1 column, the output end of the third charge storage transfer circuit 13 of the pixel unit in the Mth row and Nth column, and the output end of the second charge storage transfer circuit 12 of the pixel unit in the Mth row and Nth column are connected to the input end of the charge readout circuit 20 of the pixel unit in the Mth row and Nth column.

[0094] In a specific implementation, the first charge readout circuit 21 of the Mth row and Nth column pixel unit is located above the right side of the photoelectric conversion element 10 of the Mth row and Nth column pixel unit, and the first charge readout circuit 21 of the Mth row and Nth column pixel unit is located below the right side of the photoelectric conversion element 10 of the Mth row and Nth column pixel unit.

[0095] In the time-of-flight sensor pixel circuit, the charge readout circuit 20 is shared by the left and right adjacent pixel units, thereby saving the configuration of transistors in the charge readout circuit 20 .

[0096] In the layout of the pixel unit of the Mth row and the Nth column of the time-of-flight sensor pixel circuit, the first charge transfer storage circuit and the second charge transfer storage circuit are located at the top of the photoelectric conversion element 10, and the third charge transfer storage circuit and the fourth charge transfer storage circuit are located at the bottom of the photoelectric conversion element 10; and the layout of the two connected rows of pixel units is a structural relationship of 180 degrees flipped up and down. Alternatively, in the pixel unit of the Mth row and the Nth column, the first charge transfer storage circuit and the second charge transfer storage circuit are located at the bottom of the photoelectric conversion element, and the third charge transfer storage circuit and the fourth charge transfer storage circuit are located at the top of the photoelectric conversion element; and the layout of the two connected rows of pixel units is a structural relationship of 180 degrees flipped up and down.

[0097] In a specific implementation, in the layout of the pixel unit of the Mth row and the Nth column of the time-of-flight sensor pixel circuit, the first charge transfer storage circuit is located at the top left upper part of the photoelectric conversion element 10, the second charge transfer storage circuit is located at the top right upper part of the photoelectric conversion element 10, the third charge transfer storage circuit is located at the bottom right lower part of the photoelectric conversion element 10, and the fourth charge transfer storage circuit is located at the bottom left lower part of the photoelectric conversion element 10. The first switch transistor is located directly above the top of the photoelectric conversion element 10, and the second switch transistor is located directly below the bottom of the photoelectric conversion element 10.

[0098] The gate of the first charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the first charge transfer transistor of the pixel in the M+1th row and Nth column; the gate of the first charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the first charge storage device of the pixel in the M+1th row and Nth column; the gate of the first charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the first charge selection transistor of the pixel in the M+1th row and Nth column; the gate of the second charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the second charge transfer transistor of the pixel in the M+1th row and Nth column; the gate of the second charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the second charge storage device of the pixel in the M+1th row and Nth column; the gate of the second charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the second charge selection transistor of the pixel in the M+1th row and Nth column.

[0099] The corresponding device gates of the first charge transfer storage circuit and the corresponding device gates of the second charge transfer storage circuit of the upstream pixel unit are respectively connected to the corresponding device gates of the first charge transfer storage circuit and the corresponding device gates of the second charge transfer storage circuit of the downstream pixel, so that the gate end control line of each device is shared, thereby saving the number of metal wirings. In one embodiment, the gate material layers of the two transistors that share the gate control line are physically connected to each other, and electrical lead-out can be achieved through a contact hole. At the same time, the incident light shielding effect on the photoelectric conversion element 10 is small, which can further improve the photosensitivity of the pixel.

[0100] The gate of the third charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the third charge transfer transistor of the pixel in the M-1th row and Nth column; the gate of the third charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the third charge storage device of the pixel in the M-1th row and Nth column; the gate of the third charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the third charge selection transistor of the pixel in the M-1th row and Nth column; the gate of the fourth charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge transfer transistor of the pixel in the M-1th row and Nth column; the gate of the fourth charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge storage device of the pixel in the M-1th row and Nth column; the gate of the fourth charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge selection transistor of the pixel in the M-1th row and Nth column.

[0101] The corresponding device gates of the third charge transfer storage circuit and the corresponding device gates of the fourth charge transfer storage circuit of the upstream pixel unit are respectively connected to the corresponding device gates of the third charge transfer storage circuit and the corresponding device gates of the fourth charge transfer storage circuit of the downstream pixel, so that the gate end control lines of each device are shared, thereby saving the number of metal wirings. At the same time, the incident light shielding effect on the photoelectric conversion element 10 is small, which can further improve the photosensitivity of the pixel.

[0102] An output terminal of the first charge readout circuit is connected to a first output column line, and an output terminal of the second charge readout circuit is connected to a second output column line.

[0103] The first charge release transistor is located in the middle position on the right side of the photoelectric conversion element 10, and the second charge release transistor is located in the middle position on the left side of the photoelectric conversion element 10; the drain of the first charge release transistor of the pixel in the Mth row and Nth column is connected to the drain of the second charge release transistor of the pixel in the Mth row and Nth column, and the drain of the second charge release transistor of the pixel in the Mth row and Nth column is connected to the drain of the first charge release transistor of the pixel in the Mth row and Nth column.

[0104] By sharing the drain terminal of the first charge release transistor and the drain terminal of the second charge release transistor of the left and right adjacent pixel units, the area is saved. At the same time, the incident light shielding effect on the photoelectric conversion element 10 is small, which can further improve the pixel photosensitivity.

[0105] The first switch transistor 102 and the second switch transistor 103 are symmetrical about a horizontal center line of the pixel unit.

[0106] The first charge transfer storage circuit and the fourth charge transfer storage circuit are symmetrical about the horizontal line at the center of the pixel unit, and the second charge transfer storage circuit and the third charge transfer storage circuit are symmetrical about the horizontal line at the center of the pixel unit; and / or, the first charge transfer storage circuit and the second charge transfer storage circuit are symmetrical about the vertical line at the center of the pixel unit, and the third charge transfer storage circuit and the fourth charge transfer storage circuit are symmetrical about the vertical line at the center of the pixel unit.

[0107] The first charge readout circuit 21 and the second charge readout circuit 22 are symmetrical about the horizontal center line of the pixel unit; the first charge release transistor 122 and the second charge release transistor 123 are symmetrical about the vertical center line of the pixel unit.

[0108] By adopting a compact and reasonable layout design scheme for each shared pixel unit arranged in a tiled manner in the pixel array, the left and right pixel units in the pixel array are symmetrical, the upper and lower pixel units are symmetrical, and the structure is neat, which can effectively reduce the fixed noise of the photoelectric signal collected by the time-of-flight sensor pixel circuit, thereby improving the signal quality. The time-of-flight sensor pixel circuit of the present application can effectively improve the photosensitivity quality of the pixel.

[0109] Combine the following Figure 7 The figure shows in detail the method of reading the photoelectric signal of the pixel circuit of the time of flight sensor.

[0110] Figure 7 As shown, in each pixel unit, the first charge storage transfer circuit 11, the second charge storage transfer circuit 12, the third charge storage transfer circuit 13, and the fourth charge storage transfer circuit 14 respectively collect one of the photoelectric charge signals in the phases of 0 degree, 90 degree, 180 degree and 270 degree of the modulated light wave, which are marked as Q1, Q2, Q3 and Q4 respectively; that is: the first charge storage transfer circuit 11, the second charge storage transfer circuit 12, the third charge storage transfer circuit 13, and the fourth charge storage transfer circuit 14 respectively collect the first integrated charge signal Q1, the second integrated charge signal Q2, the third integrated charge signal Q3 and the fourth integrated charge signal Q4.

[0111] The first integrated charge signal Q1 and the second integrated charge signal Q2 are converted into photoelectric signals by the first charge readout circuit 21 for output, respectively, and are marked as the first photoelectric signal P1 and the second photoelectric signal P2; the third integrated charge signal Q3 and the fourth integrated charge signal Q4 are converted into photoelectric signals by the first charge readout circuit 21 for output, respectively, and are marked as the third photoelectric signal P3 and the fourth photoelectric signal P4.

[0112] like Figure 7 As shown. Each pixel in the pixel array collects the modulated light wave phase integral charge signal (Q1, Q2, Q3 and Q4) in a synchronous global manner, and reads the phase photoelectric signal (P1, P2, P3 and P4) in the pixel row by row in a row rolling manner, and outputs four phase photoelectric signals (P1, P2, P3 and P4) respectively by the column signal output lines PO1 and PO2.

[0113] exist Figure 7 In the schematic diagram of the embodiment shown, the column line PO1 outputs the P1 and P2 signals of the M-1th row of pixels, the P3 and P4 signals of the Mth row of pixels, and the P1 and P2 signals of the M+1th row.

[0114] The column line PO2 outputs the P3 and P4 signals of the M-1th row of pixels, the P1 and P2 signals of the Mth row of pixels, and the P3 and P4 signals of the M+1th row.

[0115] The column lines PO1 and PO2 respectively output the pixels P1, P2 and P3, P4 in the pixel array in an alternating row-wise manner to the next stage circuit for the next step of signal processing.

[0116] In a specific implementation, when the pixel circuit includes the first charge readout circuit and the second charge readout circuit, and the output end of the first charge readout circuit is connected to the first output column line PO1, and the output end of the second charge readout circuit is connected to the second output column line PO2, the reading method of the photoelectric signal in this implementation is described as follows:

[0117] Figure 8 What is shown is a schematic diagram of timing control of a time-of-flight sensor pixel array of the present invention. Figure 8 , the timing of the readout operation of the pixel P3, P4 signals of the M-1th row, the pixel P1, P2, P3, P4 signals of the Mth row, and the pixel P1, P2 signals of the M+1th row is shown, and the photoelectric signals of the pixels of other rows are adopted Figure 8 The timing shown is read out in a scrolling manner. Figure 8In the figure, the light source adopts a positive line continuous light wave, each timing low potential indicates that the gate of each corresponding transistor is set to a low potential and each corresponding transistor is in a closed state, and each timing high potential indicates that the gate of each corresponding transistor is set to a high potential and each corresponding transistor is in an open state; wherein the high potential pulses of PO1 and PO2 timings represent pixel output signal operations, M-1 represents the operation on M-1 rows of pixels, M represents the operation on M rows of pixels, M+1 represents the operation on M+1 rows of pixels, P1, P2, P3, P4 represent the operations on pixel P1, P2, P3, P4 signals respectively, R represents the operation on the reset signal, and S represents the operation on the initial photoelectric signal.

[0118] Figure 8 The timing sequence shown includes three steps in the signal acquisition operation of the time-of-flight sensor pixel array: a reset operation, a pixel exposure operation, and a signal reading operation.

[0119] The reset operation is to clear the charge in the photoelectric conversion element 101 and the charge in the MOS transistor capacitors 108, 109, 110, and 111; the specific operation is to set the gates of the transistors 102 to 107 and 112 to 117 to a high potential, and after the charge in the transistors 101, 108, 109, 110, and 111 is cleared, set the gates of the transistors 103, 105 to 107, and 112 to 115 to a low potential, and keep the gates of the transistors 102 and 104 at a high potential state. After the reset operation is completed, turn on the light source and the pixel begins to be exposed.

[0120] In the pixel exposure operation, the light source continuously emits sinusoidal modulated light waves. In the exposure period, the light source emits n 2π sinusoidal modulated light waves, where n is a natural number. The timing high potential of the first switch transistor 102 is the sum of the timing high potentials of the first charge transfer transistor 104 and the second charge transfer transistor 105. The timing high potential of the second switch transistor 103 is the sum of the timing high potentials of the third charge transfer transistor 106 and the fourth charge transfer transistor 107. The first charge transfer transistor 104, the second charge transfer transistor 105, the third charge transfer transistor 106, and the fourth charge transfer transistor 107 modulate the collected photoelectric charge signals to be Q1, Q2, Q3, and Q4, respectively.

[0121] In the signal reading operation, PO1 outputs P1 and P2 signals of M+1 rows of pixels, and outputs P3 and P4 signals of M rows of pixels; PO2 outputs P1 and P2 signals of M rows of pixels, and outputs P3 and P4 signals of M-1 rows of pixels.

[0122] The specific operation is to sequentially set the first charge release transistor 122 and the second charge release transistor 123 to a high potential state, sequentially set the first pixel selection transistor 120 to a high potential state, and give the first reset transistor 116 a sequential high potential pulse operation to reset the floating diffusion active area of ​​the pixel, and then PO1 and PO2 output reset signals of the M+1 row pixel (M+1)_P1_R and the M row pixel M_P1_R respectively;

[0123] Next, a high-potential pulse operation is given to the first charge selection transistor 112 and a low-potential pulse operation is given to the first charge storage device 108 to transfer the photoelectric charge Q1 in the first charge storage device 108 to the floating diffusion active area. Subsequently, PO1 and PO2 output the initial photoelectric signals of the M+1 row of pixels (M+1)_P1_S and the M row of pixels M_P1_S, respectively.

[0124] The subsequent signals of P2, P3, and P4 are obtained by configuring the timing of the corresponding transistors.

[0125] Among them, the above method can realize that the first photoelectric signal in the adjacent row is outputted based on the first output line PO1 and the second output line PO2 at the same time, that is, the initial photoelectric signal of the pixel (M+1)_P1_S in the M+1 row and the pixel M_P1_S in the M row. Similarly, the above method can also realize that the second photoelectric signal in the adjacent row is outputted based on the first output line and the second output line at the same time; the third photoelectric signal in the adjacent row is outputted based on the first output line and the second output line at the same time; the fourth photoelectric signal in the adjacent row is outputted based on the first output line and the second output line at the same time.

[0126] Furthermore, the calculation expression of the phase photoelectric signal of the M rows of pixels is:

[0127] P1=M_P1_R-M_P1_S (a1)

[0128] P2=M_P2_R-M_P2_S (a2)

[0129] P3=M_P3_R-M_P3_S (a3)

[0130] P4=M_P4_R-M_P4_S (a4)

[0131] The calculation expression of the phase photoelectric signal of the M-1 row of pixels is:

[0132] P3=(M-1)_P3_R-(M-1)_P3_S (b3)

[0133] P4=(M-1)_P4_R-(M-1)_P4_S (b4)

[0134] The calculation expression of the phase photoelectric signal of the M+1 row of pixels is:

[0135] P1=(M+1)_P1_R-(M+1)_P1_S (c1)

[0136] P2=(M+1)_P2_R-(M+1)_P2_S (c2)

[0137] The optical phase difference of the photoelectric signal collected by the pixel array of the time-of-flight sensor of the present invention can be calculated as:

[0138]

[0139] So the flight time of light is:

[0140]

[0141] An embodiment of the present application further provides a time-of-flight sensor, which includes the above-mentioned time-of-flight sensor pixel circuit.

[0142] The embodiment of the present invention includes a row a and b column pixel units. In the pixel unit in the Mth row and the Nth column, a modulated light wave is received by a photoelectric conversion element to generate an electric charge; the modulated light wave is sent by a light source transmitting circuit and reflected to the photoelectric conversion element by a target object; a first charge storage transfer circuit selectively modulates the charge corresponding to the first phase of the modulated light wave according to a first charge modulation signal to generate a first integrated charge signal, and outputs the first integrated charge signal according to a first control selection signal; a second charge storage transfer circuit selectively modulates the charge corresponding to the second phase of the modulated light wave according to a second charge modulation signal to generate a second integrated charge signal, and outputs the second integrated charge signal according to a second control selection signal; a third charge storage transfer circuit selectively modulates the charge corresponding to the third phase of the modulated light wave according to a third charge modulation signal to generate a third integrated charge signal, and outputs the third integrated charge signal according to the third control selection signal; a fourth charge storage transfer circuit selectively modulates the charge corresponding to the fourth phase of the modulated light wave according to a fourth charge modulation signal to generate The fourth integrated charge signal is generated, and the fourth integrated charge signal is output according to the fourth control selection signal; the charge readout circuit outputs a third photoelectric signal according to the third integrated charge signal to obtain a third calculation signal, and outputs a second photoelectric signal according to the second integrated charge signal to obtain a second calculation signal; the charge readout circuit of the Mth row and Nth column pixel unit also outputs the first photoelectric signal of the Mth row and N+1 column pixel unit according to the first integrated charge signal outputted from the Mth row and N+1 column to obtain a first calculation signal of the Mth row and N+1 column pixel unit, and outputs the fourth photoelectric signal of the Mth row and N+1 column pixel unit according to the fourth integrated charge signal outputted from the Mth row and N+1 column pixel unit to obtain a fourth calculation signal of the Mth row and N+1 column pixel unit; wherein the flight time is acquired based on the first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal corresponding to each pixel unit; a and b are both natural numbers, M is a natural number less than or equal to a, and N is a natural number less than b. Therefore, the shared charge readout circuit of the adjacent left and right pixel units can effectively save area, thereby increasing the photosensitive area of ​​the pixel photoelectric conversion element and improving the pixel photosensitivity. The time-of-flight sensor pixel array with a shared structural pixel layout proposed in the present invention adopts the acquisition method of the four-phase photoelectric signals P1, P2, P3 and P4, and the adjacent left and right column pixels share the first group of photoelectric signal reading devices and the second group of photoelectric signal reading devices, which can effectively save area, thereby increasing the photosensitive area of ​​the pixel photoelectric conversion element and improving the pixel photosensitivity; the adjacent up and down row pixels in the pixel array share the metal routing of the transistor gate terminal control line, and the adjacent left and right column pixels share the drain terminal of the charge release transistor, which has little effect on the incident light shielding of the photodiode, and can further improve the pixel photosensitivity.Each shared pixel unit arranged in a tiled manner in the pixel array adopts a compact and reasonable layout design scheme. The left and right pixels of the pixel array are symmetrical, the upper and lower pixels are symmetrical, and the structure is neat, which can effectively reduce the fixed noise of the photoelectric signal collected by the pixel array, thereby improving the signal quality. The time-of-flight sensor pixel array of the present invention can effectively improve the photosensitivity quality of the pixel.

[0143] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0144] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A time-of-flight sensor pixel circuit, characterized in that: The pixel unit includes a row and b columns, and the pixel unit of the Mth row and the Nth column includes: A photoelectric conversion element is configured to receive a modulated light wave to generate an electric charge; the modulated light wave is sent by a light source transmitting circuit and reflected by a target object to the photoelectric conversion element; a first charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the first phase of the modulated light wave according to a first charge modulation signal to generate a first integrated charge signal, and output the first integrated charge signal according to a first control selection signal; a second charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the second phase of the modulated light wave according to a second charge modulation signal to generate a second integrated charge signal, and output the second integrated charge signal according to a second control selection signal; a third charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the third phase of the modulated light wave according to a third charge modulation signal to generate a third integrated charge signal, and output the third integrated charge signal according to a third control selection signal; a fourth charge storage transfer circuit, connected to the photoelectric conversion element, configured to selectively modulate the charge corresponding to the fourth phase of the modulated light wave according to a fourth charge modulation signal to generate a fourth integrated charge signal, and output the fourth integrated charge signal according to a fourth control selection signal; a charge readout circuit connected to an output terminal of the third charge storage transfer circuit and an output terminal of the second charge storage transfer circuit, configured to output a third photoelectric signal according to the third integrated charge signal to obtain a third calculation signal, and to output a second photoelectric signal according to the second integrated charge signal to obtain a second calculation signal; Wherein, the charge readout circuit of the pixel unit of the Mth row and the Nth column is also connected to the output end of the first charge storage transfer circuit of the pixel unit of the Mth row and the N+1th column and the output end of the fourth charge storage transfer circuit of the pixel unit of the Mth row and the N+1th column, and is configured to output the first photoelectric signal of the pixel unit of the Mth row and the N+1th column according to the first integrated charge signal outputted from the Mth row and the N+1th column, so as to obtain the first calculation signal of the pixel unit of the Mth row and the N+1th column, and to output the fourth photoelectric signal of the pixel unit of the Mth row and the N+1th column according to the fourth integrated charge signal outputted from the pixel unit of the Mth row and the N+1th column, so as to obtain the fourth calculation signal of the pixel unit of the Mth row and the N+1th column; Wherein, the flight time is obtained based on the first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal corresponding to each pixel unit; a and b are both natural numbers, M is a natural number less than or equal to a, and N is a natural number less than b.

2. The time-of-flight sensor pixel circuit according to claim 1, characterized in that: The input end of the first charge storage transfer circuit and the input end of the second charge storage transfer circuit are connected to the same end of the photoelectric conversion element through a first switching circuit, and the input end of the third charge storage transfer circuit and the input end of the fourth charge storage transfer circuit are connected to the same end of the photoelectric conversion element through a second switching circuit.

3. The time-of-flight sensor pixel circuit according to claim 1, wherein: The first phase, the second phase, the third phase and the fourth phase are respectively one of 0 degrees, 90 degrees, 180 degrees and 270 degrees; The period of the modulated light wave is composed of four period intervals, and each of the period intervals corresponds to the first phase, the second phase, the third phase and the fourth phase one by one, so as to obtain the charge corresponding to each phase.

4. The time-of-flight sensor pixel circuit according to claim 1, wherein: The first charge storage transfer circuit includes a first charge transfer transistor, a first charge storage device, and a first charge selection transistor; The source of the first charge transfer transistor is connected to the charge input terminal of the first charge storage transfer circuit, the drain of the first charge transfer transistor is connected to the source of the first charge storage device, the drain of the first charge storage device is connected to the source of the first charge selection transistor, and the drain of the first charge selection transistor is connected to the first integrated charge signal output terminal of the first charge storage transfer circuit; The gate of the first charge transfer transistor is connected to the first charge modulation signal control line, and the gate of the first charge selection transistor is connected to the first control selection signal control line; The gate of the first charge storage device is connected to a first voltage; and / or; The second charge storage transfer circuit includes a second charge transfer transistor, a second charge storage device, and a second charge selection transistor; The source of the second charge transfer transistor is connected to the charge input terminal of the second charge storage transfer circuit, the drain of the second charge transfer transistor is connected to the source of the second charge storage device, the drain of the second charge storage device is connected to the source of the second charge selection transistor, and the drain of the second charge selection transistor is connected to the second integrated charge signal output terminal of the second charge storage transfer circuit; The gate of the second charge transfer transistor is connected to the second charge modulation signal control line, and the gate of the second charge selection transistor is connected to the second control selection signal control line; The gate of the second charge storage device is connected to a second voltage; and / or; The third charge storage transfer circuit includes a third charge transfer transistor, a third charge storage device and a third charge selection transistor; The source of the third charge transfer transistor is connected to the charge input terminal of the third charge storage transfer circuit, the drain of the third charge transfer transistor is connected to the source of the third charge storage device, the drain of the third charge storage device is connected to the source of the third charge selection transistor, and the drain of the third charge selection transistor is connected to the third integrated charge signal output terminal of the third charge storage transfer circuit; The gate of the third charge transfer transistor is connected to the third charge modulation signal control line, and the gate of the third charge selection transistor is connected to the third control selection signal control line; The gate of the third charge storage device is connected to a third voltage; and / or; The fourth charge storage transfer circuit includes a fourth charge transfer transistor, a fourth charge storage device and a fourth charge selection transistor; The source of the fourth charge transfer transistor is connected to the charge input terminal of the fourth charge storage transfer circuit, the drain of the fourth charge transfer transistor is connected to the source of the fourth charge storage device, the drain of the fourth charge storage device is connected to the source of the fourth charge selection transistor, and the drain of the fourth charge selection transistor is connected to the fourth integrated charge signal output terminal of the fourth charge storage transfer circuit; The gate of the fourth charge transfer transistor is connected to the fourth charge modulation signal control line, and the gate of the fourth charge selection transistor is connected to the fourth control selection signal control line; The gate of the fourth charge storage device is connected to a fourth voltage.

5. The time-of-flight sensor pixel circuit according to any one of claims 1 to 4, characterized in that: The charge readout circuit of the pixel unit of the Mth row and the Nth column comprises: A first charge readout circuit is connected to the output end of the second charge storage transfer circuit of the M-th row and N-th column pixel unit and the output end of the first charge storage transfer circuit of the M-th row and N-th column pixel unit, and is configured to output the second photoelectric signal of the M-th row and N-th column pixel unit according to the second integrated charge signal of the M-th row and N-th column pixel unit to obtain the second calculation signal of the M-th row and N-th column pixel unit, and output the first photoelectric signal of the M-th row and N-th column pixel unit according to the first integrated charge signal of the M-th row and N-th column pixel unit to obtain the first calculation signal of the M-th row and N-th column pixel unit; The second charge readout circuit is connected to the output end of the third charge storage transfer circuit of the M-th row and N-th column pixel unit and the output end of the fourth charge storage transfer circuit of the M-th row and N-th column pixel unit, and is configured to output the third photoelectric signal of the M-th row and N-th column pixel unit according to the third integrated charge signal of the M-th row and N-th column pixel unit to obtain the third calculation signal of the M-th row and N-th column pixel unit, and to output the fourth photoelectric signal of the M-th row and N-th column pixel unit according to the fourth integrated charge signal of the M-th row and N-th column pixel unit to obtain the fourth calculation signal of the M-th row and N-th column pixel unit.

6. The time-of-flight sensor pixel circuit according to claim 5, characterized in that: The first charge readout circuit includes a first reset transistor, a first source follower transistor and a first pixel selection transistor; The drain of the first reset transistor is connected to a first power supply, the drain of the first source follower transistor is connected to a second power supply, the first power supply is the same as or different from the second power supply, the source of the first reset transistor and the gate of the first source follower transistor are commonly connected to an integrated charge signal input terminal, the source of the first source follower transistor is connected to the drain of the first pixel selection transistor, and the source of the first pixel selection transistor is connected to a photoelectric signal output terminal; The gate of the first reset transistor is connected to a first reset control line to serve as a first reset control signal input terminal of the first charge readout circuit and a second reset control signal input terminal of the first charge readout circuit; and / or; The second charge readout circuit includes a second reset transistor, a second source follower transistor, and a second pixel selection transistor; The drain of the second reset transistor is connected to a first power supply, the drain of the second source follower transistor is connected to a second power supply, the first power supply is the same as or different from the second power supply, the source of the second reset transistor and the gate of the second source follower transistor are commonly connected to an integrated charge signal input terminal, the source of the second source follower transistor is connected to the drain of the second pixel selection transistor, and the source of the second pixel selection transistor is connected to a photoelectric signal output terminal; The gate of the second reset transistor is connected to a second reset control line to serve as a third reset control signal input terminal of the second charge readout circuit and a fourth reset control signal input terminal of the second charge readout circuit.

7. The time-of-flight sensor pixel circuit according to any one of claims 1 to 4, characterized in that: The pixel unit of the Mth row and the Nth column also includes: An anti-charge crosstalk circuit is connected to the photoelectric conversion element, the first charge storage transfer circuit, the second charge storage transfer circuit, the third charge storage transfer circuit and the fourth charge storage transfer circuit, and is at least configured to clear the charge in the photoelectric conversion element according to an anti-charge crosstalk control signal.

8. The time-of-flight sensor pixel circuit according to claim 7, wherein: The anti-charge crosstalk circuit includes a first charge release transistor and a second charge release transistor; The source of the first charge release transistor and the source of the second charge release transistor are connected to the output end of the photoelectric conversion element, the drain of the first charge release transistor and the drain of the second charge release transistor are connected to the control power supply, and the gate of the first charge release transistor and the gate of the second charge release transistor are connected to the anti-charge crosstalk control signal.

9. The time-of-flight sensor pixel circuit according to any one of claims 1 to 4, characterized in that: The first calculation signal, the second calculation signal, the third calculation signal and the fourth calculation signal are acquired based on a pixel one-frame operation.

10. A structure of a time-of-flight sensor pixel circuit according to any one of claims 1 to 9, characterized in that: The photoelectric conversion element of the M-th row and N-th column pixel unit is located in the middle position of the M-th row and N-th column pixel unit, the charge readout circuit of the M-th row and N-th column pixel unit is located on the right side of the photoelectric conversion element of the M-th row and N-th column pixel unit, the output end of the first charge storage transfer circuit of the M-th row and N+1-th column pixel unit, the output end of the third charge storage transfer circuit of the M-th row and N-th column pixel unit and the output end of the second charge storage transfer circuit of the M-th row and N-th column pixel unit are connected to the input end of the charge readout circuit of the M-th row and N-th column pixel unit.

11. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: In the pixel unit of the Mth row and the Nth column, the first charge storage transfer circuit and the second charge storage transfer circuit are located at the top of the photoelectric conversion element, and the third charge storage transfer circuit and the fourth charge storage transfer circuit are located at the bottom of the photoelectric conversion element; and the layout of the two connected rows of pixel units is a structural relationship of being flipped 180 degrees up and down; Alternatively, in the Mth row and Nth column pixel unit, the first charge storage transfer circuit and the second charge storage transfer circuit are located at the bottom of the photoelectric conversion element, and the third charge storage transfer circuit and the fourth charge storage transfer circuit are located at the top of the photoelectric conversion element; and the layout of the two connected rows of pixel units has a structural relationship of being flipped 180 degrees up and down.

12. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: The first charge storage transfer circuit and the fourth charge storage transfer circuit are symmetrical about the horizontal line at the center of the pixel unit, and the second charge storage transfer circuit and the third charge storage transfer circuit are symmetrical about the horizontal line at the center of the pixel unit; and / or the first charge storage transfer circuit and the second charge storage transfer circuit are symmetrical about the vertical line at the center of the pixel unit, and the third charge storage transfer circuit and the fourth charge storage transfer circuit are symmetrical about the vertical line at the center of the pixel unit.

13. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: When the pixel circuit includes a first switch circuit and a second switch circuit, the first switch circuit includes a first switch transistor, and the second switch circuit includes a second switch transistor; In the corresponding layout of the time-of-flight sensor pixel circuit, the first switch transistor and the second switch transistor are symmetrical about a central horizontal line of the pixel unit.

14. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: When the pixel circuit includes a first charge transfer transistor, a first charge storage device, a first charge selection transistor, a second charge transfer transistor, a second charge storage device, and a second charge selection transistor, The gate of the first charge transfer transistor of the pixel in the Mth row and the Nth column is connected to the gate of the first charge transfer transistor of the pixel in the M+1th row and the Nth column; the gate of the first charge storage device of the pixel in the Mth row and the Nth column is connected to the gate of the first charge storage device of the pixel in the M+1th row and the Nth column; the gate of the first charge selection transistor of the pixel in the Mth row and the Nth column is connected to the gate of the first charge selection transistor of the pixel in the M+1th row and the Nth column; The gate of the second charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the second charge transfer transistor of the pixel in the M+1th row and Nth column; the gate of the second charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the second charge storage device of the pixel in the M+1th row and Nth column; the gate of the second charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the second charge selection transistor of the pixel in the M+1th row and Nth column.

15. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: When the pixel circuit includes a third charge transfer transistor, a third charge storage device, a third charge selection transistor, a fourth charge transfer transistor, a fourth charge storage device and the fourth charge selection transistor, The gate of the third charge transfer transistor of the pixel in the Mth row and the Nth column is connected to the gate of the third charge transfer transistor of the pixel in the M-1th row and the Nth column; the gate of the third charge storage device of the pixel in the Mth row and the Nth column is connected to the gate of the third charge storage device of the pixel in the M-1th row and the Nth column; the gate of the third charge selection transistor of the pixel in the Mth row and the Nth column is connected to the gate of the third charge selection transistor of the pixel in the M-1th row and the Nth column; The gate of the fourth charge transfer transistor of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge transfer transistor of the pixel in the M-1th row and Nth column; the gate of the fourth charge storage device of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge storage device of the pixel in the M-1th row and Nth column; the gate of the fourth charge selection transistor of the pixel in the Mth row and Nth column is connected to the gate of the fourth charge selection transistor of the pixel in the M-1th row and Nth column.

16. The structure of the time-of-flight sensor pixel circuit according to claim 10, wherein: When the pixel circuit includes a first charge readout circuit and a second charge readout circuit, an output terminal of the first charge readout circuit is connected to a first output column line, and an output terminal of the second charge readout circuit is connected to a second output column line.

17. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: When the pixel circuit includes a first charge readout circuit and a second charge readout circuit, the first charge readout circuit and the second charge readout circuit are symmetrical about a horizontal line at the center of the pixel unit.

18. The structure of the time-of-flight sensor pixel circuit according to claim 10, characterized in that: When the pixel circuit includes a first charge release transistor and a second charge release transistor, the first charge release transistor is located at a middle position on the right side of the photoelectric conversion element, and the second charge release transistor is located at a middle position on the left side of the photoelectric conversion element; The drain of the first charge release transistor of the pixel in the Mth row and Nth column is connected to the drain of the second charge release transistor of the pixel in the Mth row and Nth column, and the drain of the second charge release transistor of the pixel in the Mth row and Nth column is connected to the drain of the first charge release transistor of the pixel in the Mth row and Nth column.

19. The structure of the time-of-flight sensor pixel circuit according to claim 10, wherein: The first charge release transistor and the second charge release transistor are symmetrical about a central vertical line of the pixel unit.

20. A time-of-flight sensor, characterized in that: The time-of-flight sensor comprises the time-of-flight sensor pixel circuit as claimed in any one of claims 1 to 9; and / or the time-of-flight sensor comprises the structure of the time-of-flight sensor pixel circuit as claimed in any one of claims 10 to 19.

21. A method for controlling a time-of-flight sensor pixel circuit according to any one of claims 1 to 10, characterized in that: The control method comprises the following steps: Obtaining the first integrated charge signal, the second integrated charge signal, the third integrated charge signal, and the fourth integrated charge signal based on global exposure; The first photoelectric signal, the second photoelectric signal, the third photoelectric signal and the fourth photoelectric signal corresponding to each integrated charge signal are read line by line in a rolling manner.

22. The control method of a time-of-flight sensor pixel circuit according to claim 21, characterized in that: When the pixel circuit includes a first charge readout circuit and a second charge readout circuit, and the output end of the first charge readout circuit is connected to a first output line, and the output end of the second charge readout circuit is connected to a second output line, the photoelectric signal reading method includes: The first photoelectric signal in adjacent rows is output simultaneously based on the first output line and the second output line; and / or, the second photoelectric signal in adjacent rows is output simultaneously based on the first output line and the second output line; and / or, the third photoelectric signal in adjacent rows is output simultaneously based on the first output line and the second output line; and / or, the fourth photoelectric signal in adjacent rows is output simultaneously based on the first output line and the second output line.

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