Firmware updating method, device, electronic device and storage medium

Abstract

The present invention discloses a firmware update method, device, electronic device and storage medium. The method includes: obtaining target firmware of the target chip; conducting the transmission path between the BMC chip and the target chip according to a first level signal output by a first GPIO interface; erasing the firmware stored in the memory of the target chip according to a second level signal output by a second GPIO interface, a third level signal output by a third GPIO interface and a fourth level signal output by a fourth GPIO interface; and writing the target firmware into the memory according to the second level signal, the third level signal and the fourth level signal. This method can break the limitations of chip firmware updates and improve the convenience of chip firmware updates.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of firmware updating, and in particular to a firmware updating method, device, electronic device, and storage medium. Background Art

[0002] Firmware is software embedded in hardware, storing the most basic parameters of the hardware device. Servers include various hardware devices, such as the baseboard management controller (BMC) chip, network chips connected to the BMC, and other chips. With the advancement of network technology, chip firmware needs to be updated regularly to correct software and hardware anomalies and ensure server stability and reliability.

[0003] In the prior art, chip updating requires reliance on an operating system (OS). Specifically, the chip needs to be updated within the OS.

[0004] However, in the above solution, when the OS crashes or the Basic Input Output System (BIOS) cannot be started, the chip cannot be updated, resulting in significant limitations in chip updating. Summary of the Invention

[0005] The present disclosure provides a firmware update method, device, electronic device, and storage medium, which can break the limitations of chip firmware updates and improve the convenience of chip firmware updates.

[0006] In a first aspect, the present disclosure provides a firmware update method, which is applied to a baseboard management controller (BMC) chip, wherein the BMC chip is electrically connected to a target chip via four general-purpose input and output (GPIO) interfaces;

[0007] The method comprises:

[0008] Obtaining target firmware of the target chip;

[0009] Conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface;

[0010] Erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface;

[0011] The target firmware is written into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0012] Optionally, before erasing the firmware stored in the memory of the target chip, the method further includes:

[0013] Determining the data volume of all contents in the target firmware according to all contents of the target firmware;

[0014] Determining a target number of blocks to be erased in the memory according to the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware;

[0015] Erasing the firmware stored in the memory of the target chip includes:

[0016] According to the target number, a corresponding target number of blocks in the memory are erased.

[0017] Optionally, before writing the target firmware into the memory, the method further includes:

[0018] Reading the write protection status of the memory;

[0019] If the write protection state is in the enabled state, controlling to disable the write protection of the memory so that the write protection state is switched from the enabled state to the disabled state;

[0020] The method further comprises:

[0021] After the target firmware is written into the memory, the write protection of the memory is controlled to be enabled, so that the write protection state is switched from the closed state to the enabled state.

[0022] Optionally, before writing the target firmware into the memory, the method further includes:

[0023] Acquire status information of the memory, the status information including a working state and an idle state;

[0024] If the memory is in the working state, the target firmware is controlled to be in a waiting-to-write state until the memory is in the idle state.

[0025] Optionally, before obtaining the status information of the memory, the method further includes:

[0026] Reading the value of the status register in the memory of the target chip;

[0027] According to the value of the status register, the status information of the memory of the target chip is obtained.

[0028] Optionally, obtaining the target firmware of the target chip includes:

[0029] Establish communication connection with external devices through Trivial File Transfer Protocol TFTP;

[0030] The target firmware sent by the external device is received through the TFTP.

[0031] Optionally, the target chip includes a network chip;

[0032] The method further comprises:

[0033] Reading and storing the media access control MAC address of the network chip;

[0034] Modify the data corresponding to the stored MAC address;

[0035] The MAC address stored in the memory of the network chip is erased, and the modified MAC address is written into the memory of the network chip.

[0036] In a second aspect, the present disclosure provides a firmware update device, which is applied to a baseboard management controller (BMC) chip, wherein the BMC chip is electrically connected to a target chip via four general-purpose input and output (GPIO) interfaces;

[0037] The firmware updating device comprises:

[0038] An acquisition module, configured to acquire the target firmware of the target chip;

[0039] An execution module is configured to conduct a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erase the firmware stored in the memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface, and a fourth level signal output by the fourth GPIO interface; and write the target firmware into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0040] In a third aspect, the present disclosure provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of any one of the methods provided in the first aspect when executing the computer program.

[0041] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any one of the methods provided in the first aspect.

[0042] In the technical solution provided by the present invention, the target firmware of the target chip is obtained; according to the first level signal output by the first GPIO interface, the transmission path between the BMC chip and the target chip is turned on; according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface, the firmware stored in the memory of the target chip is erased; according to the second level signal, the third level signal and the fourth level signal, the target firmware is written into the memory. In this way, based on the level signals output by the four general purpose input and output (GPIO) interfaces, the enable signal, serial data input signal, serial data output signal and shift clock signal of the SPI can be simulated, and the BMC chip can update the chip firmware through the signal output by the GPIO, breaking the limitations of the chip firmware upgrade on the operating system and control signals, thereby improving the convenience of firmware upgrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0044] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A schematic diagram of the server architecture provided by the present disclosure;

[0046] Figure 2 A flowchart of a firmware update method provided by the present disclosure;

[0047] Figure 3 A flowchart of another firmware update method provided by the present disclosure

[0048] Figure 4 A flowchart of another firmware update method provided by the present disclosure;

[0049] Figure 5 A flowchart of another firmware update method provided by the present disclosure;

[0050] Figure 6 A flowchart of another firmware update method provided by the present disclosure;

[0051] Figure 7 A flowchart of another firmware update method provided by the present disclosure;

[0052] Figure 8 A flowchart of another firmware update method provided by the present disclosure;

[0053] Figure 9 A schematic diagram of the structure of a firmware update device provided by the present disclosure;

[0054] Figure 10 A schematic diagram of the internal structure of a computer device provided by the present disclosure. DETAILED DESCRIPTION

[0055] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0057] The present disclosure is applied to a BMC chip, which is arranged on a mainboard of a server. Figure 1 A schematic diagram of a server architecture provided by the present disclosure is shown in FIG. Figure 1 As shown, the server architecture 100 includes a server 110 and an external device 120 . The server 110 includes a BMC chip 111 , other chips 112 , and a parameter detection device 113 .

[0058] The BMC chip 111 is electrically connected to other chips 112 via a GPIO interface. These chips 112 may be network chips, driver chips, or the like. The BMC chip 111 is electrically connected to a parameter detection device 113 via an I2C bus. The parameter detection device 113 may be a temperature sensor, humidity sensor, or the like. The BMC chip 111 can also communicate with an external device 120 via a local area network (LAN). The external device may be a computer, laptop, tablet, or the like. The BMC chip 111 can exchange data with other chips 112, the parameter detection device 113, and the external device 120 using corresponding communication protocols. The external device 120 can then transmit target firmware to the BMC chip 110.

[0059] The target chip in this disclosure can be one of the other chips in the aforementioned server. The BMC chip can be electrically connected to the target chip via four GPIO interfaces. The target chip's interfaces typically communicate with other devices via the SPI protocol. The target chip includes memory that stores firmware. The target firmware in this disclosure is the firmware to be updated corresponding to the target chip, i.e., the firmware that needs to be written to the target chip.

[0060] In the present disclosure, the level signal output by one of the four GPIO interfaces simulates the enable signal of SPI, and the transmission path between the BMC chip and the target chip is turned on, so that data can be transmitted between the BMC chip and the target chip. The level signals output by the other three of the four GPIO interfaces respectively simulate the serial data input signal, serial data output signal and shift clock signal of SPI, so that the firmware stored in the memory of the target chip can be erased, and the target firmware of the target chip obtained is written into the memory, thereby completing the firmware update of the target chip. Obviously, in the present disclosure, the level signal output based on the general purpose input and output (GPIO) interface can simulate the enable signal, serial data input signal, serial data output signal and shift clock signal of SPI, and the BMC chip can update the chip firmware through the signal output by GPIO, breaking the limitation of the chip firmware upgrade to the operating system and control signal, thereby improving the convenience of firmware upgrade.

[0061] The technical solution of the present disclosure is described below with several specific embodiments:

[0062] Figure 2 A flowchart of a firmware update method provided by the present disclosure is shown as follows: Figure 2 The method embodiment shown is applied to a BMC chip, which is electrically connected to a target chip via four general-purpose input and output (GPIO) interfaces. The specific steps include:

[0063] S101, obtaining the target firmware of the target chip.

[0064] Receive the target firmware of the target chip sent by the external device and store the target firmware in the memory inside the BMC chip. The memory here can be Flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0065] S103 : Conducting a transmission path between the BMC chip and the target chip according to the first level signal output by the first GPIO interface.

[0066] The first level signal output by the first GPIO interface can simulate an enable signal in SPI. The first level signal can be either a low-level signal or a high-level signal, depending on the target chip. For example, if the target chip uses a low-level signal under the SPI protocol, the first level signal is a low-level signal. If the target chip uses a high-level signal under the SPI protocol, the first level signal is a high-level signal. Based on the first level signal, the target chip is selected, i.e., the transmission path between the BMC chip and the target chip is connected, enabling data transmission between the BMC chip and the target chip.

[0067] S105 , erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface.

[0068] The second-level signal output by the second GPIO interface, the third-level signal output by the third GPIO interface, and the fourth-level signal output by the fourth GPIO interface can respectively simulate the serial data input signal, serial data output signal, and shift clock signal in SPI. By controlling the high and low levels of the second, third, and fourth-level signals, the firmware previously stored in the memory of the target chip can be erased, preparing for writing the target firmware. It should be noted that the memory of the target chip can be a Flash memory, EEPROM, or the like.

[0069] S107 , writing the target firmware into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0070] Based on the above embodiment, according to the control of the high and low levels of the second level signal, the third level signal and the fourth level signal, the target firmware can also be controlled to be written into the memory of the target chip, and the chip firmware is updated after the writing is completed.

[0071] In this embodiment, the target firmware of the target chip is obtained; according to the first level signal output by the first GPIO interface, the transmission path between the BMC chip and the target chip is turned on; according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface, the firmware stored in the memory of the target chip is erased; according to the second level signal, the third level signal and the fourth level signal, the target firmware is written into the memory. In this way, based on the level signals output by the four GPIO interfaces, the four signals of SPI, namely, the enable signal, the serial data input signal, the serial data output signal and the shift clock signal, are simulated. The BMC chip can update the chip firmware through the signal output by the GPIO, breaking the limitations of the chip firmware upgrade on the operating system and control signals, thereby improving the convenience of firmware upgrade.

[0072] Figure 3 A flowchart of another firmware update method provided by the present disclosure is shown below. Figure 3 for Figure 2 Based on the embodiment shown, before executing S105, the following steps are further included:

[0073] S1041: Determine the data volume of all contents in the target firmware according to all contents of the target firmware.

[0074] After acquiring the target firmware, all contents of the target firmware can be read and the space occupied by the contents, i.e., the data volume of all contents, can be determined based on the read contents. The data volume of all contents of the target firmware can also be determined based on the storage space occupied by the target firmware in the BMC memory.

[0075] S1042: Determine the target number of blocks that need to be erased in the memory according to the data volume of all contents in the target firmware.

[0076] The target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware.

[0077] When erasing data in the memory of the target chip, the unit is block. After erasing the data in a certain number of blocks in the memory, the target firmware needs to be stored in the erased area. In this way, the capacity of the erased area needs to be greater than or equal to the data volume of all the contents in the target firmware to ensure that all the contents of the target firmware can be written to the memory. Accordingly, the number of erased blocks can be determined according to the data volume of all the contents in the target firmware.

[0078] When the data volume of all content in the target firmware is not an integer multiple of the capacity of a block, for example, the data volume of all content in the target firmware is M, the capacity of a block is M', and N*M' < M < (N + 1)*M', it can be determined that the number of blocks to be erased in the memory is N + 1, that is, the target number is N + 1. In this way, the capacity of the target number of blocks in the memory is greater than the data volume of all content in the target firmware.

[0079] Based on the above embodiments, a specific description of a possible implementation manner when executing S105 is as Figure 3 shown:

[0080] S105’, according to the target number, erase the corresponding target number of blocks in the memory.

[0081] Erase the target number of blocks in the memory of the target chip so that there is enough space in the memory of the target chip to store all content of the target firmware.

[0082] In this embodiment, by determining the data volume of all content in the target firmware according to all content of the target firmware; determining the target number of blocks to be erased in the memory according to the data volume of all content in the target firmware, the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all content in the target firmware; erasing the corresponding target number of blocks in the memory according to the target number, so that the capacity corresponding to the erased blocks in the memory is greater than or equal to the space required to store the target firmware, ensuring the integrity of the written target firmware, thereby ensuring that the target firmware in the target chip can work properly.

[0083] Figure 4 This is a flowchart of another firmware update method provided by the present disclosure. Figure 4 For Figure 2 the embodiment shown, before executing S107, it further includes:

[0084] S1061, read the write protection status of the memory.

[0085] Read the current write protection status of the memory of the target chip. The write protection status includes an enabled state and a disabled state. If the memory of the target chip is currently in the write protection enabled state, no write operation can be performed on the memory of the target chip. If the memory of the target chip is currently in the write protection disabled state, a write operation can be performed on the memory of the target chip.

[0086] S1062, if the write protection status is the enabled state, control to turn off the write protection of the memory so that the write protection status switches from the enabled state to the disabled state.

[0087] If the memory of the target chip is currently in the write protection start state, the write protection state is changed so that the write protection state of the memory of the target chip is switched from the enabled state to the disabled state, ensuring that the target firmware can be written into the memory of the target chip subsequently.

[0088] Based on the above embodiment, after executing S107, if Figure 4 As shown, it also includes:

[0089] S108 , after the target firmware is written into the memory, controlling to enable write protection of the memory, so that the write protection state is switched from the closed state to the enabled state.

[0090] After all the target firmware is written into the memory of the target chip, the write protection of the target chip's memory is still in the off state. It is necessary to control the switching of the current write protection state of the target chip's memory so that the write protection of the target chip's memory is switched from the off state to the enabled state to prevent accidental writing to the target chip's memory.

[0091] In this embodiment, the write protection status of the memory is read; if the write protection status is enabled, the write protection of the memory is controlled to be turned off so that the write protection status is switched from enabled to disabled; after the target firmware is written into the memory, the write protection of the memory is controlled to be turned on so that the write protection status is switched from disabled to enabled, thereby protecting the writing of the memory of the target chip and preventing erroneous writing from affecting the operation of the target firmware.

[0092] Figure 5 A flowchart of another firmware update method provided by the present disclosure is shown below. Figure 5 for Figure 2 Based on the embodiment shown, before executing S107, the following steps are further included:

[0093] S201: Acquire status information of the memory.

[0094] Status information includes working status and idle status.

[0095] The current status information of the target chip's memory is obtained. If the target chip's memory currently has data transmission, it indicates that the target chip's memory is currently in a working state. If the target chip's memory currently has no data transmission, it indicates that the target chip's memory is currently in an idle state.

[0096] S202: If the memory is in the working state, control the target firmware to be in a waiting-to-write state until the memory is in the idle state.

[0097] When the target chip's memory is in an idle state, the target firmware is written into the target chip's memory. When the target chip's memory is in a working state, the target firmware is not transferred to the target chip's memory. At this time, the target firmware is in a waiting state until the target chip's memory is in an idle state, and then the target firmware is written into the target chip's memory.

[0098] In this embodiment, by obtaining the status information of the memory, the status information includes the working state and the idle state; if the memory is in the working state, the target firmware is controlled to be in the waiting-to-write state until the memory is in the idle state, so that the target firmware will only be written when the memory of the target chip is in the idle state, preventing the firmware update from affecting the normal operation of the target chip and maintaining the normal operation of the target chip.

[0099] Figure 6 A flowchart of another firmware update method provided by the present disclosure is shown below. Figure 6 for Figure 5 Based on the illustrated embodiment, a possible implementation method for executing S201 is specifically described as follows:

[0100] S2011, read the value of the status register in the memory of the target chip.

[0101] The memory of the target chip includes a status register, and the current value of the status register reflects the status information of the memory of the target chip. By reading the value of the status register in the memory of the target chip, the current status information of the memory of the target chip can be obtained.

[0102] S2012: Obtain status information of the memory of the target chip according to the value of the status register.

[0103] Different values ​​in the status register correspond to different status information. For example, if the value of the status register is 0, it means that the memory of the target chip is currently in an idle state. If the value of the status register is 1, it means that the memory of the target chip is currently in a working state.

[0104] Figure 7 A flowchart of another firmware update method provided by the present disclosure is shown below. Figure 7 for Figure 2 Based on the embodiment shown, before executing S101, the following steps are further included:

[0105] S301, establishing a communication connection with an external device via the Trivial File Transfer Protocol TFTP.

[0106] The BMC chip includes a Trivial File Transfer Protocol (TFTP) client program. External devices support TFTP. After the external device is paired with the BMC chip through TFTP, a communication connection is established between the BMC chip and the external device. The external device can be a computer, tablet, laptop, etc.

[0107] S302: Receive the target firmware sent by the external device through the TFTP.

[0108] Prepare the target firmware in the external device and send it to the BMC chip through TFTP. The BMC chip can receive the target firmware and obtain the target firmware without opening the OS.

[0109] In this embodiment, a communication connection is established with an external device through the simple file transfer protocol TFTP, and the target firmware sent by the external device is received through TFTP. The target firmware can be obtained without starting the OS, thereby improving the diversity of the target firmware acquisition channels.

[0110] Figure 8 A flowchart of another firmware update method provided by the present disclosure is shown below. Figure 8 for Figure 2 Based on the embodiment shown, the present invention further includes:

[0111] S401, reading and storing the media access control MAC address of the network chip.

[0112] Optionally, the target chip includes a network chip, each network chip corresponds to a Media Access Control (MAC) address, and the memory of the network chip stores the respective MAC addresses. The BMC chip reads the MAC address of the network chip and stores the MAC address.

[0113] S402: Modify the corresponding data in the stored MAC address.

[0114] The MAC address stored in the BMC chip is modifiable. For a MAC address that needs to be modified, the corresponding data in the BMC chip is modified to form a new MAC address.

[0115] S403: Erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

[0116] The MAC address stored in the memory of the network chip is erased, and the new MAC address stored in the BMC chip is written into the memory of the network chip, thereby updating the MAC address of the network chip.

[0117] In this embodiment, by reading and storing the media access control MAC address of the network chip; modifying the corresponding data in the stored MAC address; erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address to the memory of the network chip, the BMC chip can update the MAC address of the network chip, breaking the limitation of the network chip MAC address on the operating system, so that the MAC address of the network chip can be modified more conveniently.

[0118] The present disclosure also provides a firmware update device, Figure 9 This is a schematic diagram of the structure of a firmware update device provided by the present disclosure. Figure 9 The embodiment shown is applied to a BMC chip, which is electrically connected to a target chip via four general purpose input and output (GPIO) interfaces. Figure 9 As shown, including:

[0119] The acquisition module 210 is configured to acquire the target firmware of the target chip.

[0120] The execution module 220 is used to conduct the transmission path between the BMC chip and the target chip according to the first level signal output by the first GPIO interface; erase the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface; and write the target firmware into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0121] Optionally, the execution module 220 is further used to determine the data volume of all contents in the target firmware based on all contents of the target firmware; determine the target number of blocks that need to be erased in the memory based on the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware; and erase the corresponding target number of blocks in the memory based on the target number.

[0122] Optionally, the acquisition module 210 is further configured to read the write protection status of the memory.

[0123] The execution module 220 is also used to control the disabling of the write protection of the memory if the write protection state is in the enabled state, so that the write protection state is switched from the enabled state to the disabled state; after the target firmware is written into the memory, the write protection of the memory is controlled to be enabled, so that the write protection state is switched from the disabled state to the enabled state.

[0124] Optionally, the execution module 220 is further used to obtain status information of the memory, where the status information includes a working state and an idle state; if the memory is in the working state, the target firmware is controlled to be in a waiting-to-write state until the memory is in the idle state.

[0125] Optionally, the acquisition module 210 is further configured to read a value of a status register in the memory of the target chip; and acquire status information of the memory of the target chip according to the value of the status register.

[0126] Optionally, the execution module 220 is further configured to establish a communication connection with an external device via a simple file transfer protocol (TFTP); and receive the target firmware sent by the external device via the TFTP.

[0127] Optionally, the acquisition module 210 is further configured to read and store the media access control MAC address of the network chip.

[0128] The execution module 220 is further configured to modify the data corresponding to the stored MAC address; erase the MAC address stored in the memory of the network chip, and write the modified MAC address into the memory of the network chip.

[0129] The firmware update device provided in this embodiment is used to execute the steps of any of the above method embodiments, and has the technical solutions and technical effects of the method embodiments, which will not be described in detail here.

[0130] The embodiment of the present invention further provides a computer device, which may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 10 As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a method for switching customized applications is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad provided on the computer device housing, or an external keyboard, touchpad or mouse.

[0131] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0132] In one embodiment, the firmware update device provided by the present application can be implemented in the form of a computer program. Figure 10 The computer device shown in FIG. 1 is executed. The memory of the computer device may store various program modules constituting the switching device, such as, Figure 9 The acquisition module 110 and the execution module 120 are shown. The computer program composed of various program modules enables the processor to execute the steps of the firmware update method of each embodiment of the present application described in this specification.

[0133] For example, Figure 10 The computer device shown can be Figure 9 The acquisition module 110 in the firmware update apparatus shown executes step S101 , and the computer device can execute steps S103 , S105 , and S107 through the execution module 120 .

[0134] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0135] S101, obtaining the target firmware of the target chip.

[0136] S103 : Conducting a transmission path between the BMC chip and the target chip according to the first level signal output by the first GPIO interface.

[0137] S105 , erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface.

[0138] S107 , writing the target firmware into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0139] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0140] S1041: Determine the data volume of all contents in the target firmware according to all contents of the target firmware.

[0141] S1042: Determine a target number of blocks to be erased in the memory based on the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware.

[0142] S105 ′: erasing a corresponding target number of blocks in the memory according to the target number.

[0143] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0144] S1061: Read the write protection status of the memory.

[0145] S1062: If the write protection state is in the enabled state, control to disable the write protection of the memory, so that the write protection state is switched from the enabled state to the disabled state.

[0146] S108 , after the target firmware is written into the memory, controlling to enable write protection of the memory, so that the write protection state is switched from the closed state to the enabled state.

[0147] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0148] S201: Acquire status information of the memory.

[0149] S202: If the memory is in the working state, control the target firmware to be in a waiting-to-write state until the memory is in the idle state.

[0150] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0151] S2011, read the value of the status register in the memory of the target chip.

[0152] S2012: Obtain status information of the memory of the target chip according to the value of the status register.

[0153] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0154] S301, establishing a communication connection with an external device via the Trivial File Transfer Protocol TFTP.

[0155] S302: Receive the target firmware sent by the external device through the TFTP.

[0156] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0157] S401, reading and storing the media access control MAC address of the network chip.

[0158] S402: Modify the corresponding data in the stored MAC address.

[0159] S403: Erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

[0160] In the technical solution provided in this embodiment, the target firmware of the target chip is obtained; according to the first level signal output by the first GPIO interface, the transmission path between the BMC chip and the target chip is connected; according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface, the firmware stored in the memory of the target chip is erased; according to the second level signal, the third level signal and the fourth level signal, the target firmware is written into the memory. In this way, based on the level signals output by the four general purpose input and output (GPIO) interfaces, the enable signal, serial data input signal, serial data output signal and shift clock signal of the SPI can be simulated. The BMC chip can update the chip firmware through the signal output by the GPIO, breaking the limitations of the chip firmware upgrade on the operating system and control signals, thereby improving the convenience of firmware upgrade.

[0161] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the following steps are implemented:

[0162] S101, obtaining the target firmware of the target chip.

[0163] S103 : Conducting a transmission path between the BMC chip and the target chip according to the first level signal output by the first GPIO interface.

[0164] S105 , erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface.

[0165] S107 , writing the target firmware into the memory according to the second level signal, the third level signal, and the fourth level signal.

[0166] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0167] S1041: Determine the data volume of all contents in the target firmware according to all contents of the target firmware.

[0168] S1042: Determine a target number of blocks to be erased in the memory based on the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware.

[0169] S105 ′: erasing a corresponding target number of blocks in the memory according to the target number.

[0170] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0171] S1061: Read the write protection status of the memory.

[0172] S1062: If the write protection state is in the enabled state, control to disable the write protection of the memory, so that the write protection state is switched from the enabled state to the disabled state.

[0173] S108 , after the target firmware is written into the memory, controlling to enable write protection of the memory, so that the write protection state is switched from the closed state to the enabled state.

[0174] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0175] S201: Acquire status information of the memory.

[0176] S202: If the memory is in the working state, control the target firmware to be in a waiting-to-write state until the memory is in the idle state.

[0177] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0178] S2011, read the value of the status register in the memory of the target chip.

[0179] S2012: Obtain status information of the memory of the target chip according to the value of the status register.

[0180] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0181] S301, establishing a communication connection with an external device via the Trivial File Transfer Protocol TFTP.

[0182] S302: Receive the target firmware sent by the external device through the TFTP.

[0183] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0184] S401, reading and storing the media access control MAC address of the network chip.

[0185] S402: Modify the corresponding data in the stored MAC address.

[0186] S403: Erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

[0187] In the technical solution provided by the embodiment of the present invention, the target firmware of the target chip is obtained; according to the first level signal output by the first GPIO interface, the transmission path between the BMC chip and the target chip is connected; according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface, the firmware stored in the memory of the target chip is erased; according to the second level signal, the third level signal and the fourth level signal, the target firmware is written into the memory. In this way, based on the level signals output by the four general purpose input and output (GPIO) interfaces, the enable signal, serial data input signal, serial data output signal and shift clock signal of the SPI can be simulated. The BMC chip can update the chip firmware through the signal output by the GPIO, breaking the limitations of the chip firmware upgrade on the operating system and control signals, thereby improving the convenience of firmware upgrade.

[0188] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static random access memory (SRAM) and dynamic random access memory (DRAM).

[0189] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0190] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

[0191] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0192] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A firmware update method, characterized in that: Applied to a baseboard management controller (BMC) chip, the BMC chip is electrically connected to a target chip via four general-purpose input and output (GPIO) interfaces; The method comprises: Obtaining target firmware of the target chip; Conducting a transmission path between the BMC chip and the target chip according to a first level signal output by a first GPIO interface, wherein the first level signal output by the first GPIO interface is used to simulate an enable signal in SPI, and the first level signal output by the first GPIO interface is a low level signal or a high level signal; Erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface, wherein the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface are used to simulate the serial data input signal, the serial data output signal, and the shift clock signal in the SPI, respectively; The target firmware is written into the memory according to the second level signal, the third level signal, and the fourth level signal.

2. The method according to claim 1, characterized in that Before erasing the firmware stored in the memory of the target chip, the method further includes: Determining the data volume of all contents in the target firmware according to all contents of the target firmware; Determining a target number of blocks to be erased in the memory according to the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware; Erasing the firmware stored in the memory of the target chip includes: According to the target number, a corresponding target number of blocks in the memory are erased.

3. The method according to claim 1 or 2, characterized in that Before writing the target firmware into the memory, the method further includes: Reading the write protection status of the memory; If the write protection state is in the enabled state, controlling to disable the write protection of the memory so that the write protection state is switched from the enabled state to the disabled state; The method further comprises: After the target firmware is written into the memory, the write protection of the memory is controlled to be enabled, so that the write protection state is switched from the closed state to the enabled state.

4. The method according to claim 1 or 2, characterized in that Before writing the target firmware into the memory, the method further includes: Acquire status information of the memory, the status information including a working state and an idle state; If the memory is in the working state, the target firmware is controlled to be in a waiting-to-write state until the memory is in the idle state.

5. The method according to claim 4, characterized in that The acquiring of the state information of the memory includes: Reading the value of the status register in the memory of the target chip; According to the value of the status register, the status information of the memory of the target chip is obtained.

6. The method according to claim 1 or 2, characterized in that Before obtaining the target firmware of the target chip, the method further includes: Establish communication connection with external devices through Trivial File Transfer Protocol TFTP; The target firmware sent by the external device is received through the TFTP.

7. The method according to claim 1 or 2, characterized in that The target chip includes a network chip; The method further comprises: Reading and storing the media access control MAC address of the network chip; Modify the data corresponding to the stored MAC address; The MAC address stored in the memory of the network chip is erased, and the modified MAC address is written into the memory of the network chip.

8. A firmware update device, characterized in that: Applied to a baseboard management controller (BMC) chip, the BMC chip is electrically connected to a target chip via four general-purpose input and output (GPIO) interfaces; The firmware updating device comprises: An acquisition module, configured to acquire the target firmware of the target chip; An execution module is used to conduct the transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface, the first level signal output by the first GPIO interface is used to simulate the enable signal in SPI, and the first level signal output by the first GPIO interface is a low level signal or a high level signal; according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface, the firmware stored in the memory of the target chip is erased, the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface are used to simulate the serial data input signal, serial data output signal and shift clock signal in SPI respectively; according to the second level signal, the third level signal and the fourth level signal, the target firmware is written into the memory.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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