Storage devices for high-speed link booting and storage systems including such devices.

Abstract

A link initiation method for a storage device connected to a host via multiple channels includes performing an initialization operation in the storage device; establishing data communication via a transmission channel and a reception channel of the connection among the multiple channels; sending a high-speed link message to the host via the transmission channel of the connection of the storage device; and performing a link initiation operation in high-speed mode based on the high-speed link sent by the storage device via the transmission channel of the connection of the storage device and the reception channel of the connection of the host.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0073919, filed on June 17, 2020, and Korean Patent Application No. 10-2020-0167668, filed on December 3, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] At least some exemplary embodiments of the present invention relate to apparatuses and methods, and more specifically, to storage devices for high-speed link initiation and storage systems including said storage devices. Background Technology

[0004] A storage system consists of a host and storage devices. The host connects to the storage devices via various standard interfaces such as Universal Flash Memory (UFS), Serial Advanced Technology Attached (SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and eMMC. When the storage system is used in mobile devices, high-speed operation between the host and storage devices is crucial, and fast link startup between the host and storage devices is necessary. Summary of the Invention

[0005] At least some exemplary embodiments of the present invention provide a storage device and a storage system including the storage device capable of performing link booting in high-speed mode between a storage device and a host. According to at least some exemplary embodiments of the present invention, a link booting method for a storage device connected to a host via multiple channels includes performing an initialization operation in the storage device; establishing data communication via a transmission channel and a reception channel of the connection among the multiple channels; sending a high-speed link message to the host via the transmission channel of the connection of the storage device; and performing a link booting operation in high-speed mode via the transmission channel of the connection of the storage device and the reception channel of the connection of the host based on the high-speed link message sent by the storage device.

[0006] According to at least some exemplary embodiments of the present invention, a link initiation method for a host connected to a storage device via at least one channel includes: performing initialization in a high-speed mode in the host; establishing data communication via a transmission channel and a reception channel of the connection in at least one channel; determining whether a high-speed link message is received from the storage device via the reception channel of the host connection; identifying the reception channel of the connection through which the high-speed link message is received from the storage device, as a result of the determination; and performing a link initiation operation in high-speed mode via the transmission channel of the storage device connection and the reception channel of the host connection in response to identifying the reception channel of the connection through which the high-speed link message is received.

[0007] According to at least some exemplary embodiments of the present invention, a storage device is provided, comprising: an interconnect portion including at least one receiver and at least one transmitter, the interconnect portion performing data communication via a transmit channel and a receive channel in at least one channel connected between a host device and the storage device; a non-volatile memory; and a storage controller configured to control the non-volatile memory, wherein the storage controller is further configured such that at least one transmitter transmits a high-speed link message to the host device via the transmit channel, and is configured to perform link initiation in high-speed mode via the transmit channel and the receive channel based on a high-speed link if a low-speed link message is not received from the host device via the receive channel within a set time after the transmission of the high-speed link message.

[0008] According to at least some exemplary embodiments of the present invention, a host device is provided, comprising: an interconnect portion including at least one receiver and at least one transmitter, wherein the interconnect portion performs data communication via a transmit channel and a receive channel connected in at least one channel between the host device and a storage device, and the host device is configured to perform link initiation in high-speed mode via the receive channel and the transmit channel when the at least one receiver determines whether to receive a high-speed link message from the storage device via the receive channel and receives the high-speed link message from the storage device as a result of the determination. Attached Figure Description

[0009] The above and other features and advantages of the exemplary embodiments of the inventive concept will become more apparent from the detailed description of them with reference to the accompanying drawings. The drawings are intended to depict exemplary embodiments of the inventive concept and should not be construed as limiting the intended scope of the claims. Unless explicitly stated otherwise, the drawings should not be considered as drawn to scale.

[0010] Figure 1 This is a block diagram of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0011] Figure 2It is used to describe Figure 1 A diagram illustrating the interface between the host and storage devices in a computer.

[0012] Figure 3 It is used to describe Figure 2 A timing diagram showing the status of the lines in the diagram;

[0013] Figure 4 It is an illustration used to describe high-speed link operation through a storage device according to at least some exemplary embodiments of the present invention;

[0014] Figure 5 It is a diagram used to describe high-speed connection operations through the host, as... Figure 4 Comparison examples;

[0015] Figure 6 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0016] Figure 7 It is a diagram illustrating a method of operation of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0017] Figure 8 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0018] Figure 9 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0019] Figure 10 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0020] Figure 11 It is a diagram illustrating a method of operation of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention;

[0021] Figure 12 It is a signaling diagram used to describe at least some exemplary embodiments of the link initiation sequence according to the present invention;

[0022] Figure 13 This is a block diagram of a system applying at least one exemplary embodiment of a storage device according to the concept of the present invention;

[0023] Figure 14 This is a block diagram of a Universal Flash Memory (UFS) system according to at least one exemplary embodiment of the present invention;

[0024] Figures 15A to 15C It is a diagram used to describe the shape factor of a UFS card;

[0025] Figure 16 This is a block diagram of a non-volatile memory (NVM) storage device according to at least one exemplary embodiment of the present invention;

[0026] Figure 17 This is a block diagram of an NVM storage device according to at least one exemplary embodiment of the present invention.

[0027] Figure 18 yes Figure 17 A block diagram of a memory device;

[0028] Figure 19 It is a diagram illustrating a three-dimensional vertical NAND (3D V-NAND) structure applicable to UFS devices, according to at least one exemplary embodiment of the present invention; and

[0029] Figure 20 This is a cross-sectional view of a BVNAND structure applicable to a UFS device according to at least one exemplary embodiment of the present invention. Detailed Implementation

[0030] As is customary in the field of this invention, embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of this invention, each block, unit, and / or module of an embodiment may be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0031] Figure 1 This is a block diagram of a storage system 10 according to at least some exemplary embodiments conceived in accordance with the present invention.

[0032] See Figure 1The storage system 10 may include a host 20 and a storage device 30. The host 20 and storage device 30 may be interconnected according to the interface protocol defined in the Universal Flash Storage (UFS) specification, and accordingly, the storage device 30 may be a UFS storage device, and the host 20 may be a UFS host. However, at least some exemplary embodiments of the inventive concept are not limited thereto, and the storage device 30 and host 20 may be interconnected according to various standard interfaces.

[0033] The host 20 can control data processing operations on the storage device 30, such as data read operations or data write operations. The host 20 can instruct a data processing device capable of processing data, such as a central processing unit (CPU), processor, microprocessor, or application processor (AP). The host 20 can execute an operating system (OS) and / or various applications. According to at least one exemplary embodiment of the present invention, the storage system 10 can be included in a mobile device, and the host 20 can be implemented by an AP. According to at least one exemplary embodiment of the present invention, the host 20 can be implemented by a system-on-a-chip (SoC) and accordingly embedded in an electronic device.

[0034] Although host 20 and storage device 30 are illustrated in this embodiment as including multiple conceptual hardware components, this embodiment is not limited thereto and may include other components. Host 20 may include interconnect portion 22 and host controller 24. Interconnect portion 22 may provide an interface 40 between host 20 and storage device 30. Interconnect portion 22 may include a physical layer and a link layer. The physical layer of interconnect portion 22 may include physical components configured to exchange data with storage device 30, for example, including at least one transmitter TX and at least one receiver RX. Interconnect portion 22 in host 20 may include, for example, four transmitters TX1 to TX4 and four receivers RX1 to RX4. The link layer of interconnect portion 22 may manage the transmission and / or composition of data, and manage data integrity and errors.

[0035] Storage device 30 may include interconnect portion 32, storage controller 34, and non-volatile memory (NVM) 36. Storage controller 34 may control NVM 36 in response to a write request from host 20 to write data to NVM 36, or in response to a read request from host 20 to read data stored in NVM 36. Storage controller 34 may include processing circuitry, such as hardware including logic circuitry; hardware / software combination executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, one or more of a central processing unit (CPU), processor core, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0036] Interconnect portion 32 can provide an interface 40 between storage device 30 and host 20. For example, interconnect portion 32 may include a physical layer and a data link layer. The physical layer of interconnect portion 32 may include physical components configured to exchange data with storage device 30, such as at least one transmitter TX and at least one receiver RX. Interconnect portion 32 in storage device 30 may include, for example, four receivers RX1 to RX4 and four transmitters TX1 to TX4. The data link layer of interconnect portion 32 can manage the transmission and / or composition of data, and manage data integrity and errors.

[0037] According to at least one exemplary embodiment of the present invention, when the storage system 10 is a mobile device, the physical layers of interconnect portions 22 and 32 can be defined by the "M-PHY" specification, and their link layers can be defined by the "UniPro" specification. M-PHY and UniPro are interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance. Each link layer of interconnect portions 22 and 32 may include a physical adaptation layer, and the physical adaptation layer can control the physical layer to manage data symbols and manage power.

[0038] The transmitter TX included in the interconnect portion 22 of the host 20 and the receiver RX included in the interconnect portion 32 of the storage device 30 can form a channel, such as Figure 2As shown. Furthermore, the transmitters TX included in the interconnect portion 32 of the storage device 30 and the receivers RX included in the interconnect portion 22 of the host 20 can also form a channel. This embodiment shows that the number of transmitters TX1 to TX4 and receivers RX1 to RX4 included in the interconnect portion 22 of the host 20 are the same as the number of receivers RX1 to RX4 and transmitters TX1 to TX4 included in the interconnect portion 32 of the storage device 30. According to an exemplary embodiment, the number of transmitters TX and receivers RX included in the interconnect portion 22 of the host 20 may differ from the number of receivers RX and transmitters TX included in the interconnect portion 32 of the storage device 30. Furthermore, the function of the host 20 may differ from the function of the storage device 30.

[0039] Host 20 and storage device 30 can identify the physical connection channel and perform processing for receiving information about each other's devices, such as link initiation. Host 20 and storage device 30 can perform a Link Initiation Sequence (LSS) before exchanging data. By performing the LSS, host 20 and storage device 30 can exchange and learn information about the number of transmitters (TX) and receivers (RX), information about the physical connection channel, information about the functionality of each other's devices, etc. After completing the LSS, host 20 and storage device 30 can be configured to a link state that allows for stable data exchange.

[0040] Link start-up (LSS) can be performed during the initialization operation when storage system 10 is first used, or during the booting operation of storage system 10. Alternatively, LSS can be performed during recovery operations for link state errors. Because LSS requires exchanging a large amount of information about host 20 and storage device 30, it can take a considerable amount of time to execute. Furthermore, when LSS is performed between host 20 and storage device 30 in low-speed (LS) mode, the link start-up operation can take even longer. To shorten the link start-up time, host 20 can perform the link start-up operation in high-speed (HS) mode. The link start-up operation performed in HS mode can also be called the HS link start-up operation.

[0041] In some examples, host 20 may send an HS link start message to storage device 30 before storage device 30 is ready to perform the link start operation, thus initiating the HS link start operation. Therefore, storage device 30 may not respond to the HS link start message. Accordingly, because no link start receive response is received from storage device 30, host 20 may perform a retry operation to retry the HS link start operation (e.g., by retransmitting the HS link start message). Due to host 20's retry operation, the link start time may be long. Conversely, if storage device 30 is able to send the HS link start message after completing the initialization operation, if this is possible, storage device 30 may not wait for the HS link start message from host 20, and host 20 can perform the HS link start operation without retrying, thus shortening the link start time.

[0042] The storage controller 34 can perform data communication via a connected transmit channel and a connected receive channel among the multiple channels included in the interconnect portion 32. The storage controller 34 can perform control by issuing an activation cycle or an activation cycle and a line reset cycle via the connected transmit channel to send an HS link message to the host 20. Accordingly, the storage device 30 can perform link initiation with the host 20 in HS mode.

[0043] The host controller 24 can perform control to enable data communication via a connected transmit channel and a connected receive channel among multiple channels included in the interconnect portion 22. The host controller 24 can perform control by receiving an activation cycle or an activation cycle and a line reset cycle via the connected receive channel, so that the host 20 performs an HS link startup operation. Accordingly, the host 20 can perform a link startup operation with the storage device 30 in HS mode. The host controller 24 may include processing circuitry, such as hardware including logic circuitry; hardware / software combinations executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, one or more of a central processing unit (CPU), processor core, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0044] NVM 36 may include multiple storage cells, and the multiple storage cells may be, for example, flash memory cells. In at least one exemplary embodiment of the present invention, the multiple storage cells may be NAND flash memory cells. However, at least some exemplary embodiments of the present invention are not limited thereto, and in another embodiment, the multiple storage cells may be resistive storage cells, such as resistive random access memory (ReRAM or RRAM) storage cells, phase-change random access memory (PRAM) storage cells, or magnetic random access memory (MRAM) storage cells.

[0045] In some embodiments, storage device 30 may be implemented as a DRAM-less device, and a DRAM-less device may refer to a device that does not include a DRAM cache. In this case, storage controller 34 may not include a DRAM controller. For example, storage device 30 may use a portion of NVM 36 as buffer memory.

[0046] In some embodiments, storage device 30 may be internal memory embedded in an electronic device. For example, storage device 30 may be an embedded UFS memory device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). However, at least some exemplary embodiments of the present invention are not limited thereto, and storage device 30 may be an NVM (e.g., an OTPROM, a PROM, an EPROM, an EEPROM, a mask ROM, or a flash ROM). In some embodiments, storage device 30 may be external memory detachably attached to an electronic device. For example, storage device 30 may include at least one of a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a micro-SD card, a mini-SD card, an xD card, and a memory stick.

[0047] Storage system 10 can be implemented by electronic devices such as personal computers (PCs), laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), or digital still cameras, digital video cameras, audio equipment, portable multimedia players (PMPs), personal navigation devices or portable navigation devices (PNDs), MP3 players, handheld game consoles, or e-readers. Alternatively, storage system 10 can be implemented by various types of electronic devices, such as wearable devices like watches or head-mounted displays (HMDs).

[0048] Figure 2 It is used to describe Figure 1A diagram illustrating the interface 40 between the host 20 and the storage device 30. This will be discussed in... Figure 2 The concepts of channel, line, and link in interface 40 are described below. For ease of description, the following will representatively describe the concepts included... Figure 1 The multiple transmitters and receivers in the interconnection portions 22 and 32, the transmitter TX1 in the interconnection portion 32 of the storage device 30, and the receiver RX1 in the interconnection portion 22 of the host 20.

[0049] Reference Figure 2 Interface 40 can support multiple channels. Each channel is a transmit channel carrying unidirectional, single-signal information. A channel may include a transmitter TX1, a receiver RX1, and a point-to-point interconnect between the transmitter TX1 and the receiver RX1. The transmitter TX1 or receiver RX1 has a differential output or input line interface that matches the two signal transmission pins. The pins are indicated by DP, indicating the positive node of the differential signal, and DN, indicating the negative node of the differential signal, respectively. A selective prefix TX or RX may be attached to each of the pins DP and DN to indicate the transmitter pin or the receiver pin. The line includes a wiring of two differential wires connecting the pins of the transmitter TX1 and the receiver RX1. This wiring is the transmit line.

[0050] Interface 40 includes at least one channel in each direction. The number of channels in each direction does not need to be symmetrical. The link may include one or more channels in each direction, as well as channel management sections 21 and 31 configured to provide bidirectional data transmission capabilities. Although Figure 2 The channel management sections 21 and 31, host controller 24 and storage controller 34 shown are separately separated, but at least some exemplary embodiments of the present invention are not limited thereto, and the channel management sections 21 and 31 may be included in the host controller 24 and storage controller 34 respectively.

[0051] Figure 3 It is used to describe Figure 2 Timing diagram of the status of the intermediate circuit.

[0052] Reference Figure 2 and Figure 3 The line can have a DIF-Z state with almost zero differential line voltage, a DIF-N state with negative differential line voltage, or a DIF-P state with positive differential line voltage. Alternatively, although not in Figure 3 As shown, a line can have a DIF-Q state indicating a high impedance state, or a DIF-X state, which is neither a DIF-N state nor a DIF-P state. In this paper, the differential line voltage can be defined by subtracting the voltage of the line connected to the negative node from the voltage of the line connected to the positive node.

[0053] In the line between transmitter TX1 and receiver RX1, when transmitter TX1 is in sleep mode (hereinafter referred to as "HIBERN8 state"), receiver RX1 can keep the line in DIF-Z state, which is an ultra-low power saving state. During the period from time point T1 to time point T2 in DIF-Z state, the line is in HIBERN8 state. The time between time point T1 and time point T2 is called the sleep period T. HIBERN8 .

[0054] At time T2, transmitter TX1 can switch the line to the DIF-N state to signal its exit from the HIBERN8 state. In this case, receiver RX1 can detect the DIF-N state of the line and knows that the link between both transmitter TX1 and receiver RX1 is ready for use, and that both transmitter TX1 and receiver RX1 will exit the HIBERN8 state. The time between time T2 and time T3, during which the line is in the DIF-N state, is called the activation period T. ACTIVATE According to at least one exemplary embodiment of the present invention, the activation period T ACTIVATE The length can be less than approximately 0.9 ms. In another embodiment, the activation period T ACTIVATE The length can be less than approximately 1.6 ms.

[0055] For example, when the activation period T of the line ACTIVATE When the length is less than 0.9ms, transmitter TX1 and receiver RX1 can enter HS-MODE. When the line's activation period T... ACTIVATE When the duration is 0.9ms or longer, transmitter TX1 and receiver RX1 can enter LS mode (LS-MODE). LS mode (LS-MODE) can correspond to pulse width modulation (PWM) mode.

[0056] At time T3, transmitter TX1 can switch the line to the DIF-P state to send a signal for a line reset operation. In this case, receiver RX1 can detect the DIF-P state of the line and know that both transmitter TX1 and receiver RX1 are ready to perform a line reset operation, and will execute the line reset operation. The time between time T3 and time T4, during which the line is in the DIF-P state, is called the line reset period T. LINE-RESET According to at least one exemplary embodiment of the present invention, the line reset period T LINE-RESET The length can be approximately 3.1 ms or more.

[0057] Figure 4This is a diagram illustrating the operation of the HS link via the storage device 30 according to at least some exemplary embodiments of the present invention.

[0058] Reference Figure 4 When a power-up is detected according to the guidance of storage system 10, storage device 30 can perform initialization operation 400. Initialization operation 400 of storage device 30 may include reading initialization information stored in the NVM 36 included in storage device 30 and setting the read initialization information in a configuration register. For example, initialization information may include protection information regarding whether programming / discarding is disabled (e.g., storage or erasure of data in non-volatile memory), fine-tuning data for fine-tuning the operating voltage level in operating modes, column repair information for repairing faulty bit lines, information about bad blocks including bad memory cells, etc. Fine-tuning data is data used not only to configure voltage adjustments in the operating modes of NVM 36 (e.g., read operation, program operation, and discard operation), but also to configure adjustments to sense amplifiers or page buffers, optimization of reference cells, etc.

[0059] Storage device 30 may perform line reset operation 410 after completing initialization operation 400. Line reset operation 410 may include: resetting the transmitter TX of the connected channel and sending a line reset message to host 20, the message including information indicating that the transmitter TX has been reset. Host 20 may receive the line reset message sent from storage device 30 and perform line reset operation 412. Line reset operation 412 may include: resetting the receiver RX of the connected channel; and sending a line reset message to storage device 30, the message including information indicating that the receiver RX has been reset. Line reset operations 410 and 412 may include resetting or clearing all attributes of the physical layer of interconnect portions 32 and 22 to default values. Storage device 30 and host 20 may exchange line reset information with each other (e.g., via line reset messages).

[0060] Storage device 30 can perform a line reset operation 410, and then perform an HS link operation 420, which includes sending an HS link message to host 20. Host 20 can receive the HS link message sent by storage device 30 and perform HS operation 422, which includes performing LSS in HS mode, including the exchange of trigger events with storage device 30, function information exchange, control frame exchange, etc. The following will refer to... Figure 12 Describe LSS. For example, in Figure 12As shown in more detail below, the LSS operation between host 20 and storage device 30 includes each of host device 20 and storage device 30 performing multiple operations, including, for example, sending and receiving multiple messages (e.g., including triggering events of primitives). In this specification, a link operation performed at host device 20 (e.g., HS link operation 422) refers to a portion of the LSS between storage device 30 and host 20 performed by host device 20, and a link operation performed by storage device 30 (e.g., HS link operation 420) refers to a portion of the LSS between storage device 30 and host 20 performed by storage device 30.

[0061] When the HS link operation is performed by the storage device 30, the link startup time T between the storage device 30 and the host 20 is... LS1 This is represented as the time from the start of the line reset operation 410 of storage device 30 to the end of the HS link operation 422 of host 20. It is determined by the link startup time T of storage device 30. LS1 It can be relatively smaller than Figure 5 The link startup time T of host 20 LS2 .like Figure 5 As shown, the link between host 20 and storage device 30 via host 20 may take a relatively long time.

[0062] Figure 5 This is a diagram used to describe the HS link through host 20, as... Figure 4 Comparison examples.

[0063] Reference Figure 5 Host 20 can perform a first line reset operation 510. The first line reset operation 510 may include: resetting the transmitter TX of the connected channel; and sending a line reset message to storage device 30, which includes information indicating that the transmitter TX has been reset. After performing the line reset operation 510, host 20 can perform a first HS link operation 520. The first HS link operation 520 may include sending an HS link message to storage device 30. Host 20 can send the first HS link message and then anticipate participating in LSS with storage device 30 in HS mode. However, when host 20 sends the first line reset message and the first HS link message to storage device 30 during the first line reset operation 510 and the first HS link operation 520, respectively, storage device 30 may be performing an initialization operation 500. That is, host 20 may perform the first line reset operation 510 and the first HS link operation 520 without knowing whether storage device 30 has completed the initialization operation 500, and / or without storage device 30 being ready to perform the link initiation operation.

[0064] After the first HS link message is sent during the first HS link operation 520, a timeout period T is elapsed after which no link initiation operation with storage device 30 is performed. TIMEOUT During this time, host 20 can perform retry operations, including sending a second line reset message during second line reset operation 530 and sending a second HS link message during second HS link operation 540. Storage device 30 can receive the second line reset message and the second HS link message, and execute LSS in HS mode. This LSS includes trigger event exchange, function information exchange, control frame exchange, etc. with host 20.

[0065] When host 20 performs an HS link operation, the link startup time T between host 20 and storage device 30 is... LS2 This is represented as the time from the start of the first line reset operation 510 of host 20 to the end of the second HS link operation 542 of storage device 30. The link startup time T of host 20 is also considered. LS2 It can be relatively larger than Figure 4 The link startup time T of storage device 30 in the middle LS1 .

[0066] Figure 6 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention. (Refer to...) Figure 6 To describe Figure 1 Operation of storage device 30 in storage system 10 shown.

[0067] Reference Figure 1 , Figure 2 , Figure 3 and Figure 6 In operation S610, when power-on is detected according to the boot order of storage system 10, storage device 30 can perform an initialization operation. During the initialization operation, storage device 30 can read initialization information stored in NVM 36 and set the read initialization information in the configuration register.

[0068] After initialization information is executed in operation S610, storage device 30 can perform HS link operation, which may include HS link message sent to host 20 through the connected transmission channel in operation S620.

[0069] In operation S630, storage device 30 can determine whether an LS link message has been received through the connected receive channel. This determination may include: determining whether reception occurred during the activation period T. ACTIVATE The middle or line reset period T LINE-RESET Executed in the activation period T ACTIVATEThe receiving channel connected in the middle is in the DIF-N state, starting from the DIF-Z state, and during the reset period T of this line... LINE-RESET The intermediate line is in the DIF-P state; and the line reset period T LINE-RESET The length is either the first time or longer. For example, the first time can be set to approximately 3.1ms.

[0070] As a result of operation S630, when an LS link message is received through the connected receive channel, storage device 30 can proceed to operations S660 and S670. Storage device 30 can be initialized to LS mode in operation S660, and then LSS is executed in LS mode in operation S670. Afterwards, storage device 30 can be in an LS link state with host 20.

[0071] As a result of operation S630, if an LS link message is not received through the connected receive channel, storage device 30 may proceed to operations S640 and S650. In operation S640, storage device 30 may perform an LSS with host 20 in HS mode. In operation S650, storage device 30 may determine whether the HS link status with host 20 is successful (e.g., whether the HS mode LSS between host 20 and storage device 30 has been successfully started), and as a result, if the HS link status with host 20 is unsuccessful, storage device 30 may proceed to operation S620 to retry sending the HS link message to host 20.

[0072] In this embodiment, during LS-mode link startup executed in PWM mode, when information required for link startup is exchanged between storage device 30 and host 20 via a channel (connected transmit channel or connected receive channel), the bits indicating the information required for link startup can be represented by the pulse width of the signal transmitted via the channel. In LS-mode link startup under PWM mode, a return-to-zero (RZ) scheme can be applied, where a logic low-level period must exist between two logic high-level periods of the signal transmitted via the channel.

[0073] Unlike LS mode link startup, in HS mode link startup, the bits indicating the information required for link startup can be represented by the logic levels of signals transmitted through the channel. In HS mode link startup, a non-return-to-zero (NRZ) scheme can be applied, where even if logic high-level periods are consecutive, there need not be logic low-level periods between them. Consequently, HS link startup can be performed at a higher speed than LS link startup.

[0074] Figure 7 This is an illustration of a method of operating a storage system, based on at least some exemplary embodiments conceived in accordance with the present invention.

[0075] Reference Figure 6 and Figure 7 In operation S620, when storage device 30 is performing an HS link operation, which includes sending an HS link initiation message to host 20 to attempt to initiate an HS link operation at host 20, host 20 can perform an LS link operation, including sending an LS link message to storage device 30 via the connected transmission channel in operation S700. For example, as... Figure 7 As shown, when storage device 30 attempts to participate in an HS link startup operation (e.g., HS mode LSS) with host 20, host 20 may also be attempting to participate in an LS link startup operation (e.g., LS mode LSS) with storage device 30. In this case, host 20 can perform an LS link operation, including sending an LS link startup primitive LS_LinkStartUp.ind to storage device 30, to attempt to initiate an LS link operation at storage device 30 so that host 20 and storage device 30 can participate in LS mode LSS together. Host 20 can initiate the LS link operation through the first trigger event TRG_UPR0 of the LSS. Figure 12 The LS link startup primitive LS_LinkStartUp.ind is sent by carrying the LS link startup primitive LS_LinkStartUp.ind on the device.

[0076] Host 20 can transmit the first trigger event TRG_UPR0, including the LS link start primitive LS_LinkStartUp.ind, through all transmit channels. Host 20 can continuously transmit the first trigger event TRG_UPR0 until it is received by a channel connected to storage device 30, such as a receive channel. In operation S630, storage device 30 can receive the LS link start primitive LS_LinkStartUp.ind included in the first trigger event TRG_UPR0 transmitted from host 20 through a connected receive channel.

[0077] Storage device 30 can receive the LS link start primitive LS_LinkStartUp.ind from host 20 with priority, initialize it to LS mode state in operation S660, and execute LSS in LS mode in operation S670.

[0078] Figure 8 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention. (Refer to...) Figure 8 To describe Figure 1 Operation of storage device 30 in storage system 10 shown.

[0079] refer to Figure 8 ,and Figure 6 In contrast, the difference lies in the activation period T during which the storage device 30 determines the connection channel's line to be in the DIF-N state in operation S830. ACTIVATE Is the length less than the second time T? HS The following text will refer to... Figure 6 This will be described in detail here, and will not be repeated.

[0080] Before operating S830, the line connecting the channel to storage device 30 may not be in the DIF-N state; for example, it may be in the DIF-Z state. Second time T HS It could be, for example, 0.9 ms. According to an exemplary embodiment, the second time T... HS It can be set to something other than 0.9ms. For example, the second time T HS It can have a value less than 0.9ms or a value greater than 0.9ms (e.g., 1.6ms).

[0081] As a determined result in operation S830, when the activation period T of the connected channel... ACTIVATE The length is the second time T HS When the above is true, storage device 30 can proceed to operations S660 and S670.

[0082] As a determined result in operation S830, when the activation period T of the connected channel... ACTIVATE The length is less than the second time T HS At that time, storage device 30 can perform operations S640 and S650.

[0083] Figure 9 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention. (Refer to...) Figure 9 To describe Figure 1 Operation of host 20 in storage system 10 shown.

[0084] Reference Figure 1 , Figure 2 and Figure 9 In operation S910, host 20 can be initialized to HS mode and put into standby mode. In operation S920, host 20 can determine whether it has received an HS link message from storage device 30 through the connected receive channel. This determination may include: determining whether it is during the activation period T. ACTIVATE The middle or line reset period T LINE-RESET Receive is performed during the activation period T. ACTIVATE The receiving channel connected in the middle is in the DIF-N state from the DIF-Z state, during the line reset period T. LINE-RESETThe line is in DIF-P state; and the line reset period T LINE-RESET The length is either the first time or longer. For example, the first time can be set to approximately 3.1ms.

[0085] As a result of operation S920, when an HS link message is received through the connected receiving channel, host 20 can proceed to operations S930 and S940. In operation S930, host 20 can perform an LSS with storage device 30 in HS mode. In operation S940, host 20 can determine whether the HS link with storage device 30 is successful (e.g., determine whether an HS mode LSS between host 20 and storage device 30 has been successfully initiated). As a result of operation S940, when the HS link with storage device 30 is successful, host 20 can remain in the HS link state with storage device 30. As a result of operation S940, when the HS link with storage device 30 is unsuccessful, host 20 can proceed to operation S910 to standby in HS mode.

[0086] As a result of operation S920, if no HS link message is received through the connected receive channel, host 20 can proceed to operations S950 and S960. Host 20 can attempt an LS link operation, which may include the LS link message sent to storage device 30 in operation S950, to attempt to initiate an LS link operation at storage device 30, so that host 20 and storage device 30 can participate together in LS mode LSS in operation S960. Afterwards, host 20 can be in an LS link state with storage device 30.

[0087] Figure 10 This is a flowchart illustrating an operation method of a storage system according to at least some exemplary embodiments conceived in accordance with the present invention. (Refer to...) Figure 10 To describe Figure 1 Operation of host 20 in storage system 10 shown.

[0088] Reference Figure 10 ,and Figure 9 The difference lies in that host 20 determines in operation S1020 whether the HS link start primitive HS_LinkStartUp.ind has been received through the connected channel. This will be discussed further below. Figure 9 The description will be provided and will not be repeated.

[0089] Host 20 can be in standby mode in operation S910, and in operation S1020 it determines whether it has received the HS link start primitive HS_LinkStartUp.ind through the connected channel. The HS link start primitive HS_LinkStartUp.ind can be sent from storage device 30 to host 20, indicating that host 20 is performing an HS link operation and is attempting to initiate an HS link operation at storage device 30, so that host 20 and storage device 30 can participate in HS mode LSS together.

[0090] As a result of operation S1020, upon receiving the HS link start primitive HS_LinkStartUp.ind, host 20 knows that storage device 30 will attempt an HS link operation. Subsequently, in operation S930, host 20 can perform an LSS with storage device 30 in HS mode.

[0091] As a result of operation S1020, when the HS link start primitive HS_LinkStartUp.ind is not received, host 20 can know that storage device 30 may have product specifications that do not include attempting HS link operation. Subsequently, host 20 can attempt LS link operation, which may include sending an LS link message to storage device 30 in operation S950 to initiate the participation of storage device 30 in the LSS in LS mode in operation S960.

[0092] Figure 11 This is an illustration of a method of operating a storage system, based on at least some exemplary embodiments conceived in accordance with the present invention.

[0093] Reference Figure 10 and Figure 11 In storage system 10, a low-level activated reset signal RESET_n is released, and the line connected to the channel of host 20 is in the HIBERN8 state of DIF-Z. In operation S910, host 20 can exit the HIBERN8 state, be initialized to HS mode, and enter standby mode. In operation S1020, host 20 can determine whether, at the third time T since the release of the reset signal RESET_n... HS-DEVICE-INITIAL The HS link startup primitive HS_LinkStartUp.ind is received from storage device 30. Third time T HS-DEVICE-INITIAL This can be set to the time it takes for storage device 30 to be initialized to HS mode. In other words, it can be set in the third time T. HS-DEVICE-INITIAL The storage device 30 is initialized to HS mode and an HS link operation is attempted. For example, in the third time T HS-DEVICE-INITIAL It can be set to approximately 10ms.

[0094] Storage device 30 can transmit a first trigger event TRG_UPR0, including the HS link start primitive HS_LinkStartUp.ind, through all transmit channels. Storage device 30 can continuously transmit the first trigger event TRG_UPR0 until a channel connected to host 20 (e.g., an available receive channel) receives the first trigger event TRG_UPR0. In operation S1020, host 20 can receive the HS link start primitive HS_LinkStartUp.ind included in the first trigger event TRG_UPR0 transmitted from storage device 30 through a connected receive channel.

[0095] If the HS link start primitive HS_LinkStartUp.ind is not received via the connected channel in operation S1020, host 20 may attempt to perform a low-speed (LS) link operation in operation S950 by sending an LS link message to storage device 30 via all transmit channels. The LS link message may include a first trigger event TRG_UPR0, which may include the LS link start primitive LS_LinkStartUp.ind. Host 20 may continuously send the first trigger event TRG_UPR0 until a channel connected to storage device 30 (e.g., an available receive channel) receives the first trigger event TRG_UPR0.

[0096] In operations S960 and S1100, storage device 30 can receive a first trigger event TRG_UPR0 including the LS link start primitive LS_LinkStartUp.ind, and perform an LSS with host 20 in LS mode.

[0097] Figure 12 It is a signaling diagram used to describe at least some exemplary embodiments of the LSS according to the present invention. Figure 12 The LSS in the process is executed in a multi-phase handshake mode, in which the connected channels (e.g., available channels) exchange UniPro trigger events to establish bidirectional initial link communication.

[0098] Reference Figure 1 , Figure 2 and Figure 12In operation S1210, storage device 30 may generate and perform a line reset operation, including resetting the transmitter TX of the connected channel and sending a line reset message LINE-RESET, which includes information indicating that the transmitter TX has been reset. Host 20 may receive the line reset message LINE-RESET sent from storage device 30, perform a line reset operation including resetting the receiver RX of the connected channel, and send a line reset message LINE-RESET including information indicating that the receiver RX has been reset. The line reset operation may include resetting or clearing all physical layer attributes of interconnect portions 32 and 22 to default values. Storage device 30 and host 20 may exchange line reset information with each other (e.g., via line reset messages). Operation S1210 may be referred to as the line reset phase. After performing the line reset phase S1210, LSS may begin.

[0099] LSS can be defined by certain stages. LSS can use triggering events for each stage, and each triggering event can be sent multiple times.

[0100] In the first phase S1220 of the LSS, the LSS can discover connected channels. To this end, storage device 30 can send a first trigger event TRG_UPR0 through all transmit channels. Storage device 30 can perform an HS link operation, which may include continuously sending the first trigger event TRG_UPR0 until a channel connected to host 20 (e.g., an available receive channel) receives the first trigger event TRG_UPR0. The first trigger event TRG_UPR0 sent from storage device 30 may include the physical channel number of the transmit channel of storage device 30, through which the corresponding trigger is sent. Furthermore, the first trigger event TRG_UPR0 sent from storage device 30 may include the HS link start primitive HS_LinkStartUp.ind to attempt and initiate host 20's participation in the LSS.

[0101] Furthermore, in the first phase S1220, host 20 can send the first trigger event TRG_UPR0 through all transmit channels. Host 20 can continuously send the first trigger event TRG_UPR0 until a channel connected to storage device 30 (e.g., an available receive channel) receives the first trigger event TRG_UPR0. The first trigger event TRG_UPR0 sent from host 20 may include the physical channel number of the transmit channel of host 20, through which the corresponding trigger is sent.

[0102] In the second phase S1230 of the LSS, the LSS can be realigned with the data channels. For this purpose, storage device 30 can send the second trigger event TRG_UPR1 through all transmit channels. Storage device 30 can continuously send the second trigger event TRG_UPR1 until a channel connected to host 20 (e.g., an available receive channel) receives the second trigger event TRG_UPR1. The second trigger event TRG_UPR1 sent from storage device 30 may include information about the transmit channels connected to storage device 30.

[0103] Furthermore, in the second phase S1230, host 20 can send the second trigger event TRG_UPR1 through all transmission channels. Host 20 can continuously send the second trigger event TRG_UPR1 until a channel connected to storage device 30 (e.g., an available receive channel) receives the second trigger event TRG_UPR1. The second trigger event TRG_UPR1 sent from host 20 may include information about the transmission channels connected to host 20.

[0104] In the third stage S1240 of the LSS, the LSS can reflect the number of connection channels, such as available channels, between the storage device 30 and the host 20 based on the physical layer attributes of the interconnect portions 32 and 22. For this purpose, the storage device 30 can send a third trigger event TRG_UPR2 through a connected transmit channel (e.g., an available transmit channel). The storage device 30 can continuously send the third trigger event TRG_UPR2 until a receive channel (e.g., an available receive channel) connected to the host 20 receives the third trigger event TRG_UPR2. The third trigger event TRG_UPR2 sent from the storage device 30 may include a logical channel number associated with the transmit channel connected to the storage device 30.

[0105] Furthermore, in the third phase S1240, host 20 can send the third trigger event TRG_UPR2 via a connected transmit channel (e.g., an available transmit channel). Host 20 can continuously send the third trigger event TRG_UPR2 until a receive channel (e.g., an available receive channel) connected to storage device 30 receives the third trigger event TRG_UPR2. The third trigger event TRG_UPR2 sent from host 20 may include a logical channel number associated with the transmit channel connected to host 20.

[0106] When executing the third stage S1240 of LSS, storage device 30 and host 20 may have matching logical channel numbers associated with available channels. At this point, storage device 30 and host 20 may terminate LSS and perform a function exchange.

[0107] In operation S1250, storage device 30 and host 20 can exchange information about the functional CAP of the other device and know the exchanged information to convey the architectural requirements of interconnect parts 32 and 22. The architectural requirements of interconnect parts 32 and 22 may include, for example, bandwidth, timers, variable speed drives, termination / cancellation (e.g., resumption), and scrambling. Operation S1250 can be referred to as the functional exchange phase. When performing the functional exchange phase S1250, information about the functional CAP of the other device is collected through interconnect parts 32 and 22, and the physical layer attributes of interconnect parts 32 and 22 can be set based on the collected functional information.

[0108] In operation S1260, storage device 30 and host 20 can exchange control frames (AFCs) to provide a reliable data link. To this end, storage device 30 and host 20 can send initial data frames to each other, and a device that has received a data frame can send a control frame (AFC) back to the device that sent the data frame. The control frame (AFC) can be configured differently from the data frame and can be used to allow the sending device to know that it has been explicitly received, and can also be used to notify the sending device of available data link layer buffer space.

[0109] Figure 13 This is a block diagram of a system 1000 that applies a storage device according to at least one exemplary embodiment of the present invention. Figure 13 The system 1000 can essentially be a mobile system, such as a portable communication terminal (mobile phone), smartphone, tablet PC, wearable device, medical device, or Internet of Things (IoT) device. However, Figure 13 System 1000 is not necessarily limited to a mobile system, and can be a PC, laptop computer, server, media player, or automotive device such as a navigation device. In the following, subscripts attached to the reference numerals (e.g., a in 1200a and a in 1300a) are used to distinguish multiple circuits configured to perform the same facilities.

[0110] Reference Figure 13 The system 1000 may include a main processor 1100, memories 1200a and 1200b and storage devices 1300a and 1300b, and may further include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and a connection interface 1480.

[0111] The main processor 1100 can control the general operation of the system 1000, and more specifically, control the operation of other components included in the system 1000. The main processor 1100 can be implemented by a general-purpose processor, a dedicated processor, an application processor (AP), etc.

[0112] The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to one embodiment, the main processor 1100 may further include an accelerator block 1130, which is dedicated circuitry configured to perform HS data computations (such as artificial intelligence (AI) data computations). The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc., and may be implemented by a separate chip physically independent of other components in the main processor 1100.

[0113] Memory 1200a and 1200b can be used as the main memory device of system 1000 and may include volatile memory, such as static random access memory (SRAM) and / or DRAM, or may include NVM, such as flash memory, PRAM and / or RRAM. Memory 1200a and 1200b may be implemented in the same package as main processor 1100.

[0114] Storage devices 1300a and 1300b can be used as non-volatile storage devices for storing data, regardless of whether they are powered, and can have a relatively larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and NVM storage devices 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b, respectively. NVM storage devices 1320a and 1320b may include two-dimensional (2D) or three-dimensional (3D) structures or another type of NVM, such as V-NAND flash memory of PRAM and / or RRAM.

[0115] Storage devices 1300a and 1300b can be included in system 1000, which is physically separate from main processor 1100, or can be implemented in the same package as main processor 1100. Furthermore, storage devices 1300a and 1300b can have a shape such as a memory card to be detachably coupled to other components in system 1000 via an interface such as connection interface 1480, which will be described below. Storage devices 1300a and 1300b can be devices to which standard protocols such as the UFS protocol are applied, but are not necessarily limited to this.

[0116] Image capture device 1410 can capture still images or moving images, and may include a camera, a camcorder, and / or a webcam, etc.

[0117] User input device 1420 can receive various types of data from the user of system 1000, and may include touchpad, keypad, keyboard, mouse, microphone, etc.

[0118] Sensor 1430 can sense various types of physical quantities that can be obtained from the outside and convert the sensed physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, lighting sensors, position sensors, acceleration sensors, biosensors, gyroscopes, etc.

[0119] Communication device 1440 can perform signal transmission and reception between system 1000 and other devices outside system 1000 according to various communication protocols. Communication device 1440 can be implemented using antennas, transceivers, modems, etc.

[0120] The display 1450 and the speaker 1460 can be used as output devices configured to output visual and auditory information to the user of the system 1000, respectively.

[0121] The power supply device 1470 can appropriately convert power supplied from a battery (not shown) in the system 1000 and / or an external power source, and supply the converted power to each component in the system 1000.

[0122] The connection interface 1480 provides connectivity between the system 1000 and external devices connected to the system 1000, enabling the system to send and receive data. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, PCI Express (PCIe) interface, NVM Express (NVMe) interface, IEEE 1394 interface, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0123] Figure 14 This is a block diagram of a UFS system 2000 according to at least one exemplary embodiment of the present invention. The UFS system 2000 is a system conforming to the UFS standard published by the Joint Electronic Equipment Committee (JEDEC) and may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 13 The above description of System 1000 can also be found in the following references. Figure 14 The descriptions applied within the scope of non-conflict are applicable. Figure 14 UFS system 2000.

[0124] Reference Figure 14 UFS host 2100 and UFS device 2200 can connect to each other via UFS interface 2300. When Figure 13 When the main processor 1100 is an access point (AP), the UFS host 2100 can be implemented as part of the AP. The UFS host controller 2110 and host memory 2140 can respectively correspond to... Figure 13 The main processor 1100 includes a controller 1120 and memories 1200a and 1200b. The UFS device 2200 can correspond to... Figure 13 Storage devices 1300a and 1300b, and the UFS device controller 2210 and NVM storage 2220 can respectively correspond to Figure 13 Storage controllers 1310a and 1310b and NVM storage devices 1320a and 1320b.

[0125] UFS host 2100 may include UFS host controller 2110, application 2120, UFS drive 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, NVM storage 2220, storage interface 2230, device memory 2240, UIC layer 2250, and regulator 2260. NVM storage 2220 may include multiple storage cells 2221, and storage cells 2221 may include 2D or 3D structured V-NAND flash memory or another type of NVM (such as PRAM and / or RRAM). UFS device controller 2210 and NVM storage 2220 may be connected to each other via storage interface 2230. Storage interface 2230 may be implemented to conform to standard protocols such as toggle or Open NAND Flash Interface (ONFI) protocols.

[0126] Application 2120 can instruct programs that intend to communicate with UFS device 2200 to use the facilities of UFS device 2200. Application 2120 can send Input / Output Requests (IORs) to UFS drive 2130 for input to or output from UFS device 2200. IORs can indicate data read requests, data write requests, data discard requests, etc., but are not limited to these.

[0127] UFS drive 2130 can manage UFS host controller 2110 through the UFS-Host Controller Interface (HCI). UFS drive 2130 can translate the IOR generated by application 2120 into UFS commands defined by the UFS standard and send the translated UFS commands to UFS host controller 2110. One IOR can be translated into multiple UFS commands. UFS commands can generally be commands defined by the SCSI standard, but can also be UFS standard-specific commands.

[0128] The UFS host controller 2110 can send UFS commands translated by the UFS driver 2130 to the UIC layer 2250 in the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 in the UFS host controller 2110 can act as a command queue (CQ).

[0129] The UIC layer 2150 in the UFS host 2100 may include MIPI M-PHY 2151 and MIPI UniPro 2152, while the UIC layer 2250 in the UFS device 2200 may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0130] The UFS interface 2300 may include a line through which a reference clock signal REF_CLK is transmitted, a line through which a hardware reset signal RESET_n for the UFS device 2200 is transmitted, a pair of lines through which differential input signals to DIN_T and DIN_C are transmitted, and a pair of lines through which differential output signals to DOUT_T and DOUT_C ​​are transmitted.

[0131] The frequency value of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of four values, such as 19.2MHz, 26MHz, 38.4MHz, and 52MHz, but is not limited to these. Even during operation, for example, even when data is being sent and received between the UFS host 2100 and the UFS device 2200, the UFS host 2100 can change the frequency value of the reference clock signal REF_CLK. The UFS device 2200 can generate clock signals of various frequencies from the reference clock signal REF_CLK received from the UFS host 2100 using a phase-locked loop (PLL) or similar mechanism. Furthermore, the UFS host 2100 can set the data rate value between the UFS host 2100 and the UFS device 2200 based on the frequency value of the reference clock signal REF_CLK. That is, the data rate value can be determined based on the frequency value of the reference clock signal REF_CLK.

[0132] The UFS interface 2300 can support multiple channels, and each channel can be implemented through differential pairs. For example, the UFS interface 2300 may include one or more receive channels and one or more transmit channels. Figure 14 In this system, a receiving channel can be formed by transmitting differential input signals to a pair of lines DIN_T and DIN_C, and a transmitting channel can be formed by transmitting differential output signals to a pair of lines DOUT_T and DOUT_C. Although Figure 14 It shows one transmit channel and one receive channel, but the number of transmit channels and the number of receive channels can vary.

[0133] The receive and transmit channels can transmit data using a serial communication scheme, and full-duplex communication between the UFS host 2100 and the UFS device 2200 can be performed using a structure that separates the receive and transmit channels. That is, even while receiving data from the UFS host 2100 via the receive channel, the UFS device 2200 can also transmit data to the UFS host 2100 via the transmit channel. Furthermore, control data, such as commands from the UFS host 2100 to the UFS device 2200, and user data to be stored or retrieved from the NVM storage 2220 in the UFS device 2200, can be transmitted through the same channel. Therefore, in addition to the receive and transmit channels, it is not necessary to provide a separate channel for data transmission between the UFS host 2100 and the UFS device 2200.

[0134] The UFS device controller 2210 in the UFS device 2200 typically controls the operation of the UFS device 2200. The UFS device controller 2210 manages the NVM storage 2220 via logical units (LUs) 2211 (which are logical data storage units). The number of LUs 2211 can be eight, but is not limited to this. The UFS device controller 2210 may include a flash translation layer (FTL) and can translate logical data addresses (e.g., logical block addresses (LBAs)) sent from the UFS host 2100 into physical data addresses (e.g., physical block addresses (PBAs)) using address mapping information from the FTL. Logical blocks used to store user data in the UFS system 2000 can have a range of sizes. For example, according to at least some exemplary embodiments conceived in the present invention, the minimum size of a logical block can be set to 4KB.

[0135] When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform the operation according to the input command, and send a completion response to the UFS host 2100 when the operation is completed.

[0136] For example, when UFS host 2100 expects to store user data in UFS device 2200, UFS host 2100 can send a data write command to UFS device 2200. When it receives a ready-to-transfer response from UFS device 2200 indicating that it is ready to receive user data, UFS host 2100 can send the user data to UFS device 2200. UFS device controller 2210 can temporarily store the received user data in device memory 2240 based on FTL address mapping information, and store the user data temporarily stored in device memory 2240 in a selected location of NVM storage 2220.

[0137] As another example, when UFS host 2100 wishes to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. UFS device controller 2210, having received the data read command, can read the user data from NVM storage 2220 based on the command and temporarily store the read user data in device memory 2240. During this read process, UFS device controller 2210 can detect and correct errors in the read user data using embedded error correction code (ECC) circuitry (not shown). Afterward, UFS device controller 2210 can send the user data temporarily stored in device memory 2240 to UFS host 2100. Furthermore, UFS device controller 2210 may also include Advanced Encryption Standard (AES) circuitry (not shown), and the AES circuitry can encrypt or decrypt data using a symmetric key algorithm, which is then input to UFS device controller 2210.

[0138] UFS host 2100 can sequentially store commands to be sent to UFS device 2200 in UFS host register 2111, which can be used as a queue (CQ), and send the commands to UFS device 2200 in the order they are stored. In this case, even when UFS device 2200 is processing a previously sent command, for example, even when no notification indicating that a previously sent command has been fully processed by UFS device 2200 is received, UFS host 2100 can still send subsequent commands buffered in the CQ to UFS device 2200. Therefore, UFS device 2200 can receive subsequent commands from UFS host 2100 even while processing previously sent commands. According to at least some exemplary embodiments conceived in the present invention, the maximum number of commands (queue depth) that can be stored in the CQ can be, for example, 32. Furthermore, the CQ can be implemented as a circular queue type, wherein the start and end points of the command string stored in the CQ are indicated by a head pointer and a tail pointer, respectively.

[0139] Each of the plurality of storage cells 2221 may include a storage cell array and control circuitry configured to control the operation of the storage cell array. The storage cell array may include a 2D or 3D storage cell array. The storage cell array may include a plurality of storage cells, and each storage cell may be a single-level cell (SLC) storing one bit of information or a cell storing two or more bits of information, such as a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). A 3D storage cell array may include vertically oriented V-NAND strings such that at least one storage cell is located on top of another storage cell.

[0140] Power supply voltages such as VCC, VCCQ1, and VCCQ2 can be input to the UFS device 2200. VCC is the main power supply voltage for the UFS device 2200 and can have a value of approximately 2.4V to approximately 3.6V. VCCQ1 is a power supply voltage used to provide a low-level voltage, primarily used for the UFS device controller 2210, and can have a value of approximately 1.14V to approximately 1.26V. VCCQ2 is a power supply voltage used to provide a voltage level lower than VCC but higher than VCCQ1, primarily used for input / output interfaces such as the MIPI M-PHY2251, and can have a value of approximately 1.7V to approximately 1.95V. The power supply voltages can be supplied to each component in the UFS device 2200 via a regulator 2260. The regulator 2260 can be implemented by a set of unit regulators, each connected to the aforementioned power supply voltages.

[0141] Figures 15A to 15C This is a diagram used to describe the form factor of a UFS card. (When referring to...) Figure 14 When the described UFS device 2200 is implemented in the form of a UFS card 4000, the appearance of the UFS card 4000 can be as follows: Figure 15A and 15C As shown.

[0142] Figure 15A This is a top view of the UFS card 4000. (Refer to...) Figure 15A UFS cards 4000 typically feature a shark-shaped design. Figure 15A In this context, the UFS card 4000 can have dimensions as shown in Table 1 below.

[0143] [Table 1]

[0144] Sub-item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0145] Figure 15B This is a side view of the UFS card 4000. Figure 15B In this context, the UFS card 4000 can have dimensions as shown in Table 2 below, for example.

[0146] [Table 2]

[0147] Sub-item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0148] Figure 15C This is a top view of the UFS card 4000. (Refer to...) Figure 15C Multiple pins for electrical contact with the UFS slot can be formed on the bottom surface of the UFS card 4000, and the function of each pin will be described below. By utilizing the symmetry between the top and bottom surfaces of the UFS card 4000, refer to... Figure 15A The information about dimensions described in Table 1 (e.g., T1 to T5 and T9) can also be applied to, for example... Figure 15C The image shows a bottom view of the UFS card 4000.

[0149] Multiple pins for electrical connection with the UFS host can be formed on the bottom surface of the UFS card 4000, and according to Figure 15C The total number of pins can be 12. Each pin can have a rectangular shape, and the signal name corresponding to each pin is as follows: Figure 15C As shown. Brief information for each pin can be found in Table 3 below, and also in the references above. Figure 14 The description is as follows.

[0150] [Table 3]

[0151]

[0152] Figure 16 This is a block diagram of an NVM storage 2220a according to at least one exemplary embodiment of the present invention.

[0153] Reference Figure 16 The NVM storage 2220a may include a storage device 2224 and a storage controller 2222. The NVM storage 2220a may support multiple channels, for example, a first channel CH1 to an m-th channel CHm, and the storage device 2224 and the storage controller 2222 may be interconnected via the first channel CH1 to the m-th channel CHm. For example, the NVM storage 2220a may be implemented using a storage device such as an SSD.

[0154] Memory device 2224 may include a plurality of NVM devices NVM11 to NVMmn. Each of the plurality of NVM devices NVM11 to NVMmn may be connected to one of the first channels CH1 to the m-th channel CHm via a corresponding path. For example, NVM devices NVM11 to NVM1n may be connected to the first channel CH1 via paths W11 to W1n, and NVM devices NVM21 to NVM2n may be connected to the second channel CH2 via paths W21 to W2n, respectively. In an exemplary embodiment, each of the plurality of NVM devices NVM11 to NVMmn may be implemented in an operable random access memory cell according to individual commands from memory controller 2222. For example, each of the plurality of NVM devices NVM11 to NVMmn may be implemented by a chip or a die, but at least some exemplary embodiments of the present invention are not limited thereto.

[0155] The memory controller 2222 can send signals to and receive signals from the memory device 2224 via the first channel CH1 to the m-th channel CHm. For example, the memory controller 2222 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 2224 via the first channel CH1 to the m-th channel CHm to M22, or receive data DATAa to DATAm from the memory device 2224.

[0156] The memory controller 2222 can select one of the NVM devices connected to the corresponding channel via the appropriate channel, and send signals to and receive signals from the selected NVM device. For example, the memory controller 2222 can select NVM device NVM11 from NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 2222 can send command CMDa, address ADDRa, and data DATAa to the selected NVM device NVM11 via the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0157] The memory controller 2222 can send signals to and receive signals from the memory device 2224 in parallel via different channels. For example, the memory controller 2222 can send the command CMDb to the memory device 2224 via the second channel CH2, while simultaneously sending the command CMDa to the memory device 2224 via the first channel CH1. For example, the memory controller 2222 can receive data DATAa from the memory device 2224 via the first channel CH1 while simultaneously receiving data DATAb from the memory device 2224 via the second channel CH2.

[0158] The memory controller 2222 can control the general operation of the memory device 2224. The memory controller 2222 can control each of the plurality of NVM devices NVM11 to NVMmn connected to the first channel CH1 to the m-th channel CHm by sending signals via the first channel CH1 to the m-th channel CHm. For example, the memory controller 2222 can control one of the NVM devices NVM11 to NVM1n by sending the command CMDa and the address ADDRa via the first channel CH1.

[0159] Each of the multiple NVM devices NVM11 to NVMmn can be operated under the control of the memory controller 2222. For example, NVM device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided through the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided through the second channel CH2, and send the read data DATAb to the memory controller 2222.

[0160] although Figure 16 The memory device 2224 communicates with the memory controller 2222 through m channels and includes n NVM devices corresponding to each channel, but the number of channels and the number of NVM devices connected to a channel can vary.

[0161] Figure 17 This is a block diagram of an NVM storage 2220b according to at least one exemplary embodiment of the present invention. (Refer to...) Figure 17 The NVM storage 2220b may include a storage device 2226 and a storage controller 2222. The storage device 2226 may correspond to one of a plurality of NVM devices NVM11 to NVMmn, which are based on... Figure 16 The memory controller 2222 communicates with one of the first channels CH1 to the m-th channel CHm. The memory controller 2222 can correspond to... Figure 16 The memory controller 2222 is shown.

[0162] The memory device 2226 may include first pins P11 to eighth pins P18, memory interface circuitry 2310, control logic circuitry 2320, and memory cell array 2330.

[0163] The memory interface circuit 2310 can receive the chip enable signal nCE from the memory controller 2222 via the first pin P11. In response to the chip enable signal nCE, the memory interface circuit 2310 can send signals to and receive signals from the memory controller 2222 via the second pin P12 to the eighth pin P18. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 2310 can send signals to and receive signals from the memory controller 2222 via the second pin P12 to the eighth pin P12 to P18.

[0164] The memory interface circuit 2310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 2222 via pins P12 to P14, respectively. The memory interface circuit 2310 can receive or transmit the data signal DQ from the memory controller 2222 via pin P17. The data signal DQ can be used to transmit commands (CMD), addresses (ADDR), and data (DATA). For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signal lines.

[0165] The memory interface circuit 2310 can obtain the command CMD from the data signal DQ received during the enable cycle (e.g., high-level state) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. The memory interface circuit 2310 can also obtain the address ADDR from the data signal DQ received during the enable cycle (e.g., high-level state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0166] In one exemplary embodiment, the write enable signal nWE can remain static (e.g., high or low) and then toggle between high and low. For example, the write enable signal nWE can toggle during the cycle of sending command CMD or address ADDR. Accordingly, the memory interface circuit 2310 can obtain command CMD or address ADDR based on the switching timing of the write enable signal nWE.

[0167] The memory interface circuit 2310 can receive the read enable signal nRE from the memory controller 2222 via its fifth pin P15. The memory interface circuit 2310 can receive or send the data strobe signal DQS to the memory controller 2222 via its sixth pin P16.

[0168] In the data output operation of memory device 2226, memory interface circuit 2310 can receive a read enable signal nRE, which is toggled via pin 5 P15 before outputting data DATA. Memory interface circuit 2310 can generate a data strobe signal DQS, which is toggled based on the switching of the read enable signal nRE. For example, memory interface circuit 2310 can generate a data strobe signal DQS with a predetermined delay (e.g., t) from the start time of the switching of the read enable signal nRE. DQSRE After that, the switching begins. The memory interface circuit 2310 can transmit a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Accordingly, the data DATA can be aligned with the switching timing of the data strobe signal DQS and sent to the memory controller 2222.

[0169] In the data input operation of memory device 2226, when a data signal DQ including data DATA is received from memory controller 2222, memory interface circuit 2310 can receive a data strobe signal DQS, which switches together with the data DATA from memory controller 2222. Memory interface circuit 2310 can obtain data DATA from data signal DQ based on the switching timing of data strobe signal DQS. For example, memory interface circuit 2310 can obtain data DATA by sampling data signal DQ at the leading and trailing edges of data strobe signal DQS.

[0170] The memory interface circuit 2310 can send a ready / busy output signal nR / B to the memory controller 2222 via pin 8 P18. The memory interface circuit 2310 can also send status information of the memory device 2226 to the memory controller 2222 via the ready / busy output signal nR / B. When the memory device 2226 is in a busy state (e.g., while performing internal operations of the memory device 2226), the memory interface circuit 2310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 2222. When the memory device 2226 is in a ready state (e.g., when internal operations of the memory device 2226 are not performed or have been completed), the memory interface circuit 2310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 2222. For example, when memory device 2226 reads data DATA from memory cell array 2330 in response to a page read command, memory interface circuit 2310 can send a ready / busy output signal nR / B (e.g., low level) indicating a busy state to memory controller 2222. Similarly, when memory device 2226 programs data DATA into memory cell array 2330 in response to a programming command, memory interface circuit 2310 can send a ready / busy output signal nR / B indicating a busy state to memory controller 2222.

[0171] Control logic circuitry 2320 typically controls various operations of memory device 2226. Control logic circuitry 2320 can receive commands / addresses (CMD / ADDR) from memory interface circuitry 2310. Control logic circuitry 2320 can generate control signals for controlling other components in memory device 2226 in response to the received commands / addresses (CMD / ADDR). For example, control logic circuitry 2320 can generate various control signals for programming data DATA to or reading data DATA from memory cell array 2330.

[0172] The memory cell array 2330 can store data DATA obtained from the memory interface circuit 2310 under the control of the control logic circuit 2320. The memory cell array 2330 can also output the stored data DATA to the memory interface circuit 2310 under the control of the control logic circuit 2320.

[0173] The storage cell array 2330 may include a plurality of storage cells. For example, the plurality of storage cells may be flash memory cells. However, at least some exemplary embodiments of the present invention are not limited thereto, and the plurality of storage cells may be RRAM cells, ferroelectric random access memory (FRAM) cells, PRAM cells, thyristor random access memory (TRAM) cells, or MRAM cells. At least some exemplary embodiments of the present invention will be described below based on embodiments in which the plurality of storage cells are NAND flash memory cells.

[0174] The memory controller 2222 may include first pins P21 to eighth pins P28 and controller interface circuitry 2410. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 in the memory device 2226.

[0175] The controller interface circuit 2410 can send a chip enable signal nCE to the memory device 2226 via the first pin P21. The controller interface circuit 2410 can send signals to and receive signals from the memory device 2226 selected based on the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0176] The controller interface circuit 2410 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 2226 via pins P22 to P24, respectively. The controller interface circuit 2410 can send or receive the data signal DQ to the memory device 2226 via pin P27.

[0177] The controller interface circuit 2410 can send the data signal DQ, including the command CMD or address ADDR, together with the switched write enable signal nWE to the memory device 2226. The controller interface circuit 2410 can send the data signal DQ, including the command CMD, to the memory device 2226 based on the transmission of the command latch enable signal CLE, which has an enabled state, and can send the data signal DQ, including the address ADDR, to the memory device 2226 based on the transmission of the address latch enable signal ALE, which has an enabled state.

[0178] The controller interface circuit 2410 can send the read enable signal nRE to the memory device 2226 via pin 5 P25. The controller interface circuit 2410 can receive or send the data strobe signal DQS to the memory device 2226 via pin 6 P26.

[0179] In the data output operation of memory device 2226, controller interface circuit 2410 can generate a switched read enable signal nRE and send the read enable signal nRE to memory device 2226. For example, controller interface circuit 2410 can generate a read enable signal nRE that changes from a static state (e.g., high or low) to a switched state before outputting data DATA. Accordingly, memory device 2226 can generate a switched data strobe signal DQS based on the read enable signal nRE. Controller interface circuit 2410 can receive a data signal DQ including data DATA and the switched data strobe signal DQS from memory device 2226. Controller interface circuit 2410 can obtain data DATA from data signal DQ based on the switching timing of data strobe signal DQS.

[0180] In the data input operation of memory device 2226, controller interface circuit 2410 can generate a switching data strobe signal DQS. For example, controller interface circuit 2410 can generate a data strobe signal DQS that changes from a static state (e.g., high or low) to a switching state before transmitting data DATA. Controller interface circuit 2410 can send a data signal DQ including data DATA to memory device 2226 based on the switching timing of the data strobe signal DQS.

[0181] The controller interface circuit 2410 can receive the ready / busy output signal nR / B from the memory device 2226 via pin 8 P28. The controller interface circuit 2410 can determine the status information of the memory device 2226 based on the ready / busy output signal nR / B.

[0182] Figure 18 yes Figure 17 A block diagram of memory device 2226 is shown. (Refer to...) Figure 18 The memory device 2226 may include control logic circuitry 2320, a memory cell array 2330, a page buffer unit 2340, a voltage generator 2350, and a row decoder 3394. Although in Figure 18 As not shown in the diagram, memory device 2226 may further include Figure 17 The memory interface circuit 2310 shown is illustrated, and furthermore, the memory device 2226 may include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0183] Control logic circuit 2320 typically controls various operations of memory device 2226. Control logic circuit 2320 can output various control signals in response to commands CMD and / or addresses ADDR from memory interface circuit 2310. For example, control logic circuit 2320 can output voltage control signal CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0184] The storage cell array 2330 may include multiple storage blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple storage blocks BLK1 to BLKz may include multiple storage cells. The storage cell array 2330 can be connected to the page buffer unit 2340 via the bit line BL, and can be connected to the line decoder 3394 via the word line WL, the serial select line SSL, and the ground select line GSL.

[0185] In one exemplary embodiment, the memory cell array 2330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publications Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application No. 2011 / 0233648 are referenced herein, and the entire contents of these patent publications and patent applications are incorporated herein by reference. In one exemplary embodiment, the memory cell array 2330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0186] Page buffer unit 2340 may include multiple page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL, respectively. Page buffer unit 2340 may select at least one bit line BL from the multiple bit lines BL in response to column address Y-ADDR. Page buffer unit 2340 may operate as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer unit 2340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line BL. In a read operation, page buffer unit 2340 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line BL.

[0187] The voltage generator 2350 can generate various types of voltages for performing programming, reading, and discarding operations based on the voltage control signal CTRL_vol. For example, the voltage generator 2350 can generate programming voltages, reading voltages, programming verification voltages, discarding voltages, etc., as word line voltages VWL.

[0188] The row decoder 3394 can select one of a plurality of word lines WL and one of a plurality of string select lines SSL in response to the row address X-ADDR. For example, in a programming operation, the row decoder 3394 can apply a programming voltage and a programming verification voltage to the selected word line WL, and in a read operation, the row decoder 3394 can apply a read voltage to the selected word line WL.

[0189] Figure 19 This is a diagram illustrating a 3D V-NAND structure applicable to UFS devices, based on at least one exemplary embodiment of the present invention. When the storage module in a UFS device is implemented using 3D V-NAND type flash memory, each of the plurality of storage blocks included in the storage module can be represented by an equivalent circuit, such as... Figure 19 As shown.

[0190] Figure 19 The memory block BLKi shown indicates a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0191] Reference Figure 19 The memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Although Figure 19 Each of the plurality of memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, ..., MC8, but at least some exemplary embodiments of the present invention are not necessarily limited thereto.

[0192] The serial select transistor SST can be connected to the corresponding serial select line SSL1, SSL2, or SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to their respective gate lines GTL1, GTL2, ..., GTL8. The gating lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some gate lines GTL1, GTL2, ..., GTL8 can correspond to pseudo-word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, or BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0193] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1, GSL2, and GSL3, as well as serial select lines SSL1, SSL2, and SSL3, can be separated individually. Although Figure 19 The memory block BLKi is shown connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2 and BL3. At least some exemplary embodiments of the present invention are not necessarily limited thereto.

[0194] Figure 20 This is a cross-sectional view of a BVNAND structure applicable to a UFS device according to at least one exemplary embodiment of the present invention.

[0195] Reference Figure 20 The memory device 2226 may have a chip-to-chip (C2C) structure. A C2C structure can refer to fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer, separating them from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, the bonding metal may be copper (Cu) using Cu-to-Cu bonding. However, the exemplary embodiment is not limited to this. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0196] Each of the peripheral circuit region PERI and cell region CELL of memory device 2226 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0197] The Peripheral Circuit Region (PERI) may include a first substrate 3210, an interlayer insulating layer 3215, a plurality of circuit elements 3220a, 3220b, and 3220c formed on the first substrate 3210, first metal layers 3230a, 3230b, and 3230c respectively connected to the plurality of circuit elements 3220a, 3220b, and 3220c, and second metal layers 3240a, 3240b, and 3240c formed on the first metal layers 3230a, 3230b, and 3230c. In an exemplary embodiment, the first metal layers 3230a, 3230b, and 3230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 3240a, 3240b, and 3240c may be formed of copper, which has a relatively low resistivity.

[0198] exist Figure 20 In one exemplary embodiment shown, although only the first metal layers 3230a, 3230b, and 3230c and the second metal layers 3240a, 3240b, and 3240c are shown and described, this exemplary embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 3240a, 3240b, and 3240c. At least a portion of the one or more additional metal layers formed on the second metal layers 3240a, 3240b, and 3240c may be formed of aluminum or the like, having a lower resistivity than copper, which forms the second metal layers 3240a, 3240b, and 3240c.

[0199] An interlayer insulating layer 3215 may be disposed on a first substrate 3210 and cover multiple circuit elements 3220a, 3220b, and 3220c, first metal layers 3230a, 3230b, and 3230c, and second metal layers 3240a, 3240b, and 3240c. The interlayer insulating layer 3215 may include insulating materials such as silicon oxide and silicon nitride.

[0200] Lower bonding metals 3271b and 3272b can be formed on the second metal layer 3240b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 3271b and 3272b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 3371b and 3372b in the cell area (CELL). The lower bonding metals 3271b and 3272b, as well as the upper bonding metals 3371b and 3372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 3371b and 3372b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 3271b and 3272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0201] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 3310 and a common source line 3320. On the second substrate 3310, multiple word lines 3331 to 3338 (e.g., 3330) may be stacked in a direction perpendicular to the upper surface of the second substrate 3310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 3330, respectively, and the multiple word lines 3330 may be arranged between the at least one string select line and the at least one ground select line.

[0202] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 3310 (Z-axis direction) and pass through multiple word lines 3330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 3350c and the second metal layer 3360c. For example, the first metal layer 3350c may be a bit line contact, and the second metal layer 3360c may be a bit line. In an exemplary embodiment, the bit line 3360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 3310.

[0203] exist Figure 20 In the exemplary embodiment shown, the area where the channel structure CH, bit line 3360c, etc., are arranged can be defined as a bit line bonding area (BLBA). In the bit line bonding area (BLBA), bit line 3360c can be electrically connected to circuit element 3220c, which provides a page buffer 3393 in the peripheral circuit area (PERI). Bit line 3360c can be connected to upper bonding metals 3371c and 3372c in the cell area (CELL), and upper bonding metals 3371c and 3372c can be connected to lower bonding metals 3271c and 3272c, which are connected to the circuit element 3220c connected to the page buffer 3393.

[0204] In the word line bonding area (WLBA), multiple word lines 3330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 3310 and perpendicular to the first direction, and can be connected to multiple cell contact plugs 3341 to 3347 (e.g., 3340). The multiple word lines 3330 and the multiple cell contact plugs 3340 can be connected to each other in pads formed by at least a portion of the multiple word lines 3330 extending at different lengths in the second direction. A first metal layer 3350b and a second metal layer 3360b can be sequentially connected to the upper portion of the multiple cell contact plugs 3340 connected to the multiple word lines 3330. The multiple cell contact plugs 3340 can be connected to the peripheral circuit region PERI via upper bonding metals 3371b and 3372b of the cell region CELL in the word line bonding area (WLBA) and lower bonding metals 3271b and 3272b of the peripheral circuit region PERI.

[0205] Multiple unit contact plugs 3340 can be electrically connected to circuit elements 3220b forming the line decoder 3394 in the peripheral circuit region PERI. In one exemplary embodiment, the operating voltage of the circuit elements 3220b of the line decoder 3394 may be different from the operating voltage of the circuit elements 3220c forming the page buffer 3393. For example, the operating voltage of the circuit elements 3220c forming the page buffer 3393 may be greater than the operating voltage of the circuit elements 3220b forming the line decoder 3394.

[0206] A common source contact plug 3380 can be disposed in the external pad bonding region PA. The common source contact plug 3380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 3320. A first metal layer 3350a and a second metal layer 3360a can be sequentially stacked on top of the common source contact plug 3380. For example, the region in which the common source contact plug 3380, the first metal layer 3350a, and the second metal layer 3360a are disposed can be defined as the external pad bonding region PA.

[0207] Input / output pads 33205 and 3305 can be set in the external pad bonding area PA. (See reference...) Figure 20A lower insulating film 3201 covering the lower surface of the first substrate 3210 can be formed below the first substrate 3210, and a first input / output pad 3205 can be formed on the lower insulating film 3201. The first input / output pad 3205 can be connected to at least one of a plurality of circuit elements 3220a, 3220b, and 3220c disposed in the peripheral circuit region PERI via a first input / output contact plug 3203, and can be separated from the first substrate 3210 by the lower insulating film 3201. In addition, a side insulating film can be provided between the first input / output contact plug 3203 and the first substrate 3210 to electrically isolate the first input / output contact plug 3203 and the first substrate 3210.

[0208] Reference Figure 20 An upper insulating film 3301 covering the upper surface of the second substrate 3310 can be formed on the second substrate 3310, and a second input / output pad 3305 can be disposed on the upper insulating film 3301. The second input / output pad 3305 can be connected to at least one of a plurality of circuit elements 3220a, 3220b, and 3220c disposed in the peripheral circuit region PERI via a second input / output contact plug 3303. In an exemplary embodiment, the second input / output pad 3305 is electrically connected to the circuit element 3220a.

[0209] According to an embodiment, the second substrate 3310 and the common source line 3320 may not be located in the area where the second input / output contact plug 3303 is arranged. Furthermore, the second input / output pad 3305 may not overlap with the word line 3330 in the third direction (Z-axis direction). (See also...) Figure 20 The second input / output contact plug 3303 can be separated from the second substrate 3310 in a direction parallel to the upper surface of the second substrate 3310, and can pass through the interlayer insulating layer 3315 of the cell region CELL to be connected to the second input / output pad 3305.

[0210] According to embodiments, the first input / output pad 3205 and the second input / output pad 3305 can be selectively formed. For example, the memory device 2226 may include only the first input / output pad 3205 disposed on the first substrate 3210 or the second input / output pad 3305 disposed on the second substrate 3310. Alternatively, the memory device 2226 may include both the first input / output pad 3205 and the second input / output pad 3305.

[0211] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern set on the top metal layer can be set as a pseudo pattern, or the top metal layer can be omitted.

[0212] In the external pad bonding region PA, the memory device 2226 may include a lower metal pattern 3273a corresponding to the upper metal pattern 3372a formed in the uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 3372a of the cell region CELL, thereby connecting to each other in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 3273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to the contacts. Similarly, in the external pad bonding region PA, an upper metal pattern 3372a corresponding to the lower metal pattern 3273a formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern 3273a of the peripheral circuit region PERI, may be formed in the uppermost metal layer of the cell region CELL.

[0213] The lower bonding metals 3271b and 3272b can be formed on the second metal layer 3240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 3271b and 3272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 3371b and 3372b of the cell region CELL via Cu-to-Cu bonding.

[0214] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 3392, corresponding to the lower metal pattern 3252 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 3252 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. No contact may be formed above the upper metal pattern 3392 formed in the uppermost metal layer of the cell region CELL.

[0215] In one exemplary embodiment, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern formed in the uppermost metal layer of either the cell region (CELL) or the peripheral circuit region (PERI) may be formed in the uppermost metal layer of the other. No contacts may be formed above the reinforcing metal pattern.

[0216] Exemplary embodiments of the inventive concept have now been described, and it will be apparent that they can be varied in many ways. Such variations should not be considered as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and all modifications that are obvious to those skilled in the art should be included within the scope of the appended claims.

Claims

1. A link boot method for a storage device connected to a host via multiple channels, the method comprising: Perform initialization operations on the storage device; Data communication is established through the connected sending channel and the connected receiving channel among the multiple channels; Send high-speed link messages to the host via the transmission channel of the storage device connection; as well as Based on the high-speed link message sent by the storage device, the link initiation operation is performed in high-speed mode through the sending channel of the storage device's connection and the receiving channel of the host's connection. Specifically, sending a high-speed link message to the host through the transmission channel of the storage device connection includes: changing the activation period of the line in the transmission channel of the storage device connection from zero differential line voltage DIF-Z to an activation period with negative differential line voltage DIF-N. Specifically, when the length of the activation period is less than the second time, the sending channel of the storage device connection and the receiving channel of the host connection enter high-speed mode; and when the length of the activation period is the second time or longer, the sending channel of the storage device connection and the receiving channel of the host connection enter low-speed mode.

2. The method according to claim 1, further comprising: Receive low-speed link messages from the host via the receive channel of the storage device connection; as well as Based on low-speed link messages, the link initiation operation is performed in low-speed mode through the sending channel of the host connection and the receiving channel of the storage device connection.

3. The method according to claim 2, wherein, Receiving low-speed link messages from the host via the receive channel of the storage device connection includes receiving low-speed link initiation primitives via the receive channel of the storage device connection.

4. The method according to claim 3, wherein, Receive the low-speed link startup primitive in the first trigger event of the link startup sequence, and The first trigger event of the link startup sequence is executed to send the physical channel number of the host's connection's transmit channel to the storage device's connection receive channel.

5. The method according to claim 1, wherein, The second time was set to 0.9ms.

6. The method according to claim 1, wherein, The second time was set to 1.6ms.

7. The method according to claim 1, wherein, Performing initialization operations in a storage device includes: when booting the storage device, reading initialization information stored in non-volatile memory embedded in the storage device, and setting the read initialization information in a configuration register.

8. The method according to claim 7, wherein, Initialization information includes at least one of the following: protection information regarding whether to prohibit the storage or erasure of data in non-volatile memory, fine-tuning data for fine-tuning the operating voltage level in operating mode, column repair information for repairing faulty bit lines, or information regarding bad blocks including bad memory cells.

9. A link boot method for a host connected to a storage device via at least one channel, the method comprising: Initialization is performed in high-speed mode on the host machine; Data communication is established through the connected sending channel and the connected receiving channel in at least one of the channels; After initialization, determine whether to receive high-speed link messages from the storage device through the host's connection receive channel; As a result, the receiving channel of the connection through which high-speed link messages are received from the storage device is identified; as well as In response to the identification of the receive channel of the connection through which high-speed link messages are received, a link initiation operation is performed in high-speed mode via the send channel of the storage device connection and the receive channel of the host connection.

10. The method according to claim 9, wherein, Determining whether to receive high-speed link messages from the storage device via the host's connection's receive channel includes: The line in the transmit channel of the storage device connection is converted from zero differential line voltage DIF-Z to negative differential line voltage DIF-N, and then converted to a line reset cycle with positive differential line voltage DIF-P. The length of the line reset cycle is set to the first time or longer.

11. The method according to claim 10, wherein, The first time was set to 3.1ms.

12. The method according to claim 9, wherein, Determining whether to receive high-speed link messages from the storage device via the host's connection receive channel includes: switching the line in the storage device's connection transmit channel from a zero differential line voltage DIF-Z to an activation period with a negative differential line voltage DIF-N. The length of the activation period is set to be shorter than the second time.

13. The method according to claim 12, wherein, The second time was set to 0.9ms.

14. The method according to claim 12, wherein, The second time was set to 1.6ms.

15. The method according to claim 9, wherein, Determining whether to receive high-speed link messages from the storage device via the host's connection's receive channel includes: Receive high-speed link startup primitives through the receiving channel of the host connection.

16. The method according to claim 15, wherein, Receive the high-speed link startup primitive in the first trigger event of the link startup sequence, and The first trigger event of the link initiation sequence is executed so that the physical channel number of the transmission channel of the storage device connection is received by the reception channel of the host connection.

17. The method according to claim 9, wherein, The receiving channel for identifying the connection that receives high-speed link messages from the storage device includes: the host receiving the high-speed link initiation primitive within a third time period from the release of the reset signal.

Images