Super junction power device and method of manufacturing the same

Abstract

This invention provides a superjunction power device and its fabrication method. In fabricating the superjunction power device, after forming a first conductivity type epitaxial layer, a superjunction mask can be added; before or after forming a second conductivity type well region, a well region mask can be directly applied; and before or after forming a contact structure, a contact mask can be directly applied. This allows for the injection of second conductivity type impurities into the first conductivity type epitaxial layer, sequentially forming second conductivity type floating islands and second conductivity type pillars. This fabrication process eliminates the need for multiple epitaxial processes and deep trench etching, resulting in a simple, low-cost fabrication process with high yield and reliability. The superjunction power device of this invention simultaneously possesses second conductivity type floating islands and second conductivity type pillars. In the off-circuit state, it can improve the breakdown voltage of the power device and reduce Miller capacitance and input capacitance; and in the on-circuit state, it can reduce the on-resistance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices and relates to a superjunction power device and its fabrication method. Background Technology

[0002] In the field of power devices, VDMOSFETs (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistors) are widely used due to their advantages such as high operating frequency, good thermal stability, and simple driving circuits. Breakdown voltage (BV) and on-resistance (Ron) are two of the most important performance parameters in power devices. A common design requirement for these two parameters is that power devices must not only have high breakdown voltage but also low on-resistance to reduce power consumption.

[0003] The limiting relationship between breakdown voltage and on-resistance of traditional power devices has hindered further improvement in device performance. Therefore, a superjunction structure is introduced into the drift region of traditional VDMOSFET devices to form a superjunction transistor (Super Junction MOS, or SJMOS) to optimize the trade-off between breakdown voltage and on-resistance. With its advantages of low on-resistance, fast turn-on speed and low switching loss, it has attracted widespread attention in the industry.

[0004] Existing methods for forming superjunction structures typically employ deep trench etching and backfilling techniques in the epitaxial layer, or multiple epitaxial layers and implantation doping to form the superjunction structure. This leverages the charge-sharing effect to increase the base volume (BV), allowing for a significant increase in the doping concentration of the epitaxial layer while maintaining the same BV, thus achieving a lower resonant charge (Ron) at the same BV. However, when forming superjunction structures in the epitaxial layer through deep trench etching and backfilling, the BV largely depends on the trench depth and the precision of charge sharing; greater depth results in a higher BV. Deep trenches increase the aspect ratio, increasing the difficulty of the backfilling process and potentially leading to stress, defects, and uniformity issues, thereby affecting device yield and reliability. Forming superjunction structures through multiple epitaxial layers and implantation doping is more complex and costly.

[0005] Therefore, it is necessary to provide a novel superjunction power device and its fabrication method. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction power device and its fabrication method, so as to solve the problems of stress, defects and uniformity, as well as the problems of complex fabrication process and high cost in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a superjunction power device, comprising the following steps:

[0008] Form an epitaxial layer of the first conductivity type;

[0009] A trench gate structure is formed in the epitaxial layer of the first conductivity type, the trench gate structure including a gate oxide layer and a gate conductive layer;

[0010] A second conductivity type well region is formed within the first conductivity type epitaxial layer between the trench gate structures using a well region mask.

[0011] A first conductivity type source region is formed within the second conductivity type well region using a source region mask;

[0012] A contact structure is formed by using a contact mask, the contact structure penetrating the first conductivity type source region and contacting the second conductivity type well region;

[0013] A second type of conductive floating island is formed, which is located within the first type of conductive epitaxial layer, and the upper and lower surfaces of the second type of conductive floating island are in contact with the first type of conductive epitaxial layer.

[0014] A second conductive type pillar is formed, which is located within the first conductive type epitaxial layer, directly above the second conductive type floating layer, and in contact with the second conductive type well region.

[0015] Optionally, after forming the first conductivity type epitaxial layer, a superjunction mask is formed on the surface of the first conductivity type epitaxial layer, and a second conductivity type impurity is injected into the first conductivity type epitaxial layer through the superjunction mask to sequentially form the second conductivity type floating island and the second conductivity type pillar.

[0016] Optionally, before or after forming the second conductivity type well region, a second conductivity type impurity is implanted into the first conductivity type epitaxial layer through the well region mask to sequentially form the second conductivity type floating island and the second conductivity type pillar.

[0017] Optionally, before or after forming the contact structure, a second conductivity type impurity is implanted into the first conductivity type epitaxial layer through the contact mask to sequentially form a second conductivity type floating island and a second conductivity type pillar.

[0018] Optionally, the thickness of the first conductive type epitaxial layer between the formed second conductive type floating island and the formed second conductive type pillar is greater than 0.1 μm.

[0019] Optionally, the step of forming the contact structure includes:

[0020] The first conductivity type source region is etched through the contact mask to form a contact trench that penetrates the first conductivity type source region;

[0021] A second type of conductive impurity is injected into the second type of conductive well region through the contact mask to form a second type of conductive contact region;

[0022] The contact mask forms a metal contact area that fills the contact trench, and the metal contact area is in contact with the second type of conductive contact area.

[0023] Optionally, the first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

[0024] Optionally, the method further includes the step of forming a first conductivity type buffer layer on the lower surface of the first conductivity type epitaxial layer.

[0025] Optionally, the method further includes the step of forming a second conductivity type implantation layer on the lower surface of the first conductivity type epitaxial layer.

[0026] The present invention also provides a superjunction power device, the superjunction power device comprising:

[0027] First conductivity type epitaxial layer;

[0028] The second conductivity type well region is located within the first conductivity type epitaxial layer;

[0029] The first conductivity type source region is located within the second conductivity type well region;

[0030] A trench gate structure, comprising a gate oxide layer and a gate conductive layer, wherein the trench gate structure is located within a first conductivity type epitaxial layer and penetrates the first conductivity type source region and the second conductivity type well region;

[0031] The contact structure extends through the first conductivity type source region and contacts the second conductivity type well region;

[0032] The second type of conductive floating island is located within the first type of conductive epitaxial layer, and both the upper and lower surfaces of the second type of conductive floating island are in contact with the first type of conductive epitaxial layer.

[0033] The second conductive type pillar is located within the first conductive type epitaxial layer, directly above the second conductive type floating island, and in contact with the second conductive type well region.

[0034] Optionally, the second conductive type floating island has the same width as the second conductive type pillar.

[0035] Optionally, the thickness of the first conductive type epitaxial layer between the second conductive type floating island and the second conductive type pillar is greater than 0.1 μm.

[0036] Optionally, the contact structure includes a second conductivity type contact area located within the second conductivity type well region and a metal contact area that penetrates the first conductivity type source region and contacts the second conductivity type contact area.

[0037] Optionally, the first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

[0038] Optionally, the lower surface of the first conductivity type epitaxial layer may further include a first conductivity type buffer layer.

[0039] Optionally, the lower surface of the first conductivity type epitaxial layer may further include a second conductivity type implantation layer.

[0040] As described above, the superjunction power device and its fabrication method of the present invention have the following beneficial effects:

[0041] In fabricating superjunction power devices, a second conductivity type impurity can be implanted into the first conductivity type epitaxial layer by adding a superjunction mask after forming the first conductivity type epitaxial layer, directly passing through a well region mask before or after forming the second conductivity type well region, and directly passing through a contact mask before or after forming the contact structure, thereby sequentially forming a second conductivity type floating island and a second conductivity type pillar. This fabrication process does not require multiple epitaxial processes and does not require deep trench etching. Therefore, the fabrication process is simple, low-cost, and has a high yield and reliability.

[0042] In a superjunction power device that simultaneously possesses both a second-type conductive floating island and a second-type conductive pillar, in the off-circuit state, both the second-type conductive floating island and the second-type conductive pillar contribute to the charge-sharing effect of the drift region in the first-type conductive epitaxial layer, thereby increasing the breakdown voltage of the power device and reducing Miller capacitance and input capacitance. In the on-circuit state, the second-type conductive floating island and the second-type conductive pillar allow for a higher doping concentration in the drift region of the first-type conductive epitaxial layer, significantly improving current conduction and reducing the on-resistance of the VDMOSFET device. Furthermore, since the first-type conductive epitaxial layer exists between the second-type conductive floating island and the second-type conductive pillar, an additional transistor can be formed within the first-type conductive epitaxial layer, further reducing the on-resistance of the IGBT device. Attached Figure Description

[0043] Figure 1 The diagram shows the fabrication process flow of the superjunction power device in this invention.

[0044] Figure 2 The diagram shows the fabrication process flow of the superjunction power device in Example 1.

[0045] Figure 3 The diagram shown is a schematic of the superjunction power device in Example 1.

[0046] Figure 4 The diagram shown is a schematic of the structure of the superjunction VDMOSFET device in Example 1.

[0047] Figure 5 The diagram shown is a schematic diagram of the superjunction IGBT device in Example 1.

[0048] Figure 6 The diagram shows the fabrication process flow of the superjunction power device in Example 2.

[0049] Figure 7 The diagram shown is a schematic of the superjunction power device in Example 2.

[0050] Figure 8 The diagram shown is a schematic of the superjunction VDMOSFET device in Example 2.

[0051] Figure 9 The diagram shown is a schematic diagram of the superjunction IGBT device in Example 2.

[0052] Figure 10 The diagram shows the fabrication process flow of the superjunction power device in Example 3.

[0053] Figure 11 The diagram shown is a schematic of the superjunction power device in Example 3.

[0054] Figure 12The diagram shown is a schematic of the superjunction VDMOSFET device in Example 3.

[0055] Figure 13 The diagram shown is a schematic diagram of the superjunction IGBT device in Example 3.

[0056] Component designation explanation

[0057] 101, 201, 301 First conductivity type substrate

[0058] 102, 202, 302 First conductivity type epitaxial layer

[0059] 103, 203, 303 Second type of conductivity well region

[0060] 104, 204, 304 - Source regions of the first conductivity type

[0061] 105, 205, 305 contact structures

[0062] 3051 Second type of conductive contact area

[0063] 3052 Metal Contact Area

[0064] 106, 206, 306 Second type of conductive floating islands

[0065] 107, 207, 307 Second type of conductive column

[0066] 108, 208, 308 gate oxide layers

[0067] 109, 209, 309 Gate conductive layers

[0068] 110, 210, 310 interlayer dielectric layers

[0069] 111, 211, 311 source metal layers

[0070] 112, 212, 312 Drain metal layers

[0071] 113, 213, 313 Second conductivity type injection layer

[0072] 314 First conductivity type buffer layer Detailed Implementation

[0073] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0075] For information on the fabrication of superjunction power devices, please refer to [link / reference]. Figure 1 The steps for forming the second type of conductive floating island and the second type of conductive pillar are relatively flexible and can be selected according to specific needs. The following will explain them through specific embodiments.

[0076] Example 1

[0077] See Figure 2 This embodiment provides a method for fabricating a superjunction power device that simultaneously possesses a second type of conductive floating island and a second type of conductive pillar, wherein, see reference... Figures 3-5 The diagram shows a schematic representation of the structure of the superjunction power device.

[0078] In this embodiment, a superjunction mask is added after the formation of the first conductivity type epitaxial layer, and the superjunction mask is used as a mask to directly inject the second conductivity type impurity into the first conductivity type epitaxial layer, thereby sequentially forming a second conductivity type floating island and a second conductivity type pillar with the same width. This fabrication process does not require multiple epitaxial processes and does not require deep trench etching. Therefore, the fabrication process is simple, low-cost, and has a high yield and reliability.

[0079] It should be noted that in this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is not limited to this. In another embodiment, the first conductivity type can also be p-type and the second conductivity type can also be n-type. No excessive restrictions are imposed here.

[0080] See Figure 2 The specific preparation process steps include:

[0081] A substrate 101 of a first conductivity type is provided;

[0082] A first conductivity type epitaxial layer 102 is formed on the first conductivity type substrate 101;

[0083] A superjunction mask is formed on the surface of the first conductivity type epitaxial layer 102;

[0084] Using the superjunction mask, a second type of impurity is injected into the first type of conductive epitaxial layer 102 to form a second type of conductive floating island 106. The second type of conductive floating island 106 is located in the first type of conductive epitaxial layer 102, and the upper and lower surfaces of the second type of conductive floating island 106 are in contact with the first type of conductive epitaxial layer 102.

[0085] Using the superjunction mask, a second type of impurity is injected into the first type of conductive epitaxial layer 102 to form a second type of conductive pillar 107. The second type of conductive pillar 107 is located in the first type of conductive epitaxial layer 102 and is located directly above the second type of conductive floating island 106.

[0086] A trench gate structure is formed in the first conductivity type epitaxial layer 102, the trench gate structure including a gate oxide layer 108 and a gate conductive layer 109.

[0087] Using a well region mask, a second conductivity type well region 103 is formed within the first conductivity type epitaxial layer 102 between the trench gate structures. The second conductivity type well region 103 is located above and in contact with the second conductivity type pillar 107.

[0088] A first conductivity type source region 104 is formed within the second conductivity type well region 103 using a source region mask;

[0089] A contact structure 105 is formed by using a contact mask. The contact structure 105 penetrates the first conductivity type source region 104 and is in contact with the second conductivity type well region 103.

[0090] Specifically, firstly, a first conductivity type substrate 101 is provided, which may be made of doped semiconductor materials such as silicon (Si), silicon germanium (SiGe), gallium nitride (GaN), or silicon carbide (SiC).

[0091] Next, an epitaxial layer 102 of the first conductivity type is formed on the first conductivity type substrate 101 by epitaxial growth.

[0092] Next, the superjunction mask is formed on the surface of the first conductivity type epitaxial layer 102.

[0093] Specifically, a hard mask material layer can be deposited on the surface of the first conductivity type epitaxial layer 102. The deposition method may include chemical vapor deposition, and the hard mask material layer may be a silicon dioxide layer, but is not limited to this. Next, a patterned photoresist layer defining the second conductivity type floating island 106 and the second conductivity type pillar 107 can be formed on the surface of the hard mask material layer by photolithography. Then, the hard mask material layer is dry etched using the photoresist layer as an etching mask to form a superjunction mask with the pattern of the second conductivity type floating island 106 and the second conductivity type pillar 107.

[0094] Next, through the superjunction mask, a second type of impurity is implanted into the first conductivity type epitaxial layer 102 to form a second conductivity type floating island 106. The second conductivity type floating island 106 can help the power device to achieve a charge sharing effect in the drift region of the first conductivity type epitaxial layer 102 when it is in the off-circuit state, thereby improving the breakdown voltage of the power device and reducing Miller capacitance and input capacitance. In the on-circuit state, the second conductivity type floating island 106 can make the drift region of the first conductivity type epitaxial layer 102 have a higher doping concentration, so as to significantly conduct current and reduce the on-resistance of the device.

[0095] Next, through the superjunction mask, a second type of impurity is implanted into the first conductivity type epitaxial layer 102 to form a second conductivity type pillar 107. The second conductivity type pillar 107 can help the power device to achieve a charge sharing effect in the drift region of the first conductivity type epitaxial layer 102 when it is in the off-circuit state, thereby improving the breakdown voltage of the power device and reducing Miller capacitance and input capacitance. In the on-circuit state, the second conductivity type pillar 107 can make the drift region of the first conductivity type epitaxial layer 102 have a higher doping concentration, so as to significantly conduct current and reduce the on-resistance of the device.

[0096] The order in which the second conductive type floating island 106 and the second conductive type pillar 107 are formed is not overly restricted. To reduce process complexity, the doping concentrations of the second conductive type floating island 106 and the second conductive type pillar 107 can be the same, and the doping implantation source can be B11, but it is not limited to this. Since the second conductive type floating island 106 and the second conductive type pillar 107 are formed using the same superjunction mask in this embodiment, the second conductive type floating island 106 and the second conductive type pillar 107 have the same width.

[0097] As an example, the thickness of the first conductive type epitaxial layer 102 between the formed second conductive type floating island 106 and the formed second conductive type pillar 107 is greater than 0.1 μm, so as to form a PNP transistor between the second conductive type pillar 107 and the second conductive type floating island 106, thereby further reducing the on-resistance of the IGBT device.

[0098] Next, the trench gate structure is formed within the first conductivity type epitaxial layer 102.

[0099] Specifically, the trench gate structure can reduce the unit area of ​​the power device, wherein the step of fabricating the trench gate structure may include:

[0100] The first conductivity type epitaxial layer 102 is etched to form a gate trench;

[0101] A gate oxide layer 108 is grown on the surface of the gate trench using a thermal oxidation growth process, covering the bottom and sidewalls of the gate trench.

[0102] Polysilicon is deposited in the gate trench to form the gate conductive layer 109.

[0103] The trench gate structure can reduce the unit area of ​​the power device. The preparation method of the trench gate structure is not limited to this. A split gate structure can also be selected as needed. The specific preparation process and structure are not limited here.

[0104] Next, using a well region mask, a second conductivity type well region 103 is formed within the first conductivity type epitaxial layer 102 between the trench gate structures. The second conductivity type well region 103 is located above and in contact with the second conductivity type pillar 107.

[0105] Next, a first conductivity type source region 104 is formed within the second conductivity type well region 103 using a source region mask.

[0106] Next, a contact structure 105 is formed through a contact mask. The contact structure 105 penetrates the first conductivity type source region 104 and is in contact with the second conductivity type well region 103.

[0107] Specifically, such as Figure 3In this embodiment, the contact structure 105 is formed by injecting a second type of conductive impurity into the second conductive type well region 103 to short-circuit the first conductive type source region 104. However, it is not limited to this. The contact structure 105 can also be a trench contact structure, which includes a second conductive type contact region located in the second conductive type well region 103 and a metal contact region, such as metal W, that penetrates the first conductive type source region 104 and contacts the second conductive type contact region, to further reduce the on-resistance and reduce the area of ​​the traditional planar contact structure. The trench contact structure will be described in subsequent embodiments and will not be described here.

[0108] Next, as Figure 4 It may also include the steps of forming an interlayer dielectric layer 110, a source metal layer 111, and a drain metal layer 112 to form a VDMOSFET device. The order of the steps in forming the superjunction power device can be selected according to specific needs, and no excessive restrictions are imposed here.

[0109] As an example, the method also includes the step of forming a first conductivity type buffer layer on the lower surface of the first conductivity type epitaxial layer 102.

[0110] Specifically, the doping concentration of the first conductivity type buffer layer can be between the doping concentrations of the first conductivity type substrate 101 and the first conductivity type epitaxial layer 102. Through the first conductivity type buffer layer, in the VDMOSFET device, it can prevent impurity atoms from the first conductivity type substrate 101 from diffusing into the first conductivity type epitaxial layer 102 during the high-temperature process, avoid the breakdown voltage of the superjunction power device from decreasing due to the increase in the doping concentration of the first conductivity type epitaxial layer 102, and solve the tail current problem of the device when it is turned off through the first conductivity type substrate 101.

[0111] See Figure 5 This embodiment also provides a method for fabricating an IGBT device, which is related to... Figure 4 The main difference in fabricating the VDMOSFET device is that an additional step of fabricating a second conductivity type implantation layer 113 is added between the drain metal layer 112 and the first conductivity type epitaxial layer 102. Specifically, the first conductivity type substrate 101 can be removed by CMP, and the second conductivity type impurity can be implanted to form the second conductivity type implantation layer 113, but it is not limited to this.

[0112] See Figure 3 This embodiment also provides a superjunction power device, which can be prepared using the above method, but is not limited thereto.

[0113] Specifically, the superjunction power device includes a first conductivity type epitaxial layer 102, a trench gate structure, a second conductivity type well region 103, a first conductivity type source region 104, a contact structure 105, a second conductivity type floating island 106, and a second conductivity type pillar 107. Wherein, the second conductivity type well region 103 is located within the first conductivity type epitaxial layer 102; the first conductivity type source region 104 is located within the second conductivity type well region 103; the trench gate structure is located within the first conductivity type epitaxial layer 102, including a gate oxide layer 108 and a gate conductive layer 109, and the trench gate structure penetrates the first conductivity type source region 104 and the second conductivity type well region 103; the contact structure 105 penetrates the first conductivity type source region 104 and contacts the second conductivity type well region 103; the second conductivity type floating island 106 is located within the first conductivity type epitaxial layer 102, and both the upper and lower surfaces of the second conductivity type floating island 106 are in contact with the first conductivity type epitaxial layer 102; the second conductivity type pillar 107 is located within the first conductivity type epitaxial layer 102, directly above the second conductivity type floating island 106, and in contact with the second conductivity type well region 103; and the second conductivity type floating island 106 and the second conductivity type pillar 107 have the same width.

[0114] In this embodiment, the superjunction power device with the second conductivity type floating island 106 and the second conductivity type pillar 107, in the off-circuit state, both the second conductivity type floating island 106 and the second conductivity type pillar 107 contribute to the charge sharing effect of the drift region in the first conductivity type epitaxial layer 102, thereby improving the breakdown voltage of the power device and reducing Miller capacitance and input capacitance. In the on-circuit state, the second conductivity type floating island 106 and the second conductivity type pillar 107 allow the drift region in the first conductivity type epitaxial layer 102 to have a higher doping concentration, significantly conducting current and reducing on-resistance. Furthermore, since the first conductivity type epitaxial layer 102 is between the second conductivity type floating island 106 and the second conductivity type pillar 107, an additional transistor can be formed within the first conductivity type epitaxial layer 102, further reducing the on-resistance of the IGBT device.

[0115] As an example, the thickness of the first conductive type epitaxial layer 102 between the second conductive type floating island 106 and the second conductive type pillar 107 is greater than 0.1 μm, such as 1 μm, 5 μm, etc., and is not excessively limited here.

[0116] As an example, the contact structure 105 includes a second conductivity type contact area located within the second conductivity type well region 103 and a metal contact area that penetrates the first conductivity type source region 104 and contacts the second conductivity type contact area.

[0117] As an example, the lower surface of the first conductivity type epitaxial layer 102 may also include a first conductivity type buffer layer to prevent impurity atoms from the first conductivity type substrate 101 from diffusing into the first conductivity type epitaxial layer 102 during high-temperature processing, thereby preventing the increase of impurity concentration in the first conductivity type epitaxial layer 102 and thus reducing the breakdown voltage of the superjunction power device. The first conductivity type buffer layer can also solve the problem of tail current when the device is turned off.

[0118] As an example, the lower surface of the first conductivity type epitaxial layer 102 also includes a second conductivity type injection layer.

[0119] For details, please refer to Figure 4 It may also include an interlayer dielectric layer 110, a source metal layer 111, and a drain metal layer 112 to form a VDMOSFET device, and see also Figure 5 Furthermore, an additional second conductivity type injection layer 113 may be added between the drain metal layer 112 and the first conductivity type epitaxial layer 102 to form an IGBT device. Additionally, a split-gate structure may also be used for the gate structure; this is not a strict limitation.

[0120] Example 2

[0121] See Figure 6 This embodiment also provides another method for fabricating a superjunction power device that simultaneously possesses a second type of conductive floating island and a second type of conductive pillar, wherein, see reference... Figures 7-9 The diagram shows a schematic of the structure of the superjunction power device formed. The main difference from Embodiment 1 is that, in this embodiment, before or after forming the second conductivity type well region, a second conductivity type impurity is implanted into the first conductivity type epitaxial layer using the well region mask to sequentially form a second conductivity type floating island and a second conductivity type pillar with the same width as the second conductivity type well region.

[0122] In this embodiment, the second conductivity type impurities are directly implanted into the first conductivity type epitaxial layer through the well region mask to sequentially form the second conductivity type floating island and the second conductivity type pillar. This fabrication process does not require multiple epitaxial processes, deep trench etching, or additional masking. Therefore, the fabrication process is simple, low-cost, and has a high yield and reliability.

[0123] It should be noted that in this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is not limited to this. In another embodiment, the first conductivity type can also be p-type and the second conductivity type can also be n-type.

[0124] See Figure 6 Specific preparation process steps may include:

[0125] A substrate 201 of a first conductivity type is provided;

[0126] A first conductivity type epitaxial layer 202 is formed on the first conductivity type substrate 201;

[0127] A trench gate structure is formed in the first conductivity type epitaxial layer 202, the trench gate structure including a gate oxide layer 208 and a gate conductive layer 209;

[0128] Form a trap region mask;

[0129] Through the well region mask, a second type of impurity is injected into the first type of conductive epitaxial layer 202 to form a second type of conductive floating island 206. The second type of conductive floating island 206 is located in the first type of conductive epitaxial layer 202, and the upper and lower surfaces of the second type of conductive floating island 206 are in contact with the first type of conductive epitaxial layer 202.

[0130] Through the well mask, a second type of impurity is injected into the first type of conductive epitaxial layer 202 to form a second type of conductive pillar 207. The second type of conductive pillar 207 is located in the first type of conductive epitaxial layer 202 and is located directly above the second type of conductive island 206.

[0131] Through the well region mask, a second conductivity type well region 203 is formed in the first conductivity type epitaxial layer 202 between the trench gate structures, and the second conductivity type pillar 207 is in contact with the second conductivity type well region 203.

[0132] A first conductivity type source region 204 is formed within the second conductivity type well region 203 using a source region mask;

[0133] A contact structure 205 is formed by using a contact mask. The contact structure 205 penetrates the first conductivity type source region 204 and is in contact with the second conductivity type well region 203.

[0134] Specifically, the trench gate structure can reduce the unit area of ​​the power device. The trench gate structure can also be selected with a segmented gate structure as needed; the specific fabrication process and structure are not limited here. The order in which the second conductivity type floating island 206, the second conductivity type pillar 207, and the second conductivity type well region 203 are formed through the well region mask is not limited to this. For example, the second conductivity type floating island 206 and the second conductivity type pillar 207 can also be implanted after the second conductivity type well region 203 is formed, and the specific order can be adjusted as needed. The function of the second conductivity type floating island 206 and the second conductivity type pillar 207 can be found in Embodiment 1, and will not be repeated here.

[0135] As an example, the thickness of the first conductive type epitaxial layer 202 between the formed second conductive type floating island 206 and the formed second conductive type pillar 207 is greater than 0.1 μm, such as 1 μm, 5 μm, etc., and is not excessively limited here.

[0136] As an example, the contact structure 205 is formed by injecting a second type of impurity into the second type of conductivity well region 203 to short-circuit the first type of conductivity source region 204. However, it is not limited to this. The contact structure 205 can also adopt a trench contact structure. The trench contact structure will be described in subsequent embodiments and will not be described here.

[0137] Next, as Figure 8 It may also include the steps of forming an interlayer dielectric layer 210, a source metal layer 211, and a drain metal layer 212 to form a VDMOSFET device. The order of the steps in forming the superjunction power device can be selected according to specific needs and is not excessively restricted here.

[0138] As an example, the method also includes the step of forming a first conductivity type buffer layer on the lower surface of the first conductivity type epitaxial layer 202.

[0139] See Figure 9 This embodiment also provides a method for fabricating an IGBT device, which is related to... Figure 8 The main difference in fabricating the VDMOSFET device lies in the addition of a step to fabricate an additional second conductivity type implantation layer 213 between the drain metal layer 212 and the first conductivity type epitaxial layer 202. Specifically, the first conductivity type substrate 201 can be removed by CMP, and the second conductivity type impurity can be implanted to form the second conductivity type implantation layer 213, but it is not limited to this.

[0140] See Figure 7This embodiment also provides a superjunction power device, which can be prepared using the above method, but is not limited thereto.

[0141] Specifically, the superjunction power device includes a first conductivity type epitaxial layer 202, a trench gate structure, a second conductivity type well region 203, a first conductivity type source region 204, a contact structure 205, a second conductivity type floating island 206, and a second conductivity type pillar 207. The second conductivity type well region 203 is located within the first conductivity type epitaxial layer 202; the first conductivity type source region 204 is located within the second conductivity type well region 203; the trench gate structure is located within the first conductivity type epitaxial layer 202, including a gate oxide layer 208 and a gate conductive layer 209, and the trench gate structure penetrates both the first conductivity type source region 204 and the second conductivity type well region 203; the contact structure 205 penetrates the first conductivity type source region 204 and contacts the second conductivity type well region 203. The second conductive type floating island 206 is located within the first conductive type epitaxial layer 202, and both its upper and lower surfaces are in contact with the first conductive type epitaxial layer 202; the second conductive type pillar 207 is located within the first conductive type epitaxial layer 202, directly above the second conductive type floating island 206, and in contact with the second conductive type well region 203; and the second conductive type floating island 206, the second conductive type pillar 207, and the second conductive type well region 203 have the same width.

[0142] As an example, the thickness of the first conductive type epitaxial layer 202 between the second conductive type floating island 206 and the second conductive type pillar 207 is greater than 0.1 μm, such as 1 μm, 5 μm, etc., and is not excessively limited here.

[0143] As an example, the contact structure 205 includes a second conductivity type contact area located within the second conductivity type well region 203 and a metal contact area that penetrates the first conductivity type source region 204 and contacts the second conductivity type contact area.

[0144] As an example, the lower surface of the first conductivity type epitaxial layer 202 may also include a first conductivity type buffer layer.

[0145] As an example, the lower surface of the first conductivity type epitaxial layer 202 also includes a second conductivity type injection layer.

[0146] For details, please refer to Figure 8 It may also include an interlayer dielectric layer 210, a source metal layer 211, and a drain metal layer 212 to form a VDMOSFET device, and see also Figure 9Furthermore, an additional second conductivity type injection layer 213 may be added between the drain metal layer 212 and the first conductivity type epitaxial layer 202 to form an IGBT device. Additionally, a split-gate structure may also be used for the gate structure; this is not a strict limitation.

[0147] Example 3

[0148] See Figure 10 This embodiment also provides another method for fabricating a superjunction power device that simultaneously possesses a second type of conductive floating island and a second type of conductive pillar, wherein, see reference... Figures 11-13 The diagram shows a schematic of the structure of the superjunction power device. The main difference from Embodiments 1 and 2 is that, in this embodiment, before or after forming the contact structure, a second conductivity type impurity is directly injected into the first conductivity type epitaxial layer through a contact mask to sequentially form a second conductivity type floating island and a second conductivity type pillar with the same width as the contact structure; the contact structure adopts a trench contact structure, i.e., it includes a second conductivity type contact area and a metal contact area; a first conductivity type buffer layer is formed on the lower surface of the first conductivity type epitaxial layer.

[0149] In this embodiment, a second conductive type impurity is directly implanted into the first conductive type epitaxial layer through the contact mask to sequentially form the second conductive type floating island and the second conductive type pillar. This fabrication process does not require multiple epitaxial processes, deep trench etching, or additional masks. Therefore, the fabrication process is simple, low-cost, and has a high yield and reliability. Preferably, the second conductive type floating island and the second conductive type pillar are formed after the contact mask is formed and before the contact structure is formed, so that the annealing process of the second conductive type floating island and the second conductive type pillar can be completed simultaneously through the annealing step of the contact structure, thereby further reducing the process complexity and cost.

[0150] It should be noted that in this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is not limited to this. In another embodiment, the first conductivity type can also be p-type and the second conductivity type can also be n-type.

[0151] See Figure 10 Specific preparation process steps may include:

[0152] A substrate 301 of a first conductivity type is provided;

[0153] A first conductivity type epitaxial layer 302 is formed on the first conductivity type substrate 301;

[0154] A trench gate structure is formed in the first conductivity type epitaxial layer 302, the trench gate structure including a gate oxide layer 308 and a gate conductive layer 309;

[0155] A second conductivity type well region 303 is formed within the first conductivity type epitaxial layer 302 between the trench gate structures using a well region mask.

[0156] A first conductivity type source region 304 is formed within the second conductivity type well region 303 using a source region mask;

[0157] Forming a contact mask;

[0158] Through the contact mask, a second type of impurity is injected into the first type of conductive epitaxial layer 302 to form a second type of conductive floating island 306. The second type of conductive floating island 306 is located in the first type of conductive epitaxial layer 302, and the upper and lower surfaces of the second type of conductive floating island 306 are in contact with the first type of conductive epitaxial layer 302.

[0159] Through the contact mask, a second type of impurity is injected into the first type of conductive epitaxial layer 302 to form a second type of conductive pillar 307. The second type of conductive pillar 307 is located in the first type of conductive epitaxial layer 302, directly above the second type of conductive island 306, and in contact with the second type of conductive well region 303.

[0160] A contact structure 305 is formed through the contact mask, the contact structure 305 penetrating the first conductivity type source region 304 and contacting the second conductivity type well region 303.

[0161] Specifically, the trench gate structure can reduce the unit area of ​​the power device. The trench gate structure can also be selected as a split gate structure as needed. The specific fabrication process and structure are not limited here.

[0162] As an example, the steps for forming the contact structure 305 include:

[0163] The first conductivity type source region 304 is etched through the contact mask to form a contact trench that penetrates the first conductivity type source region 304.

[0164] A second type of impurity is injected into the second type of conductivity well region 303 through the contact mask to form a second type of conductivity contact region 3051;

[0165] The contact mask forms a metal contact area 3052 that fills the contact trench, and the metal contact area 3052 is in contact with the second conductivity type contact area 3051.

[0166] Specifically, the second conductive type pillar 307 contacts the second conductive type contact area 3051. The metal contact area 3052 can be made of metal W to short-circuit the first conductive type source area 304, further reducing the on-resistance and shrinking the area of ​​the traditional planar contact structure. Preferably, the second conductive type floating island 306 and the second conductive type pillar 307 are formed after the contact mask is formed and before the contact structure 305 is formed. This allows the annealing process of the second conductive type floating island 306 and the second conductive type pillar 307 to be completed simultaneously during the annealing step of the second conductive type contact area 3051, thereby further reducing process complexity and cost. The order in which the second conductive type floating island 306, the second conductive type pillar 307, and the contact structure 305 are formed using the contact mask is not limited to this and can be set as needed. The functions of the second conductive type floating island 306 and the second conductive type pillar 307 can be found in Embodiment 1, and will not be repeated here.

[0167] As an example, the thickness of the first conductive type epitaxial layer 302 between the formed second conductive type floating island 306 and the formed second conductive type pillar 307 is greater than 0.1 μm, such as 1 μm, 5 μm, etc., and is not excessively limited here.

[0168] Next, as Figure 12 It may also include the steps of forming an interlayer dielectric layer 310, a source metal layer 311, and a drain metal layer 312 to form a VDMOSFET device. The order of the steps in forming the superjunction power device can be selected according to specific needs and is not excessively restricted here.

[0169] As an example, the method also includes the step of forming a first conductivity type buffer layer 314 on the lower surface of the first conductivity type epitaxial layer 302.

[0170] Specifically, the first conductivity type buffer layer 314 can prevent impurity atoms from the first conductivity type substrate 301 from diffusing into the first conductivity type epitaxial layer 302 during the high-temperature process, thereby avoiding an increase in the impurity concentration of the first conductivity type epitaxial layer 302, which would lead to a decrease in the breakdown voltage of the superjunction power device. Furthermore, the first conductivity type buffer layer 314 can solve the problem of tail current during device turn-off.

[0171] See Figure 13 This embodiment also provides a method for fabricating an IGBT device, which is related to... Figure 12The main difference in fabricating the VDMOSFET device lies in the addition of a step to fabricate an additional second conductivity type implantation layer 313 between the drain metal layer 313 and the first conductivity type epitaxial layer 302. Specifically, the first conductivity type substrate 301 can be removed by CMP, and the second conductivity type impurity can be implanted to form the second conductivity type implantation layer 313, but it is not limited to this.

[0172] See Figure 11 This embodiment also provides a superjunction power device, which can be prepared using the above method, but is not limited thereto.

[0173] Specifically, the superjunction power device includes a first conductivity type epitaxial layer 302, a trench gate structure, a second conductivity type well region 303, a first conductivity type source region 304, a contact structure 305, a second conductivity type floating island 306, and a second conductivity type pillar 307. The second conductivity type well region 303 is located within the first conductivity type epitaxial layer 302; the first conductivity type source region 304 is located within the second conductivity type well region 303; the trench gate structure is located within the first conductivity type epitaxial layer 302, including a gate oxide layer 308 and a gate conductive layer 309, and the trench gate structure penetrates both the first conductivity type source region 304 and the second conductivity type well region 303; the contact structure 305 penetrates the first conductivity type source region 304 and is connected to the second conductivity type well region 303. The second conductive type floating island 306 is located within the first conductive type epitaxial layer 302, and both its upper and lower surfaces are in contact with the first conductive type epitaxial layer 302; the second conductive type pillar 307 is located within the first conductive type epitaxial layer 302, directly above the second conductive type floating island 306, and in contact with the second conductive type well region 303; and the second conductive type floating island 306, the second conductive type pillar 307, and the contact structure 305 have the same width.

[0174] As an example, the contact structure 305 includes a second conductivity type contact area 3051 located within the second conductivity type well area 303 and a metal contact area 3052 that penetrates the first conductivity type source area 304 and contacts the second conductivity type contact area 3051, and the second conductivity type post 307 contacts the second conductivity type contact area 3051.

[0175] As an example, the thickness of the first conductive type epitaxial layer 302 between the second conductive type floating island 306 and the second conductive type pillar 307 is greater than 0.1 μm, such as 1 μm, 5 μm, etc., and is not excessively limited here.

[0176] As an example, the lower surface of the first conductivity type epitaxial layer 302 may also include a first conductivity type buffer layer 314.

[0177] As an example, the lower surface of the first conductivity type epitaxial layer 302 also includes a second conductivity type injection layer 313.

[0178] For details, please refer to Figure 12 It may also include an interlayer dielectric layer 310, a source metal layer 311, and a drain metal layer 312 to form a VDMOSFET device, and see also Figure 13 Furthermore, an additional second conductivity type injection layer 313 may be added between the drain metal layer 312 and the first conductivity type epitaxial layer 302 to form an IGBT device. Additionally, a split-gate structure may also be used for the gate structure; this is not a strict limitation.

[0179] In summary, the superjunction power device and its fabrication method of the present invention, when fabricating the superjunction power device, can inject second conductivity type impurities into the first conductivity type epitaxial layer by adding a superjunction mask after forming the first conductivity type epitaxial layer, directly passing through the well region mask before or after forming the second conductivity type well region, and directly passing through the contact mask before or after forming the contact structure, thereby sequentially forming second conductivity type floating islands and second conductivity type pillars. This fabrication process does not require multiple epitaxial processes and does not require deep trench etching. Therefore, the fabrication process is simple, low-cost, and has high yield and reliability. In a superjunction power device that simultaneously possesses both a second-type conductive floating island and a second-type conductive pillar, in the off-circuit state, both the second-type conductive floating island and the second-type conductive pillar contribute to the charge-sharing effect of the drift region in the first-type conductive epitaxial layer, thereby increasing the breakdown voltage of the power device and reducing Miller capacitance and input capacitance. In the on-circuit state, the second-type conductive floating island and the second-type conductive pillar allow for a higher doping concentration in the drift region of the first-type conductive epitaxial layer, significantly improving current conduction and reducing the on-resistance of the VDMOSFET device. Furthermore, since the first-type conductive epitaxial layer exists between the second-type conductive floating island and the second-type conductive pillar, an additional transistor can be formed within the first-type conductive epitaxial layer, further reducing the on-resistance of the IGBT device.

[0180] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a superjunction power device, characterized in that, Includes the following steps: Form an epitaxial layer of the first conductivity type; A trench gate structure is formed in the epitaxial layer of the first conductivity type, the trench gate structure including a gate oxide layer and a gate conductive layer; A second conductivity type well region is formed within the first conductivity type epitaxial layer between the trench gate structures using a well region mask. A first conductivity type source region is formed within the second conductivity type well region using a source region mask; A contact structure is formed by using a contact mask. The contact structure penetrates the first conductivity type source region and contacts the second conductivity type well region. The contact structure includes a second conductivity type contact region located in the second conductivity type well region and a metal contact region that penetrates the first conductivity type source region and contacts the second conductivity type contact region. A second type of conductive floating island is formed, which is located within the first type of conductive epitaxial layer, and the upper and lower surfaces of the second type of conductive floating island are in contact with the first type of conductive epitaxial layer. A second conductive type pillar is formed, which is located within the first conductive type epitaxial layer and directly above the second conductive type floating island. The thickness of the first conductive type epitaxial layer between the second conductive type floating island and the second conductive type pillar is greater than 0.1 μm. The second conductive type pillar is in contact with the second conductive type well region and the second conductive type contact region. The trench gate structure, the second conductivity type well region, the first conductivity type source region, the contact structure, the second conductivity type floating island, and the second conductivity type pillar are all located within the same first conductivity type epitaxial layer. The second conductivity type floating island and the second conductivity type pillar are formed by sequentially implanting second conductivity type impurities into the first conductivity type epitaxial layer based on the contact mask before forming the contact structure, so that the second conductivity type floating island and the second conductivity type pillar are sequentially prepared based on the same mask, and the second conductivity type floating island, the second conductivity type pillar, the second conductivity type contact region, and the metal contact region have the same width. The annealing process of the second conductivity type floating island and the second conductivity type pillar is completed simultaneously through the annealing step of the contact structure.

2. The preparation method according to claim 1, characterized in that, The steps for forming the contact structure include: The first conductivity type source region is etched through the contact mask to form a contact trench that penetrates the first conductivity type source region; A second type of conductive impurity is injected into the second type of conductive well region through the contact mask to form a second type of conductive contact region; The contact mask forms a metal contact area that fills the contact trench, and the metal contact area is in contact with the second type of conductive contact area.

3. The preparation method according to claim 1, characterized in that: The first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

4. The preparation method according to claim 1, characterized in that: It also includes the step of forming a first conductivity type buffer layer on the lower surface of the first conductivity type epitaxial layer.

5. The preparation method according to any one of claims 1 to 4, characterized in that: It also includes the step of forming a second conductivity type implantation layer on the lower surface of the first conductivity type epitaxial layer.

6. A superjunction power device, characterized in that, The superjunction power device includes: First conductivity type epitaxial layer; The second conductivity type well region is located within the first conductivity type epitaxial layer; The first conductivity type source region is located within the second conductivity type well region; A trench gate structure, comprising a gate oxide layer and a gate conductive layer, wherein the trench gate structure is located within a first conductivity type epitaxial layer and penetrates the first conductivity type source region and the second conductivity type well region; A contact structure extends through the first conductivity type source region and contacts the second conductivity type well region. The contact structure includes a second conductivity type contact region located within the second conductivity type well region and a metal contact region extending through the first conductivity type source region and contacting the second conductivity type contact region. The second type of conductive floating island is located within the first type of conductive epitaxial layer, and both the upper and lower surfaces of the second type of conductive floating island are in contact with the first type of conductive epitaxial layer. The second conductive type pillar is located within the first conductive type epitaxial layer and directly above the second conductive type floating island. The thickness of the first conductive type epitaxial layer between the second conductive type floating island and the second conductive type pillar is greater than 0.1 μm. The second conductive type pillar is in contact with the second conductive type well region and the second conductive type contact region. The trench gate structure, the second conductivity type well region, the first conductivity type source region, the contact structure, the second conductivity type floating island, and the second conductivity type pillar are all located within the same first conductivity type epitaxial layer. The second conductivity type floating island and the second conductivity type pillar are formed by sequentially implanting second conductivity type impurities into the first conductivity type epitaxial layer based on a contact mask, so that the second conductivity type floating island and the second conductivity type pillar are sequentially fabricated based on the same mask, and the second conductivity type floating island, the second conductivity type pillar, the second conductivity type contact region, and the metal contact region have the same width.

7. The superjunction power device according to claim 6, characterized in that: The first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

8. The superjunction power device according to claim 6, characterized in that: The lower surface of the first conductivity type epitaxial layer also includes a first conductivity type buffer layer.

9. The superjunction power device according to any one of claims 6 to 8, characterized in that: The lower surface of the first conductivity type epitaxial layer also includes a second conductivity type injection layer.

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