Package structure and manufacturing method thereof

Abstract

A structure including a first semiconductor die, an interposer, and a first insulative encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a via disposed on the interconnect structure. The interposer includes a dielectric layer and a via through the dielectric layer. The first insulative encapsulation laterally encapsulates the first semiconductor die and the interposer, where a thickness of the dielectric layer of the interposer is substantially equal to a thickness of the first semiconductor die and a thickness of the first insulative encapsulation.

Description

Technical Field

[0001] The embodiments of the present invention relate to an encapsulation structure and a method for manufacturing the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. This improvement in integration density primarily stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. With the recent increase in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the need for smaller and more innovative semiconductor die packaging technologies has also grown. Currently, integrated fan-out packages are becoming increasingly favored due to their versatility, compactness, and high performance. However, challenges associated with integrated fan-out technology exist (e.g., warpage issues). Summary of the Invention

[0003] This invention provides a packaging structure including a first semiconductor die, an interposer, and a first insulating encapsulator. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and vias disposed on the interconnect structure. The interposer includes a dielectric layer and through-holes penetrating the dielectric layer. The first insulating encapsulator laterally encapsulates the first semiconductor die and the interposer, wherein the thickness of the dielectric layer of the interposer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator.

[0004] This invention provides a packaging structure including a first semiconductor die, a first dielectric layer, a first insulating encapsulator, a first redistribution layer, and a second redistribution layer. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a via disposed on the interconnect structure. The first dielectric layer includes a dielectric layer and through-holes penetrating the dielectric layer, wherein the first semiconductor die and the first dielectric layer are arranged side-by-side. The first insulating encapsulator laterally encapsulates the first semiconductor die and the first dielectric layer, wherein the through-holes are spaced apart from the first insulating encapsulator by passing through the dielectric layer, and the thickness of the dielectric layer of the first dielectric layer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. The first redistribution layer is disposed on a first surface of the first insulating encapsulator, an active surface of the first semiconductor die, and a first surface of the first dielectric layer. The second re-laid circuit layer is disposed on the second surface of the first insulating encapsulation, the rear surface of the first semiconductor die, and the second surface of the first dielectric interlayer, wherein the first semiconductor die is electrically connected to the second re-laid circuit layer through through-holes in the first re-laid circuit layer and the first dielectric interlayer.

[0005] This invention provides a method for fabricating a package structure, comprising the following steps: A first semiconductor die is provided, the first semiconductor die including a first semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, and vias disposed on the interconnect structure. An interposer die is provided, the interposer die including a second semiconductor substrate, a dielectric layer disposed on the second semiconductor substrate, and vias penetrating the dielectric layer. An insulating material is used to laterally encapsulate the first semiconductor die and the interposer die. A thinning process is performed to remove the insulating material, the second semiconductor substrate, and a portion of the first semiconductor substrate, thereby forming a dielectric interposer encapsulated by a first insulating encapsulator, wherein the dielectric interposer includes a dielectric layer and vias, and the thickness of the dielectric layer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. Attached Figure Description

[0006] A thorough understanding of all aspects of this disclosure is best achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1I This is a cross-sectional view schematically illustrating the process flow for fabricating a packaging structure according to some embodiments of the present disclosure.

[0008] Figure 2 This is a top view schematically illustrating a packaging structure according to some embodiments of the present disclosure.

[0009] Figures 3 to 5 This is a cross-sectional view schematically illustrating the packaging structure according to various embodiments of the present disclosure.

[0010] Figure 6 and Figure 7 This is a top view schematically illustrating the packaging structure according to various embodiments of the present disclosure.

[0011] Figures 8A to 8I This is a cross-sectional view schematically illustrating a process flow for fabricating passive devices according to some alternative embodiments of the present disclosure. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples to implement various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for simplicity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. In addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0014] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional (3D) packaged or 3D integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which allow testing of the 3D package or 3DIC, and allow the use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that include verifying known good dies in the intermediate stages to improve yield and reduce costs.

[0015] Figures 1A to 1I This is a cross-sectional view schematically illustrating the process flow for fabricating a packaging structure according to some embodiments of the present disclosure.

[0016] refer to Figure 1AA carrier C1 is provided. In some embodiments, a release layer (not shown) is formed thereon on the carrier C1. In some embodiments, the carrier C1 is a wafer-form glass substrate, and the release layer is a light-to-heat conversion (LTHC) release layer formed on the wafer-form glass substrate. The materials of the carrier C1 and the release layer are not limited in this invention. In some alternative embodiments, the release layer formed on the carrier C1 may be omitted.

[0017] In some embodiments, a semiconductor die 110, at least one interposer die 120a, and an interposer die 120b are provided and disposed on a carrier C1. The semiconductor die 110, the at least one interposer die 120a, and the interposer die 120b may be substantially the same thickness. The semiconductor die 110, the at least one interposer die 120a, and the interposer die 120b disposed on the carrier C1 may be arranged side-by-side. The semiconductor die 110, the at least one interposer die 120a, and the interposer die 120b may be mounted on the carrier C1 via die attachment films, adhesives, or the like. Figure 1A As described, the at least one interposer die 120a may be disposed between semiconductor dies 110, with the left semiconductor die 110 disposed between the at least one interposer die 120a and the left interposer die 120b, and the right semiconductor die 110 disposed between the at least one interposer die 120a and the right interposer die 120b. In some alternative embodiments, the interposer die 120b is omitted.

[0018] Semiconductor dies 110 can be monolithically generated from semiconductor wafers fabricated through a series of semiconductor processes. Each semiconductor die 110 may include a semiconductor substrate 112, an interconnect structure 114, a via 116, and a protective layer 118. Each semiconductor die 110 may include an active surface 111 and a rear surface 113 opposite to the active surface 111. The semiconductor substrate 112 may be a silicon substrate including active components (e.g., transistors) and passive components (e.g., resistors, capacitors, inductors), which are formed in the semiconductor substrate 112. The active and passive components are formed in the semiconductor substrate 112 via a front-end of line (FEOL) fabrication process. The interconnect structure 114 is disposed on the semiconductor substrate 112. The interconnect structure 114 may include alternately stacked interconnect wirings (e.g., copper interconnect wirings) and a dielectric layer, wherein the interconnect wirings of the interconnect structure 114 are electrically connected to active and / or passive components in the semiconductor substrate 112. The interconnect structure 114 is formed via a back-end of line (BEOL) fabrication process for a semiconductor wafer. The topmost interconnect wiring may include conductive pads, which may be aluminum pads, copper pads, or other suitable metal pads. The interconnect structure 114 may also include a passivation layer, wherein the conductive pads are partially covered by the passivation layer. In other words, the conductive pads are partially exposed from openings defined in the passivation layer. The passivation layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable inorganic dielectric materials. The interconnect structure 114 may further include a post-passivation layer formed over the passivation layer, wherein the post-passivation layer covers the passivation layer and conductive pads, the post-passivation layer including a plurality of contact openings, and the conductive pads partially exposed from the contact openings defined in the post-passivation layer. The post-passivation layer may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable organic dielectric materials. In some embodiments, the post-passivation layer is omitted.

[0019] In some embodiments, such as Figure 1AAs described, via 116 penetrates through protective layer 118, exposing the top surface of via 116, and the height of via 116 is substantially equal to the thickness of protective layer 118. Via 116 can be a copper via or other suitable metal via, and protective layer 118 can be a polyimide (PI) layer, a PBO layer, or a dielectric layer formed from other suitable organic dielectric materials. Via 116 can be first formed on interconnect structure 114, a dielectric material can be formed on interconnect structure 114 to cover via 116, and then a polishing process (e.g., chemical mechanical polishing, mechanical polishing, combinations thereof) can be performed to remove some portions of the dielectric material until the top surface of via 116 is exposed.

[0020] In some alternative embodiments, Figure 1A It is not explained in the text that the via is covered by a protective layer, the top surface of the via is not exposed, and the height of the via is less than the thickness of the protective layer.

[0021] In some embodiments, the at least one interposer die 120a can be monomerized from a semiconductor wafer fabricated through a series of semiconductor processes, and the interposer die 120b can be monomerized from another semiconductor wafer fabricated through a series of semiconductor processes. In some alternative embodiments, the at least one interposer die 120a and the interposer die 120b can be monomerized from a single semiconductor wafer.

[0022] The at least one interposer die 120a may include a semiconductor substrate 122a, a dielectric layer 124a disposed on the semiconductor substrate 122a, and a via 126a penetrating the dielectric layer 124a. The semiconductor substrate 122a may be a bare silicon substrate in which no active components (e.g., transistors, etc.) or passive components (e.g., resistors, capacitors, inductors, etc.) are formed. The dielectric layer 124a may be a molding compound, an underfill material, a molded underfill material, a polyimide (PI) layer, a PBO layer, or a dielectric layer formed by other suitable organic dielectric materials. For example, the molding compound includes epoxy resin. Furthermore, the via 126a may be a copper via or other suitable metal via.

[0023] In some embodiments, such as Figure 1AAs described, the via 126a penetrates the dielectric layer 124a, exposing the top surface of the via 126a, and the height of the via 126a is substantially equal to the thickness of the dielectric layer 124a. The dielectric layer 124a can be a molding compound, an underfill material, a molded underfill material, a polyimide (PI) layer, a PBO layer, or a dielectric layer formed from other suitable organic dielectric materials. For example, molding compounds include epoxy resins. Furthermore, the via 126a can be a copper via or other suitable metal via. The via 126a can be formed first on a semiconductor substrate 122a, a dielectric material can be formed on the semiconductor substrate 122a to cover the via 126a, and then a polishing process (e.g., chemical mechanical polishing, mechanical polishing, combinations thereof) can be performed to remove portions of the dielectric material until the top surface of the via 126a is exposed.

[0024] In some alternative embodiments, Figure 1A It is not explained in the text that the perforation is covered by a dielectric layer, the top surface of the perforation is not exposed, and the height of the perforation is less than the thickness of the dielectric layer.

[0025] Each of the interposer dies 120b may include a semiconductor substrate 122b, a dielectric layer 124b disposed on the semiconductor substrate 122b, and a via 126b penetrating the dielectric layer 124b. The semiconductor substrate 122b may be a bare silicon substrate in which no active components (e.g., transistors, etc.) or passive components (e.g., resistors, capacitors, inductors, etc.) are formed. The dielectric layer 124b may be a molding compound, an underfill material, a molded underfill material, a polyimide (PI) layer, a PBO layer, or a dielectric layer formed from other suitable organic dielectric materials. For example, the molding compound includes epoxy resin. Furthermore, the via 126b may be a copper via or other suitable metal via.

[0026] In some embodiments, such as Figure 1A As described, the via 126b penetrates through the dielectric layer 124b, exposing the top surface of the via 126b, and the height of the via 126b is substantially equal to the thickness of the dielectric layer 124b. The dielectric layer 124b can be a molding compound, an underfill material, a molded underfill material, a polyimide (PI) layer, a PBO layer, or a dielectric layer formed from other suitable organic dielectric materials. For example, molding compounds include epoxy resins. Furthermore, the via 126b can be a copper via or other suitable metal via. The via 126b can be formed first on the semiconductor substrate 122b, a dielectric material can be formed on the semiconductor substrate 122b to cover the via 126b, and then a polishing process (e.g., chemical mechanical polishing, mechanical polishing, combinations thereof) can be performed to remove portions of the dielectric material until the top surface of the via 126b is exposed.

[0027] In some alternative embodiments, Figure 1A It is not explained in the text that the perforation is covered by a dielectric layer, the top surface of the perforation is not exposed, and the height of the perforation is less than the thickness of the dielectric layer.

[0028] like Figure 1A As described herein, the at least one interlayer die 120a and interlayer die 120b are similar, but the lateral dimension of the at least one interlayer die 120a is greater than the lateral dimension of the interlayer die 120b.

[0029] The thickness of the semiconductor substrate 112 in semiconductor die 110 may be greater than the thickness of semiconductor substrates 122a and 122b in interposers 120a and 120b. The thickness of the semiconductor substrate 112 in semiconductor die 110 may be in the range of approximately 100 micrometers to approximately 780 micrometers, and the thickness of semiconductor substrates 122a and 122b in interposers 120a and 120b may be in the range of approximately 80 micrometers to approximately 760 micrometers. In other words, the top surface of semiconductor substrate 112 may be higher than the top surfaces of semiconductor substrates 122a and 122b. Furthermore, the sum of the height of via 116 and the thickness of interconnect structure 114 may be less than the thickness of dielectric layer 124a and dielectric layer 124b, or the sum of the height of via 116 and the thickness of interconnect structure 114 may be less than the height of through via 126a and through via 126b.

[0030] refer to Figure 1B The insulating material can be formed by an over-molding process or a film deposition process. After performing the over-molding process or film deposition process, a polishing process can be performed to partially remove the insulating material until the via 116 of the semiconductor die 110 and the through holes 126a and 126b of the interposer dies 120a and 120b are exposed. After polishing the insulating material, an insulating encapsulation 130 is formed on the carrier C1 to laterally encapsulate the semiconductor die 110, interposer die 120a, and interposer die 120b. In some embodiments, the polishing process for partially removing the insulating material includes mechanical polishing, chemical mechanical polishing (CMP), or combinations thereof. For example, the material of the insulating encapsulation 130 includes a molding compound, an underfill material, a molded underfill material, or other suitable dielectric material. For example, the molding compound includes epoxy resin.

[0031] After the insulating material is polished, the top surface of the insulating encapsulation 130 may be substantially flush with the top surfaces of the via 116, the protective layer 118, the dielectric layer 124a, the through-hole 126a, the dielectric layer 124b, and the through-hole 126b. In some alternative embodiments, due to polishing selectivity, the top surface of the insulating encapsulation 130 may be slightly higher or slightly lower than the top surfaces of the via 116, the protective layer 118, the dielectric layer 124a, the through-hole 126a, the dielectric layer 124b, and the through-hole 126b.

[0032] Because the interposer die 120a, interposer die 120b, and semiconductor die 110 have similar coefficients of thermal expansion (CTE) and the semiconductor die 110, interposer die 120a, and interposer die 120b are laterally encapsulated using a smaller amount of insulating encapsulant 130, warpage of the encapsulated structure including the semiconductor die 110, interposer die 120a, interposer die 120b, and insulating encapsulant 130 can be minimized. Furthermore, because the encapsulated structure has a thickness of approximately 130 micrometers to approximately 810 micrometers, warpage of the thick encapsulated structure can be minimized. In some embodiments, the CTE of the semiconductor die 110 is in the range of approximately 2 to approximately 6, the CTE of the interposer dies 120a and 120b is in the range of approximately 2 to approximately 6, and the CTE of the insulating encapsulant 130 is in the range of approximately 5 to approximately 35.

[0033] A front-side redistribution layer 140 can be formed to cover the active surface 111 of the semiconductor die 110, the top surface of the interposer die 120a, the top surface of the interposer die 120b, and the top surface of the insulating encapsulation 130. The front-side redistribution layer 140 can be formed on the top surface of the insulating encapsulation 130, the top surface of the via 116, the top surface of the protective layer 118, the top surface of the dielectric layer 124a, the top surface of the via 126a, the top surface of the dielectric layer 124b, and the top surface of the via 126b. The front-side redistribution layer 140 may include a plurality of alternately stacked redistribution wiring layers and a plurality of insulating layers, wherein the redistribution wiring is embedded in the insulating layers and is electrically connected to the via 116, the via 126a, and the via 126b. The rewiring of the front rewiring layer 140 can be copper rewiring, and the insulation layer of the front rewiring layer 140 can be polyimide (PI), PBO, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or a combination thereof.

[0034] Because the warpage of the encapsulated structure is minimized, the risk of defects in the redistributed wiring layer 140 caused by depressions formed in the insulating encapsulation 130 is reduced.

[0035] refer to Figure 1C The system provides at least one semiconductor die 150 with bumps 152 formed thereon and a memory device 160 with bumps 162. The semiconductor die 150 and the memory device 160 are mounted on a redistribution layer 140 and electrically connected to the redistribution layer 140 via bumps 152 and bumps 162, respectively. In some embodiments, the semiconductor die 150 may be a system-on-chip (SoC) die, and the memory device 160 may be a high-bandwidth memory (HBM) cube including stacked memory dies. Figure 1B The warpage of the resulting structure is minimized, thus improving the yield of the bump connector between the redistribution layer 140 and the semiconductor die 150, as well as the yield of the bump connector between the redistribution layer 140 and the memory device 160.

[0036] refer to Figure 1D An insulating encapsulation 170 is formed on the redistribution layer 140 to cover the semiconductor die 150 and the memory device 160. The insulating encapsulation 170 can be formed by an overlay molding process or a film deposition process, and the material of the insulating encapsulation 170 may include a molding compound, an underfill material, a molded underfill material, or other suitable dielectric material. For example, the molding compound includes epoxy resin. In some embodiments, the material of the insulating encapsulation 170 is the same as the material of the insulating encapsulation 130. In some alternative embodiments, the material of the insulating encapsulation 170 is different from the material of the insulating encapsulation 130. The thickness of the insulating encapsulation 130 may be less than the thickness of the insulating encapsulation 170. For example, the thickness of the insulating encapsulation 170 is in the range of about 100 micrometers to about 1000 micrometers, and the thickness of the semiconductor die 150 and the memory device 160 is in the range of about 50 micrometers to about 800 micrometers.

[0037] refer to Figure 1D and Figure 1E ,Will Figure 1D The structure described herein is inverted and mounted onto another carrier C2, such that the insulating encapsulation 170 is bonded to the carrier C2. A stripping process is performed to peel the carrier C1 from the semiconductor die 110, the interposer die 120a, the interposer die 120b, and the insulating encapsulation 130. After the stripping process, the semiconductor substrate 112 of the semiconductor die 110, the semiconductor substrate 122a of the interposer die 120a, and the semiconductor substrate 122b of the interposer die 120b are exposed.

[0038] refer to Figure 1E and Figure 1FA thinning process is performed to remove a portion of semiconductor substrate 122a, semiconductor substrate 122b, semiconductor substrate 112, and insulating encapsulation 130 until vias 126a and 126b, dielectric layer 124a, and dielectric layer 124b are exposed. In some embodiments, the thinning process includes mechanical polishing, chemical mechanical polishing (CMP), or combinations thereof. After the thinning process, a semiconductor die 110', dielectric interposer 120a', dielectric interposer 120b', and insulating encapsulation 130' with reduced thickness are formed, wherein the insulating encapsulation 130' laterally encapsulates the semiconductor die 110', dielectric interposer 120a', and dielectric interposer 120b'. The semiconductor die 110' may each include a semiconductor substrate 112', an interconnect structure 114, a via 116, and a protective layer 118. Semiconductor die 110' may each include an active surface 111 and a rear surface 113' opposite to the active surface 111. Dielectric interposer 120a' may include a dielectric layer 124a and a via 126a penetrating the dielectric layer 124a. Dielectric interposer 120b' may each include a dielectric layer 124b and a via 126b penetrating the dielectric layer 124b. The thicknesses of semiconductor die 110', dielectric interposer 120a', dielectric interposer 120b', and insulating encapsulator 130' may be substantially the same and range from about 15 micrometers to about 100 micrometers. Furthermore, the thickness of semiconductor substrate 112' in semiconductor die 110' may range from about 5 micrometers to about 90 micrometers.

[0039] like Figure 1F As explained, the through-hole 126a of dielectric interlayer 120a' is spaced apart from the insulating encapsulation 130' through dielectric layer 124a, and the through-hole 126b of dielectric interlayer 120b' is spaced apart from the insulating encapsulation 130' through dielectric layer 124b. In other words, the through-hole 126a of dielectric interlayer 120a' and the through-hole 126b of dielectric interlayer 120b' do not contact the insulating encapsulation 130'.

[0040] refer to Figure 1F and Figure 1GA rear redistribution layer 180 can be formed to cover the rear surface 113' of the semiconductor die 110', the exposed surfaces of the dielectric interposer 120a', the dielectric interposer 120b', and the insulating encapsulation 130'. The rear redistribution layer 180 can be formed on the exposed surfaces of the insulating encapsulation 130', the semiconductor substrate 112', the dielectric layer 124a, the via 126a, the dielectric layer 124b, and the via 126b. The rear redistribution layer 180 may include a plurality of alternately stacked redistribution wiring layers and a plurality of insulating layers, wherein the redistribution wiring is embedded in the insulating layers and is electrically connected to the vias 126a and 126b. The rewiring of the rear rewiring layer 180 can be copper rewiring, and the insulation layer of the rear rewiring layer 180 can be polyimide (PI), PBO, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or a combination thereof.

[0041] In some embodiments, the semiconductor die 110' is electrically connected to the redistribution layer 180 via vias 126a and / or 126b of the redistribution layer 120a' and dielectric interposer 120b'. Conductive terminals 190 are formed on the back-side redistribution layer 180. The conductive terminals 190 are electrically connected to redistribution wiring of the back-side redistribution layer 180. The conductive terminals 190 may include solder balls (e.g., lead-free solder balls) arranged in an array. After the redistribution layer 180 and conductive terminals 190 are formed, a reconstructed wafer W is formed on the carrier C2.

[0042] refer to Figures 1G to 1I The monomerization process S (i.e., wafer sawing process) is performed along the cutting path SL, so that the reconstructed wafer W is monomerized into multiple package structures P1.

[0043] like Figure 1I As described herein, the package structure P1 may include at least one semiconductor die 110', at least one dielectric interposer 120a', and an insulating encapsulator 130'. The package structure P1 may also include a dielectric interposer 120b'. Figure 1IThe document describes two semiconductor dies 110', one dielectric interposer 120a', and two dielectric interposers 120b'; however, the number of semiconductor dies 110' and interposers 120a' and 120b' is not limited in this invention. Each semiconductor die 110' includes a semiconductor substrate 112', an interconnect structure 114 disposed on the semiconductor substrate 112', and a via 116 disposed on the interconnect structure 114. The dielectric interposer 120a' includes a dielectric layer 124a and a through-hole 126a penetrating the dielectric layer 124a. An insulating encapsulator 130' laterally encapsulates the semiconductor die 110' and the interposers, wherein the thickness of the dielectric layer 124a of the dielectric interposer 120a' is substantially equal to the thickness of the semiconductor die 110' and the thickness of the insulating encapsulator 130'.

[0044] The semiconductor die 110' may also include a protective layer 118 disposed on the interconnect structure 114 and laterally enclosing the via 116. The dielectric interposer 120a' may be spaced apart from the semiconductor die 110' by the insulating encapsulator 130'. The package structure P1 may also include a front redistribution layer 140 disposed on the surface of the insulating encapsulator 130' (e.g., the upper surface), the active surface 111 of the semiconductor die 110', and the surfaces of the dielectric interposers 120a' and 120b' (e.g., the upper surface), wherein the front redistribution layer 140 is electrically connected to the via 116 of the semiconductor die 110', the through-hole 126a of the dielectric interposer 120a', and the through-hole 126b of the dielectric interposer 120b'. In some embodiments, the package structure P1 may further include a rear redistribution layer 180 disposed on the other surface (e.g., the lower surface) of the insulating encapsulator 130', the rear surface 113' of the semiconductor die 110', and the other surface (e.g., the lower surface) of the dielectric interposers 120a' and 120b', wherein the rear redistribution layer 180 is electrically connected to the front redistribution layer 140 via through-holes 126a and 126b of the dielectric interposers 120a' and 120b'.

[0045] In some embodiments, the package structure P1 further includes a semiconductor die 150 and an insulating encapsulator 170. The semiconductor die 150 is disposed on and electrically connected to the front redistribution layer 140, and the insulating encapsulator 170 is disposed on the front redistribution layer 140 and laterally encapsulates the semiconductor die 150. Additionally, the package structure P1 may also include a memory device 160 laterally encapsulated by the insulating encapsulator 170.

[0046] Figure 2 This is a top view schematically illustrating a packaging structure according to some embodiments of the present disclosure.

[0047] refer to Figure 1I and Figure 2 In package structure P1, semiconductor die 150 and memory device 160 are stacked on top of semiconductor die 110', dielectric interposer 120a', and dielectric interposer 120b', which are encapsulated by insulating encapsulator 130'. When viewed from above, semiconductor die 110', dielectric interposer 120a', and dielectric interposer 120b' are arranged within a rectangular area surrounded by insulating encapsulator 130'. When viewed from above, semiconductor die 110' overlaps with semiconductor die 150 and memory device 160, dielectric interposer 120a' overlaps only with semiconductor die 150, and dielectric interposer 120b' overlaps only with memory device 160. When viewed from above, memory device 160 overlaps with semiconductor die 110' and dielectric interposer 120b', and semiconductor die 150 overlaps with semiconductor die 110' and dielectric interposer 120a'.

[0048] Figures 3 to 5 This is a cross-sectional view schematically illustrating the packaging structure according to various embodiments of the present disclosure.

[0049] refer to Figure 1I and Figure 3 , Figure 3 The packaging structure P2 described herein is... Figure 1I Similar to the packaging structure P1 described herein, but packaging structure P2 further includes an underfill adhesive 165 that laterally encapsulates the semiconductor die 150 and memory device 160, wherein the semiconductor die 150 and memory device 160 are spaced apart from the insulating encapsulator 130' by the underfill adhesive 165. The underfill adhesive 165 can serve as a stress buffer for bumps 152 and bumps 162, thereby improving the reliability of the bump connectors.

[0050] refer to Figure 4 , Figure 4 The packaging structure P3 described herein is... Figure 1I The package structure P1 described herein is similar, but the semiconductor die 110' in the package structure P3 also includes a semiconductor via 119 that penetrates through the semiconductor substrate 112', and the semiconductor via 119 is electrically connected to the interconnect structure 114.

[0051] refer to Figure 5 , Figure 5 The packaging structure P4 described herein is... Figure 1ISimilar to the packaging structure P1 described herein, but packaging structure P4 also includes at least one passive device 200 embedded in the insulating enclosure 130', wherein the thickness of the passive device 200 is substantially equal to the thickness of dielectric layers 124a and 124b of dielectric interposers 120a' and 120b'. Furthermore, packaging structure P4 includes an insulating layer 142 and bumps 144 partially embedded in the insulating layer 142, wherein bumps 144 are electrically connected to bumps 152 and 162.

[0052] Figure 6 and Figure 7 This is a top view schematically illustrating the packaging structure according to various embodiments of the present disclosure.

[0053] refer to Figure 5 and Figure 6 In a package structure P4 according to one embodiment, a passive device 200 and two dielectric interposers 120a' are used, with the passive device 200 disposed between the two dielectric interposers 120a'. A semiconductor die 150 and a memory device 160 are stacked on top of the passive device 200, semiconductor die 110', dielectric interposers 120a' and 120b', which are encapsulated by an insulating encapsulator 130'. When viewed from above, the passive device 200, semiconductor die 110', dielectric interposers 120a' and 120b' are arranged within a rectangular area surrounded by the insulating encapsulator 130'. When viewed from above, passive device 200 overlaps only with semiconductor die 150, semiconductor die 110' overlaps with semiconductor die 150 and memory device 160, dielectric interlayer 120a' overlaps only with semiconductor die 150, and dielectric interlayer 120b' overlaps only with memory device 160. When viewed from above, memory device 160 overlaps with semiconductor die 110' and dielectric interlayer 120b', and semiconductor die 150 overlaps with passive device 200, semiconductor die 110' and dielectric interlayer 120a'.

[0054] refer to Figure 5 and Figure 7In a package structure P4 according to another embodiment, two passive devices 200 and four semiconductor dies 110' are used, with each of the passive devices 200 disposed between two adjacent semiconductor dies 110'. Semiconductor dies 150 and memory devices 160 are stacked on top of the passive devices 200, semiconductor dies 110', dielectric interposers 120a' and 120b' encapsulated by an insulating encapsulator 130'. When viewed from above, the passive devices 200, semiconductor dies 110', dielectric interposers 120a' and 120b' are arranged within a rectangular area surrounded by the insulating encapsulator 130'. When viewed from above, passive device 200 overlaps only with semiconductor die 150, semiconductor die 110' overlaps with semiconductor die 150 and memory device 160, dielectric interlayer 120a' overlaps only with semiconductor die 150, and dielectric interlayer 120b' overlaps only with memory device 160. When viewed from above, memory device 160 overlaps with semiconductor die 110' and dielectric interlayer 120b', and semiconductor die 150 overlaps with passive device 200, semiconductor die 110' and dielectric interlayer 120a'.

[0055] Combination Figures 8A to 8I The fabrication of passive device 200 is described.

[0056] Figures 8A to 8I This is a cross-sectional view schematically illustrating a process flow for fabricating passive devices according to some alternative embodiments of the present disclosure.

[0057] refer to Figure 8A A semiconductor substrate 202 is provided, and a conductor 204 is formed on the semiconductor substrate 202, for example, via a plating process. In some embodiments, a seed layer is formed on the semiconductor substrate 202 via a sputtering process; a patterned photoresist layer is formed on the seed layer and a plating process is performed to form the conductor 204 on the seed layer; the patterned photoresist layer is removed; and the seed layer not covered by the conductor 204 is removed via an etching process until the semiconductor substrate 202 is exposed.

[0058] After conductor 204 is formed, a dielectric layer 206 is formed on semiconductor substrate 202 to laterally encapsulate conductor 240. In some embodiments, a dielectric material is deposited on semiconductor substrate 202 to cover conductor 204, and then a CMP process is performed to remove portions of the dielectric material until the top surface of conductor 204 is exposed, thereby forming dielectric layer 206 on semiconductor substrate 202. The top surface of conductor 204 may be substantially flush with the top surface of dielectric layer 206. Semiconductor substrate 202 may be a bare silicon substrate and no active components (e.g., transistors, etc.) or passive components (e.g., resistors, capacitors, inductors, etc.) are formed in semiconductor substrate 202. Conductor 204 may be a copper pillar or other suitable metal pillar, and dielectric layer 206 may be a polyimide (PI) layer, a PBO layer, or a dielectric layer formed by other suitable organic dielectric materials.

[0059] refer to Figure 8B A bottom electrode 208 is formed on conductor 204 and dielectric layer 206 via a plating process. In some embodiments, a seed layer 208a is formed on conductor 204 and dielectric layer 206 via a sputtering process; a patterned photoresist layer is formed on seed layer 208a and a plating process is performed to form electrode layer 208b on seed layer 208a; the patterned photoresist layer is removed; and the seed layer 208a not covered by electrode layer 208b is removed via an etching process until dielectric layer 206 is exposed.

[0060] refer to Figure 8C and Figure 8D A dielectric layer 210 and an upper electrode material layer 212 are formed to cover the dielectric layer 206 and the bottom electrode 208. In some embodiments, the dielectric layer 210 and the upper electrode material layer 212 are conformally formed on the dielectric layer 206 and the bottom electrode 208. The material of the dielectric layer 210 may be silicon oxide, silicon nitride, etc., and the material of the upper electrode material layer 212 may be a sputtered Ti / Cu layer or other suitable metal layer.

[0061] refer to Figure 8D and Figure 8E A patterned photoresist layer PR1 is formed on the upper electrode material layer 212, and an etching process is performed to remove a portion of the upper electrode material layer 212 until the dielectric layer 210 is exposed, thereby forming an upper electrode 212' on the dielectric layer 210. Then, the patterned photoresist layer PR1 is removed from the upper electrode 212'.

[0062] refer to Figure 8E and Figure 8FA patterned photoresist layer PR2 is formed on the portion of the upper electrode 212' and dielectric layer 210 not covered by the upper electrode 212'. An etching process is performed to remove some portions of the dielectric layer 210 until the portions of the dielectric layer 206 not covered by the patterned photoresist layer PR2 and the portions of the bottom electrode 208 not covered by the patterned photoresist layer PR2 are exposed. After removing the portions of the dielectric layer 210 not covered by the patterned photoresist layer PR2, a patterned dielectric layer 210' is formed. Then, the patterned photoresist layer PR2 is removed.

[0063] refer to Figure 8G and Figure 8H A seed layer 214 is formed by sputtering to cover the dielectric layer 206, the bottom electrode 208, the patterned dielectric layer 210', and the upper electrode 212'. A patterned photoresist layer is formed on the seed layer 214, and a plating process is performed to form a conductor 216 including conductors 216a and 216b on the seed layer 214. The patterned photoresist layer is removed, and the seed layer 214 not covered by conductors 216a and 216b is removed by etching, thereby forming a patterned seed layer 214'.

[0064] refer to Figure 8H and Figure 8I After forming the patterned seed layer 214' and conductors 216a and 216b, a dielectric layer 218 is formed to laterally encapsulate the dielectric layer 206, bottom electrode 208, patterned dielectric layer 210', top electrode 212', and conductors 216a and 216b. In some embodiments, dielectric material is deposited to cover the dielectric layer 206, bottom electrode 208, patterned dielectric layer 210', top electrode 212', and conductors 216a and 216b, and then a CMP process is performed to remove portions of the dielectric material until the top surfaces of conductors 216a and 216b are exposed. The top surfaces of conductors 216a and 216b may be substantially flush with the top surface of the dielectric layer 218. Conductors 216a and 216b may be copper pillars or other suitable metal pillars, and dielectric layer 218 may be a polyimide (PI) layer, a PBO layer, or a dielectric layer formed by other suitable organic dielectric materials.

[0065] After forming the dielectric layer 218, a metal-insulator-metal (MIM) type passive device 200 is fabricated. However, the invention is not limited thereto. Other types of passive devices (e.g., fin-type passive devices or trench-type passive devices) can be used. Figures 1A to 1I The process described herein and Figures 2 to 7 The structure described herein.

[0066] like Figure 5 and Figure 8I As described, the passive device 200 included in the package structure P4 may include a semiconductor substrate 202, a conductor 204, a dielectric layer 206, a bottom electrode 208, a patterned dielectric layer 210', a top electrode 212', a patterned seed layer 214', conductors 216a and 216b, and a dielectric layer 218, wherein conductors 216a and 216b are in contact with and electrically connected to the front redistribution layer 140. In some other embodiments, the passive device 200 included in the package structure P4 does not include the semiconductor substrate 202, wherein conductor 204 is in contact with and electrically connected to the rear redistribution layer 180, and conductors 216a and 216b are in contact with and electrically connected to the front redistribution layer 140.

[0067] According to some embodiments of this disclosure, a package structure including a first semiconductor die, an interposer, and a first insulating encapsulator is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and vias disposed on the interconnect structure. The interposer includes a dielectric layer and vias penetrating the dielectric layer. The first insulating encapsulator laterally encapsulates the first semiconductor die and the interposer, wherein the thickness of the dielectric layer of the interposer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. In some embodiments, the first semiconductor die further includes a protective layer disposed on the interconnect structure and laterally encapsulating the vias. In some embodiments, the first semiconductor die further includes semiconductor vias penetrating the semiconductor substrate, and the semiconductor vias are electrically connected to the interconnect structure. In some embodiments, the interposer is spaced apart from the first semiconductor die by the first insulating encapsulator. In some embodiments, the packaging structure further includes: a first redistribution layer disposed on a first surface of the first insulating encapsulation, an active surface of the first semiconductor die, and a first surface of the interposer, wherein the first redistribution layer is electrically connected to the vias of the first semiconductor die and the through-holes of the interposer. In some embodiments, the packaging structure further includes: a second redistribution layer disposed on a second surface of the first insulating encapsulation, a rear surface of the first semiconductor die, and a second surface of the interposer, wherein the second redistribution layer is electrically connected to the first redistribution layer through the through-holes of the interposer. In some embodiments, the packaging structure further includes a second semiconductor die and a second insulating encapsulation. The second semiconductor die is disposed on and electrically connected to the first redistribution layer, and the second insulating encapsulation is disposed on the first redistribution layer to laterally encapsulate the second semiconductor die. In some embodiments, the packaging structure further includes a passive device embedded in the first insulating encapsulation, wherein the thickness of the passive device is substantially equal to the thickness of the dielectric layer of the interposer.

[0068] According to some other embodiments of this disclosure, a package structure is provided including a first semiconductor die, a first dielectric layer, a first insulating encapsulator, a first redistribution layer, and a second redistribution layer. Each of the first semiconductor dies includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a via disposed on the interconnect structure. The first dielectric layer includes a dielectric layer and a through-hole penetrating the dielectric layer, wherein the first semiconductor die and the first dielectric layer are arranged side-by-side. The first insulating encapsulator laterally encapsulates the first semiconductor die and the first dielectric layer, wherein the through-hole is spaced apart from the first insulating encapsulator through the dielectric layer, and the thickness of the dielectric layer of the first dielectric layer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. The first redistribution layer is disposed on a first surface of the first insulating encapsulator, an active surface of the first semiconductor die, and a first surface of the first dielectric layer. The second redistribution layer is disposed on the second surface of the first insulating encapsulation, the rear surface of the first semiconductor die, and the second surface of the first dielectric interposer, wherein the first semiconductor die is electrically connected to the second redistribution layer through the through-holes of the first redistribution layer and the first dielectric interposer. In some embodiments, each of the first semiconductor dies further includes a protective layer disposed on the interconnect structure and laterally encapsulating the via. In some embodiments, each of the first semiconductor dies further includes a semiconductor via penetrating the semiconductor substrate, and the semiconductor via is electrically connected to the interconnect structure. In some embodiments, the first dielectric interposer is disposed between the first semiconductor dies. In some embodiments, the first dielectric interposer is spaced apart from the first semiconductor die by the first insulating encapsulation. In some embodiments, the package structure further includes at least one second dielectric interposer, wherein the first dielectric interposer is spaced apart from the at least one of the first semiconductor dies by at least one of the first semiconductor dies. In some embodiments, the package structure further includes a second semiconductor die, a memory device, and a second insulating encapsulation. The second semiconductor die is disposed on the first redistribution layer and electrically connected to the first redistribution layer. The memory device is disposed on and electrically connected to the first redistribution layer. A second insulating encapsulation is disposed on the first redistribution layer, wherein the second insulating encapsulation laterally encapsulates the second semiconductor die and the memory device. In some embodiments, the package structure further includes a passive device embedded in the first insulating encapsulation, wherein the passive device, the first semiconductor die, and the first dielectric interposer are arranged side-by-side, and the thickness of the passive device is substantially equal to the thickness of the dielectric layer of the first dielectric interposer.

[0069] According to some other embodiments of this disclosure, a method for fabricating a package structure including the following steps is provided. A first semiconductor die is provided, the first semiconductor die including a first semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, and a via disposed on the interconnect structure. An interposer die is provided, the interposer die including a second semiconductor substrate, a dielectric layer disposed on the second semiconductor substrate, and a through-hole penetrating the dielectric layer. The first semiconductor die and the interposer die are laterally encapsulated using an insulating material. A thinning process is performed to remove the insulating material, the second semiconductor substrate, and a portion of the first semiconductor substrate, such that a dielectric interposer encapsulated by a first insulating encapsulator is formed, wherein the dielectric interposer includes the dielectric layer and the through-hole, and the thickness of the dielectric layer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. In some embodiments, the method further includes: forming a first redistribution layer on the surface of the insulating material, the active surface of the first semiconductor die, and the surface of the dielectric die before performing the thinning process; mounting a second semiconductor die on the first redistribution layer, wherein the second semiconductor die is electrically connected to the first redistribution layer; and encapsulating the second semiconductor die using a second insulating encapsulator. In some embodiments, the second semiconductor die is mounted on the first redistribution layer via a bump connector. In some embodiments, the method further includes: forming a second redistribution layer on the surface of the first insulating encapsulator, the rear surface of the first semiconductor die, and the surface of the dielectric interposer after performing the thinning process.

[0070] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A packaging structure, characterized in that, include: A first semiconductor die includes a semiconductor substrate, a semiconductor via penetrating the semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a via disposed on the interconnect structure, and a protective layer disposed on the interconnect structure and laterally enclosing the entire sidewall of the via, wherein the semiconductor via is electrically connected to the interconnect structure, and wherein the top surface of the via is exposed from the protective layer. The first interposer includes a dielectric layer and a via penetrating the dielectric layer; A first insulating encapsulation laterally encapsulates the first semiconductor die and the first interposer, wherein the thickness of the dielectric layer of the first interposer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulation. A first redistribution layer is disposed on a first surface of the first insulating encapsulation, an active surface of the first semiconductor die, and a first surface of the first interposer, wherein the first redistribution layer is electrically connected to the via of the first semiconductor die and the through-hole of the first interposer. The second semiconductor die is disposed on the first redistribution layer and electrically connected to the first redistribution layer. A memory device is disposed on and electrically connected to the first redistribution layer, wherein, when viewed from the top, the first interposer layer overlaps only with the second semiconductor die, and the first semiconductor die overlaps with the second semiconductor die and the memory device.

2. The packaging structure according to claim 1, characterized in that, The first interposer is spaced apart from the first semiconductor die by the first insulating encapsulation.

3. The packaging structure according to claim 1, characterized in that, The top surface of the first interlayer is flush with the top surface of the first insulating encapsulation.

4. The packaging structure according to claim 1, characterized in that, Also includes: The second re-laid circuit layer is disposed on the second surface of the first insulating encapsulation, the rear surface of the first semiconductor die, and the second surface of the first interposer, wherein the second re-laid circuit layer is electrically connected to the first re-laid circuit layer through the through-hole of the first interposer.

5. The packaging structure according to claim 1, characterized in that, Also includes: The second interposer includes a dielectric layer and a via penetrating the dielectric layer, wherein the first insulating encapsulator laterally encapsulates the first semiconductor die, the first interposer, and the second interposer; and the second insulating encapsulator is disposed on the first redistribution layer and laterally encapsulates the second semiconductor die and the memory device, wherein when viewed from the top, the second interposer overlaps only with the memory device.

6. The packaging structure according to claim 1, characterized in that, It also includes passive devices embedded in the first insulating encapsulation. The passive device includes a second semiconductor substrate, a bottom electrode disposed on the second semiconductor substrate, a patterned dielectric layer disposed on the bottom electrode, a top electrode disposed on the patterned dielectric layer, a conductor disposed on the top electrode, and a second dielectric layer that laterally encloses the entire sidewall of the conductor. The top surface of the conductor is exposed from the second dielectric layer, and the thickness of the passive device is substantially equal to the thickness of the dielectric layer of the first interposer. The passive device therein overlaps only with the second semiconductor die.

7. A packaging structure, characterized in that, include: Each of the first semiconductor dies includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a via disposed on the interconnect structure, and a protective layer disposed on the interconnect structure and laterally enclosing the entire sidewall of the via, wherein the top surface of the via is exposed from the protective layer. The first dielectric interlayer includes a dielectric layer and a via penetrating the dielectric layer, wherein the first semiconductor die is arranged side by side with the first dielectric interlayer; A first insulating encapsulation laterally encapsulates the first semiconductor die and the first dielectric interlayer, wherein the through-hole is spaced apart from the first insulating encapsulation by the dielectric layer, and the thickness of the dielectric layer of the first dielectric interlayer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulation. The first redistribution layer is disposed on the first surface of the first insulating encapsulation, the active surface of the first semiconductor die, and the first surface of the first dielectric interlayer, wherein the top surface of the via is in contact with the first redistribution layer. The second redistribution layer is disposed on the second surface of the first insulating encapsulation, the rear surface of the first semiconductor die, and the second surface of the first dielectric interlayer, wherein the first semiconductor die is electrically connected to the second redistribution layer through the through-holes in the first redistribution layer and the first dielectric interlayer. A second semiconductor die, disposed on and electrically connected to the first redistribution layer; and A memory device is disposed on and electrically connected to the first redistribution layer, wherein, when viewed from the top, the first dielectric interlayer overlaps only with the second semiconductor die, and the first semiconductor die overlaps with the second semiconductor die and the memory device.

8. The packaging structure according to claim 7, characterized in that, Each of the first semiconductor dies further includes a semiconductor via penetrating the semiconductor substrate, and the semiconductor via is electrically connected to the interconnect structure.

9. The packaging structure according to claim 7, characterized in that, The first dielectric interlayer is disposed between the first semiconductor dies.

10. The packaging structure according to claim 7, characterized in that, The first dielectric interlayer is spaced apart from the first semiconductor die by the first insulating encapsulation.

11. The packaging structure according to claim 7, characterized in that, It also includes at least one second dielectric interposer, wherein the first dielectric interposer is spaced apart from the at least one of the first semiconductor dies, wherein, when viewed from above, the at least one second dielectric interposer overlaps only with the memory device.

12. The packaging structure according to claim 7, characterized in that, Also includes: A second insulating encapsulation is disposed on the first redistribution layer, wherein the second insulating encapsulation laterally encapsulates the second semiconductor die and the memory device.

13. The packaging structure according to claim 7, characterized in that, It also includes passive devices embedded in the first insulating encapsulation. The passive device, the first semiconductor die, and the first dielectric layer are arranged side by side. The passive device includes a second semiconductor substrate, a bottom electrode disposed on the second semiconductor substrate, a patterned dielectric layer disposed on the bottom electrode, a top electrode disposed on the patterned dielectric layer, a conductor disposed on the top electrode, and a second dielectric layer that laterally encloses the entire sidewall of the conductor. The top surface of the conductor is exposed from the second dielectric layer, and the thickness of the passive device is substantially equal to the thickness of the dielectric layer of the first dielectric interposer. The passive device therein overlaps only with the second semiconductor die.

14. A method for manufacturing an encapsulation structure, characterized in that, include: A first semiconductor die is provided, the first semiconductor die including a first semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, a via disposed on the interconnect structure, and a protective layer disposed on the interconnect structure and laterally enclosing the entire sidewall of the via, wherein the top surface of the via is exposed from the protective layer; An interposer die is provided, the interposer die comprising a second semiconductor substrate, a dielectric layer disposed on the second semiconductor substrate, and a via penetrating the dielectric layer; The first semiconductor die and the interposer die are laterally encapsulated using an insulating material. A first redistribution layer is formed on the surface of the insulating material, the active surface of the first semiconductor die, and the surface of the interposer die. A second semiconductor die and a memory device are mounted on the first redistribution layer, wherein the second semiconductor die and the memory device are electrically connected to the first redistribution layer. as well as A thinning process is performed to remove the insulating material, the second semiconductor substrate, and a portion of the first semiconductor substrate, thereby forming a dielectric interposer encapsulated by a first insulating encapsulator. The dielectric interposer includes the dielectric layer and the vias, and the thickness of the dielectric layer is substantially equal to the thickness of the first semiconductor die and the thickness of the first insulating encapsulator. When viewed from the top, the dielectric interposer overlaps only with the second semiconductor die, and the first semiconductor die overlaps with the second semiconductor die and the memory device.

15. The method according to claim 14, characterized in that, Also includes: The second semiconductor die is encapsulated using a second insulating encapsulator.

16. The method according to claim 15, characterized in that, The second semiconductor die is mounted on the first redistribution layer via a bump connector.

17. The method according to claim 14, characterized in that, Also includes: After the thinning process is performed, a second redistribution layer is formed on the surface of the first insulating encapsulation, the rear surface of the first semiconductor die, and the surface of the dielectric interlayer.

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