Semiconductor device and imaging device

Abstract

A semiconductor device according to the present disclosure includes a plurality of substrates (100A, 200A) stacked; a semiconductor element (TR, AMP) formed in at least one of the plurality of substrates (100A, 200A); and a protective layer element (TF, TS) formed in at least one of the plurality of substrates (100A, 200A) to have a PN junction and to protect the semiconductor element (TR, AMP).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and an imaging device. Background Technology

[0002] There are three-dimensional packaging technologies for stacking multiple semiconductor substrates. For example, in imaging devices, it is known to stack a first semiconductor substrate in which pixel regions are formed and a second semiconductor substrate in which logic circuits are formed (see, for example, Patent Document 1).

[0003] List of cited references

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-245506 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In the aforementioned imaging apparatus, sufficient space for configuring pixel transistors cannot be guaranteed. Therefore, for example, it is conceivable to further divide and stack the substrate in which the photoelectric conversion element is formed and the substrate in which the pixel transistor is formed.

[0008] However, in this configuration, for example, when the number of photoelectric conversion elements differs from the number of pixel transistors, the required area of ​​each substrate may differ. When multiple substrates are stacked, it is necessary to ensure that each substrate has the same area. Therefore, there is a problem that the chip area of ​​the device increases with the substrate having a larger required area.

[0009] Therefore, this disclosure proposes a semiconductor device and an imaging device capable of suppressing the increase of chip area.

[0010] Solution to the problem

[0011] The semiconductor device according to this disclosure includes a plurality of stacked substrates; a semiconductor element formed in at least one of the plurality of substrates; and a protective element formed in at least one of the plurality of substrates having a PN junction and protecting the semiconductor element. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example of the functional configuration of an imaging apparatus according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 The diagram shows a schematic plan view of the imaging device.

[0014] Figure 3 It shows along Figure 2 The diagram shows the cross-section formed by the section cut by line III-III'.

[0015] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0016] Figure 5 This is a diagram illustrating an example of the connection pattern of multiple pixel-shared units and multiple vertical signal lines.

[0017] Figure 6 It is shown Figure 3 A schematic cross-sectional view of an example of the specific configuration of the imaging device shown.

[0018] Figure 7A It is shown Figure 6 A schematic diagram illustrating an example of the planar configuration of the main portion of the first substrate.

[0019] Figure 7B It shows the pad area together with Figure 7A A schematic diagram of the planar configuration of the main part of the first substrate shown.

[0020] Figure 8 It is shown Figure 6 A schematic diagram of an example of the planar configuration of the second substrate (semiconductor layer).

[0021] Figure 9 This shows the main parts of the pixel circuit and the first substrate together. Figure 6 A schematic diagram of an example of the planar configuration of the first wiring layer is shown.

[0022] Figure 10 It is shown Figure 6 The diagram shows an example of the planar configuration of the first wiring layer and the second wiring layer.

[0023] Figure 11 It is shown Figure 6 A schematic diagram illustrating an example of the planar configuration of the second and third wiring layers.

[0024] Figure 12 It is shown Figure 6 The diagram shows an example of the planar configuration of the third and fourth wiring layers.

[0025] Figure 13 It is used to explain Figure 3 A schematic diagram of the input signal path of the imaging device shown.

[0026] Figure 14 It is used for explanation Figure 3 A schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0027] Figure 15 It is shown Figure 8 A schematic diagram of a modified example of the planar configuration of the second substrate (semiconductor layer) shown.

[0028] Figure 16 This shows the main part of the first wiring layer and the first substrate together. Figure 15 The diagram shows a planar configuration of the pixel circuit.

[0029] Figure 17 This shows the second wiring layer together with Figure 16 A schematic diagram of an example of the planar configuration of the first wiring layer is shown.

[0030] Figure 18 This shows the third wiring layer together with Figure 17 A schematic diagram illustrating an example of the planar configuration of the second wiring layer.

[0031] Figure 19 This shows the fourth wiring layer together with Figure 18 A schematic diagram illustrating an example of the planar configuration of the third wiring layer.

[0032] Figure 20 It is shown Figure 7A A schematic diagram of a modified example of the planar configuration of the first substrate shown.

[0033] Figure 21 It shows the layering on Figure 20 A schematic diagram illustrating an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate.

[0034] Figure 22 It is shown Figure 21 The diagram shows an example of a pixel circuit and a planar first wiring layer.

[0035] Figure 23 This shows the second wiring layer together with Figure 22 A schematic diagram of an example of the planar configuration of the first wiring layer is shown.

[0036] Figure 24 This shows the third wiring layer together with Figure 23 A schematic diagram illustrating an example of the planar configuration of the second wiring layer.

[0037] Figure 25 This shows the fourth wiring layer together with Figure 24 A schematic diagram illustrating an example of the planar configuration of the third wiring layer.

[0038] Figure 26 It is shown Figure 20 A schematic diagram of another example of the planar configuration of the first substrate shown.

[0039] Figure 27 It shows the layering on Figure 26 A schematic diagram illustrating an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate.

[0040] Figure 28 This shows the first wiring layer together with Figure 27 The diagram shows an example of a planar configuration of a pixel circuit.

[0041] Figure 29 This shows the second wiring layer together with Figure 28 A schematic diagram of an example of the planar configuration of the first wiring layer is shown.

[0042] Figure 30 This shows the third wiring layer together with Figure 29 A schematic diagram illustrating an example of the planar configuration of the second wiring layer.

[0043] Figure 31 This shows the fourth wiring layer together with Figure 30 A schematic diagram illustrating an example of the planar configuration of the third wiring layer.

[0044] Figure 32 It is shown Figure 3 Schematic cross-sectional view of other examples of the imaging apparatus shown.

[0045] Figure 33 It is used to explain Figure 32 A schematic diagram of the input signal path of the imaging device shown.

[0046] Figure 34 It is used for explanation Figure 32 A schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0047] Figure 35 It is shown Figure 6 Schematic cross-sectional view of other examples of the imaging apparatus shown.

[0048] Figure 36 It is shown Figure 4 Figures of other examples of the equivalent circuit shown.

[0049] Figure 37 It is shown Figure 7A Schematic plan view of other examples of pixel separation sections, etc.

[0050] Figure 38 This is a cross-sectional view in the thickness direction showing a configuration example of an imaging device according to a first embodiment of the present disclosure, variant 8.

[0051] Figure 39This is a cross-sectional view (part 1) in the thickness direction showing a configuration example of an imaging device according to a first embodiment of the present disclosure, variant 8.

[0052] Figure 40 This is a cross-sectional view (part 2) in the thickness direction showing a configuration example of an imaging device according to a first embodiment of the present disclosure, variant 8.

[0053] Figure 41 This is a horizontal cross-sectional view (part 1) showing an example of the layout of a plurality of pixel units according to a first embodiment of the present disclosure, variation 8.

[0054] Figure 42 This is a horizontal cross-sectional view (part 2) showing an example of the layout of a plurality of pixel units according to a first embodiment of the present disclosure.

[0055] Figure 43 This is a horizontal cross-sectional view (part 3) showing an example of the layout of a plurality of pixel units according to a first embodiment of the present disclosure.

[0056] Figure 44 This is a diagram illustrating an example of the circuit configuration of an imaging apparatus according to a second embodiment of the present disclosure.

[0057] Figure 45 This is a schematic longitudinal section view of the imaging device.

[0058] Figure 46 This is a diagram illustrating a schematic structural example of the first substrate.

[0059] Figure 47 This is a diagram illustrating a schematic structural example of the second substrate.

[0060] Figure 48 This is a diagram illustrating an example of the cross-sectional structure of an imaging device.

[0061] Figure 49 This is a diagram illustrating an example of the planar configuration of the first substrate and the second substrate.

[0062] Figure 50 This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0063] Figure 51 This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0064] Figure 52 This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0065] Figure 53This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0066] Figure 54 This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0067] Figure 55 This is a flowchart illustrating an example of the manufacturing process of an imaging apparatus according to a second embodiment of the present disclosure.

[0068] Figure 56 This is a diagram showing the imaging apparatus according to the comparative example.

[0069] Figure 57 This is a diagram showing the imaging apparatus according to the comparative example.

[0070] Figure 58 This is a schematic diagram illustrating a variation of a PID protection element.

[0071] Figure 59 This is a schematic diagram illustrating a variation of a PID protection element.

[0072] Figure 60 This is a schematic diagram illustrating a variation of a PID protection element.

[0073] Figure 61 This is a schematic diagram illustrating a variation of a PID protection element.

[0074] Figure 62 This is a schematic diagram illustrating a variation of a PID protection element.

[0075] Figure 63 This is a schematic diagram illustrating a variation of a PID protection element.

[0076] Figure 64 This is a schematic diagram illustrating a variation of a PID protection element.

[0077] Figure 65 This is a schematic diagram illustrating a variation of a PID protection element.

[0078] Figure 66 This is a schematic diagram illustrating a modified example of the imaging device.

[0079] Figure 67 This is a schematic diagram illustrating a modified example of the imaging device.

[0080] Figure 68 This is a diagram used to illustrate an application example of semiconductor memory (DRAM).

[0081] Figure 69This is a diagram used to illustrate application examples of a SoC.

[0082] Figure 70 This is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging apparatus according to an embodiment and its variations.

[0083] Figure 71 It is shown Figure 70 A diagram illustrating an example of the imaging process in an imaging system.

[0084] Figure 72 This is a block diagram illustrating an example of the schematic configuration of a vehicle control system.

[0085] Figure 73 This is an explanatory diagram showing an example of the mounting positions of the vehicle exterior information detection unit and the imaging unit.

[0086] Figure 74 This is a diagram illustrating an example of the schematic configuration of an endoscopic surgical system.

[0087] Figure 75 This is a block diagram illustrating an example of the functional configuration of a camera and a CCU. Detailed Implementation

[0088] The mode used to implement this disclosure will be described in detail below with reference to the accompanying drawings. Note that the description will be given in the following order.

[0089] 1. First embodiment (imaging device with a stacked structure of three substrates)

[0090] 1.1. Functional Composition of Imaging Device 1

[0091] 1.2. Schematic configuration of imaging device 1

[0092] 1.3. Specific Composition of Imaging Device 1

[0093] 1.4. Operation of Imaging Device 1

[0094] 1.5. Effects

[0095] 2. Variations (Variations on the first implementation scheme)

[0096] 2.1. Variation Example 1-1 (Example 1 of planar composition)

[0097] 2.2. Variation Example 1-2 (Example 2 of planar composition)

[0098] 2.3. Variations 1-3 (Example 3 of planar composition)

[0099] 2.4. Variations 1-4 (Examples where the contact portion between substrates is located in the center of the pixel array unit)

[0100] 2.5. Variations 1-5 (including examples of planar transmission transistors)

[0101] 2.6. Variations 1-6 (Examples of one pixel connected to one pixel circuit)

[0102] 2.7. Variations 1-7 (Examples of pixel separation section construction)

[0103] 2.8. Variations 1-8

[0104] 3. Second Implementation Scheme (Imaging Device with PID Protection Element)

[0105] 3.1. Example of the functional configuration of imaging device 1A

[0106] 3.2. Schematic structural example of imaging device 1A

[0107] 3.3. Specific configuration example of imaging device 1A

[0108] 3.4. Example of manufacturing process for imaging device 1A

[0109] 3.5. Comparative Example

[0110] 4. Variations (Variations on the second implementation scheme)

[0111] 4.1. Variation Example 2-1 (Example 1 of PID protection element)

[0112] 4.2. Variation Example 2-2 (Example 2 of PID protection element)

[0113] 4.3. Variation Example 2-3 (Example 3 of PID protection element)

[0114] 4.4. Variation 2-4 (Example of PID protection element disposed in the first and second substrates)

[0115] 4.5. Variations 2-5 (Examples of PID protection elements disposed in the first substrate)

[0116] 5. Application Examples (Application Examples of the Semiconductor Device in the Second Embodiment)

[0117] 6. Applicable Examples

[0118] 6.1. Examples of Application of Imaging Systems

[0119] 6.2. Application Examples of Product Systems

[0120] 6.2.1. Mobile Body Control System

[0121] 6.2.2. Endoscopic surgical system

[0122] <1. First Implementation Plan>

[0123] [1.1. Functional Composition of Imaging Device 1]

[0124] (Functional configuration of imaging device 1)

[0125] Figure 1 This is a block diagram illustrating an example of the functional configuration of an imaging apparatus (imaging apparatus 1) according to an embodiment of the present disclosure.

[0126] Figure 1 The imaging device 1 includes, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0127] In pixel array unit 540, pixels 541 are arranged repeatedly in an array. More specifically, pixel sharing units 539, comprising multiple pixels, form repeating units and are arranged repeatedly in an array in both the row and column directions. Note that, for convenience, in this specification, the row direction may be referred to as the H direction, and the column direction, orthogonal to the row direction, may be referred to as the V direction. Figure 1 In the example, a pixel-sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Pixels 541A, 541B, 541C, and 541D all have photodiodes PD (described later). Figure 6 (As shown in the diagram). Pixel sharing unit 539 shares a pixel circuit (described later). Figure 3 The pixel array unit 540 is a unit of pixel circuit 210. In other words, one pixel circuit (pixel circuit 210 described below) is set for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating the pixel circuit in a time-division manner, the individual pixel signals of pixels 541A, 541B, 541C, and 541D are read out sequentially. Pixels 541A, 541B, 541C, and 541D are configured, for example, in two rows × two columns. In the pixel array unit 540, along with pixels 541A, 541B, 541C, and 541D, a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided. The row drive signal lines 542 drive each of the pixels 541 included in the plurality of pixel sharing units 539 arranged side by side in the row direction in the pixel array unit 540. In the pixel sharing unit 539, each pixel arranged side by side in the row direction is driven. As will be referred to below Figure 4As detailed in the description, the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to a pixel sharing unit 539. The pixel sharing unit 539 is connected to a vertical signal line (column readout line) 543. Pixel signals are read out from the respective pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.

[0128] The row driving unit 520 includes, for example, a row address control unit (in other words, a row decoder unit) that determines the row position for pixel driving, and a row driving circuit unit that generates signals for driving pixels 541A, 541B, 541C, and 541D.

[0129] The column signal processing unit 550 includes, for example, a load circuit unit connected to the vertical signal line 543 and forming a source follower circuit with pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539). The column signal processing unit 550 may have an amplifier circuit unit that amplifies the signal read from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may also have a noise processing unit. In the noise processing unit, for example, as a result of photoelectric conversion, the system noise level is removed from the signal read from the pixel sharing unit 539.

[0130] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the ADC, the signal read from the pixel sharing unit 539, or the aforementioned noise-processed analog signal, is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal used as the comparison object. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that performs control to scan the readout column.

[0131] The timing control unit 530 supplies signals for controlling timing to the row drive unit 520 and the column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.

[0132] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion (in other words, data obtained as an imaging operation in the imaging device 1). The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0133] An example of signal processing performed by the image signal processing unit 560 is tone curve correction processing, which increases grayscale when the imaging data obtained by AD conversion is obtained by imaging a dark subject, and decreases grayscale when it is obtained by imaging a bright subject. In this case, it is desirable to store characteristic data of the tone curve in advance in the data holding unit of the image signal processing unit 560 regarding the tone curve to be corrected based on the grayscale of the imaging data.

[0134] The input unit 510A is used to input, for example, the aforementioned reference clock signal, timing control signal, and characteristic data from outside the device to the imaging device 1. The timing control signal may be, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data may be stored, for example, in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0135] Input terminal 511 is an external terminal for inputting data. Input circuit unit 512 is used to acquire the signal input to input terminal 511 into the imaging device 1. In input amplitude changing unit 513, the amplitude of the signal acquired by input circuit unit 512 is changed to an amplitude that can be easily used inside the imaging device 1. In input data conversion circuit unit 514, the arrangement of the data columns of the input data is changed. Input data conversion circuit unit 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in input unit 510A, input amplitude changing unit 513 and input data conversion circuit unit 514 can be omitted. Power supply unit supplies power to various voltages required inside the imaging device 1 based on the power supplied from the outside to the imaging device 1.

[0136] When the imaging device 1 is connected to an external storage device, the input unit 510A may be equipped with a storage interface circuit for receiving data from the external storage device. Examples of external storage devices include flash memory, SRAM, and DRAM.

[0137] The output unit 510B outputs image data to the outside of the device. The image data includes, for example, image data captured by the imaging device 1 and image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0138] The output data conversion circuit unit 515 is configured, for example, as a parallel-to-serial conversion circuit, and converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude changing unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used in an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit unit 517 drives the wiring connected to the outside of the imaging device 1 at the output terminal 518. At the output terminal 518, data is output from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude changing unit 516 can be omitted.

[0139] When the imaging device 1 is connected to an external storage device, the output unit 510B may be equipped with a storage interface circuit that outputs data to the external storage device. Examples of external storage devices include flash memory, SRAM, and DRAM.

[0140] [1.2. Schematic configuration of imaging device 1]

[0141] Figure 2 and Figure 3 An example of a schematic configuration of imaging device 1 is shown. Imaging device 1 includes three substrates (first substrate 100, second substrate 200 and third substrate 300). Figure 2 The planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300 is schematically shown. Figure 3 The cross-sectional configuration of the first substrate 100, the second substrate 200, and the second substrate 300 stacked on top of each other is schematically shown. Figure 3 Corresponding to along Figure 2The cross-section shown is formed by line III-III'. Imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (first substrate 100, second substrate 200, and third substrate 300) together. First substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. Second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. Third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 with the interlayer insulating film surrounding the wiring is referred to as the wiring layer (100T, 200T, and 300T) provided in each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and along the stacking direction, the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged sequentially. The specific configuration of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 3 The arrows shown indicate the direction of the light L incident on the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light-incident side of the imaging device 1 may be referred to as "lower," "lower side," or "below," and the side opposite to the light-incident side may be referred to as "upper," "upper side," or "above." Furthermore, in this specification, for convenience, regarding the substrate including the semiconductor layer and the wiring layer, the surface on the wiring layer side may be referred to as the front side, and the surface on the semiconductor layer side may be referred to as the back side. Note that the description in this specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated type imaging device, in which light is incident from the back side of the first substrate 100 having a photodiode.

[0142] The pixel array unit 540 and the pixel sharing unit 539 included in the pixel array unit 540 are constructed using both a first substrate 100 and a second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each of these pixels 541 has a photodiode (PD, described later) and a transmission transistor (TR, described later). The second substrate 200 is provided with pixel circuitry (pixel circuitry 210, described later) included in the pixel sharing unit 539. The pixel circuitry reads out pixel signals transmitted via the transmission transistors from the photodiodes of each pixel 541A, 541B, 541C, and 541D, or resets the photodiodes. In addition to this pixel circuitry, the second substrate 200 also has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also has power lines 544 extending along the row direction. The third substrate 300 includes, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. For example, in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300, the row driving unit 520 is disposed in a region that partially overlaps with the pixel array unit 540. More specifically, in the stacking direction, the row driving unit 520 is disposed in a region that overlaps with the end of the pixel array unit 540 in the H direction. Figure 2 In the stacking direction, the column signal processing unit 550 is, for example, disposed in a region that partially overlaps with the pixel array unit 540. More specifically, in the stacking direction, the column signal processing unit 550 is disposed in a region that overlaps with the end of the pixel array unit 540 in the V direction. Figure 2 Although not shown, the input unit 510A and the output unit 510B can be configured in a portion other than the third substrate 300, and can be configured, for example, in the second substrate 200. Alternatively, the input unit 510A and the output unit 510B can be disposed on the back side (light incident surface) of the first substrate 100. Note that the pixel circuit disposed on the second substrate 200 described above can also be referred to as a pixel transistor circuit, pixel transistor group, pixel transistor, pixel readout circuit, or readout circuit. In this specification, the term "pixel circuit" is used.

[0143] The first substrate 100 and the second substrate 200 are connected by, for example, through electrodes (described later). Figure 6The second substrate 200 and the third substrate 300 are electrically connected via, for example, contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. Contact portion 201 of the second substrate 200 contacts contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 contacts contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. Contact regions 201R and 301R are disposed between the pixel array unit 540 and the row driving unit 520 in the stacking direction. Figure 3 In other words, contact regions 201R and 301R are disposed in, for example, the region where the row driving unit 520 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or are disposed near such region. Contact regions 201R and 301R are, for example, disposed at their ends in the H direction within this region. Figure 2 In the third substrate 300, for example, the contact region 301R is disposed at a position overlapping with a portion of the row driving unit 520 (specifically, the end of the row driving unit 520 in the H direction). Figure 2 and Figure 3 Contact portions 201 and 301 connect, for example, a row driving unit 520 disposed in the third substrate 300 and a row driving line 542 disposed in the second substrate 200. Contact portions 201 and 301 can, for example, connect an input unit 510A disposed in the third substrate 300 to a power supply line 544 and a reference potential line (VSS described later). Contact regions 202R and 302R are disposed in the stacking direction between the pixel array unit 540 and the column signal processing unit 550. Figure 3 In other words, contact regions 202R and 302R are disposed, for example, in the region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or are disposed near such region. Contact regions 202R and 302R are, for example, disposed at their V-direction ends in such region. Figure 2 In the third substrate 300, for example, the contact region 301R is disposed at a position overlapping with a portion of the column signal processing unit 550 (specifically, the V-direction end of the column signal processing unit 550). Figure 2 and Figure 3For example, contacts 202 and 302 are used to connect pixel signals (signals corresponding to the amount of charge generated by photoelectric conversion as a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array unit 540 to a column signal processing unit 550 disposed in the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0144] Figure 3 This is an example of a cross-sectional view of the imaging apparatus 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging apparatus 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact portions 201, 202, 301, and 302 are formed of electrodes made of a conductive material. The conductive material is, for example, a metallic material such as copper (Cu), aluminum (Al), or gold (Au). Contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300, for example, by directly joining the wiring formed as electrodes to each other, thereby enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0145] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be positioned at a desired location. For example, similar to Figure 3 The contact areas 201R, 202R, 301R, and 302R described herein may have electrical connection portions disposed in areas overlapping with the pixel array unit 540 in the stacking direction. Alternatively, the electrical connection portions may be disposed in areas not overlapping with the pixel array unit 540 in the stacking direction. Specifically, the electrical connection portions may be disposed in areas overlapping with the peripheral portions disposed on the outer side of the pixel array unit 540 in the stacking direction.

[0146] For example, the first substrate 100 and the second substrate 200 are provided with connecting holes H1 and H2. Connecting holes H1 and H2 penetrate through the first substrate 100 and the second substrate 200. Figure 3 The connecting holes H1 and H2 are located on the outer side of the pixel array unit 540 (or the portion overlapping with the pixel array unit 540). Figure 2For example, connection hole H1 is disposed on the outside of pixel array unit 540 in the H direction, and connection hole H2 is disposed on the outside of pixel array unit 540 in the V direction. For example, connection hole H1 reaches input unit 510A disposed in third substrate 300, and connection hole H2 reaches output unit 510B disposed in third substrate 300. Connection holes H1 and H2 may be hollow or at least a portion thereof may contain conductive material. For example, there is a configuration in which bonding lines are connected to electrodes formed as input unit 510A and / or output unit 510B. Alternatively, there is a configuration in which electrodes formed as input unit 510A and / or output unit 510B are connected to conductive material disposed in connection holes H1 and H2. The conductive material disposed in connection holes H1 and H2 may be embedded in part or all of connection holes H1 and H2, or the conductive material may be formed on the sidewalls of connection holes H1 and H2.

[0147] Note that in Figure 3 In this embodiment, the third substrate 300 is provided with an input unit 510A and an output unit 510B, but this disclosure is not limited thereto. For example, by transmitting signals from the third substrate 300 to the second substrate 200 via wiring layers 200T and 300T, the input unit 510A and / or the output unit 510B can be provided in the second substrate 200. Similarly, by transmitting signals from the second substrate 200 to the first substrate 100 via wiring layers 100T and 200T, the input unit 510A and / or the output unit 510B can be provided in the first substrate 100.

[0148] Figure 4 This is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 4 The diagram shows four pixels 541 (541A, 541B, 541C, and 541D), a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors: an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, by operating the pixel circuit 210 in a time-division manner, the pixel sharing unit 539 sequentially outputs the respective pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The mode of connecting a pixel circuit 210 to a plurality of pixels 541 and outputting the pixel signals of the plurality of pixels 541 in a time-division manner through a pixel circuit 210 is called "multiple pixels 541 sharing a pixel circuit 210".

[0149] Pixels 541A, 541B, 541C, and 541D share common constituent elements. In the following text, to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, identification number 1 is added to the end of the reference numeral for the constituent element of pixel 541A, identification number 2 is added to the end of the reference numeral for the constituent element of pixel 541B, identification number 3 is added to the end of the reference numeral for the constituent element of pixel 541C, and identification number 4 is added to the end of the reference numeral for the constituent element of pixel 541D. When it is not necessary to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals for the constituent elements of pixels 541A, 541B, 541C, and 541D are omitted.

[0150] Pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transmission transistor TR electrically connected to the photodiode PD, and a floating diffuser FD electrically connected to the transmission transistor TR. In the photodiode PD (PD1, PD2, PD3, or PD4), the cathode is electrically connected to the source of the transmission transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates a charge corresponding to the amount of light received. The transmission transistor TR (transmission transistor TR1, TR2, TR3, or TR4) is, for example, an n-type complementary metal-oxide-semiconductor (CMOS) transistor. In the transmission transistor TR, the drain is electrically connected to the floating diffuser FD, and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (refer to) connected to a pixel sharing unit 539. Figure 1 Part of the process. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion section FD. The floating diffusion section FD (floating diffusion section FD1, FD2, FD3 or FD4) is an n-type diffusion layer region formed in the p-type semiconductor layer. The floating diffusion section FD is a charge retention means that temporarily holds the charge transferred from the photodiode PD, and a charge-voltage conversion means that generates a voltage corresponding to the amount of charge.

[0151] Four floating diffusers FD (FD1, FD2, FD3, and FD4) included in a pixel sharing unit 539 are electrically connected to each other and to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. The drive signal line is part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539. The gate of the amplifying transistor AMP is connected to the floating diffuser FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 543, and the gate of the select transistor SEL is connected to the drive signal line. The drive signal lines are part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539.

[0152] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffuser FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is described later... Figure 6 As shown, it is configured to be from the semiconductor layer ( Figure 6 The surface of the semiconductor layer 100S extends to the depth reaching the PD. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffuser FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the timing of the output of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffuser FD as a pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP and the load circuit unit (refer to) connected to the vertical signal line 543 are connected to the load circuit unit (refer to the load circuit unit 543). Figure 1 Together, they form a source follower. When the select transistor SEL is turned on, the amplifying transistor AMP outputs the voltage of the floating diffuser FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplifying transistor AMP, and the select transistor SEL are, for example, N-type CMOS transistors.

[0153] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffuser FD. Typically, when capturing images in dark environments, the pixel signal is small. In the case of charge-to-voltage conversion based on Q=CV, when the capacitance of the floating diffuser FD (FD capacitance C) is large, the voltage V converted by the amplifying transistor AMP becomes small. On the other hand, in bright environments, because the pixel signal is large, the floating diffuser FD cannot receive the charge of the photodiode PD unless the FD capacitance C is very large. Furthermore, the FD capacitance C needs to be large so that the voltage V converted by the amplifying transistor AMP does not become too large (in other words, it becomes small). Therefore, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FDG increases. Thus, the overall FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0154] Note that it is also possible to configure the circuit without the FD conversion gain switching transistor FDG. In this case, for example, pixel circuit 210 includes three transistors, such as an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST. Pixel circuit 210 has at least one of the pixel transistors such as the amplifying transistor AMP, the selecting transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0155] The select transistor SEL can be positioned between the power supply line VDD and the amplifying transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to both the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifying transistor AMP, and the gate of the select transistor SEL is electrically connected to the horizontal drive signal line 542 (see reference). Figure 1 The source of the amplifying transistor AMP (output of pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. Note that, although not shown, the number of pixels 541 sharing a pixel circuit 210 can be more than four. For example, two or eight pixels 541 can share a pixel circuit 210.

[0156] Figure 5An example of the connection pattern of multiple pixel sharing units 539 and vertical signal lines 543 is shown. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and the vertical signal lines 543 are connected to each of the four groups. To simplify the illustration, Figure 5 An example is shown where each of the four groups has one pixel sharing unit 539, but each of the four groups may include multiple pixel sharing units 539. As described above, in the imaging apparatus 1, the multiple pixel sharing units 539 arranged in the column direction can be divided into groups comprising one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of these groups, and pixel signals can be read out from each group simultaneously. Alternatively, in the imaging apparatus 1, a vertical signal line 543 may be connected to multiple pixel sharing units 539 juxtaposed in the column direction. In this case, pixel signals are read out sequentially from the multiple pixel sharing units 539 connected to a vertical signal line 543 in a time-division manner.

[0157] [1.3. Specific composition of imaging device 1]

[0158] Figure 6 An example of the cross-sectional configuration in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 is shown. For ease of understanding, Figure 6 The positional relationship of the constituent elements is schematically shown and may differ from the actual cross-section. In imaging apparatus 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. Imaging apparatus 1 also includes a light-receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. For example, the light-receiving lens 401 is provided in each of pixels 541A, 541B, 541C, and 541D. Imaging apparatus 1 is, for example, a back-illuminated type imaging apparatus. Imaging apparatus 1 has a pixel array unit 540 disposed in the central portion and a peripheral portion 540B disposed outside the pixel array unit 540.

[0159] The first substrate 100 sequentially comprises an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T from the light-receiving lens 401 side. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a portion of its surface (the surface on the side of the wiring layer 100T) and its vicinity, and has an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0160] Figure 7A An example of the planar configuration of the first substrate 100 is shown. Figure 7A The planar configuration of the pixel separation section 117, photodiode PD, floating diffuser FD, VSS contact region 118, and transmission transistor TR is mainly shown. (The text will use...) Figure 7A Together Figure 6 Let's explain the structure of the first substrate 100 together.

[0161] The floating diffuser FD and VSS contact region 118 are disposed near the surface of semiconductor layer 100S. The floating diffuser FD includes an n-type semiconductor region disposed within p-well layer 115. The individual floating diffusers FD (floating diffusers FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D are positioned, for example, close to each other at the center of pixel shared unit 539. Figure 7A Details will be explained later, including that the four floating diffusion sections (floating diffusion sections FD1, FD2, FD3, and FD4) in the pixel sharing unit 539 are electrically connected to each other via electrical connection means (pad section 120 described later) within the first substrate 100 (more specifically, within the wiring layer 100T). Additionally, the floating diffusion section FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrode 120E described later). Within the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion section FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via electrical means.

[0162] VSS contact area 118 is an area electrically connected to the reference potential line VSS and is configured to be separate from the floating diffuser FD. For example, in pixels 541A, 541B, 541C, and 541D, the floating diffuser FD is disposed at one end of the V direction of each pixel, while the VSS contact area 118 is disposed at the other end of each pixel. Figure 7A The VSS contact region 118 is composed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is supplied to the semiconductor layer 100S.

[0163] In addition to the photodiode PD, the floating diffuser FD, and the VSS contact region 118, a transmission transistor TR is also disposed in the first substrate 100. The photodiode PD, the floating diffuser FD, the VSS contact region 118, and the transmission transistor TR are disposed in each of pixels 541A, 541B, 541C, and 541D. The transmission transistor TR is disposed on the front side of the semiconductor layer 100S (the side opposite to the light incident surface, i.e., the second substrate 200 side). The transmission transistor TR has a transmission gate TG. The transmission gate TG includes, for example, a horizontal portion TGb facing the front side of the semiconductor layer 100S and a vertical portion TGa disposed within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end is disposed within the n-type semiconductor region 114. Because the transmission transistor TR is constructed using this vertically oriented transistor, pixel signal transmission defects are almost nonexistent, and the pixel signal readout efficiency is improved.

[0164] The horizontal portion TGb of the transmission gate TG extends from a position facing the vertical portion TGA, for example, in the H direction toward the center of the pixel sharing unit 539. Figure 7A Therefore, the position in the H direction of the through electrode reaching the transmission gate TG (the through electrode TGV described later) can be made close to the position in the H direction of the through electrodes (the through electrodes 120E and 121E described later) connected to the floating diffuser FD and the VSS contact region 118. For example, the plurality of pixel sharing units 539 provided on the first substrate 100 have the same configuration as each other. Figure 7A ).

[0165] The semiconductor layer 100S is provided with a pixel separation portion 117 that separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction (perpendicular to the surface of the semiconductor layer 100S) of the semiconductor layer 100S. The pixel separation portion 117 is configured to space pixels 541A, 541B, 541C, and 541D from each other and has, for example, a grid-like planar shape. Figure 7A and Figure 7BThe pixel separation section 117 electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other, for example. The pixel separation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For the light-shielding film 117A, for example, tungsten (W) is used. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is formed of, for example, silicon oxide (SiO). The pixel separation section 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation section 117 is not limited to an FTI structure penetrating the semiconductor layer 100S. For example, a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S can be used. The pixel separation section 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0166] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back side of the semiconductor layer 100S and is positioned between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are, for example, composed of a p-type semiconductor region.

[0167] A fixed-charge film 112 with a negative fixed charge is disposed between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of a hole accumulation layer is formed on the interface of the semiconductor layer 100S on the light-receiving surface (back side) side by an electric field induced by the fixed-charge film 112. Therefore, the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S is suppressed. The fixed-charge film 112 is formed, for example, from an insulating film with a negative fixed charge. Examples of materials for insulating films with a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0168] A light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A may be continuously disposed with the light-shielding film 117A constituting the pixel separation section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 may be selectively disposed, for example, at a position facing the pixel separation section 117 within the semiconductor layer 100S. The insulating film 111 is configured to cover the light-shielding film 117A. The insulating film 111 is formed of, for example, silicon oxide.

[0169] A wiring layer 100T disposed between a semiconductor layer 100S and a second substrate 200 sequentially comprises an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 from the semiconductor layer 100S side. A horizontal portion TGb of the transmission gate TG is disposed, for example, in the wiring layer 100T. The interlayer insulating film 119 is disposed on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above description and may also include both wiring and an insulating film.

[0170] Figure 7B The configuration of pad portions 120 and 121 is shown. Figure 7A The planar configuration is shown. Pad portions 120 and 121 are disposed in selected areas on the interlayer insulating film 119. Pad portion 120 is used to connect the floating diffuser portions FD (floating diffuser portions FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D to each other. For example, for each pixel sharing unit 539, pad portion 120 is disposed in the central portion of pixel sharing unit 539 in the planar view. Figure 7B The pad portion 120 is configured to span the pixel separation portion 117 and is configured to overlap at least a portion of each of the floating diffusion portions FD1, FD2, FD3, and FD4. Figure 6 and Figure 7B Specifically, the pad portion 120 is formed in a region overlapping with at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4. The connection via 120C is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, since a portion of the pad portion 120 is buried in the connection via 120C, the pad portion 120 is electrically connected to the floating diffusion portions FD1, FD2, FD3, and FD4.

[0171] The pad portion 121 is used to connect multiple VSS contact regions 118 to each other. For example, VSS contact regions 118 provided in pixels 541C and 541D of a pixel sharing unit 539 adjacent in the V direction and VSS contact regions 118 provided in pixels 541A and 541B of other pixel sharing units 539 are electrically connected via the pad portion 121. The pad portion 121 is configured to, for example, span across the pixel separation portion 117 and is configured to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with connection vias 121C for electrically connecting the pad portion 121 and the VSS contact regions 118. The via 121C is configured for each of pixels 541A, 541B, 541C, and 541D. For example, since a portion of the pad portion 121 is embedded in the via 121C, the pad portion 121 is electrically connected to the VSS contact area 118. For example, the pad portions 120 and 121 of each of the plurality of pixel sharing units 539 juxtaposed in the V direction are configured at substantially the same position in the H direction. Figure 7B ).

[0172] By providing pad portions 120, the wiring throughout the chip for connecting each floating diffuser FD to the pixel circuit 210 (e.g., the gate electrode of the amplifying transistor AMP) can be reduced. Similarly, by providing pad portions 121, the wiring throughout the chip for supplying potential to each VSS contact region 118 can be reduced. Therefore, the overall chip area can be reduced, electrical interference between wirings in miniaturized pixels can be suppressed, and / or costs can be reduced by reducing the number of components.

[0173] Pad portions 120 and 121 can be disposed at desired locations on the first substrate 100 and the second substrate 200. Specifically, pad portions 120 and 121 can be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. When disposed in the wiring layer 100T, pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, pad portions 120 and 121 can be directly connected to at least a portion of each of the floating diffusion portions FD and / or VSS contact regions 118. Furthermore, connecting vias 120C and 121C can be disposed from each of the floating diffusion portions FD and / or VSS contact regions 118 connected to pad portions 120 and 121, and pad portions 120 and 121 can be disposed at desired locations in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0174] Specifically, when pads 120 and 121 are provided in wiring layer 100T, the wiring connecting to floating diffuser FD and / or VSS contact region 118 in insulating region 212 of semiconductor layer 200S can be reduced. Therefore, in second substrate 200 for forming pixel circuit 210, the area of ​​insulating region 212 for forming through wiring connecting floating diffuser FD to pixel circuit 210 can be reduced. Thus, a large area of ​​second substrate 200 for forming pixel circuit 210 can be ensured. By ensuring sufficient area for pixel circuit 210, large pixel transistors can be formed, and image quality can be improved by reducing noise, etc.

[0175] In particular, when using the FTI structure for the pixel separation section 117, it is preferable to provide a floating diffuser (FD) and / or a VSS contact area 118 in each pixel 541. Therefore, by using the configuration of the pads 120 and 121, the number of wirings connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0176] In addition, such as Figure 7B As shown, for example, pad portions 120 connected to multiple floating diffusers FD and pad portions 121 connected to multiple VSS contact regions 118 are arranged alternately in a straight line in the V direction. Furthermore, pad portions 120 and 121 are formed at locations surrounded by multiple photodiodes PD, multiple transmission gates TG, and multiple floating diffusers FD. Therefore, in the first substrate 100 for forming multiple components, components other than floating diffusers FD and VSS contact regions 118 can be freely arranged, and the overall chip layout efficiency can be improved. Furthermore, the symmetry of the layout of components formed in the pixel-sharing units 539 is ensured, and variations in the characteristics of each pixel 541 can be suppressed.

[0177] The pad portions 120 and 121 are formed of, for example, polysilicon (Poly Si), and more specifically, doped polysilicon with added impurities. Preferably, the pad portions 120 and 121 are formed of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). Therefore, the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason for this will be explained below. Note that in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layers 200S of the first substrate 100 and the second substrate 200 together is referred to as the first manufacturing method.

[0178] Here, it is also possible to form the pixel circuit 210 on the second substrate 200 and then attach the pixel circuit 210 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are attached together, the electrodes for electrical connection formed on each of the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the configuration of the imaging device 1 using the second manufacturing method, it is possible to manufacture a high-quality, high-performance imaging device by using appropriate processes according to the respective configurations of the first substrate 100 and the second substrate 200.

[0179] In the second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, alignment errors may occur due to the manufacturing equipment used for bonding. Furthermore, the first substrate 100 and the second substrate 200 have dimensions, for example, a diameter of about several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, expansion and contraction of the substrates may occur in the microscopic regions of each portion of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by slight misalignment of the contact timing between the substrates. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the position of electrodes for electrical connection formed on each of the surfaces of the first substrate 100 and the second substrate. In the second manufacturing method, it is preferable to take measures such that even if such errors occur, the respective electrodes of the first substrate 100 and the second substrate 200 are in contact with each other. Specifically, considering the aforementioned errors, at least one of the electrodes of the first substrate 100 and the second substrate 200 is increased, or preferably both are increased. Therefore, when the second manufacturing method is used, for example, the size (size in the planar direction of the substrate) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode that extends from the interior of the first substrate 100 or the second substrate 200 to the surface in the thickness direction.

[0180] On the other hand, since the pads 120 and 121 are formed using a heat-resistant conductive material, the first manufacturing method described above can be used. In the first manufacturing method, after forming a first substrate 100 including a photodiode PD and a transmission transistor TR, the first substrate 100 and a second substrate 200 (semiconductor layer 200S) are bonded together. At this time, the second substrate 200 is in a state where the patterns constituting the active elements and wiring layers of the pixel circuit 210 have not been formed. Since the second substrate 200 is in a state before patterning, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded, the bonding error will not cause an alignment error between the patterns of the first substrate 100 and the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. Note that when a pattern is formed on the second substrate, for example, in an exposure apparatus for pattern formation, the pattern is formed simultaneously with the pattern formed on the first substrate as the alignment target. For the reasons stated above, in the manufacture of the imaging device 1 by the first manufacturing method, the error in the bonding position between the first substrate 100 and the second substrate 200 is not a problem. For the same reason, the error caused by the expansion and contraction of the substrate due to the second manufacturing method is not a problem in the manufacture of the imaging device 1 by the first manufacturing method.

[0181] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, an active element is formed on the second substrate 200. Subsequently, through electrodes 120E and 121E, as well as a through electrode TGV, are formed. Figure 6 When forming the through electrodes 120E, 121E, and TGV, for example, the pattern of the through electrodes is formed from above the second substrate 200 by using reduced projection exposure with an exposure apparatus. Because reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure apparatus, the magnitude of the error is only a fraction of the error of the second manufacturing method described above in the second substrate 200 (the reciprocal of the reduced exposure projection magnification). Therefore, by forming the imaging device 1 using the first manufacturing method, it is easy to align the various elements formed on the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

[0182] The imaging device 1 manufactured using the first manufacturing method has features different from those of the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (dimension in the plane of the substrate) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant tilt angle. In the imaging device 1 having such through electrodes 120E, 121E, and TGV, the pixel 541 can be easily miniaturized.

[0183] Here, when the imaging device 1 is manufactured using the first manufacturing method, the first substrate 100 is also subjected to the heat treatment required to form the active element after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided on the first substrate 100. For example, the pad portions 120 and 121 are preferably formed of a material having a higher melting point (i.e., higher heat resistance) than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200. For example, conductive materials with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, are used for the pad portions 120 and 121. Therefore, the imaging device 1 can be manufactured using the first manufacturing method described above.

[0184] For example, a passivation film 122 is disposed on the entire surface of the semiconductor layer 100S to cover the pad portions 120 and 121. Figure 6 The passivation film 122 is formed, for example, of a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pad portions 120 and 121 across the passivation film 122. The interlayer insulating film 123 is, for example, disposed on the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is, for example, formed of a silicon oxide (SiO) film. A bonding film 124 is disposed on the mating surface of the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is disposed on the entire main surface of the first substrate 100. The bonding film 124 is, for example, formed of a silicon nitride film.

[0185] The light-receiving lens 401 faces the semiconductor layer 100S, for example, through the fixed charge film 112 and the insulating film 111. Figure 6 The light-receiving lens 401 is, for example, positioned facing the respective photodiodes PD of pixels 541A, 541B, 541C, and 541D.

[0186] The second substrate 200 sequentially comprises a semiconductor layer 200S and a wiring layer 200T from the side of the first substrate 100. The semiconductor layer 200S is formed of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 configured for each pixel sharing unit 539. The pixel circuit 210 is, for example, provided on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging apparatus 1, the second substrate 200 is attached to the first substrate 100 such that the back side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is attached to the first substrate 100 front to back.

[0187] Figures 8-12 An example of the planar configuration of the second substrate 200 is schematically shown. Figure 8 The configuration of the pixel circuit 210 disposed near the surface of the semiconductor layer 200S is shown. Figure 9 The schematic diagram shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and various parts of the first substrate 100. Figures 10-12 An example of the planar configuration of the 200T wiring layer is shown. In the following text, reference will be made to... Figures 8-12 Together Figure 6 The structure of the second substrate 200 will be explained together. Figure 8 and Figure 9 In the diagram, the outline of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is represented by dashed lines, and the boundary between the semiconductor layer 200S and the element isolation region 213 or insulating region 212 at the portion overlapping with the gate electrodes of each transistor constituting the pixel circuit 210 is represented by dotted lines. In the portion overlapping with the gate electrode of the amplifying transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213, and the boundary between the element isolation region 213 and the insulating region 212, are provided on one side in the channel width direction.

[0188] The second substrate 200 is provided with an insulating region 212 for dividing the semiconductor layer 200S and a component isolation region 213 disposed in a portion of the thickness direction of the semiconductor layer 200S. Figure 6 For example, in an insulating region 212 located between two adjacent pixel circuits 210 in the H direction, through electrodes 120E and 121E connected to two pixel shared units 539 of the two pixel circuits 210, as well as through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are disposed. Figure 9 ).

[0189] The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 200S. Figure 6 The semiconductor layer 200S is divided by an insulating region 212. Through electrodes 120E and 121E, as well as a through electrode TGV, are disposed in the insulating region 212. The insulating region 212 is formed of, for example, silicon oxide.

[0190] Through electrodes 120E and 121E are provided in a manner that penetrates the insulating region 212 in the thickness direction. The upper ends of through electrodes 120E and 121E are connected to the wiring of wiring layer 200T (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4, described later). Through electrodes 120E and 121E are provided in a manner that penetrates the insulating region 212, bonding film 124, interlayer insulating film 123, and passivation film 122, and their lower ends are connected to pad portions 120 and 121. Figure 6 The through electrode 120E is used for electrical connection between the pad portion 120 and the pixel circuit 210. That is, the through electrode 120E electrically connects the floating diffusion portion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200. The through electrode 121E is used for electrical connection between the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact area 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0191] The through electrode TGV is configured to penetrate the insulation region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring layer 200T. The through electrode TGV is configured to penetrate the insulation region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transmission gate TG (…). Figure 6 The through electrode TGV is used to electrically connect the transmission gate TG (transmission gate TG1, TG2, TG3 or TG4) of each of pixels 541A, 541B, 541C and 541D to the wiring of the wiring layer 200T (part of the line drive signal line 542, specifically, described later). Figure 11 The wirings TRG1, TRG2, TRG3, and TRG4. That is, the transmission gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and the drive signal is sent to each transmission transistor TR (transmission transistors TR1, TR2, TR3, and TR4).

[0192] The insulating region 212 is a region used to insulate the through electrodes 120E and 121E, and the through electrode TGV, which are used to electrically connect the first substrate 100 and the second substrate 200, from the semiconductor layer 200S. For example, in the insulating region 212 disposed between two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction, through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3 and TGV4) connected to the two pixel circuits 210 are disposed. The insulating region 212 is configured to extend, for example, in the V direction ( Figure 8 and Figure 9 Here, by designing the configuration of the horizontal portion TGb of the transmission gate TG, the position of the through electrode TGV in the H direction is configured to be closer to the positions of the through electrodes 120E and 121E in the H direction compared to the position of the vertical portion TGA. Figure 7A and Figure 9 For example, the through electrode TGV is positioned in the H direction at substantially the same location as the through electrodes 120E and 121E. Therefore, the through electrodes 120E and 121E and the through electrode TGV can be disposed together in the insulating region 212 extending along the V direction. As another configuration example, it is conceivable that the horizontal portion TGb is disposed only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and for example, the through electrode TGV is disposed approximately at the center of each pixel 541 in the H and V directions. At this time, the position of the through electrode TGV in the H direction is significantly different from the position of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is disposed around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E and 121E in the H direction, an insulating region 212 needs to be independently formed around each through electrode 120E, 121E, and TGV. Therefore, the semiconductor layer 200S is finely divided. In contrast, in a layout where the through electrodes 120E and 121E and the through electrode TGV are arranged together in an insulating region 212 extending along the V direction, the size of the semiconductor layer 200S in the H direction can be increased. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Thus, for example, the size of the amplification transistor AMP can be increased and noise can be suppressed.

[0193] For reference Figure 4As described, the pixel sharing unit 539 has the following structure, wherein electrical connections are provided between each floating diffuser portion FD in a plurality of pixels 541, and the plurality of pixels 541 share a single pixel circuit 210. The electrical connections between the floating diffuser portions FD are made by pad portions 120 provided on the first substrate 100. Figure 6 and Figure 7B An electrical connection portion (pad portion 120) provided on the first substrate 100 and a pixel circuit 210 provided on the second substrate 200 are electrically connected via a through electrode 120E. As another structural example, it is conceivable to provide an electrical connection portion between floating diffusers FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusers FD1, FD2, FD3, and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 surrounding these through electrodes becomes larger. In contrast, in a structure where the pad portion 120 is provided on the first substrate 100 ( Figure 6 and Figure 7B This reduces the number of through electrodes and the size of the insulating region 212. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Thus, for example, the size of the amplifying transistor AMP can be increased and noise can be suppressed.

[0194] Component isolation region 213 is disposed on the surface side of semiconductor layer 200S. Component isolation region 213 has an STI (shallow trench isolation) structure. In component isolation region 213, semiconductor layer 200S is excavated in the thickness direction (perpendicular to the main surface of second substrate 200), and an insulating film is buried in the excavated portion. The insulating film is formed of, for example, silicon oxide. Component isolation region 213 isolates multiple transistors constituting pixel circuit 210 from each other according to the layout of pixel circuit 210. Semiconductor layer 200S (specifically, well region 211) extends below component isolation region 213 (deep within semiconductor layer 200S).

[0195] Here, refer to Figure 7A , Figure 7B and Figure 8 The difference between the external shape (outer shape in the planar direction of the substrate) of the pixel sharing unit 539 in the first substrate 100 and the external shape of the pixel sharing unit 539 in the second substrate 200 will be explained.

[0196] In the imaging apparatus 1, a pixel sharing unit 539 is disposed on both the first substrate 100 and the second substrate 200. For example, the external shape of the pixel sharing unit 539 disposed on the first substrate 100 and the external shape of the pixel sharing unit 539 disposed on the second substrate 200 are different from each other.

[0197] exist Figure 7A and Figure 7B In the diagram, the outlines of pixels 541A, 541B, 541C, and 541D are represented by alternating dashed and dotted lines, and the shape of the pixel sharing unit 539 is represented by thick lines. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four pixels 541 arranged in two adjacent rows × two columns, and the pixel sharing unit 539 of the first substrate 100 has a generally square shape. In the pixel array unit 540, such pixel sharing units 539 are arranged adjacent to each other with two pixel pitches in the H direction (the pitch corresponds to two pixels 541) and two pixel pitches in the V direction (the pitch corresponds to two pixels 541).

[0198] exist Figure 8 and Figure 9 In the diagram, the outlines of pixels 541A, 541B, 541C, and 541D are represented by alternating long and short dashed lines, and the shape of the pixel sharing unit 539 is represented by a thick line. For example, the shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction and larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size corresponding to pixels arranged in an adjacent row × four columns, and the pixel sharing unit 539 of the second substrate 200 has a generally rectangular shape.

[0199] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in the V direction. Figure 8 As described above, by setting the outline shape of each pixel circuit 210 to a roughly rectangular shape, four transistors (selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) can be aligned in one direction. Figure 8 The drains of the amplifying transistor AMP and the reset transistor RST are arranged side-by-side in the V direction. Therefore, the drains of both transistors can be shared by a single diffusion region (a diffusion region connected to the power line VDD). For example, the formation regions of each pixel circuit 210 can also be configured in a roughly square shape (see below). Figure 21In this case, arranging two transistors along one direction makes it difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST within a single diffusion region. Therefore, by setting the formation region of the pixel circuit 210 to a roughly rectangular shape, it is easy to arrange the four transistors closely together, and the formation region of the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. Furthermore, when it is not necessary to reduce the formation region of the pixel circuit 210, the formation region of the amplification transistor AMP can be increased and noise can be suppressed.

[0200] For example, near the surface of semiconductor layer 200S, in addition to the select transistor SEL, amplify transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is also provided. VSS contact region 218 is formed, for example, from a p-type semiconductor region. VSS contact region 218 is electrically connected to VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via wiring of wiring layer 200T and through electrode 121E. VSS contact region 218 is located, for example, adjacent to the source of FD conversion gain switching transistor FDG via element isolation region 213. Figure 8 ).

[0201] Next, we will refer to Figure 7B and Figure 8 The positional relationship between the pixel sharing unit 539 disposed in the first substrate 100 and the pixel sharing unit 539 disposed in the second substrate 200 is explained. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (e.g., Figure 7B The upper side of the paper in the middle) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Figure 8 (The left side of the paper in the image). For example, another pixel sharing unit 539 in one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (e.g., Figure 7B The lower side of the paper in the middle) is connected to another pixel sharing unit 539 of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Figure 8 (The right side of the paper in the middle).

[0202] For example, in two pixel-sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (transistor configuration, etc.) of one pixel-sharing unit 539 is approximately equal to the layout of the other pixel-sharing unit 539 inverted in the V and H directions. The effect obtained by this layout will be explained below.

[0203] In the two pixel sharing units 539 arranged in the V direction of the first substrate 100, each pad portion 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, at the center of the pixel sharing unit 539 in both the V and H directions. Figure 7B On the other hand, as described above, since the pixel sharing unit 539 of the second substrate 200 has a generally rectangular shape that is longer in the V direction, for example, the amplifying transistor AMP connected to the pad portion 120 is positioned offset upwards from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layout of two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, the distance between the amplifying transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 7) is relatively short. However, the distance between the amplifying transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper in FIG. 7) is longer. Therefore, the area of ​​the wiring required to connect the amplifying transistor AMP and the pad portion 120 increases, and the wiring layout of the pixel sharing unit 539 may become complex. This may affect the miniaturization of the imaging device 1.

[0204] On the other hand, in the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, by reversing their internal layout at least in the V direction, the distance between the amplification transistor AMP and the pad portion 120 of both pixel-sharing units 539 can be shortened. Therefore, compared with the same configuration of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, the imaging device 1 can be easily miniaturized. Note that although the planar layout of each of the plurality of pixel-sharing units 539 in the second substrate 200 is in... Figure 8 The area shown is symmetrical from left to right, but when including the area described later... Figure 9 When the first wiring layer W1 is laid out as shown, the planar layout is asymmetrical.

[0205] Furthermore, preferably, the internal layout of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 is reversed relative to each other in the H direction. The reason for this will be explained below. Figure 9As shown, two pixel-sharing units 539 arranged in the H direction of the second substrate 200 are respectively connected to pad portions 120 and 121 of the first substrate 100. For example, pad portions 120 and 121 are disposed at the center of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel-sharing units 539 arranged in the H direction). Therefore, by reversing the internal layout of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 from each other in the H direction, the distance between each of the plurality of pixel-sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, the imaging device 1 can be miniaturized more easily.

[0206] Furthermore, the position of the outline of the pixel sharing unit 539 of the second substrate 200 may not be aligned with the position of any outline of the pixel sharing unit 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Figure 9 On the left side of the paper (e.g., the side in the V direction) Figure 9 The outline of the upper side of the paper in the middle) is arranged in the corresponding pixel sharing unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the contour on the V direction side of the paper surface (upper side of the paper). Furthermore, another pixel-sharing unit 539 (e.g., one of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200) is also present. Figure 9 On the right side of the paper (in the image), on the other side in the V direction (e.g., Figure 9 The outline of the lower side of the paper in the middle) is arranged in the corresponding pixel sharing unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the outline in the V direction on the lower side of the paper surface. As described above, by arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 side by side, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging device 1 can be easily miniaturized.

[0207] Furthermore, the positions of the outlines of the plurality of pixel-sharing units 539 on the second substrate 200 may not be aligned with each other. For example, two pixel-sharing units 539 arranged in the H direction of the second substrate 200 are configured such that the positions of their outlines in the V direction are shifted. Therefore, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging device 1 can be easily miniaturized.

[0208] Reference Figure 7B and Figure 9This describes the repeated configuration of pixel sharing units 539 in pixel array unit 540. The pixel sharing units 539 of the first substrate 100 have the dimensions of two pixels 541 in the H direction and the dimensions of two pixels 541 in the V direction (…). Figure 7B For example, in the pixel array unit 540 of the first substrate 100, pixel sharing units 539 having a size corresponding to four pixels 541 are arranged adjacently and repeatedly with two pixel spacings in the H direction (the spacing corresponds to two pixels 541) and two pixel spacings in the V direction (the spacing corresponds to two pixels 541). Alternatively, the pixel array unit 540 of the first substrate 100 may be provided with pairs of pixel sharing units 539, wherein every two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array unit 540 of the first substrate 100, for example, pairs of pixel sharing units 539 are arranged adjacently and repeatedly with two pixel spacings in the H direction (the spacing corresponds to two pixels 541) and four pixel spacings in the V direction (the spacing corresponds to four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction (the size of one pixel 541 in the H direction and the size of four pixels 541 in the V direction). Figure 9 For example, the pixel array unit 540 of the second substrate 200 is provided with a pair of pixel sharing units 539, which includes two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset in the V direction. In the pixel array unit 540 of the second substrate 200, for example, such pairs of pixel sharing units 539 are arranged adjacently and without gaps at a two-pixel spacing in the H direction (the spacing corresponds to two pixels 541) and a four-pixel spacing in the V direction (the spacing corresponds to four pixels 541). Therefore, through this repeated arrangement of the pixel sharing units 539, the pixel sharing units 539 can be arranged without gaps. Therefore, the imaging device 1 can be easily miniaturized.

[0209] The amplifying transistor AMP preferably has, for example, a three-dimensional structure of the Fin type. Figure 6 Therefore, the effective gate width becomes larger, and noise can be suppressed. The select transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG have, for example, planar structures. The amplifying transistor AMP can also have a planar structure. Alternatively, the select transistor SEL, reset transistor RST, or FD conversion gain switching transistor FDG can have a three-dimensional structure.

[0210] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S and covers the entire surface of the semiconductor layer 200S. The passivation film 221 covers the respective gate electrodes of the select transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 is formed, for example, silicon oxide.

[0211] The wiring layer 200T is sequentially provided from the semiconductor layer 200S side with, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202. The interlayer insulating film 222 is provided with multiple connection portions for connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the underlying layer. Each connection portion is a portion in which conductive material is embedded in a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 is provided with a connection portion 218V connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of the connection portion connecting the components of the second substrate 200 to each other is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, preferably, the aperture of the connection holes connecting the components of the second substrate 200 to each other is smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV. The reason for this will be explained below. The depth of the connection portions (connection portions 218V, etc.) provided within the wiring layer 200T is smaller than the depth of the through electrodes 120E and 121E and the through electrode TGV. Therefore, compared to the through electrodes 120E and 121E and the through electrode TGV, the connection portions allow for easier filling of the connection holes with conductive material. By making the aperture of the connection portions smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV, the imaging device 1 can be easily miniaturized.

[0212] For example, the first wiring layer W1 connects the through electrode 120E, the gate of the amplifying transistor AMP, and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0213] Next, we will refer to Figures 10-12Explain the planar configuration of the 200T wiring layer. Figure 10 An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 11 An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 12 An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0214] For example, the third wiring layer W3 includes wiring TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Figure 11 These wirings correspond to the reference. Figure 4 Multiple row drive signal lines 542 are described. Wirings TRG1, TRG2, TRG3, and TRG4 are used to send drive signals to transmission gates TG1, TG2, TG3, and TG4, respectively. Wirings TRG1, TRG2, TRG3, and TRG4 are connected to transmission gates TG1, TG2, TG3, and TG4 via a second wiring layer W2, a first wiring layer W1, and a through electrode 120E, respectively. Wiring SELL is used to send drive signals to the gate of the select transistor SEL, wiring RSTL is used to send drive signals to the gate of the reset transistor RST, and wiring FDGL is used to send drive signals to the gate of the FD conversion gain switching transistor FDG. Wirings SELL, RSTL, and FDGL are connected to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via a second wiring layer W2, a first wiring layer W1, and a connection portion, respectively.

[0215] For example, the fourth wiring layer W4 includes a power line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction). Figure 12 The power line VDD is connected to the drain of the amplifying transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Furthermore, the reference potential line VSS is connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0216] Contact portions 201 and 202 can be disposed at positions overlapping with pixel array unit 540 in the plan view (e.g., Figure 3Alternatively, it can be disposed on the peripheral portion 540B outside the pixel array unit 540 (e.g., Figure 6 Contact portions 201 and 202 are disposed on the surface of the second substrate 200 (the surface on the side of the wiring layer 200T). Contact portions 201 and 202 are formed of metals such as Cu (copper) and Al (aluminum). Contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the side of the third substrate 300). Contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 to each other.

[0217] Figure 6 An example is shown in which peripheral circuitry is disposed in the peripheral portion 540B of the second substrate 200. This peripheral circuitry may include a portion of a row driving unit 520 or a portion of a column signal processing unit 550, etc. Furthermore, as... Figure 3 As shown, the peripheral circuit may not be configured in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be configured near the pixel array unit 540.

[0218] The third substrate 300 sequentially comprises, for example, a wiring layer 300T and a semiconductor layer 300S from the side of the second substrate 200. For example, the surface of the semiconductor layer 300S is disposed on the side of the second substrate 200. The semiconductor layer 300S is formed of a silicon substrate. Circuitry is disposed on a portion of the front side of the semiconductor layer 300S. Specifically, at least a portion of, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, or an output unit 510B is disposed on a portion of the front side of the semiconductor layer 300S. The wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. Contacts 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the side of the second substrate 200). Contact 301 contacts contact 201 of the second substrate 200, and contact 302 contacts contact 202 of the second substrate 200. Contacts 301 and 302 are electrically connected to a circuit formed in the semiconductor layer 300S (e.g., at least one of input unit 510A, row drive unit 520, timing control unit 530, column signal processing unit 550, image signal processing unit 560, and output unit 510B). Contacts 301 and 302 are formed of metals such as Cu (copper) and Al (aluminum). For example, external terminal TA is connected to input unit 510A via connection hole H1, and external terminal TB is connected to output unit 510B via connection hole H2.

[0219] Here, the features of imaging device 1 will be described.

[0220] Typically, imaging devices mainly consist of photodiodes and pixel circuits. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thus improving the signal-to-noise ratio (S / N ratio) of the pixel signal and allowing the imaging device to output better image data (image information). Conversely, increasing the size of the transistors included in the pixel circuit (especially the size of the amplifying transistors) reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal and allowing the imaging device to output better image data (image information).

[0221] However, in imaging devices where the photodiode and pixel circuit are mounted on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, it is conceivable that the size of the transistor mounted in the pixel circuit can be reduced. Furthermore, if the size of the transistor mounted in the pixel circuit is increased, it is conceivable that the area of ​​the photodiode can be reduced.

[0222] To address these issues, for example, the imaging apparatus 1 of this embodiment uses a structure in which multiple pixels 541 share a pixel circuit 210, and the shared pixel circuit 210 is configured to overlap with a photodiode PD. Therefore, it is possible to maximize the area of ​​the photodiode PD and maximize the size of the transistors disposed in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. Consequently, the signal-to-noise ratio (S / N) of the pixel signal can be improved, and the imaging apparatus 1 can output better image data (image information).

[0223] When multiple pixels 541 share a single pixel circuit 210 and the pixel circuit 210 is configured by overlapping with a photodiode PD, multiple wirings connected to the pixel circuit 210 extend from the respective floating diffusers FD of the multiple pixels 541. To ensure a large area of ​​the semiconductor substrate 200 used to form the pixel circuit 210, for example, a connection wiring that interconnects and integrates the multiple extended wirings into a single connection wiring can be formed. Similarly, for multiple wirings extending from the VSS contact region 118, a connection wiring that interconnects and integrates the multiple extended wirings into a single connection wiring can be formed.

[0224] For example, if a connecting wire interconnecting multiple wires extending from the respective floating diffuser portions FD of the multiple pixels 541 is formed on the semiconductor substrate 200 on which the pixel circuit 210 is formed, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 is reduced. Similarly, if a connecting wire interconnecting and integrating multiple wires extending from the respective VSS contact regions 118 of the multiple pixels 541 into a single connection wire is formed on the semiconductor substrate 200 on which the pixel circuit 210 is formed, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 is reduced.

[0225] To address these issues, for example, in the imaging apparatus 1 of this embodiment, a structure can be provided in which multiple pixels 541 share a pixel circuit 210 and the shared pixel circuit 210 is configured to overlap with a photodiode PD, wherein a connection wiring is provided on the first substrate 100 to interconnect and integrate the respective floating diffuser portions FD of the multiple pixels 541 into a single connection wiring and to interconnect and integrate the respective VSS contact regions 118 provided in the multiple pixels 541 into a single connection wiring.

[0226] Here, if the above-described second manufacturing method is used as a method for providing a connection wiring in the first substrate 100 that interconnects and integrates the respective floating diffuser portions FD of a plurality of pixels 541 into a single connection wiring and interconnects and integrates the respective VSS contact regions 118 of a plurality of pixels 541 into a single connection wiring, for example, manufacturing can be performed using appropriate processes according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when using the above-described second manufacturing method, electrodes connected to the floating diffuser portions FD and electrodes connected to the VSS contact regions 118 are respectively provided on the surface of the first substrate 100, which forms the bonding boundary between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to enlarge the electrodes formed on the surfaces of the first substrate 100 and the second substrate 200 so that when the two substrates are bonded together, even if the electrodes provided on the surfaces of the two substrates shift, the electrodes formed on the surfaces of the two substrates will still contact each other. In this case, it is conceivable that it may be difficult to arrange the aforementioned electrodes within the limited area of ​​each pixel in the imaging device 1.

[0227] To address the issue of requiring a large electrode at the bonding boundary between the first substrate 100 and the second substrate 200, the first manufacturing method described above can be used, for example, as a manufacturing method for the imaging device 1 of this embodiment (where multiple pixels 541 share a pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping with a photodiode PD). Therefore, the components formed on the first substrate 100 and the second substrate 200 can be easily aligned with each other, and an imaging device with high quality and high performance can be manufactured. Furthermore, an inherent structure produced by this manufacturing method can be provided. That is, the structure is configured such that the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked sequentially. In other words, the first substrate 100 and the second substrate 200 are stacked face to back, and through electrodes 120E and 121E are provided that penetrate the semiconductor layer 200S of the second substrate 200 and the wiring layer 100T of the first substrate 100 to reach the front side of the semiconductor layer 100S of the first substrate 100.

[0228] In a structure in which the respective floating diffuser portions FD of a plurality of pixels 541 are interconnected and integrated into a single connection wiring and the respective VSS contact regions 118 of a plurality of pixels 541 are interconnected and integrated into a single connection wiring disposed on the first substrate 100, if such a structure and the second substrate 200 are stacked using the first manufacturing method and a pixel circuit 210 is formed on the second substrate 200, there is a possibility that the heat treatment required to form the active element disposed on the pixel circuit 210 will affect the aforementioned connection wiring formed on the first substrate 100.

[0229] Therefore, in order to solve the aforementioned problem of heat treatment affecting the connection wiring when forming active elements, in the imaging apparatus 1 of this embodiment, it is desirable to use a conductive material with high heat resistance for the connection wiring that interconnects and integrates the respective floating diffuser portions FD of multiple pixels 541 into one connection wiring and the respective VSS contact regions 118 of multiple pixels 541 into one connection wiring. Specifically, as a conductive material with high heat resistance, a material having a higher melting point than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200 can be used.

[0230] As described above, for example, the imaging apparatus 1 of this embodiment has (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, in which the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked sequentially), (2) a structure in which through electrodes 120E and 121E are provided that pass through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 200 and reach the front side of the semiconductor layer 100S of the first substrate 100, and (3) in which The connection wiring that interconnects and integrates the floating diffusers FDs disposed in the plurality of pixels 541 into a single connection wiring and the connection wiring that interconnects and integrates the VSS contact areas 118 disposed in the plurality of pixels 541 into a single connection wiring is made of a highly heat-resistant conductive material. Therefore, even if a large electrode is not disposed at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 can be provided with a connection wiring that interconnects and integrates the floating diffusers FDs disposed in the plurality of pixels 541 into a single connection wiring and the connection wiring that interconnects and integrates the VSS contact areas 118 disposed in the plurality of pixels 541 into a single connection wiring.

[0231] [1.4. Operation of Imaging Device 1]

[0232] Next, we will refer to Figure 13 and Figure 14 Explain the operation of imaging device 1. Figure 13 and Figure 14 This is achieved by adding arrows representing the paths of each signal. Figure 3 The image was created using [the medium / method]. Figure 13 In the diagram, the paths from external input to the input signal of imaging device 1, as well as the power supply potential and reference potential, are indicated by arrows. Figure 14In the diagram, the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by arrows. For example, the input signal (e.g., pixel clock and synchronization signal) input to the imaging device 1 via the input unit 510A is transmitted to the row driving unit 520 of the third substrate 300, and a row driving signal is created in the row driving unit 520. The row driving signal is sent to the second substrate 200 via the contacts 301 and 201. Furthermore, the row driving signal reaches the respective pixel sharing units 539 of the pixel array unit 540 via the row driving signal line 542 in the wiring layer 200T. In the row driving signal that has reached the pixel sharing unit 539 of the second substrate 200, the driving signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and drives pixels 541A, 541B, 541C and 541D. Figure 13 Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contacts 301 and 201, and supplied to each pixel circuit 210 of the pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via through electrode 121E. On the other hand, the pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 in each pixel sharing unit 539 via through electrode 120E. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via vertical signal line 543 and contacts 202 and 302. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0233] [1.5. Effects]

[0234] In this embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are respectively disposed on different substrates (first substrate 100 and second substrate 200). Therefore, compared with the case where pixels 541A, 541B, 541C, 541D, and pixel circuit 210 are formed on the same substrate, the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210 can be increased. Therefore, the amount of pixel signal obtained by photoelectric conversion can be increased and the noise of the transistors in pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the imaging device 1 can be reduced). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size and can output high-quality images.

[0235] Furthermore, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other via through electrodes 120E and 121E disposed in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting via wiring through the semiconductor layer (e.g., through-silicon vias (TSVs)), can be considered. Compared to this method, by providing through electrodes 120E and 121E in the insulating region 212, the area used to connect the first substrate 100 and the second substrate 200 can be reduced. Therefore, the pixel size can be reduced, and the size of the imaging device 1 can be further reduced. Furthermore, the resolution can be further improved by further minimizing the area of ​​each pixel. When it is not necessary to reduce the chip size, the formation areas of pixels 541A, 541B, 541C, and 541D, as well as the pixel circuit 210, can be enlarged. Therefore, the amount of pixel signal obtained by photoelectric conversion can be increased, and the noise of the transistors disposed in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0236] Furthermore, in imaging apparatus 1, the pixel circuit 210, column signal processing unit 550, and image signal processing unit 560 are respectively disposed on different substrates (second substrate 200 and third substrate 300). Therefore, compared to the case where the pixel circuit 210, column signal processing unit 550, and image signal processing unit 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the areas of the column signal processing unit 550 and image signal processing unit 560 can be increased. Therefore, noise generated in the column signal processing unit 550 can be reduced, and advanced image processing circuitry can be incorporated into the image signal processing unit 560. As a result, the signal-to-noise ratio of the pixel signal is improved, and imaging apparatus 1 can output better pixel data (image information).

[0237] Furthermore, in the imaging apparatus 1, a pixel array unit 540 is disposed on a first substrate 100 and a second substrate 200, and a column signal processing unit 550 and an image signal processing unit 560 are disposed on a third substrate 300. Additionally, contact portions 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array unit 540. Therefore, the contact portions 201, 202, 301, and 302 can be freely arranged without interference from the various wirings disposed in the pixel array. Thus, the contact portions 201, 202, 301, and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. By using the contact portions 201, 202, 301, and 302, for example, the column signal processing unit 550 and the image signal processing unit 560 have a high degree of freedom in their layout. Therefore, noise generated in the column signal processing unit 550 can be reduced, and advanced image processing circuitry can be mounted in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0238] Furthermore, in the imaging device 1, the pixel separation section 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is shortened due to the miniaturization of the area of ​​each pixel, color mixing between pixels 541A, 541B, 541C, and 541D can be suppressed. As a result, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0239] Furthermore, in the imaging apparatus 1, a pixel circuit 210 is provided for each pixel sharing unit 539. Therefore, compared to the case where a pixel circuit 210 is provided for each of pixels 541A, 541B, 541C, and 541D, the formation area of ​​the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 can be increased. For example, noise can be suppressed by increasing the formation area of ​​the amplification transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging apparatus 1 can output better pixel data (image information).

[0240] Furthermore, in the imaging apparatus 1, pad portions 120 for electrically connecting the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of four pixels (pixels 541A, 541B, 541C, and 541D) are provided on the first substrate 100. Therefore, compared to providing such pad portions 120 on the second substrate 200, the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, the insulating region 212 can be reduced in size, and the formation region (semiconductor layer 200S) of the transistors constituting the pixel circuit 210 can be ensured to have sufficient size. Therefore, the noise of the transistors provided in the pixel circuit 210 can be reduced, and the signal-to-noise ratio of the pixel signal can be improved, and the imaging apparatus 1 can output better pixel data (image information).

[0241] In the following description, variations of the imaging apparatus 1 according to the above embodiment will be explained. In the following variations, the same configuration as the above embodiment will be described using the same reference numerals.

[0242] <2. Variations>

[0243] [2.1. Variation Example 1-1]

[0244] Figures 15-19 A modified example of the planar configuration of the imaging device 1 according to the above embodiment is shown. Figure 15 The planar configuration near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to the configuration described in the above embodiment. Figure 8 . Figure 16 The diagram schematically illustrates the configuration of the first wiring layer W1 and the various portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to the embodiments described above. Figure 9 . Figure 17 An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 18An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 19 An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0245] In this variation, such as Figure 16 As shown, in the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel-sharing unit 539 (e.g., the right side of the paper) has a configuration in which the internal layout of the other pixel-sharing unit 539 (e.g., the left side of the paper) is reversed only in the H direction. Furthermore, the displacement in the V direction between the outlines of one pixel-sharing unit 539 and the outlines of the other pixel-sharing unit 539 is greater than the displacement described in the above embodiment ( Figure 9 In this way, by increasing the shift in the V direction, the distance between the amplifying transistor AMP of the other pixel sharing unit 539 and its connecting pad 120 (the pad 120 of the other (on the lower side of the paper) of the two pixel sharing units 539 juxtaposed in the V direction shown in FIG. 7) can be reduced. With this arrangement, in Figures 15-19 In the modified example 1-1 of the imaging apparatus 1 shown, without reversing the planar layout of the two pixel-sharing units 539 juxtaposed along the H direction in the V direction, their area can be the same as that of the pixel-sharing units 539 of the second substrate 200 described in the above embodiment. Note that the planar layout of the pixel-sharing units 539 of the first substrate 100 is the same as the planar layout described in the above embodiment ( Figure 7A and Figure 7B The same applies. Therefore, the imaging apparatus 1 of this modified example can achieve effects similar to those described in the above embodiments. The configuration of the pixel sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above embodiments and this modified example.

[0246] [2.2. Variations 1-2]

[0247] Figures 20-25 This illustrates a variation of the planar configuration of the imaging device 1 according to the above-described embodiment. Figure 20 The planar configuration of the first substrate 100 is schematically shown, and corresponds to the configuration described in the above embodiments. Figure 7A . Figure 21 The planar configuration near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to the configuration described in the above embodiment. Figure 8 . Figure 22The diagram schematically illustrates the configuration of the first wiring layer W1 and the various portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to the embodiments described above. Figure 9 . Figure 23 An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 24 An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 25 An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0248] In this modified example, each pixel circuit 210 has a roughly square planar shape. Figure 21 (etc.). In this respect, the planar configuration of the imaging device 1 in this modified example differs from the planar configuration of the imaging device 1 described in the above embodiment.

[0249] For example, as described in the above embodiments, the pixel sharing units 539 of the first substrate 100 are formed on a two-row × two-column pixel area and have a generally square planar shape. Figure 20 For example, in each pixel sharing unit 539, the horizontal portion TGb of the transmission gates TG1 and TG3 of pixels 541A and 541C of one pixel column extends in the H direction toward the center of the pixel sharing unit 539 (more specifically, toward the outer edge of pixels 541A and 541C and toward the center of the pixel sharing unit 539) from the position where it overlaps with the vertical portion TGa, and the horizontal portion TGb of the transmission gates TG2 and TG4 of pixels 541B and 541D of another pixel column extends in the H direction toward the outside of the pixel sharing unit 539 (more specifically, toward the outer edge of pixels 541B and 541D and toward the outside of the pixel sharing unit 539) from the position where it overlaps with the vertical portion TGa. The pad portion 120 connected to the floating diffuser FD is provided in the central portion of the pixel sharing unit 539 (the central portion of the pixel sharing unit 539 in the H direction and V direction), and the pad portion 121 connected to the VSS contact area 118 is at least in the H direction (in Figure 20 The pixel sharing unit 539 is located at the end of the pixel sharing unit 539 in both the H and V directions.

[0250] As another configuration example, it is conceivable to set the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 only in the region facing the vertical portion TGa. In this case, as explained in the above embodiment, it is easy to finely divide the semiconductor layer 200S. Therefore, it is difficult to form large transistors in the pixel circuit 210. On the other hand, similar to the above variation, if the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 extend in the H direction from their position overlapping with the vertical portion TGa, then, similar to the above embodiment, the width of the semiconductor layer 200S can be increased. Specifically, the H-direction positions of the through electrodes TGV1 and TGV3 connected to the transmission gates TG1 and TG3 can be configured to be close to the H-direction position of the through electrode 120E, and the H-direction positions of the through electrodes TGV2 and TGV4 connected to the transmission gates TG2 and TG4 can be configured to be close to the through electrode 121E. Figure 22 Therefore, as explained in the above embodiment, the width (dimension in the H direction) of the semiconductor layer 200S extending in the V direction can be increased. Consequently, the size of the transistors in the pixel circuit 210, particularly the size of the amplifying transistor AMP, can be increased. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0251] The pixel sharing unit 539 of the second substrate 200 has, for example, substantially the same dimensions in the H and V directions as the pixel sharing unit 539 of the first substrate 100, and is disposed in a region corresponding to, for example, approximately two rows × two columns of pixel regions. For example, in each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side-by-side in the V direction on a semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are also arranged side-by-side in the V direction on a semiconductor layer 200S extending in the V direction. The semiconductor layer 200S on which the selection transistor SEL and the amplification transistor AMP are disposed and the semiconductor layer 200S on which the FD conversion gain switching transistor FDG and the reset transistor RST are disposed are juxtaposed in the H direction via an insulating region 212. The insulating region 212 extends in the V direction (…). Figure 21 ).

[0252] Here, we will refer to Figure 21 and Figure 22 The outline of the pixel sharing unit 539 of the second substrate 200 is described. For example, Figure 20 The pixel sharing unit 539 of the first substrate 100 shown is connected to one side of the pad portion 120 in the H direction. Figure 22The amplifying transistor AMP and the selecting transistor SEL (located on the left side of the paper) and the other side (located in the H direction of the pad section 120) Figure 22 The FD conversion gain switching transistor FDG and the reset transistor RST are located on the right side of the paper. The outline of the pixel sharing unit 539 of the second substrate 200, which includes the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST, is defined by the following four outer edges.

[0253] The first outer edge is at one end in the V direction of the semiconductor layer 200S, which includes the selection transistor SEL and the amplification transistor AMP. Figure 22 The outer edge is located at the upper end of the paper surface. The first outer edge is disposed on the amplifying transistor AMP included in the pixel sharing unit 539 and on one side in the V direction relative to the pixel sharing unit 539. Figure 22 The selection transistors SEL in adjacent pixel-sharing units 539 are located on the upper side of the paper. More specifically, the first outer edge is disposed at the center of the element isolation region 213 in the V direction between the amplifying transistor AMP and the selection transistor SEL. The second outer edge is located at the other end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP. Figure 22 The outer edge is located at the lower end of the paper surface. The second outer edge is disposed on the selection transistor SEL included in the pixel sharing unit 539 and on the other side in the V direction relative to the pixel sharing unit 539. Figure 22 The second outer edge is located between the amplifying transistors AMP in adjacent pixel-sharing units 539 (on the lower side of the paper). More specifically, the second outer edge is located at the center of the element isolation region 213 between the select transistor SEL and the amplifying transistor AMP in the V direction. The third outer edge is located at the other end of the semiconductor layer 200S, which includes the reset transistor RST and the FD conversion gain switching transistor FDG, in the V direction. Figure 22 The outer edge is located at the lower end of the paper surface. The third outer edge is disposed on the FD conversion gain switching transistor FDG included in the pixel sharing unit 539 and on the other side in the V direction relative to the pixel sharing unit 539. Figure 22 The third outer edge is located between the reset transistors RST in adjacent pixel-sharing units 539 (on the lower side of the paper). More specifically, the third outer edge is located at the center of the element isolation region 213 in the V direction between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is located at one end of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction. Figure 22The fourth outer edge is located at the upper end of the paper surface. The fourth outer edge is disposed on the reset transistor RST included in the pixel sharing unit 539 and on one side in the V direction relative to the pixel sharing unit 539. Figure 22 The fourth outer edge is located between the FD conversion gain switching transistor FDG (not shown) in the adjacent pixel sharing unit 539 (on the upper side of the paper). More specifically, the fourth outer edge is disposed at the center of the element isolation region 213 (not shown) in the V direction between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0254] In the outline of the pixel sharing unit 539 of the second substrate 200, which includes a first outer edge, a second outer edge, a third outer edge, and a fourth outer edge, the third and fourth outer edges are configured to be shifted to one side in the V direction (in other words, offset to one side in the V direction) relative to the first and second outer edges. By using such a layout, the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG can be configured as close as possible to the pad portion 120. Therefore, the area of ​​the wiring connecting the amplifying transistor AMP and the FD conversion gain switching transistor FDG is reduced, and the imaging device 1 can be easily miniaturized. Note that the VSS contact region 218 is disposed between the semiconductor layer 200S including the select transistor SEL and the amplifying transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, the multiple pixel circuits 210 have the same configuration as each other.

[0255] The imaging apparatus 1 having such a second substrate 200 can also achieve effects similar to those described in the above embodiments. The configuration of the pixel sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above embodiments and this variation.

[0256] [2.3. Variations 1-3]

[0257] Figures 26-31 This illustrates a variation of the planar configuration of the imaging device 1 according to the above-described embodiment. Figure 26 The planar configuration of the first substrate 100 is schematically shown, and corresponds to the configuration described in the above embodiments. Figure 7B . Figure 27 The planar configuration near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to the configuration described in the above embodiment. Figure 8 . Figure 28 The diagram schematically illustrates the configuration of the first wiring layer W1 and the various portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to the embodiments described above. Figure 9 . Figure 29An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 30 An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 31 An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0258] In this modified example, the semiconductor layer 200S of the second substrate 200 extends in the H direction ( Figure 28 That is, it basically corresponds to the above mentioned above. Figure 21 The imaging device 1 shown is configured with its plane rotated 90 degrees.

[0259] For example, as described in the above embodiments, the pixel sharing units 539 of the first substrate 100 are formed on a two-row × two-column pixel area and have a generally square planar shape. Figure 26 For example, in each pixel sharing unit 539, the transmission gates TG1 and TG2 of pixels 541A and 541B in one pixel row extend toward the center of the pixel sharing unit 539 in the V direction, and the transmission gates TG3 and TG4 of pixels 541C and 541D in another pixel row extend toward the outside of the pixel sharing unit 539 in the V direction. A pad portion 120 connected to the floating diffuser portion FD is provided at the center of the pixel sharing unit 539, and a pad portion 121 connected to the VSS contact area 118 extends at least in the V direction (in... Figure 26 The electrodes (TGV1 and TGV2) of the transmission gates TG1 and TG2 are positioned in the V direction and the H direction respectively, at the end of the pixel sharing unit 539. At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 are close to the V-direction position of the through electrode 120E, and the V-direction positions of the through electrodes TGV3 and TGV4 of the transmission gates TG3 and TG4 are close to the V-direction position of the through electrode 121E. Figure 28 Therefore, for reasons similar to those described in the above embodiments, the width (dimension in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. This allows for an increase in the size of the amplification transistor AMP and suppression of noise.

[0260] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL and the insulating region 212 in the V direction. Figure 27The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side-by-side in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction ( Figure 30 The fourth wiring layer W4 extends in the V direction. Figure 31 ).

[0261] The imaging apparatus 1 having such a second substrate 200 can also achieve effects similar to those described in the above embodiments. The configuration of the pixel sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above embodiments and modifications. For example, the semiconductor layer 200S described in the above embodiments and modifications 1-1 can extend in the H direction.

[0262] [2.4. Variations 1-4]

[0263] Figure 32 A modified example of the cross-sectional configuration of the imaging device 1 according to the above embodiment is shown schematically. Figure 32 Corresponding to the description in the above implementation scheme Figure 3 In this modified example, in addition to contact portions 201, 202, 301, and 302, the imaging device 1 also has contact portions 203, 204, 303, and 304 at a position facing the central portion of the pixel array unit 540. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above-described embodiment.

[0264] Contact portions 203 and 204 are disposed on the second substrate 200 and exposed on the mating surface with the third substrate 300. Contact portions 303 and 304 are disposed on the third substrate 300 and exposed on the mating surface with the second substrate. Contact portion 203 contacts contact portion 303, and contact portion 204 contacts contact portion 304. That is, in the imaging apparatus 1, in addition to contact portions 201, 202, 301, and 302, the second substrate 200 and the third substrate 300 are also connected by contact portions 203, 204, 303, and 304.

[0265] Next, we will refer to Figure 33 and Figure 34 Explain the operation of imaging device 1. Figure 33 In the diagram, the paths from external input to the input signal of imaging device 1, as well as the power supply potential and reference potential, are indicated by arrows. Figure 34In the diagram, the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by arrows. For example, the input signal input to the imaging device 1 via the input unit 510A is transmitted to the row driving unit 520 of the third substrate 300, and a row driving signal is created in the row driving unit 520. The row driving signal is sent to the second substrate 200 via contacts 303 and 203. Furthermore, the row driving signal reaches each pixel sharing unit 539 of the pixel array unit 540 via the row driving signal line 542 in the wiring layer 200T. In the row driving signal that has reached the pixel sharing unit 539 of the second substrate 200, the driving signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and drives pixels 541A, 541B, 541C and 541D. Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contacts 303 and 203, and supplied to each pixel circuit 210 of the pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via through electrode 121E. On the other hand, the pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 in each pixel sharing unit 539. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via vertical signal line 543 and contacts 204 and 304. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0266] The imaging device 1 having such contacts 203, 204, 303 and 304 can also achieve effects similar to those described in the above embodiment. The position and number of the contacts (wiring is connected to them via contacts 303 and 304) can be changed according to the design of the circuit of the third substrate 300.

[0267] [2.5. Variations 1-5]

[0268] Figure 35 A modified example of the cross-sectional configuration of the imaging device 1 according to the above embodiment is shown. Figure 35 Corresponding to the description in the above implementation scheme Figure 6In this modified example, a transmission transistor TR with a planar structure is disposed on the first substrate 100. In this respect, the imaging apparatus 1 of this modified example differs from the imaging apparatus 1 described in the above embodiments.

[0269] In the transfer transistor TR, the transfer gate TG only includes the horizontal portion TGb. In other words, the transfer gate TG does not have a vertical portion TGa and is positioned to face the semiconductor layer 100S.

[0270] Imaging apparatus 1 having a planar transmission transistor TR can also achieve effects similar to those described in the above embodiments. Furthermore, by providing a planar transmission gate TG on the first substrate 100, compared to providing a vertical transmission gate TG on the first substrate 100, it is conceivable that a photodiode PD can be formed closer to the front of the semiconductor layer 100S, thereby increasing the saturation signal quantity (Qs). Moreover, compared to the method of forming a vertical transmission gate TG on the first substrate 100, the method of forming a planar transmission gate TG on the first substrate 100 has fewer manufacturing steps, and it is also conceivable that adverse effects on the photodiode PD caused by manufacturing steps are less likely to occur.

[0271] [2.6. Variations 1-6]

[0272] Figure 36 A modified example of the pixel circuit of the imaging apparatus 1 according to the above embodiment is shown. Figure 36 Corresponding to the description in the above implementation scheme Figure 4 In this variation, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by multiple pixels. In this respect, the imaging apparatus 1 of this variation differs from the imaging apparatus 1 described in the above embodiments.

[0273] The imaging apparatus 1 of this modified example is similar to the imaging apparatus 1 described in the above embodiment in that the pixel unit 541A and the pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200). Therefore, the imaging apparatus 1 according to this modified example can also obtain effects similar to those described in the above embodiment.

[0274] [2.7. Variations 1-7]

[0275] Figure 37A modified example of the planar configuration of the pixel separation portion 117 described in the above embodiment is shown. A gap may be provided in the pixel separation portion 117 surrounding each of pixels 541A, 541B, 541C, and 541D. That is, the entire outer periphery of pixels 541A, 541B, 541C, and 541D may not be surrounded by the pixel separation portion 117. For example, the gap in the pixel separation portion 117 may be provided near pad portions 120 and 121 (see reference). Figure 7B ).

[0276] In the above embodiments, an example has been described of the pixel separation section 117 having an FTI structure that penetrates the semiconductor layer 100S (see reference). Figure 6 However, the pixel separation section 117 may have a configuration other than the FTI structure. For example, the pixel separation section 117 may not be configured to completely penetrate the semiconductor layer 100S, and may have a so-called deep trench isolation (DTI) structure.

[0277] [2.8. Variations 1-8]

[0278] On the other hand, in the embodiments described so far, the pixel circuit 210, including the amplifying transistor AMP, the reset transistor RST, and the select transistor SEL, has been described as a circuit disposed in the second substrate 200. In other words, in the embodiments described so far, the amplifying transistor AMP, the reset transistor RST, and the select transistor SEL are formed in the same substrate 200. However, in the embodiments of this disclosure, for example, two stacked substrates can be used instead of one second substrate 200. In this case, at least one transistor of the transistors included in the pixel circuit 210 can be disposed on one of the stacked substrates, and the remaining transistors can be disposed on the other substrate. Specifically, for example, a stacked lower substrate 2200A and upper substrate 2200B (see reference) can be used. Figure 38 A second substrate 200 is replaced by an interlayer insulating film 53 and wiring formed in the lower substrate 2200A, and an upper substrate 2200B is also stacked thereon. The upper substrate 2200B is stacked on the side of the lower substrate 2200A opposite to the surface facing the semiconductor substrate 11, and the desired transistor can be disposed on the upper substrate 2200B. As an example, an amplifying transistor AMP can be formed in the lower substrate 2200A, and a reset transistor RST and / or a select transistor SEL can be formed in the upper substrate 2200B.

[0279] Furthermore, in embodiments of this disclosure, three or more stacked substrates can be used instead of one second substrate 200. Thus, desired transistors, including those in the plurality of transistors in the pixel circuit 210, can be disposed in each stacked substrate. In this case, the type of transistor disposed in the stacked substrates is not limited.

[0280] As described above, by using multiple stacked substrates instead of a single second substrate 200, the area occupied by the pixel circuit 210 can be reduced. Furthermore, by reducing the area of ​​the pixel circuit 210 and miniaturizing the individual transistors, the area of ​​the chip constituting the imaging device 1 can be reduced. In this case, the area of ​​only the desired transistors in the amplification transistor AMP, reset transistor RST, and selection transistor SEL that can constitute the pixel circuit 210 can be increased. For example, noise can be reduced by increasing the area of ​​the amplification transistor AMP.

[0281] Reference Figures 38-43 Examples 1-8 illustrate variations in which two stacked substrates are used instead of a second substrate 200. Figures 38-40 This is a cross-sectional view in the thickness direction showing a configuration example of the imaging device 1B according to the modified examples 1-8 of the embodiment. Figures 41-43 This is a horizontal cross-sectional view showing an example of the layout of multiple pixel units PU according to variations 1-8 of the embodiment. Note that... Figures 38-40 The cross-sectional views shown are schematic diagrams only and are not intended to strictly and accurately illustrate the actual structure. Figures 38-40 In the cross-sectional view shown, the positions of the transistor and the impurity diffusion layer in the horizontal direction have been intentionally changed from position sec1 to position sec3 in order to easily illustrate the configuration of the imaging device 1B on paper.

[0282] Specifically, in Figure 38 In the pixel unit PU of the imaging device 1B shown, the cross-section at position sec1 is along... Figure 41 The cross-section taken from line A1-A1', the cross-section at position sec2 is along... Figure 42 The cross-section taken from line B1-B1', the cross-section at position sec3 is along... Figure 43 The cross-section intercepted by line C1-C1'. Similarly, in Figure 39 In the imaging device 1B shown, the cross-section at position sec1 is along... Figure 41 The cross-section taken from line A2-A2', the cross-section at position sec2 is along... Figure 42 The cross-section taken from line B2-B2', the cross-section at position sec3 is along... Figure 43 The cross-section intercepted by line C2-C2'. Figure 40 In the imaging device 1B shown, the cross-section at position sec1 is along... Figure 41 The cross-section taken from line A3-A3', the cross-section at position sec2 is along... Figure 42 The cross-section taken from line B3-B3', the cross-section at position sec3 is along... Figure 43 The cross section taken from line C3-C3'.

[0283] like Figure 39 and Figure 43 As shown, the imaging device 1B shares a common pad electrode 1020 arranged across multiple pixels 541 and a wiring L2 disposed on the common pad electrode 1020. For example, in the imaging device 1B, there exists a region where, in a plan view, the floating diffusers FD1 to FD4 of the four pixels 541 are adjacent to each other via the element separation layer 16. The common pad electrode 1020 is disposed in this region. The common pad electrode 1020 is arranged across the four floating diffusers FD1 to FD4 and is electrically connected to each of the four floating diffusers FD1 to FD4. The common pad electrode 1020 is, for example, made of a polycrystalline silicon film doped with n-type or p-type impurities.

[0284] A wiring L2 (i.e., a contact for the floating diffusion section) is provided at the center of the common pad electrode 1020. For example... Figure 39 and Figures 41-43 As shown, the wiring L2 provided on the center of the common pad electrode 1020 extends from the first substrate 10 through the lower substrate 2200A of the second substrate 20 to the upper substrate 2200B of the second substrate 20, and is connected to the gate electrode AG of the amplifying transistor AMP via wiring provided in the upper substrate 2200B.

[0285] In addition, such as Figure 38 and Figure 43 As shown, the imaging device 1B shares a common pad electrode 1100 configured across multiple pixels 541 and a wiring L10 disposed on the common pad electrode 1100. For example, in the imaging device 1B, there exists a region where, in a plan view, the respective well layers WE of the four pixels 541 are adjacent to each other via a component separation layer 16. The common pad electrode 1100 is disposed in this region. The common pad electrode 1100 is configured across the respective well layers WE of the four pixels 541 and is electrically connected to the respective well layers WE of the four pixels 541. As an example, the common pad electrode 1100 is configured between one common pad electrode 1020 and another common pad electrode 1020 configured in the Y-axis direction. In the Y-axis direction, the common pad electrodes 1020 and 1100 are alternately configured. The common pad electrode 1100 is, for example, made of a polycrystalline silicon film doped with n-type or p-type impurities.

[0286] A wiring L10 (i.e., a trap contact) is provided at the center of the common pad electrode 1100. For example... Figure 38 , Figure 40 and Figures 41-43 As shown, the wiring L10 provided on the center of the common pad electrode 1100 extends from the first substrate 10 through the lower substrate 2200A of the second substrate 20 to the upper substrate 2200B of the second substrate 20, and is connected to the reference potential line that supplies the reference potential (e.g., ground potential: 0V) via wiring provided in the upper substrate 2200B.

[0287] A wiring L10 disposed on the center portion of the common pad electrode 1100 is electrically connected to the top of the common pad electrode 1100, the inner surface of a via disposed in the lower substrate 2200A, and the inner surface of a via disposed in the upper substrate 2200B. Therefore, the well layer WE of the semiconductor substrate 11 of the first substrate portion 10, the well layer of the lower substrate 2200A of the second substrate portion 20, and the well layer of the upper substrate 2200B are connected to a reference potential (e.g., ground potential: 0V).

[0288] The imaging apparatus 1B according to this modification exhibits the same effects as the imaging apparatus 1 according to the embodiment of this disclosure described above. Furthermore, the imaging apparatus 1B includes common pad electrodes 1020 and 1100 disposed on the front 11a side of the semiconductor substrate 11 constituting the first substrate portion 10 and arranged adjacent to each other across a plurality of (e.g., four) pixels 541. The common pad electrode 1020 is electrically connected to the floating diffuser portion FD of the four pixels 541. The common pad electrode 1100 is electrically connected to the well layer WE of the four pixels 541. Accordingly, for each group of four pixels 541, the wiring L2 connected to the floating diffuser portion FD can be shared. For each group of four pixels 541, the wiring L10 connected to the well layer WE can be shared. Therefore, since the number of wirings L2 and L10 can be reduced, the area of ​​the pixels 541 can be reduced, and the size of the imaging apparatus 1B can be reduced.

[0289] <3. Second Implementation Plan>

[0290] Reference Figures 44-57 The imaging apparatus 1A according to the second embodiment is described below. The imaging apparatus 1A according to the second embodiment of this disclosure includes a plasma (process) induced damage (PID) protection element for preventing damage (PID) caused by plasma processes during manufacturing. Note that in the following description, the same content as in the first embodiment will not be described, and only the content different from the first embodiment will be described.

[0291] PID occurs when the wiring or through-electrode connected to the gate electrode of a transistor is used as an antenna in a plasma process. Specifically, PID occurs when charges in the plasma accumulate in the antenna and flow as current into the gate insulating film. Because PID creates defects or carrier trapping levels at the interface between the gate insulating film and the semiconductor substrate or within the gate insulating film, the threshold voltage of the transistor changes.

[0292] Therefore, in the second embodiment of this disclosure, PID protection elements are provided for each transistor (transfer transistor TR, selection transistor SEL, etc.) included in the imaging apparatus 1A. Thus, charge in the plasma can flow into the substrate via the PID protection elements instead of the gate insulating film, and changes in the threshold voltage of the transistors can be suppressed.

[0293] [3.1. Example of the functional configuration of imaging device 1A]

[0294] Here, we will refer to Figure 44 This section describes an example of the circuit configuration of an imaging device 1A equipped with a PID protection element. Figure 44 This is a diagram illustrating an example of the circuit configuration of the imaging apparatus 1A according to a second embodiment of the present disclosure. For example, Figure 44 This shows that the PID protection elements TF1-TF4 and TS1-TS3 are set at... Figure 4 The circuit configuration shown includes pixels 541A, 541B, 541C, and 541D, as well as the pixel circuit 210. Similarly, the PID protection element can be set up... Figure 36 In the other circuits shown. Note that, where it is not necessary to distinguish the PID protection elements TF1-TF4 and TS1-TS3 from each other, the identification numbers at the end of the reference numerals such as PID protection elements TF and TS are omitted.

[0295] like Figure 44 As shown, the gates of the transmission transistors TR1 to TR4 are connected to the row drive unit 520 via drivers DR1 to DR4, respectively.

[0296] The PID protection element TF is a device with a PN junction, and is, for example, a thyristor-type protection element or a bipolar protection element. One end of the PID protection element TF is connected to the gate of the transfer transistor TR, and the other end is grounded. The PID protection element TF protects the transfer transistor TR from plasma damage (PID) generated during plasma processing.

[0297] One end of the PID protection element TS1 is connected to the gate of the reset transistor RST, and the other end is grounded. PID protection element TS1 protects the reset transistor RST from PID. One end of the PID protection element TS2 is connected to the gate of the FD transfer transistor FDG, and the other end is grounded. PID protection element TS2 protects the FD transfer transistor FDG from PID. One end of the PID protection element TS3 is connected to the gate of the select transistor SEL, and the other end is grounded. PID protection element TS3 protects the select transistor SEL from PID. PID protection elements TS1 to TS3 are devices with a PN junction, and are, for example, thyristor-type protection elements or bipolar protection elements.

[0298] Note that a floating diffuser (not shown) temporarily holding the data captured by the photodiode PD is connected to the gate of the amplifying transistor AMP. The floating diffuser has a PN diode and functions to protect the amplifying transistor AMP from PID. As described above, when the floating diffuser with a PN diode is connected to the amplifying transistor AMP, the addition of a PID protection element for the amplifying transistor AMP can be omitted, and the increase in the chip area of ​​the imaging device 1A can be suppressed.

[0299] As described above, the PID protection elements TS1 to TS3 are protection elements for protecting the pixel transistors (in the embodiment, including the reset transistor RST, the FD transfer transistor FDG, and the select transistor SEL in the pixel transistor, excluding the amplification transistor AMP).

[0300] [3.2. Schematic structural example of imaging device 1A]

[0301] Reference Figures 45-47 A schematic structural example illustrating the imaging device 1A. Figure 45 This is a schematic longitudinal section view of imaging device 1A. Figure 46 This is a schematic structural example of the first substrate 100A. Figure 47 This is a schematic structural example showing the second substrate 200A. Note that... Figure 45 Schematic illustration along Figure 46 and Figure 47 The section formed by the line A-A' shown in the diagram. Furthermore, in Figures 45-47 For the sake of simplicity, details such as connecting holes H1 and H2 (see reference) have been omitted. Figure 2 A diagram that is part of a series of components such as )

[0302] like Figure 45As shown, the imaging device 1A includes a first substrate 100A, a second substrate 200A, and a third substrate 300A. The first substrate 100A to the third substrate 300A are formed in a stacked manner. Furthermore, the first substrate 100A and the second substrate 200A are semiconductor substrates having, for example, a device layer and a wiring layer formed of silicon (Si). The third substrate 300A is a semiconductor substrate on which logic circuits are formed. In addition, a multilayer wiring layer (not shown) is formed between the second substrate 200A and the third substrate 300A. The second substrate 200A and the third substrate 300A are connected to each other, for example, via a connection formed by copper-copper interconnects (CCC). The imaging device 1A, for example, receives incident light from... Figure 45 A rear-facing imaging device that enters from the lower side.

[0303] Note that in the following text, the stacking direction of the first substrate 100A, the second substrate 200A, and the third substrate 300A is also referred to as the Z-axis direction. Furthermore, the arrangement direction of the third substrate 300A in the Z-axis direction is defined as the positive direction of the Z-axis. Additionally, two directions orthogonal to each other on a plane (horizontal plane) perpendicular to the Z-axis direction are also referred to as the X-axis direction and the Y-axis direction, respectively.

[0304] Furthermore, in the following description, since pixels 541A, 541B, 541C and 541D are not distinguished from each other, each pixel is also referred to as pixel 5410.

[0305] like Figure 45 and Figure 46 As shown, the first substrate 100A is provided with an effective pixel area 151 and a dummy pixel area 152.

[0306] In the effective pixel region 151, for example, a matrix of effective pixels among a plurality of pixels 5410 are arranged. The effective pixel region 151 corresponds to the region in which an image of the subject is formed via an optical system (not shown), such as a lens, in the pixel array unit 540 of the imaging device 1A. That is, an image signal based on electrical signals read from the effective pixels in the effective pixel region 151 included in the pixel array unit 540 of the imaging device 1A is output from the imaging device 1A as an image capture result.

[0307] The dummy pixel region 152 is, for example, a region disposed around the effective pixel region 151 and shielded from light by metal or the like. Within the dummy pixel region 152, optical black (OPB) pixels and dummy pixels are provided among the plurality of pixels 5410. An OPB pixel is a pixel in which a transmission transistor TR is connected to the pixel circuit 210 among the plurality of pixels 5410, and is used, for example, to measure the level of a pixel signal that serves as a reference for correcting the black level. A dummy pixel is a pixel in which the transmission transistor TR is not connected to the pixel circuit 210 among the plurality of pixels 5410, and is disposed, for example, between the OPB pixel and the effective pixel. Therefore, for example, incident light leakage into the OPB pixel can be reduced.

[0308] In the dummy pixel region 152 on the light incident surface of the first substrate 100A, a light-shielding film 117C is formed to block incident light from the negative Z-axis direction.

[0309] like Figure 45 and Figure 47 As shown, the effective pixel transistor region 251, the OPB pixel transistor region 252, and the protection element region 253 are disposed in the second substrate 200A.

[0310] The effective pixel transistor region 251 is provided with an effective pixel circuit that outputs a pixel signal based on the charge output from the effective pixel in the pixel circuit 220. The OPB pixel transistor region 252 is provided with an OPB pixel circuit that outputs a pixel signal based on the charge output from the OPB pixel in the pixel circuit 220. In addition, the protection element region 253 is provided with PID protection elements TF and TS.

[0311] Note that the effective pixel transistor region 251 is disposed above the effective pixel region 151 in the Z-axis direction. Furthermore, the OPB pixel transistor region 252 and the protective element region 253 are disposed above the dummy pixel region 152 in the Z-axis direction. In other words, when viewed from the positive Z-axis direction, the effective pixel region 151 overlaps with the effective pixel transistor region 251, and the dummy pixel region 152 overlaps with the OPB pixel transistor region 252 and the protective element region 253.

[0312] [3.3. Specific configuration example of imaging device 1A]

[0313] Next, we will refer to Figure 48 and Figure 49 The following describes a specific configuration example of the imaging apparatus 1A according to the second embodiment of this disclosure. Figure 48 This is a diagram illustrating an example of the cross-sectional configuration of the imaging device 1A. Figure 49 This is a diagram illustrating an example of the planar configuration of the first substrate 100A and the second substrate 200A.

[0314] For ease of understanding, Figure 48 and Figure 49 The positional relationship of the constituent elements is schematically shown, and some constituent elements such as the third substrate 300A, light-receiving lens, color filter layer, and wiring layer are not shown. Furthermore, in Figure 49 The diagram of the insulating film is omitted. As mentioned above, Figure 48 and Figure 49 The cross-sectional and planar configurations shown may differ from the actual cross-sections and planes of the imaging device 1A. Note that in Figure 48 and Figure 49 In the diagram, solid lines represent the connections between the constituent elements. Furthermore, Figure 49 The above figure schematically shows a top view of the second substrate 200A, and Figure 49 The figure below schematically shows a top view of the first substrate 100A.

[0315] The first substrate 100A includes, for example, a semiconductor layer. In the semiconductor layer of the first substrate 100A, a plurality of active pixels 5411 are formed in the active pixel region 151. Furthermore, a plurality of OPB pixels 5412 and a plurality of dummy pixels 5413 are formed in the dummy pixel region 152. Since the configurations of each active pixel 5411, each OPB pixel 5412, and each dummy pixel 5413 are identical except for the presence or absence of wiring, the configuration of pixel 5410 will be described without distinguishing between them.

[0316] The photodiode PD of pixel 5410 includes, for example, an N-type semiconductor region 115A having a first substrate 100A and a P-type semiconductor region 114A formed to cover the N-type semiconductor region 115A. Note that each photodiode PD is electrically separated by a pixel separation section (not shown). A through contact C11 connected to an upper layer wiring (not shown) is provided in the P-type semiconductor region 114A of the effective pixel 5411 and the OPB pixel 5412. The P-type semiconductor region 114A of the photodiode PD is connected to the first P-type semiconductor region 2110F of the PID protection element TF via the through contact C11.

[0317] The first substrate 100A includes a transfer transistor TR having a gate electrode TGA and an N-type source region as a floating diffusion portion FD. The transfer transistor TR is configured as, for example, a metal-oxide-semiconductor (MOS) type field-effect transistor (MOSFET). A through contact C14 connected to an upper layer wiring (not shown) is provided in the gate electrode TGA of the transfer transistor TR. The gate electrode TGA is connected to the second N-type semiconductor region 2140F of the PID protection element TF via the through contact C14.

[0318] In the dummy pixel region 152 (the region in which OPB pixel 5412 and dummy pixel 5413 are formed) on the light incident surface of the first substrate 100A, a light-shielding film 117C is formed to block incident light from the negative Z-axis direction.

[0319] The second substrate 200A includes, for example, a semiconductor layer and a wiring layer (not shown). In the semiconductor layer of the second substrate 200A, an effective pixel circuit corresponding to the effective pixel 5411 is provided in the effective pixel transistor region 251. In the OPB pixel transistor region 252, an OPB pixel circuit corresponding to the OPB pixel 5412 is provided. PID protection elements TF and TS are provided in the protection element region 253.

[0320] Figure 48 and Figure 49 The select transistor SEL for the effective pixel circuit and the OPB pixel circuit is shown, but the amplification transistor AMP, the reset transistor RST, and the FD transfer transistor FDG are not shown.

[0321] Note that since the selection transistor SEL of the effective pixel circuit and the OPB pixel circuit has the same configuration, the configuration of the selection transistor SEL will be described without distinguishing between the effective pixel circuit and the OPB pixel circuit. Furthermore, to distinguish the components of the PID protection elements TF and TS from each other, an identification symbol F is appended to the end of the symbol of the component of the PID protection element TF, and an identification symbol S is appended to the end of the symbol of the component of the PID protection element TS. When it is not necessary to distinguish the components of the PID protection elements TF and TS from each other, the identification symbols at the end of the symbols of the components of the PID protection elements TF and TS are omitted.

[0322] The selector transistor SEL includes an N-type source region 233 and an N-type drain region 232 disposed in a P-type semiconductor region 231 of the second substrate 200A. The gate electrode 234 of the selector transistor SEL is disposed on the second substrate 200A between the source region 233 and the drain region 232. A contact C12 connected to an upper layer wiring (not shown) is disposed in the P-type semiconductor region 231. The P-type semiconductor region 231 is connected to the P-type semiconductor region 2110S of the PID protection element TS via the contact C12. A contact C13 connected to the upper layer wiring (not shown) is disposed in the gate electrode 234. The gate electrode 234 is connected to the second N-type semiconductor region 2140S of the PID protection element TS via the contact C13.

[0323] The PID protection elements TF and TS disposed in the protection element region 253 of the second substrate 200A have, for example, a first P-type semiconductor region 2110, a first N-type semiconductor region 2120, a second P-type semiconductor region 2130, and a second N-type semiconductor region 2140 arranged sequentially in the positive X-axis direction. As described above, the PID protection elements TF and TS are disposed in the horizontal direction of the second substrate 200A ( Figure 48 and Figure 49 It has a PN-PN junction structure in the X-axis direction.

[0324] Note that the PID protection elements TF and TS can have an NP-NP junction structure instead of a PN-PN junction structure. Furthermore, the first P-type semiconductor region 2110, the first N-type semiconductor region 2120, the second P-type semiconductor region 2130, and the second N-type semiconductor region 2140 can be arranged side-by-side (in the horizontal direction) on the horizontal plane of the second substrate 200A, and can, for example, have a PN-PN junction structure in the Y-axis direction.

[0325] When the first substrate 100A to the third substrate 300A are stacked, the thickness (length in the stacking direction) of the imaging device 1A increases. Therefore, there is a need to reduce the thickness of each substrate. In particular, as with substrates stacked on top of substrates, there is a need to reduce the thickness of the substrates. Therefore, in the second embodiment of this disclosure, the first P-type semiconductor region 2110, the first N-type semiconductor region 2120, the second P-type semiconductor region 2130, and the second N-type semiconductor region 2140 of the PID protection elements TF and TS are arranged side-by-side on the horizontal plane of the second substrate 200A. Therefore, the thickness of the PID protection elements TF and TS can be reduced, and the thickness of the second substrate 200A can also be reduced.

[0326] [3.4. Example of manufacturing process for imaging device 1A]

[0327] Next, we will refer to Figures 50-55 An example of the manufacturing process of the imaging apparatus 1A according to the second embodiment of this disclosure is provided. Figures 50-55 This is a flowchart illustrating an example of the manufacturing process of the imaging apparatus 1A according to a second embodiment of this disclosure. Note that... Figures 50-55 A portion of the cross-section of the imaging device 1A is shown.

[0328] like Figure 50 As shown, a photodiode PD including an N-type semiconductor region 115A and a P-type semiconductor region 114A, a gate electrode TGA of a transmission transistor TR, and a source region serving as a floating diffusion portion FD are formed in a first substrate 100A. The gate electrode TGA and the floating diffusion portion FD are covered by an insulating film 140.

[0329] Next, as Figure 51 As shown, a first substrate 100A and a second substrate 200A, such as a P-type silicon substrate, are bonded together. At this time, a pressure of 0.1 MPa to several MPa is applied, and heat treatment is performed at approximately 350°C to 600°C. As a result, the first substrate 100A and the second substrate 200A are bonded together via an insulating film 140. Note that before the first substrate 100A and the second substrate 200A are bonded together, both the bonding surfaces of the first substrate 100A and the second substrate 200A can be subjected to O2 plasma treatment.

[0330] Subsequently, as Figure 52 As shown, the second substrate 200A is polished to a thickness of a few micrometers to a few micrometers using chemical mechanical polishing (CMP), and component separation is performed on the second substrate 200A while retaining the areas 2100 in which pixel circuits such as select transistors (SELs) and PID protection elements (TF and TS) are formed. Specifically, a resist pattern is formed in the areas in which the pixel circuits and PID protection elements (TF and TS) are formed by photolithography, and other areas are etched by dry etching. After the resist pattern is ashed, an insulating film 240, such as a silicon oxide film, is formed by CVD, and the portions removed by etching are backfilled using the second substrate 200A. Excess insulating film 240 is removed by CMP to expose the front side of the second substrate 200A.

[0331] like Figure 53 As shown, a selective transistor (SEL) and PID protection elements TF and TS are formed in a second substrate 200A. Specifically, a gate oxide film is formed on the front side of the second substrate 200A by thermal oxidation. A polysilicon film is formed by CVD, a resist pattern is formed by photolithography, the polysilicon film is etched, and the resist pattern is ashed to form a gate electrode 234. Phosphorus or arsenic is implanted into the second substrate 200A on both sides of the gate electrode 234 by ion implantation, and a rapid thermal annealing (RTA) is performed to form a source region 233 and a drain region 232. Similarly, phosphorus or arsenic is implanted into the region 2100 of the second substrate 200A in which the PID protection elements TF and TS are formed by ion implantation, and a rapid thermal annealing (RTA) is performed to form a first P-type semiconductor region 2110 and a second P-type semiconductor region 2130, as well as a first N-type semiconductor region 2120 and a second N-type semiconductor region 2140. As a result, the PID protection elements TF and TS are formed. Note that the source region 233, the drain region 232, and the PID protection elements TF and TS are formed through simultaneous processing.

[0332] like Figure 54As shown, through-holes T21 to T26 are formed. Specifically, an insulating film 240 covering the select transistor SEL is further formed by CVD, and the front surface of the insulating film 240 is planarized by CMP. A resist pattern is formed on the front surface of the insulating film 240 by photolithography, and through-holes T21 to T26 reaching the N-type semiconductor region 115A, the gate electrode TGA, the P-type semiconductor region 231, the gate electrode 234, the first P-type semiconductor region 2110, and the second N-type semiconductor region 2140 are formed by dry etching.

[0333] Next, as Figure 55 As shown, after forming through holes T21 to T26, each through hole is filled with a W film or the like using CVD, and excess W film is removed by CMP to form contact portions C11 to C16. Then, wirings M1 to M5 are formed, and a third substrate 300A, in which logic circuits are formed, is bonded, thus completing the manufacturing process of the imaging device 1A.

[0334] [3.5. Comparative Example]

[0335] Reference Figure 56 and Figure 57 The configuration of the comparative example is compared with the configuration of the second implementation scheme. Figure 56 This is a diagram showing the imaging apparatus 1a according to the comparative example. Figure 56 The difference between the imaging device 1a shown and the second embodiment is that the effective pixel region 101a, the dummy pixel region 102a and the pixel circuit 210a are formed in a substrate 100a. Figure 57 This is a diagram showing the imaging apparatus 1b according to the comparative example. Figure 57 The imaging device 1b shown is similar to the second embodiment in that the effective pixel region 101b, the dummy pixel region 102b, and the pixel circuit 210b are formed on different substrates, but the layout of the PID protection elements TF and TS is different. Note that in Figure 56 and Figure 57 The illustration of the substrate in which the logic circuits are formed is omitted.

[0336] like Figure 56As shown, when the effective pixel region 101a, the dummy pixel region 102a (hereinafter referred to as the pixel region), and the pixel circuit 210a are formed in a substrate 100a, for example, the dummy pixel region 102a is disposed around the effective pixel region 101a, and further, the pixel circuit 210a is disposed around the dummy pixel region 102a. When the PID protection elements TF and TS are further disposed in the substrate 100a, for example, the protection element region 253a1 of the PID protection element TF for forming the protection transmission transistor TR is disposed near the pixel region of the substrate 100a. Furthermore, the protection element region 253a2 of the PID protection element TS for forming each transistor of the pixel circuit 210a is disposed near the pixel circuit 210a. As described above, when the PID protection elements TF and TS are formed, from the perspective of wiring arrangement, the PID protection elements TF and TS are generally disposed near the transistor to be protected.

[0337] However, when the pixel 5410, pixel circuit 210a, and PID protection elements TF and TS are formed in a substrate 100a, the chip area of ​​the imaging device 1a increases.

[0338] Therefore, for example, as Figure 57 The imaging device 1b shown can be conceived to reduce the chip area by stacking a first substrate 100b to form the pixel 5410 and a second substrate 200b to form the pixel circuit 210b.

[0339] Here, as described above, when PID protection elements TF and TS are formed, from the perspective of wiring arrangement, the PID protection elements TF and TS are typically positioned near the transistor to be protected. Therefore, when the first substrate 100b forming the pixel 5410 and the second substrate 200b forming the pixel circuit 210b are separated, as... Figure 57 As shown, the PID protection element TF for protecting the transmission transistor TR is disposed in the protection element region 253b1 of the first substrate 100b, and the PID protection element TS for protecting each transistor of the pixel circuit 210b is disposed in the protection element region 253b2 of the second substrate 200b.

[0340] In this configuration, the protective element region 253b1 of the first substrate 100b is disposed around the dummy pixel region 102b. Therefore, the protective element region 253b2 of the second substrate 200b is disposed around the pixel circuit 210b, and the chip area increases by the area of ​​the protective element regions 253b1 and 253b2. As described above, the increase in chip area cannot be suppressed by simply stacking substrates.

[0341] In the imaging apparatus 1A according to the second embodiment of this disclosure, a first substrate 100A in which pixels 5410 are formed and a second substrate 200A in which pixel circuits 210 are formed are stacked. Considering that the pixel circuits 210 corresponding to dummy pixels 5423 are not formed in the second substrate 200A, PID protection elements TF and TS are formed in the region (empty region) of the second substrate 200A in which the pixel circuits 210 are not formed. In this way, in the second substrate 200A, not only the PID protection elements TS protecting each transistor of the pixel circuits 210, but also the PID protection elements TF protecting the transmission transistors TR are formed in the empty region of the second substrate 200A. In other words, by forming the PID protection elements TF in a second substrate 200A, which is different from the first substrate 100A in which the transmission transistors TR to be protected are formed, the area of ​​the first substrate 100A can be reduced, and the increase in the chip area of ​​the imaging apparatus 1A can be suppressed.

[0342] <4. Variations>

[0343] [4.1. Variation Example 2-1]

[0344] Reference Figure 58 This section describes a variation of the PID protection elements TF and TS of the imaging apparatus 1A according to the second embodiment. Figure 58 This is a schematic diagram illustrating a variation of the PID protection elements TF and TS.

[0345] The PID protection elements TF and TS of this modification include two first N-type semiconductor regions 2120a and 2120b. The two first N-type semiconductor regions 2120a and 2120b are connected to each other by wiring. In this respect, the configuration of the PID protection elements TF and TS of this modification differs from that of the PID protection elements TF and TS described in the second embodiment.

[0346] As described above, even when the first N-type semiconductor region 2120 is divided into two and connected by wiring, the same effect as that described in the second embodiment can be obtained. Furthermore, by dividing the semiconductor region, the PID protection elements TF and TS can be configured in the vacant space of the second substrate 200A, increasing the freedom of element layout and suppressing the increase in chip area.

[0347] Note that the case where the first N-type semiconductor region 2120 is divided into two has been described here, but this disclosure is not limited thereto. For example, the first P-type semiconductor region 2110, the second P-type semiconductor region 2130, and the second N-type semiconductor region 2140 can be divided into two. Furthermore, the number of divisions is not limited to two, and can be three or more.

[0348] [4.2. Variation Example 2-2]

[0349] Reference Figure 59 This section describes a variation of the PID protection elements TF and TS of the imaging apparatus 1A according to the second embodiment. Figure 59 This is a schematic diagram illustrating a variation of the PID protection elements TF and TS.

[0350] In this modified example, the PID protection elements TF and TS have a triple-well structure with a PNP junction. Figure 59 In the example shown, the first N-type semiconductor region 2120 is disposed in the second P-type semiconductor region 2130, and the first P-type semiconductor region 2110 is disposed in the first N-type semiconductor region 2120. In this respect, the configuration of the PID protection elements TF and TS in this variant differs from the configuration of the PID protection elements TF and TS described in the second embodiment. As described above, even when the PID protection elements TF and TS have a triple-well structure with a PNP junction, the same effect as described in the second embodiment can be obtained.

[0351] Note that the case of PID protection elements TF and TS with a triple-well structure having a PNP junction has been described here, but this disclosure is not limited thereto. For example, PID protection elements TF and TS can have a triple-well structure with an NPN junction.

[0352] [4.3. Variations 2-3]

[0353] Reference Figures 60-65 This section describes a variation of the PID protection elements TF and TS of the imaging apparatus 1A according to the second embodiment. Figures 60-65 This is a schematic diagram illustrating a variation of the PID protection elements TF and TS.

[0354] In this modified example, the PID protection elements TF and TS have a double-well structure with a PNP junction. Figure 60 In the example shown, the second N-type semiconductor region 2140 is disposed above the second P-type semiconductor region 2130. Figure 61 In the example shown, the first P-type semiconductor region 2110 is disposed above the first N-type semiconductor region 2120. Figure 62 In the example shown, the second N-type semiconductor region 2140 is disposed above the second P-type semiconductor region 2130, and the first P-type semiconductor region 2110 is disposed above the first N-type semiconductor region 2120.

[0355] Optionally, such as Figures 63-65As shown, the first P-type semiconductor region 2110 and / or the second N-type semiconductor region 2140 may be disposed on the lower layer of the first N-type semiconductor region 2120 and / or the second P-type semiconductor region 2130.

[0356] As described above, the difference between the configuration of the PID protection elements TF and TS in this modified example and that in the second embodiment is the provision of a double-well structure in which a second conductivity type (N-type or P-type) well is formed in the upper or lower layer of the first conductivity type (P-type or N-type) well. As described above, even when the PID protection elements TF and TS have a double-well structure, the same effect as described in the second embodiment can be obtained.

[0357] [4.4. Variations 2-4]

[0358] Reference Figure 66 A variation of the imaging device 1A according to the second embodiment is described. Figure 66 This is a schematic diagram illustrating a modified example of the imaging device 1A. Figure 66 This is a schematic longitudinal sectional view of the imaging device 1A, and corresponds to the one described in the second embodiment. Figure 48 .

[0359] In this modified example, the PID protection elements TF and TS are disposed in the first substrate 100A and the second substrate 200A of the imaging device 1A. In this respect, the configuration of the imaging device 1A differs from that described in the second embodiment. Figure 66 In this circuit, a PID protection element TF for protecting the transmission transistor TR is formed in the first substrate 100A, and a PID protection element TS for protecting each transistor of the pixel circuit 210 is formed in the second substrate 200A. Here, for example, the PID protection element TF has a triple-well structure with an NPN junction.

[0360] For example, suppose that when the number of components formed in the second substrate 200A (e.g., the number of transistors in the pixel circuit 210) is large and the PID protection elements TF and TS are formed in the second substrate 200A, the area of ​​the second substrate 200A becomes larger than the area of ​​the first substrate 100A. In this case, the PID protection elements TF and TS are respectively disposed in the first substrate 100A and the second substrate 200A, such that the area of ​​the first substrate 100A is substantially equal to the area of ​​the second substrate 200A. Therefore, the increase in the chip area of ​​the imaging device 1A can be suppressed.

[0361] Note that in Figure 66In this embodiment, a PID protection element TF for protecting the transmission transistor TR is formed in the first substrate 100A, and a PID protection element TS for protecting each transistor of the pixel circuit 210 is formed in the second substrate 200A; however, this disclosure is not limited thereto. The PID protection elements TF and TS can be configured such that the difference between the area of ​​the first substrate 100A and the area of ​​the second substrate 200A is reduced according to the number of transistors (number of elements) formed in the imaging apparatus 1A or the area of ​​the substrate required for the element formation. For example, a portion of the PID protection element TS for protecting each transistor of the pixel circuit 210 can be formed in the first substrate 100A, and a portion of the PID protection element TF for protecting the transmission transistor TR can be formed in the second substrate 200A.

[0362] [4.5. Variations 2-5]

[0363] Reference Figure 67 A variation of the imaging device 1A according to the second embodiment is described. Figure 67 This is a schematic diagram illustrating a modified example of the imaging device 1A. Figure 67 This is a schematic longitudinal sectional view of the imaging device 1A, and corresponds to the one described in the second embodiment. Figure 48 .

[0364] In this modified example, the PID protection elements TF and TS are disposed in the first substrate 100A of the imaging device 1A. In this respect, the configuration of the imaging device 1A differs from that described in the second embodiment. Figure 67 In this circuit, the PID protection element TF for protecting the transmission transistor TR and the PID protection elements TS for protecting each transistor in the pixel circuit 210 are both formed in the first substrate 100A. Here, for example, a first N-type semiconductor region 2120 is formed in the first P-type semiconductor region 2110 of the PID protection elements TF and TS, and a second P-type semiconductor region 2130 is formed in the first N-type semiconductor region 2120. A second N-type semiconductor region 2140 is formed in the second P-type semiconductor region 2130. Furthermore, the PID protection elements TF and TS share the first P-type semiconductor region 2110.

[0365] For example, suppose that when the number of components formed in the second substrate 200A (e.g., the number of transistors in the pixel circuit 210) is large and the PID protection elements TF and TS are formed in the second substrate 200A, the area of ​​the second substrate 200A becomes larger than the area of ​​the first substrate 100A. In this case, the PID protection elements TF and TS are arranged in the first substrate 100A such that the area of ​​the first substrate 100A is substantially equal to the area of ​​the second substrate 200A. In this way, the PID protection elements TF and TS are configured such that the difference between the area of ​​the first substrate 100A and the area of ​​the second substrate 200A is reduced according to the number of transistors (number of components) formed in the imaging device 1A or the area of ​​the substrate required for component formation. Therefore, the increase in the chip area of ​​the imaging device 1A can be suppressed.

[0366] Note that, for example, in the case where multiple semiconductor substrates are stacked in place of the second substrate 200 (see variations 1-8), the PID protection elements TF and TS according to the second embodiment described above and its variations 2-1 to 2-5 can be provided on the multiple semiconductor substrates of the second substrate 200.

[0367] <5. Application Examples>

[0368] The technology according to the second embodiment and its variations can be applied to a variety of products. For example, the technology can be applied to semiconductor memories such as dynamic random access memory (DRAM) or static random access memory (SRAM) or semiconductor devices such as system-on-a-chip (SoC).

[0369] Figure 68 This is a diagram used to illustrate an example applied to semiconductor memory (DRAM). Figure 68 In the example, a System-on-a-Chip (SoC), such as a memory controller, is configured in the first substrate 100A, and a DRAM, such as a memory array, is configured in the second substrate 200A. In this case, when a PID protection element is provided to protect the transistors formed in the SoC or DRAM from PID, such as... Figure 68 As shown, PID protection elements TF and TS are respectively disposed in the protection element regions 253 of the first substrate 100A and the second substrate 200A. At this time, by disposing PID protection elements TF and TS in the first substrate 100A and the second substrate 200A, the areas of the first substrate 100A and the second substrate 200A are substantially equal to each other, which can suppress the increase in the chip area of ​​the semiconductor memory.

[0370] In addition, such as Figure 69 As shown, it is also possible to apply it to SoC. Figure 69 This is a diagram used to illustrate application examples of a SoC. In Figure 69In this configuration, the first substrate 100A is a SoC using NMOS, and the second substrate 200A is a SoC using PMOS. As described above, in the case of stacked SoCs, when a PID protection element is provided to protect the transistors formed in the first substrate 100A and the second substrate 200A from PID, such as... Figure 69 As shown, the protection element regions 253 forming the PID protection elements TF and TS are respectively disposed in the first substrate 100A and the second substrate 200A. At this time, by disposing the PID protection elements TF and TS in the first substrate 100A and the second substrate 200A, the areas of the first substrate 100A and the second substrate 200A are substantially equal to each other, which can suppress the increase in the chip area of ​​the semiconductor memory.

[0371] Note that while the case where the protective element region 253 is disposed in each of the first substrate 100A and the second substrate 200A has been described here, this disclosure is not limited thereto. The protective element region 253 may be disposed in at least one of the first substrate 100A and the second substrate 200A. Furthermore, the number of substrates to be stacked is two, but this disclosure is not limited thereto. The number of substrates to be stacked may be three or more. In this case, a semiconductor element (e.g., a transistor) having a gate electrode is formed in at least one of the multiple substrates, and a PID protective element protecting the semiconductor element is formed in at least one of the multiple substrates.

[0372] As described above, the technology according to the second embodiment and its variations can be applied not only to imaging devices but also to semiconductor devices such as semiconductor memories.

[0373] <6. Application Examples>

[0374] [6.1. Examples of Application of Imaging Systems]

[0375] Figure 70 An example of a schematic configuration of an imaging system 7 including an imaging device 1 (1A) according to an embodiment and its variations is shown.

[0376] Imaging system 7 is, for example, an electronic device, such as an imaging device like a digital camera or camcorder, or a portable terminal device like a smartphone or tablet computer. Imaging system 7 includes, for example, an imaging device 1, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248, according to embodiments and variations thereof. In imaging system 7, the imaging device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, operation unit 247, and power supply unit 248 are interconnected via bus 249.

[0377] The imaging apparatus 1 (1A) according to the embodiment and its modifications outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging apparatus 1 according to the embodiment and its modifications. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in frames. The display unit 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays moving or still images captured by the imaging apparatus 1 according to the embodiment and its modifications. The storage unit 246 stores the image data of the moving or still images captured by the imaging apparatus 1 according to the embodiment and its modifications in a storage medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to user operations. The power supply unit 248 appropriately supplies various power sources to these supply targets as operating power sources for the imaging apparatus 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to the embodiment and its modifications.

[0378] Next, the imaging steps in imaging system 7 will be explained.

[0379] Figure 71 An example of the imaging operation flow in imaging system 7 is shown. The user gives an instruction to start imaging through operation unit 247 (step S101). Then, operation unit 247 sends an imaging instruction to imaging device 1 (step S102). When the imaging instruction is received, imaging device 1 (specifically, system control circuit 36) performs imaging in a predetermined imaging mode (step S103).

[0380] Imaging device 1 outputs image data obtained through imaging to DSP circuit 243. Here, the image data is data of all pixels based on pixel signals generated by charges temporarily held in the floating diffuser FD. DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from imaging device 1 (step S104). DSP circuit 243 causes frame memory 244 to hold the image data after predetermined signal processing, and frame memory 244 causes storage unit 246 to store the image data (step S105). In this way, imaging in imaging system 7 is performed.

[0381] In applicable examples, the imaging device 1 according to the embodiments and their variations is suitable for the imaging system 7. Therefore, since the imaging device 1 can be miniaturized or have high resolution, a small or high-definition imaging system 7 can be provided.

[0382] [6.2. Application Examples of Product Systems]

[0383] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0384] [6.2.1. Mobile Body Control System]

[0385] Figure 72 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to this disclosure is applicable.

[0386] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 72 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0387] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a drive force generating device such as an internal combustion engine or drive motor to generate drive force for the vehicle, a drive force transmission mechanism to transmit drive force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a control device to generate braking force for the vehicle.

[0388] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used to replace buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0389] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing such as people, cars, obstacles, signs, and text on the road, or distance detection processing based on the received images.

[0390] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image or as ranging information. Furthermore, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0391] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041, which detects the driver's state, is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0392] For example, the microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of advanced driver assistance systems (ADAS), including collision avoidance or mitigation, distance-based tracking, speed maintenance, collision warning, and lane departure warning.

[0393] Furthermore, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, in order to achieve autonomous driving, where the vehicle drives itself without relying on the driver's operation.

[0394] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the exterior of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can coordinate the control of the headlights according to the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030 to achieve glare prevention, such as switching the high beams to low beams.

[0395] The audio / image output unit 12052 transmits at least one of the audio and image output signals to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle. Figure 72 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0396] Figure 73 This is a diagram showing an example of the mounting location of the imaging unit 12031.

[0397] exist Figure 73 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are included as imaging units 12031.

[0398] Imaging units 12101, 12102, 12103, 12104, and 12105 are positioned, for example, at the front of vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Imaging unit 12101, positioned at the front of the vehicle, and imaging unit 12105, positioned at the upper part of the windshield inside the vehicle, primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103, positioned at the side mirrors, primarily acquire images of the sides of vehicle 12100. Imaging unit 12104, positioned at the rear bumper or rear door, primarily acquires images of the rear of vehicle 12100. The front images acquired by imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0399] also, Figure 73An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front of the vehicle; imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively; and imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 as seen from above is obtained.

[0400] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0401] For example, based on distance information obtained from imaging units 12101 to 12104, by obtaining the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to vehicle 12100), microcomputer 12051 extracts the closest three-dimensional object on the driving path of vehicle 12100, and identifies the three-dimensional object traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher) as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-defined distance between vehicles for the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. As described above, coordinated control for autonomous driving, etc., can be performed, in which the vehicle drives autonomously without relying on driver operation.

[0402] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify three-dimensional object data into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, extract the three-dimensional object data, and use the three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult to visually recognize. Then, microcomputer 12051 determines the collision risk indicating the degree of danger of colliding with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, it can provide driving assistance for collision avoidance by outputting a warning to the driver via audio speaker 12061 and display unit 12062 or by performing forced deceleration or evasive steering via drive system control unit 12010.

[0403] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 causes the display unit 12062 to overlay and display a quadrilateral outline for emphasis on the identified pedestrian. Furthermore, the audio / image output unit 12052 can cause the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0404] Examples of mobile body control systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure is applicable to the imaging unit 12031 in the above configuration. Specifically, the imaging apparatus 1 according to the embodiment and its modifications can be applied to the imaging unit 12031. Since a high-definition captured image with very little noise can be obtained by applying the technology according to this disclosure to the imaging unit 12031, high-precision control can be performed using the captured image in the mobile body control system.

[0405] [6.2.2. Endoscopic Surgical System]

[0406] Figure 74 This is a diagram illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology (the present technology) can be applied.

[0407] Figure 74 This illustration shows a surgeon (physician) 11131 using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on bed 11133. Figure 74 As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 supporting the endoscope 11100, and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0408] Endoscope 11100 includes a lens tube 11101 in which a region of a predetermined distance from the distal end is inserted into a body cavity of patient 11132, and a camera 11102 connected to the proximal end of the lens tube 11101. In the example shown, an endoscope 11100 configured as a so-called rigid endoscope with a rigid lens tube 11101 is shown, but endoscope 11100 can be configured as a so-called flexible endoscope with a flexible lens tube.

[0409] The opening into which the objective lens is mounted is located at the distal end of the lens tube 11101. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the distal end of the lens tube via a light guide extending into the lens tube 11101, and emitted via the objective lens toward the object being observed within the body cavity of the patient 11132. Note that the endoscope 11100 can be a direct-viewing endoscope, an oblique-viewing endoscope, or a lateral-viewing endoscope.

[0410] An optical system and imaging element are housed inside the camera 11102, and reflected light from the observed object (observation light) is converged onto the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0411] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrates the operation of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives image signals from the camera 11102 and performs various image processing on the image signals, such as image processing (de-mosaic processing), for displaying images based on the image signals.

[0412] The display device 11202 displays an image based on the image signal processed by the CCU 11201 under the control of the CCU 11201.

[0413] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light for imaging surgical sites to the endoscope 11100.

[0414] Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various information and commands into endoscopic surgical system 11000 via input device 11204. For example, users can input commands through endoscope 11100 to change imaging conditions (type of illumination light, magnification, focal length, etc.).

[0415] The treatment device control unit 11205 controls the drive of the energy treatment device 11112 for purposes such as tissue cauterization and incision, and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the patient's body cavity 11132 via the pneumoperitoneum tube 11111 to inflate the patient's body cavity, ensuring the field of vision of the endoscope 11100 and ensuring the surgeon's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, and graphics.

[0416] Note that the light source device 11203, which supplies illumination light to the endoscope 11100 for imaging the surgical site, may include, for example, an LED, a laser light source, or a white light source comprising a combination thereof. When the white light source is constructed using a combination of RGB laser light sources, the white balance of the captured image can be adjusted within the light source device 11203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. Furthermore, in this case, by illuminating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the driving of the imaging element of the camera 11102 in synchronization with the illumination timing, images corresponding to each of the RGB can also be captured in a time-division manner. According to this method, a color image can be obtained without a color filter in the imaging element.

[0417] Furthermore, the drive of the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined intervals. By controlling the drive of the imaging element of the camera 11102 in time-segmented synchronization with the change in light intensity to acquire and synthesize images, high dynamic range images without so-called underexposed shadows and overexposed highlights can be generated.

[0418] Furthermore, the light source device 11203 can be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow-band light observation (narrow-band imaging) is performed, where predetermined tissues, such as blood vessels in the mucosal surface, are imaged with high contrast by using light in a narrower band than the illumination light used in ordinary observation (i.e., white light) by utilizing the wavelength dependence of light absorption in body tissue. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by irradiating fluorescence generated by excitation light. In fluorescence observation, for example, body tissue can be irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to this special light observation.

[0419] Figure 75 It is shown Figure 74 The block diagram shown illustrates an example of the functional configuration of the camera 11102 and CCU 11201.

[0420] Camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are communicatively connected to each other via a transmission cable 11400.

[0421] Lens unit 11401 is an optical system disposed at the connection portion with lens barrel 11101. Observation light received from the distal end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 is constructed by combining multiple lenses, including zoom lenses and focal lenses.

[0422] Imaging unit 11402 includes imaging elements. The number of imaging elements constituting imaging unit 11402 can be a single element (so-called single-plate type) or multiple elements (so-called multi-plate type). When imaging unit 11402 is configured as multi-plate type, for example, an image signal corresponding to each RGB can be generated by each imaging element, and a color image can be obtained by combining the image signals. Alternatively, imaging unit 11402 may include a pair of imaging elements for acquiring image signals for the right and left eyes corresponding to three-dimensional (3D) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of body tissue in the surgical site. Note that when imaging unit 11402 is configured as multi-plate type, multiple lens units 11401 corresponding to each imaging element can be provided.

[0423] Furthermore, the imaging unit 11402 does not necessarily have to be located within the camera 11102. For example, the imaging unit 11402 can be located directly behind the objective lens inside the lens barrel 11101.

[0424] The drive unit 11403 includes an actuator that, under the control of the camera control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0425] Communication unit 11404 includes communication means for transmitting and receiving various information to / from CCU 11201. Communication unit 11404 transmits image signals acquired from imaging unit 11402 as RAW data to CCU 11201 via transmission cable 11400.

[0426] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and supplies the control signals to the camera control unit 11405. The control signals include, for example, information related to imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image.

[0427] Note that imaging conditions such as frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU 11201 based on the captured image signal. In the latter case, so-called automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions are installed in endoscope 11100.

[0428] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0429] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via a transmission cable 11400.

[0430] In addition, the communication unit 11411 transmits control signals for controlling the camera 11102 to the camera 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0431] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera 11102.

[0432] The control unit 11413 performs various controls related to imaging of surgical sites, etc., using the endoscope 11100, and displaying the captured images obtained by imaging the surgical sites, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0433] Furthermore, the control unit 11413 causes the display device 11202 to display captured images of the surgical site, etc., based on image signals processed by the image processing unit 11412. At this time, the control unit 11413 can identify various objects within the captured image using various image recognition technologies. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living sites, bleeding, fog during the use of the energy treatment device 11112, etc., by detecting the edge shape and / or color of objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can overlay and display various surgical support information related to the image of the surgical site using the recognition results. Since the surgical support information is overlaid and displayed and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0434] The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber or a composite cable corresponding to optical communication.

[0435] Here, in the example shown, communication is wired using transmission cable 11400, but wireless communication between camera 11102 and CCU 11201 is also possible.

[0436] Examples of endoscopic surgical systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure can be suitably applied to the imaging unit 11402 disposed at the camera 11102 of the endoscope 11100 in the above-described configuration. Since the imaging unit 11402 can be miniaturized or have high resolution by applying the technology according to this disclosure to the imaging unit 11402, an endoscope 11100 with small size or high resolution can be provided.

[0437] This disclosure has been described with reference to embodiments, modifications, applicable examples, and application examples; however, this disclosure is not limited to the embodiments, and various modifications are possible. Note that the effects described in this specification are merely illustrative. The effects of this disclosure are not limited to those described in this specification. This disclosure may have effects other than those described in this application.

[0438] Furthermore, for example, this disclosure may have the following structure.

[0439] (1) A semiconductor device, comprising:

[0440] Multiple substrates stacked on top of each other;

[0441] Semiconductor elements formed in at least one of the plurality of substrates; and

[0442] A protective element, which is formed in at least one of the plurality of substrates to have a PN junction, and protects the semiconductor element.

[0443] (2) The semiconductor device according to (1), wherein the protective element is disposed in at least one of the plurality of substrates according to the formation area or number of semiconductor elements formed in the plurality of substrates.

[0444] (3) The semiconductor device according to (1) or (2), wherein the protection element is a bipolar transistor type protection element or a thyristor type protection element.

[0445] (4) The semiconductor device according to any one of (1) to (3), wherein the protective element has a PNPN junction structure or an NPNP junction structure in the horizontal direction of the substrate.

[0446] (5) The semiconductor device according to any one of (1) to (4), wherein the protection element comprises a plurality of first conductivity type traps connected to each other by wiring.

[0447] (6) The semiconductor device according to any one of (1) to (5), wherein the protection element has a double-well structure in which a second conductivity type well is formed above or below a first conductivity type well.

[0448] (7) The semiconductor device according to any one of (1) to (5), wherein the protection element has a triple-well structure of a PNP junction or an NPN junction.

[0449] (8) The semiconductor device according to any one of (1) to (7), wherein,

[0450] The semiconductor element is an element with a gate electrode, and

[0451] The protective element is a component used to discharge the charge generated in the gate electrode to the substrate during plasma processing.

[0452] (9) The semiconductor device according to any one of (1) to (8), wherein the protective element is formed in a substrate different from the substrate on which the semiconductor element to be protected is formed.

[0453] (10) An imaging device, comprising:

[0454] A first substrate in which a photoelectric conversion element and a transmission transistor for transmitting electrical signals output by the photoelectric conversion element are formed;

[0455] A second substrate, which is stacked on the first substrate, and in which pixel transistors for outputting the electrical signals are formed; and

[0456] A protective element, which is formed in at least one of a first substrate and a second substrate to have a PN junction, and protects the transmission transistor or the pixel transistor.

[0457] (11) The imaging apparatus according to (10), wherein the protective element is formed in the second substrate and above the area where the dummy pixel of the first substrate is formed.

[0458] List of reference numerals

[0459] 1,1A Imaging Device

[0460] 100, 100A First substrate

[0461] 200, 200A Second Substrate

[0462] 300, 300A Third substrate

[0463] 541A, 541B, 541C, 541D, 5410 pixels

[0464] TR Transmission Transistor

[0465] RST reset transistor

[0466] AMP amplifier transistor

[0467] SEL selects transistors

[0468] FDG FD transfer transistor

[0469] FD floating diffuser

[0470] TF, TS PID protection components

Claims

1. An imaging device, comprising: A pixel sharing unit, comprising a plurality of pixels each having a photoelectric conversion element and a transmission transistor, and a pixel circuit shared by the plurality of pixels; A first substrate and a second substrate are stacked on top of each other. The first substrate is provided with the photoelectric conversion element and the transmission transistor of the pixel sharing unit, and the second substrate is provided with the pixel circuit of the pixel sharing unit. The pixel circuit includes a pixel transistor and reads out pixel signals from each pixel via the transmission transistor. and A protective element is formed in at least one of the first substrate and the second substrate to have a PN junction and is connected to the gate of at least one of the transmission transistor and the pixel transistor to protect the transmission transistor and / or the pixel transistor.

2. The imaging device according to claim 1, wherein, The protective element is disposed in at least one of the first substrate and the second substrate according to the formation area or number of elements of the transmission transistor and the pixel transistor formed in the first substrate and the second substrate.

3. The imaging apparatus according to claim 1 or 2, wherein, The protection element is a bipolar transistor type protection element or a thyristor type protection element.

4. The imaging device according to claim 3, wherein, The protective element has a PNPN junction structure or an NPNP junction structure in the horizontal direction of the substrate.

5. The imaging apparatus according to claim 4, wherein, The protection element includes a plurality of first conductivity type traps connected to each other by wiring.

6. The imaging apparatus according to claim 4, wherein, The protective element has a double-well structure in which a second conductivity type well is formed above or below a first conductivity type well.

7. The imaging apparatus according to claim 4, wherein, The protection element has a triple-well structure with a PNP junction or an NPN junction.

8. The imaging apparatus according to claim 4, wherein, The protective element is a component used to discharge the charge generated in the gate to the substrate during the plasma process.

9. The imaging apparatus according to claim 1, wherein, The protective element is formed in the second substrate and above the area where the dummy pixel of the first substrate is formed.

Images