Efficient Error Correction of Codewords Encoded by Binary Symmetric Invariant Product Codes

Abstract

A decoder for decoding a binary symmetric invariant product code includes a data array having an orthogonal first dimension and a second dimension. The data array is configured to access a binary symmetric invariant product code buffered therein only along the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and store the error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on the data symmetry of the symmetric invariant product code. The decoder also includes a second correction circuit that corrects the data accessed from the data array based on the error locations stored in the error storage array before the first correction circuit receives the data accessed from the data array along the first dimension.

Description

Background Art

[0001] The present disclosure relates to data processing, and more particularly, to efficient error correction of data encoded using a binary symmetric invariant product code (eg, a half-product code), such as in a data storage system or a data communication system.

[0002] Error correction coding is employed in data storage systems and data communication systems to improve the accuracy with which data can be recovered from a data channel. By encoding the data according to an error correction code (ECC) before providing the data to the channel, errors at the output of the channel can be identified and corrected to an extent that depends on the characteristics of the ECC. Many such ECC schemes are known. One well-known class of ECC schemes is based on product codes. Product codes encode the rows and columns of a nominal two-dimensional array of input data using two component ECC codes.

[0003] Figure 1 The basic structure of the traditional product code is schematically shown. The input data symbol (which can usually be q ary Symbols, with q possible symbol values, where q ≧ 2) are assigned to symbol positions in a nominal array having n2 rows and n1 columns of symbol positions. In this example, k2×k1 data symbols are assigned to positions in a k2×k1 subarray located at the intersection of the first k2 rows and first k1 columns of the n2×n1 array. The resulting array of input data symbols is encoded by encoding the rows and columns of the array separately. The first ECC code C1 is used to convert the k in each row of the array to i -symbol data words are encoded into C1 code words of length n1. This example uses systematic encoding, whereby the input data is retained in the code word. Specifically, the n1 code elements of the C1 code word are obtained by adding (n1-k1) parity check codes after the k1-symbol data word in a given row. The k2 symbols in each column of the array are then encoded into a C2 code word of length n2 using a second ECC code C2, here by adding (n2-k2) parity check symbols at the end of each column. The n2×n1 code symbols obtained in the array form the output code word of the product code. In an extension of this basic idea, the interleaved product code applies the C2 code to s>1 evenly spaced columns of the array, resulting in n1 / s C2 code words.

[0004] Product codes can provide practical encoder / decoder implementations whose decoders are hard-decision based, thus avoiding various complexity and delay issues associated with soft-decision decoding. Some decoders for interleaved product codes use iterative decoding techniques based on graphs defined from the basic code structure. In short, a bipartite graph can be defined as having n2 right nodes, each corresponding to a C1 codeword, and n1 / s left nodes corresponding to respective C2 codewords. Each right node is connected to each left node by s edges. The s edges connecting a pair of nodes represent the s common symbols at the intersection of the C1 and C2 codewords of those nodes in the above conceptual array. Iterative decoding is performed based on the graph by decoding the C1 codewords one by one and then decoding the C2 codewords one by one. Each time a codeword is successfully decoded, the edge leaving the appropriate node is corrected. The process iterates until the decoding is complete, i.e., the decoder no longer detects errors or reaches a predetermined maximum number of iterations, in which case the decoder can declare decoding failure.

[0005] In J. Justesen, “Error Correcting coding for OTN”, IEEE Communications Magazine, September 2010 and J. Justesen, Performance of Product Codes and Related Structures with Iterative Decoding, IEEE Transactions on Communications, 2011. These codes are called half-product codes (HPC), which are product codes that use the same code for the row code C1 and the column code C2. If each component code C1 and C2 is a ratio k / n code with code length (i.e., the number of symbols in a codeword) of n and dimension (i.e., the number of data symbols encoded into each codeword) of k, then the length of the resulting product code C is N=n 2 , the dimension is K = k 2 , the ratio is (k / n) 2 The codewords of C can be defined by the (n×n)-symbol matrix X corresponding to the above conceptual array, where each row and column of X is a codeword of the row / column code. The corresponding semi-product code C H It is defined as C H ={XX T :X∈C}, where X T is the transposed matrix of X.

[0006] Note that if X is a codeword, then X T is also a codeword, because the row code and column code are the same. By construction, C H Each codeword Y HThe main diagonal of is zero (although any main diagonal can be a zero main diagonal, a zero main diagonal is defined in this paper as spanning the (n×n)-symbol matrix Y from the upper right symbol to the lower left symbol H That is, all the symbols on the zero main diagonal have a value of zero. H Definition of Y H =Y H T , the set of n(n-1) / 2 symbols on each side of the zero main diagonal in the triangular subarray is identical. These n(n-1) / 2 symbols thus define the codeword Y H , so that the half-product code has N H = effective length of n(n-1) / 2. For HPC, encoding and iterative decoding are usually performed in the same way as for product codes, but the input data is limited to triangular subarrays on one side of the zero main diagonal, so the dimension of HPC is K H =k(k-1) / 2.

[0007] Figure 2 An exemplary prior art HPC 200 is shown in FIG. 2. To form the HPC 200, original input data 204 is placed in a square array below the zero main diagonal 202. Symmetric replicated data 206 is then formed by replicating the original input data 204, transposing the original input data, and placing the resulting data above the zero main diagonal 202. Parity data 208 is then calculated separately for each row and column (e.g., using a Bose-Chaudhuri-Hocquenghem (BCH) error correction function). After encoding, only the portion of the array above or below the zero main diagonal 202 needs to be stored and / or transmitted due to the symmetry of the data.

[0008] When data is retrieved from storage or received via data transfer, the HPC 200 can be reconstructed by copying and transposing the retrieved / received data to fill the array. Therefore, any errors that occur during the storage, retention, retrieval and / or transmission of data will also be symmetrical about the zero main diagonal of the reconstructed array, such as Figure 3 In a conventional decoding process (ie, an error correction process that iteratively processes rows and columns to correct row and column errors), data in an array is first accessed in a row format and then in a column format.

[0009] In real-world implementations, standard software approaches typically do not copy data in CPU memory, but instead operate on only one set of data and benefit from implicit correction of duplication errors. Figure 3In , rows are processed from the bottom to the top of the array. If only one copy of each bit is stored in CPU memory, correcting the row containing errors at A, B, and C inherently results in correct values ​​for A, B, and C in the three subsequent rows containing those bit values. While seemingly efficient, this software-based approach has higher latency than hardware-based solutions and is therefore not suitable for truly high-performance applications.

[0010] To achieve high performance decoding, a hardware implementation of HPC decoding would typically form the complete HPC array (including duplicate data 206) in memory and then iteratively decode each row, then each column, one by one. While this approach provides higher performance than conventional software implementations, the present disclosure recognizes that circuitry capable of accessing data in row and column format is very expensive. The present disclosure also recognizes that conventional hardware implementations require independent reading and correction of row and column data, which means that hardware HPC decoding implementations do not benefit from array symmetry. Summary of the invention

[0011] In at least one embodiment, the decoder performs iterative decoding in hardware on codewords encoded by a binary symmetric invariant product code, such as a half product code (HPC). The symmetric invariant product code cached in the data array is accessed only along a first dimension of the data array, and errors in the data of the symmetric invariant product code are detected and corrected by an error correction circuit. When an error is detected, the error location of the orthogonal second dimension of the data array is stored in an error storage array, where the error location is determined based on the known data symmetry of the symmetric invariant product code. Based on the stored error location, the error is corrected "on the fly" when the data is accessed from the data array and sent to the error correction circuit.

[0012] According to one aspect, a decoder for decoding a binary symmetric invariant product code is provided, the decoder comprising a circuit, the circuit comprising: a data array having an orthogonal first dimension and a second dimension, wherein the data array is configured to access a binary symmetric invariant product code buffered therein only along the first dimension; an error storage array for storing error positions; a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension, and store the error positions along the second dimension in the error storage array, wherein the first correction circuit determines the error positions based on the data symmetry of the symmetric invariant product code; and before the first correction circuit receives the data accessed from the data array along the first dimension, the second correction circuit corrects the data accessed from the data array based on the error positions stored in the error storage array.

[0013] According to another aspect, a method for decoding a binary symmetric invariant product code is provided, the method comprising: accessing a binary symmetric invariant product code buffered in a data array having orthogonal first and second dimensions only along a first dimension; a first correction circuit detecting and correcting errors in data accessed from the data array along the first dimension; the first correction circuit determining error positions along the second dimension in an error storage array based on data symmetry of the symmetric invariant product code and storing the error positions in the error storage array; and before the first correction circuit receives the data accessed from the data array along the first dimension, the second correction circuit correcting the data accessed from the data array based on the error positions stored in the error storage array.

[0014] According to another aspect, there is provided a computer program comprising program code means adapted to perform the method described in the preceding paragraph when the program is run on a computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0016] Figure 1 A prior art product code is shown;

[0017] Figure 2 A prior art half product code (HPC) is shown;

[0018] Figure 3 A prior art HPC containing symmetric data errors is shown;

[0019] Figure 4 is a high-level block diagram of a data storage system according to one embodiment;

[0020] Figure 5 is a high-level block diagram of a data communication system according to one embodiment;

[0021] Figure 6-7 Shows Figure 4 An exemplary embodiment of a data storage system;

[0022] Figure 8 An exemplary decoder according to one embodiment is shown;

[0023] Fig. 9 is a high-level logic flow diagram of an exemplary process for a decoder to decode a binary symmetric invariant product code according to one embodiment; and

[0024] Figure 10-13 Error correction of a decoder in an exemplary HPC is shown according to one embodiment. DETAILED DESCRIPTION

[0025] According to at least one embodiment, the present application is directed to a decoder that performs iterative decoding in a hardware circuit on codewords encoded by a binary symmetric invariant product code, such as a half product code (HPC). The symmetric invariant product code cached in a data array is accessed only along a first dimension of the data array, and errors in the data of the symmetric invariant product code are detected and corrected by a first correction circuit. When an error is detected, the error position of the orthogonal second dimension of the data array is stored in an error storage array, where the error position is determined based on the known data symmetry of the symmetric invariant product code. Based on the stored error position, the second correction circuit corrects the error "on the fly" when the data is accessed from the data array and sent to the first correction circuit. The application further relates to related methods and program products.

[0026] Although the solutions described herein can be applied to conventional HPC as described above, it should be understood that the solutions disclosed herein are also applicable to symmetric invariant product codes formed by more than one type of component code per row and more than one type of component code per column. Similarly, further extensions of HPC can be obtained by using more than one component code in the code construction. For example, two types of component codes of the same length n but with different error correction capabilities t1 and t2 can be used. In the case of HPC, it can be required that the first half of the rows / columns are codewords from the t1-error correction component code, while the second half of the rows / columns are codewords from the t2-error correction component code.

[0027] Again, reference is made to the drawings, and in particular to Figure 4 , there is a high-level block diagram of an exemplary embodiment of a data storage system 400 for reading and writing ECC encoded data on a data storage device. The data storage system 400 includes a recording channel 402, including a memory 404 (e.g., flash memory or other non-volatile random access memory (NVRAM)) and a read / write device 406 for reading and writing data in the memory 404. Although Figure 4 404 is shown as a single block, but the memory 404 may include any desired data storage unit configuration ranging from, for example, a single chip or die to multiple memory banks, each memory bank including multiple memory chip packages. The read / write device 406 performs read and write operations in a known manner by applying appropriate voltages to the word line and bit line arrays in the memory 404 to address the memory cells for read and write purposes.

[0028] The data storage system 400 also includes an encoder 410 and a decoder 412. The encoder 410 encodes input data into code symbols according to a binary symmetric invariant product code (e.g., HPC) and outputs the code symbols to the recording channel 402. The decoder 412 processes the read-back symbols obtained by the read / write device 406 from the memory 404 to decode the symmetric invariant product code, thereby recovering and outputting the original input data.

[0029] like Figure 5 As further described in , symmetric invariant product codes (eg, HPC) may also be applied to data communication systems, such as data communication system 500. The transmitter of data communication system 500 includes the transmitter described above with reference to Figure 4 The encoder 510, modulator 508 and transmission device (TX) 506 are described. The code symbols output by the encoder 510 are provided to the transmission device 506 via the modulator 508 for generating a signal for transmitting the code symbols through the communication link 504. The communication link 504 may include a physical (wired or wireless) link or a logical link on one or more physical links. The receiver of the data communication system includes a receiving device (RX) 516 for receiving a signal transmitted through the link 504, a demodulator 518 for demodulating the received signal, and a decoder 512 as described above for decoding the result code symbol received from the demodulator 518.

[0030] In a preferred embodiment, the functions of the encoders 410, 510 and decoders 412, 512 are implemented in hardware circuits (i.e., integrated circuits) to achieve high performance. However, in other embodiments, the functions of the encoders 410, 510 and decoders 412, 512 can be implemented in hardware that executes program instructions of software and / or firmware. For example, encoding and decoding can be performed in whole or in part by executing software that configures one or more processors as encoders and / or decoders to perform encoding and decoding.

[0031] Reference now Figure 6-7 , depicting data storage systems (e.g. Figure 4 A more detailed block diagram of an exemplary embodiment of a data storage system 400 is provided. Figure 6 A data processing environment 600 is illustrated that includes one or more hosts, such as a processor system 602 having one or more processors 604 that process instructions and data. The processor system 602 may additionally include a local memory 606 (e.g., dynamic random access memory (DRAM) or a disk) that may store program code, operands, and / or execution results of processes performed by the processor 604. In various embodiments, the processor system 602 may be, for example, a mobile computing device (e.g., a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (e.g., one of the POWER series servers available from International Business Machines Corporation), or a mainframe computer system. The processor system 602 may also be an embedded processor system using a variety of processors, such as ARM, POWER, Intel X86, or any other processor in combination with any memory cache, memory controller, local memory, I / O bus hub, etc.

[0032] Each processor system 602 also includes an input / output (I / O) adapter 608 that is directly (i.e., without any intermediary device) or indirectly (i.e., through at least one intermediary device) coupled to a data storage system 620 via an I / O channel 610. In various embodiments, the I / O channel 610 may employ any one or combination of known or future developed communication protocols, including, for example, Fibre Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transmission Control Protocol / Internet Protocol (TCP / IP), Peripheral Component Interconnect Express (PCIe), etc. I / O requests transmitted via the I / O channel 610 include read requests from the processor system 602 requesting data from the data storage system 620 and write requests from the processor system 602 requesting data to be stored in the data storage system 620.

[0033] Although not required, in the illustrated embodiment, the data storage system 620 includes a plurality of interface cards 622 through which the data storage system 620 receives and responds to I / O requests from the host via the I / O channel 610. Each interface card 622 is coupled to each of a plurality of redundant array of inexpensive disks (RAID) controllers 624 to facilitate fault tolerance and load balancing. Each of the RAID controllers 624 is in turn coupled (e.g., via a PCIe bus) to a non-volatile storage medium, including, in the illustrated example, a plurality of flash memory cards 626 carrying NAND flash memory. In other embodiments, alternative and / or additional non-volatile storage devices may be employed.

[0034] In the depicted embodiment, operation of data storage system 620 is managed by redundant system management controller (SMC) 623, coupled to interface card 622 and RAID controller 624. In various embodiments, system management controller 623 may be implemented in hardware or hardware executing firmware and / or software.

[0035] Figure 7 Depicted Figure 6 6 is a more detailed block diagram of an exemplary embodiment of a flash memory card 626 of a data storage system 620. The flash memory card 626 includes a gateway 730 that serves as an interface between the flash memory card 626 and the RAID controller 624. The gateway 730 is coupled to a general purpose processor (GPP) 732, which can be configured (e.g., by program code) to perform pre-processing of I / O requests received by the gateway 730 and / or schedule I / O requests of the flash memory card 626. The GPP 732 is coupled to a GPP memory 734 (e.g., dynamic random access memory (DRAM)), which can conveniently buffer data created, referenced and / or modified by the GPP 732 during its processing or data streams flowing through the gateway 730 destined for one or more flash memory controllers 740.

[0036] The gateway 730 is also coupled to a plurality of flash controllers 740, each of which controls a respective NAND flash memory system 750. The flash controllers 740 may be implemented, for example, by an application specific integrated circuit (ASIC) and / or a field programmable gate array (FPGA) and / or a microprocessor, and each has an associated flash controller memory 742 (e.g., DRAM). In an embodiment where the flash controllers 740 are implemented with FPGAs, the GPP 732 may program and configure the flash controllers 740 during boot-up of the data storage system 620. After boot-up, the flash controllers 740 are typically operated to receive requests from the gateway 730 to read data stored in the NAND flash memory system 750 and / or to store data in the NAND flash memory system 750. The flash controllers 740 service these requests, for example, by accessing the NAND flash memory system 750 to read or write the requested data from or to the NAND flash memory system 750 or by accessing a memory cache (not shown) associated with the NAND flash memory system 750.

[0037] Flash controller 740 implements a flash translation layer (FTL) that provides logical to physical address translation to allow access to specific memory locations within NAND flash memory system 750. Typically, an I / O request received by flash controller 740 from a host device (e.g., processor system 602) contains a logical block address (LBA) of data to be accessed (read or written), and, if it is a write request, stores the write data to data storage system 620. The I / O request may also specify the amount (or size) of data to be accessed. Other information may also be transmitted based on the protocols and features supported by data storage system 620. The flash translation layer converts the LBA received from RAID controller 624 into a physical address assigned to a corresponding physical location in NAND flash memory system 750. Flash controller 740 may perform address translation and / or store a mapping between logical and physical addresses in a logical to physical translation data structure, such as a logical to physical translation table (LPT) that may be conveniently stored in flash controller memory 742.

[0038] In various embodiments, NAND flash memory system 750 may take a variety of forms. Figure 7In the illustrated embodiment, each NAND flash memory system 750 includes a plurality (e.g., 32) of individually addressable NAND flash memory storage devices 752. In the illustrated example, the flash memory storage devices 752 are in the form of board-mounted flash memory modules, such as single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) NAND flash memory modules. The fidelity of data read from the flash memory storage devices 752 is preferably enhanced by the implementation of ECC encoding, for example, by the flash memory controller 740 and / or a higher-level controller such as the GPP 732 or the RAID controller 624. In the illustrated embodiment, the ECC encoding and decoding is implemented at least in the flash memory controller 740 by an encoder 744 and a decoder 746.

[0039] Reference now Figure 8 , shows an exemplary embodiment of a decoder 800 according to one embodiment. Decoder 800, which may be used to implement any of decoders 412, 512, or 746, decodes data that has been encoded using a binary symmetric invariant product code (eg, HPC).

[0040] like Figure 8 As shown, the decoder 200 includes a control circuit 802 that controls the decoding of uncorrected codewords encoded using a binary symmetric invariant product code. In addition, the decoder 800 includes a data array 804 that buffers the binary symmetric invariant product code during decoding. By convention, the data array 804 includes orthogonal, equal-sized first and second dimensions, referred to herein as rows and columns, respectively. Compared to conventional decoders, the data array 804 preferably includes circuitry that allows access to the binary symmetric invariant product code buffered therein to be decoded along only one of its first and second dimensions but not the other. This restriction greatly reduces the cost of implementing the decoder 800 in hardware circuits. For simplicity, it is assumed below that the data array 804 is accessed only by row and not by column; however, it should be understood that the choice of access dimension is entirely arbitrary, given the data symmetry of the binary symmetric invariant product code buffered in the data array 804.

[0041] The data array 804 is coupled to a column correction circuit 806 that is configured to correct individual bit positions within a row codeword read from the data array 804 "on the fly" as needed and based on error location information stored in an error storage array 810. The row codeword may be modified by the column corrector circuit 806 and then fully decoded by the row correction circuit 808. The row correction circuit 808 may implement, for example, a Bose-Chaudhuri-Hocquenghem (BCH) error correction function as is known in the art. Based on the decoding of the row codeword, the row correction circuit 808 records the location of any corrected errors within the error.

[0042] Reference now Fig. 9, shows a high-level logical flow diagram of an exemplary process by which, such as Figure 8 A decoder such as decoder 800 of , in one embodiment, decodes binary symmetric invariant product codes. Fig. 9 The process of begins at block 900 and then proceeds to block 902, which illustrates that the decoder 800 receives a portion of a binary symmetric invariant product code, hereinafter assumed to be an HPC. As described above, the HPC may be received by the decoder 800, for example, from a recording channel 402 of a data storage system 400 or a transmission link 504 of a data communication system 500. In response to receiving a portion of the HPC, the control circuit 802 of the decoder 800 fills a portion of a data array 804 with the received HPC portion (e.g., a triangular portion of the array below the zero main diagonal), and copies the data within the received HPC portion to form a complete data symmetric HPC in the data array 804.

[0043] After block 902, control circuit 802 directs iterative decoding of the HPC only along a single dimension of data array 804. Thus, in one example, control circuit 802 causes the HPC to be accessed and decoded by row codewords rather than column codewords. By eliminating HPC access along the second dimension, the latency of decoding the HPC is reduced by half.

[0044] The control circuit 802 begins the iterative decoding process at block 904 by determining whether all row codewords of the HPC buffered within the data array 804 have been accessed for decoding. If so, the process proceeds to block 920, as described below. If not, the process proceeds to block 910. At block 910, the control circuit 802 causes the first or next row of codewords of the HPC to be read out from the data array 804. As shown in block 912, when the row codeword is transmitted to the row correction circuit 808 for decoding, the column correction circuit 806 corrects (i.e., inverts) any bits of the row codeword identified by the error storage array 80 as containing errors "on the fly" and forwards the row codeword with any such corrections to the row correction circuit 808. In response to receiving the row codeword that may be modified by the column correction circuit 806, the row correction circuit 808 decodes the codeword using the parity portion of the codeword to correct any errors (block 914). As described above, in one embodiment, the row correction circuit 808 can utilize, for example, conventional BCH error correction functions. As further indicated at block 914, if any errors are corrected in the row codeword, the row correction circuit 808 records the error location in the error storage array 810, thus allowing the column correction circuit 806 to utilize the error location information to correct bits in one or more additional row codewords based on the known data symmetry of the HPC. At block 916, the row correction circuit 808 writes the decoded row codeword back to its original location in the data array 802. Thereafter, the process returns to block 904.

[0045] Referring now to block 920, control circuit 802 determines whether any errors were detected in any row codeword of the HPC during the last iteration through all row codewords. If no errors were detected in any row codeword during the last iteration, the HPC was successfully decoded, and the process passes to block 922, which depicts control circuit 802 causing the decoded row codeword of the HPC to be output 804 from a data array, e.g., a component of processor system 602 or data communication system 500. Thereafter, Fig. 9 The process ends at block 924. However, if control circuit 802 determines at block 920 that at least one error was found in at least one row codeword during the last iteration of all row codewords through the HPC, control circuit 802 determines at block 926 whether a maximum number of iterations (e.g., 3) of row codewords through the HPC have been performed. If not, Fig. 9 The process returns to block 910 and subsequent blocks already described through page connector A. However, if control circuit 802 determines at block 926 that the maximum number of iterations through all row codewords of the HPC has been performed, then Fig. 9 The process terminates with an error at block 928 and the decoder 800 initiates any required error handling.

[0046] Reference now Figure 10-13 , given by Figure 8 The decoder uses Fig. 9 An example of a process for correcting errors in an exemplary HPC. In this example, the data array 804 has 20 rows and 20 columns, numbered R0 to R19 and C0 to C19, respectively. In this example, it is assumed that the HPC is encoded using a Bose-Chaudhuri-Hocquenghem (BCH) error correction function that is capable of correcting up to three errors in a given row (or column) with zero delay. As a result of this error correction capability, the error storage array 810 preferably includes the capacity to store up to three error locations per row. The error storage array is initialized to all "invalid" values ​​(empty state) so that the column correction circuit 806 does not initially perform any correction on the row codewords read out from the data array 804.

[0047] After the full input HPC is established in the data array 804, the control circuit 802 causes the row codewords to be iteratively and sequentially read out from the data array 804 and passed through the set correction circuit 806 to the row correction circuit 808 for BCH decoding, starting from row R0. Fig.10As shown, the row code words in rows R0 and R1 do not contain any errors, but the row code word in row R2 initially contains three errors in columns C10, C4, and C3. In response to detecting these bit errors, row correction circuit 808 updates error storage array 810, which can be represented as shown in Table I. As indicated, error storage array 810 records three errors to be repaired, namely, the bits in column C2 in rows R3, R4, and R10. It should be observed that these three errors are symmetrical with the errors detected in columns C3, C4, and C10 of row R2.

[0048] Table I

[0049]

[0050] After the error correction in row R2, row correction circuit 808 updates data array 804, which will temporarily become asymmetric, such as Fig.11 shown.

[0051] Continuing with the example, the row codeword in row R3 is next read from the data array 804 and passes through the column correction circuit 806 to the row correction circuit 808. As the row codeword is transmitted, the column correction circuit 806 corrects the error in the C2 column and updates the error storage array 810 to remove the "3" from the entry corresponding to the C2 column in the error storage array 810. When the row correction circuit 808 performs BCH decoding on the row codeword for row R3, no error is found because the column correction circuit 806 has corrected the only error before the row correction circuit 808 receives the row codeword. Therefore, the row correction circuit 808 does not store any new error locations in the error storage array 810, which will then appear as shown in Table II below. After the row correction circuit 808 writes the corrected row codeword back to row R3, the data array 804 will appear as shown in Table II below. Fig.12 shown.

[0052] Table II

[0053]

[0054] The row codeword in row R4 is next read out of data array 804 and passed through column correction circuit 806 to row correction circuit 808. As shown, the row codeword for row R4 initially contains four errors, which is more than can be corrected by the BCH algorithm implemented by row correction circuit 808. However, because column correction circuit 806 corrects the bits in column 2 of the row codeword based on information provided by error storage array 810 before row correction circuit 808 receives the row codeword, row correction circuit 808 is able to fully decode the row codeword assuming that only three errors instead of four exist after the column correction. After row correction circuit 808 decodes the row codeword and updates data array 802 and error storage array 810, data array 802 will be as follows: Fig.13The error occurs and the memory array 810 will have the state shown in Table III below.

[0055] Table III

[0056]

[0057] The decoding process will continue iteratively through row R19. Once the first iteration through all rows of data array 802 is complete, error storage array 810 is not cleared and the second iteration begins. This process will continue until one of two exit conditions is met: (1) the HPC contains no errors (i.e., all row codewords of the HPC are decoded by row correction circuit 808 without finding any errors) or (2) the maximum iteration limit is reached (i.e., the HPC is not corrected).

[0058] In the foregoing description, for ease of description, the effects of delays and pipelines in actual hardware implementations are ignored. To illustrate the additional effects of delays and pipelines, it is assumed that the delay of the row correction circuit 808 is five cycles, which means that when a particular row codeword begins BCH decoding, the resulting correction will not be available until 5 clock cycles later. Based on this assumption, the error position in row R2 will not be available for correction of subsequent rows before row R7 enters the row correction circuit 808. Therefore, although the row correction circuit 808 will record the correction to the column C2 of rows R3, R4, and R10 in the error storage array 810 based on the decoded row R2, the row correction circuit 808 will receive the codeword position information of rows R3 and R4 before this error. Therefore, the row codewords of rows R3 and R4 that can be column-corrected "on the fly" by the column correction circuit 806 during the same iteration through the data array 804 in an ideal zero-delay situation have been processed by the row correction circuit 808 by the time error storage array 810 reflecting the error positions in these row codewords. Fortunately, the failure of the column correction circuit 806 to correct these column errors in the first iteration will not affect the final result of BCH decoding, because the column correction circuit 806 will use any error location information recorded in the error storage array 810 to correct the bits (e.g., the bits in the C2 column of the row codeword for rows R3 and R4) in the next pass. Simulation and analysis show that the delay as described above does not result in any significant loss in decoding performance compared to the ideal zero-delay case.

[0059] In a preferred embodiment, row correction circuit 808 is designed to know its decoding latency and to order the storage of error locations in the error storage array according to its decoding latency. Thus, for example, row correction circuit 808 can intelligently order the storage of error locations in column C2 of row R10 within error storage array 810 before storing error locations in column C2 of rows R3 and R4. This intelligent ordering of the storage of error locations in error storage array 810 ensures that, to the greatest extent possible, symmetric errors (e.g., errors in column C2 of row R10) can be corrected by column correction circuit 806 during the same iteration through the row codeword in which the corresponding error is detected.

[0060] The examples provided above also do not explicitly discuss the impact of parallelism. In at least some embodiments, it is desirable to increase decoding throughput by implementing parallel instances of column correction logic within the column correction circuit 806 and implementing parallel instances of decoding logic within the row correction circuit 808. For example, in one embodiment, the row correction circuit 808 may include four instances of decoding logic capable of decoding four codewords per clock cycle, and the column correction circuit 806 may similarly include four instances of column correction logic capable of correcting bits within four codewords per clock cycle. In such an embodiment, if one instance of logic processes row codewords for rows R0, R4, R8, R12, ..., it is preferred that a second instance of logic processes row codewords for rows R1, R5, R9, R13, etc. The dimensions of the data array are determined modulo the number of logic instances. It should be noted that the error position corrected by any column correction logic instance can be detected by any decoding logic instance.

[0061] As has been described, in at least one embodiment, a decoder for decoding a binary symmetric invariant product code includes a data array having an orthogonal first dimension and a second dimension. The data array is configured to access a binary symmetric invariant product code buffered therein only along the first dimension. The decoder also includes an error storage array for storing error positions and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and store the error positions along the second dimension in the error storage array. The first correction circuit determines the error position based on the data symmetry of the symmetric invariant product code. The decoder also includes a second correction circuit that corrects the data accessed from the data array based on the error positions stored in the error storage array before the first correction circuit receives the data accessed from the data array along the first dimension.

[0062] The described embodiments can provide significant advantages over prior art decoders in terms of cost and performance. For example, by eliminating the requirement to access a binary symmetric invariant product code along two dimensions, a significant amount of circuit cost and area is saved, particularly for larger binary symmetric invariant product codes, which may have three hundred or more bits in each dimension. In addition, by eliminating the need to access a binary symmetric invariant product code along two dimensions, decoding latency can be reduced by half. Furthermore, the described embodiments exploit data symmetry to correct symmetric errors "on the fly," rather than waiting for such symmetric errors to be "rediscovered" and corrected during decoding of subsequent codewords.

[0063] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0064] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0065] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0066] The computer program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0067] Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0068] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0069] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0070] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0071] Although the present invention has been particularly illustrated as described with reference to one or more preferred embodiments, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention. For example, although aspects have been described with respect to a data storage system including a flash memory controller that directs certain functions, it should be understood that the present invention may alternatively be implemented as a program product including a storage device storing program code that can be processed by a processor to perform those functions or cause those functions to be performed. As used herein, a "storage device" is specifically defined as including only legal articles and does not include the signal medium itself, the transient propagating signal itself, and the energy form itself.

[0072] Furthermore, while embodiments have been described that include the use of NAND flash memory, it should be understood that embodiments of the present invention may also be used with any other type of non-volatile random access memory (NVRAM).

[0073] The figures described above and the written description of the specific structures and functions below are not intended to limit the scope of the invention of the applicant or the scope of the appended claims. On the contrary, the drawings and written descriptions are provided to teach any technician in the field to make and use the invention for which patent protection is sought. Those skilled in the art will understand that for the sake of clarity and understanding, not all features of the commercial embodiments of the present invention are described or shown. Those skilled in the art will also understand that the development of actual commercial embodiments in conjunction with aspects of the present invention will require many implementation-specific decisions to achieve the ultimate goal of the developer for the commercial embodiment. Such implementation-specific decisions may include but may not be limited to compliance with system-related, business-related, government-related and other constraints, which may vary from time to time depending on the specific implementation, location and time. Although the efforts of the developers may be complex and time-consuming in an absolute sense, such efforts will be routine work for those skilled in the art who benefit from the present disclosure. It must be understood that the invention disclosed and taught herein is susceptible to a variety of different modifications and alternative forms. Finally, the use of singular terms (such as but not limited to "one") is not intended to limit the number of items.

Claims

1. A decoder for decoding a binary symmetric invariant product code, the decoder comprising a circuit comprising: a data array having orthogonal first and second dimensions, wherein the data array is configured to access a binary symmetric invariant product code buffered therein only along the first dimension; an error storage array for storing error locations; a first correction circuit configured to detect and correct errors in data accessed from the data array along a first dimension and store error locations along a second dimension in an error storage array, wherein the first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code; as well as The second correction circuit corrects the data accessed from the data array based on the error locations stored in the error storage array before the first correction circuit receives the data accessed from the data array along the first dimension.

2. The decoder of claim 1, wherein the binary symmetric invariant product code is a half product code (HPC).

3. The decoder of claim 1, wherein the data array is configured to access the binary symmetric invariant product code buffered therein only by rows.

4. The decoder of claim 1, wherein the first correction circuit updates the data array with the correction data.

5. The decoder of claim 4, wherein the decoder iteratively accesses codewords of the binary symmetric invariant product code buffered in the data array only along the first dimension, such that at least some codewords are accessed multiple times along the first dimension.

6. The decoder of claim 5, wherein the decoder discontinues iterative access to the codeword of the binary symmetric invariant product code upon reaching a predetermined number of iterations or upon not detecting a first occurrence of an error in the binary symmetric invariant product code.

7. The decoder of claim 1, wherein: The first correction circuit is configured to decode a plurality of codewords in each clock cycle; as well as The second correction circuit is configured to apply a correction indicated by the erroneous storage array to a plurality of codewords per clock cycle.

8. The decoder of claim 1, wherein: The first correction circuit orders the storage of error locations in the error storage array according to a latency of the decoder.

9. A data storage system comprising: Non-volatile storage systems; as well as A controller coupled to a non-volatile memory system, wherein the controller includes the decoder of claim 1.

10. A data communication system, comprising: a demodulator configured to receive modulated coded data from a communication channel, demodulate the modulated coded data, and output coded data; as well as The decoder of claim 1, wherein the decoder is coupled to the demodulator to receive as input encoded data comprising a binary symmetric invariant product code.

11. A method for decoding a binary symmetric invariant product code, the method comprising: accessing a binary symmetric invariant product code buffered in a data array having orthogonal first and second dimensions only along a first dimension; a first correction circuit to detect and correct errors in data accessed from the data array along a first dimension; a first correction circuit determining an error position along a second dimension in the error storage array based on the data symmetry of the symmetry-invariant product code and storing the error position in the error storage array; as well as Before the first correction circuit receives data accessed from the data array along the first dimension, the second correction circuit corrects the data accessed from the data array based on error locations stored in the error storage array.

12. The method of claim 11, wherein the binary symmetric invariant product code is a half product code (HPC).

13. The method of claim 11, wherein the data array is configured to access the binary symmetric invariant product code buffered therein only by rows.

14. The method of claim 11, further comprising the first correction circuit updating the data array with the correction data.

15. The method of claim 14, wherein accessing comprises iteratively accessing codewords of the binary symmetric invariant product code buffered in the data array along only the first dimension such that at least some of the codewords are accessed multiple times along the first dimension.

16. The method of claim 15, further comprising discontinuing iterative access to codewords of the binary symmetric invariant product code based on reaching a predetermined number of iterations or a first occurrence of no error being detected in the binary symmetric invariant product code.

17. The method of claim 11, wherein: The first correction circuit detecting and correcting includes the first correction circuit detecting and correcting errors in the plurality of code words at each clock cycle; as well as The second correction circuit correcting the data includes the second correction circuit applying a correction indicated by the erroneous storage array to the plurality of codewords per clock cycle.

18. The method according to claim 11, further comprising: The first correction circuit orders the storage of error locations in the error storage array according to a latency of the decoder.

19. The method of claim 11, further comprising retrieving a portion of the binary symmetric invariant product code from a non-volatile memory system.

20. The method of claim 11, further comprising receiving a portion of a binary symmetric invariant product code from a communication link.

21. A computer program product comprising program code for executing the method as claimed in any one of claims 11 to 20.

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