SoC architecture and device for arc detection

Abstract

The present application relates to a SoC architecture for sampling electrical signals in a power grid and obtaining target sampling data for identifying fault arcs, the SoC architecture comprising: an acquisition front end for sampling electrical signals in a power grid, obtaining initial sampling data, and processing the initial sampling data to obtain target sampling data including fault arcs; a memory for storing programs and data, the programs including user programs and boot programs; a microcontroller electrically connected to the memory and the acquisition front end, for responding to a startup instruction, controlling the user program in an external storage space to be stored in a first preset position in the memory; and controlling the target sampling data in a preset sampling mode to be stored in a second preset position in the memory according to the program. The present method can be used to sample electrical signals taken out of a power grid, and then study fault arcs through software analysis and arc identification processing.

Description

Technical Field

[0001] The present application relates to the technical field of power fault detection, and in particular to a SoC architecture and device for arc detection. Background Art

[0002] When the power supply of the wires or electrical appliances in the power distribution system is in an overloaded state for a long time, or there is a bad electrical connection, the insulation layer of the wires will age, reducing the insulation effect, or the insulation layer will be damaged, causing an arc fault. When an arc fault occurs in the line, it is likely to cause a fire by spraying high-temperature particles or high-temperature gases to ignite the surrounding combustibles.

[0003] Since the 1990s, the international community has begun to conduct in-depth and detailed research on the causes, damages and preventive measures of arc faults. However, due to the complexity of arc faults, there is currently no reliable method to fully realize the detection and protection of arc faults. With the rise and rapid development of smart grids, the application of air switches and leakage protectors can effectively and timely disconnect the line when a circuit fails. However, traditional circuit breakers cannot effectively identify fault arcs and disconnect the line to play a protective role. Therefore, the detection of fault arcs occupies an extremely important position in the intelligent distribution system.

[0004] Most of the research at home and abroad focuses on the analysis of arc identification methods, such as time domain and frequency domain characteristics, wavelet analysis, neural networks, fault identification based on the fusion technology of one or some characteristics of the series arc current and the overall characteristics, etc. They are all based on the arc detection system-on-chip (SoC) hardware platform. However, with the development of nano-scale CMOS technology, large-scale integrated circuits have been rapidly developed and applied, and the traditional system (SoC) hardware platform cannot meet the above arc identification methods well. Therefore, how to design a power-specific SoC for arc detection is of great significance. Summary of the invention

[0005] Based on this, it is necessary to provide a SoC architecture and device for arc detection to address the above technical issues.

[0006] In order to achieve the above-mentioned and other purposes, one aspect of the present application provides a SoC architecture for arc detection, characterized in that it is used to sample electrical signals in a power grid and obtain target sampling data for identifying fault arcs, and the SoC architecture includes:

[0007] The acquisition front end is used to sample the electrical signals in the power grid, obtain initial sampling data, and process the initial sampling data to obtain target sampling data including the fault arc;

[0008] A memory, used for storing programs and data, wherein the programs include user programs and boot programs;

[0009] The microcontroller is electrically connected to the memory and the acquisition front end, and is used to respond to a startup instruction, control the user program in the external storage space to be stored in the first preset position in the memory; and control the target sampling data in the preset sampling mode to be stored in the second preset position in the memory according to the program.

[0010] In the SoC architecture for arc detection in the above embodiment, the electrical signal taken out from the power grid is sampled, processed and analyzed by the acquisition front end, and the processed target sampled data is stored so that the type of fault can be quickly determined and corresponding measures can be taken when an arc fault occurs.

[0011] In one embodiment, the acquisition front end includes a Nyquist analog-to-digital converter; the Nyquist analog-to-digital converter includes:

[0012] The sampling switch is configured as follows: the input end is connected to the common mode voltage;

[0013] A comparator is configured as follows: an inverting input terminal is connected to the output terminal of the sampling switch, a non-inverting input terminal is connected to a common mode voltage, and an output terminal is used to output the target sampling data;

[0014] A capacitor array digital-to-analog converter includes a capacitor array and a plurality of switching switches, each of the switching switches includes an output terminal connected to a corresponding capacitor and a first input terminal, a second input terminal, and a third input terminal; the first input terminal is connected to a reference voltage, the second input terminal is connected to a signal voltage, and the third input terminal is connected to a ground wire. The Nyquist analog-to-digital converter adopts a successive approximation analog-to-digital converter structure, which is widely used in medium and low-speed applications due to its simple structure, few analog modules, small area, and low power consumption. In order to make the sampling rate reach 1M.

[0015] In one embodiment, the second preset location includes a register; the comparator includes:

[0016] The preamplifier unit is configured as follows: a first input terminal is connected to a common mode voltage, a second input terminal is connected to an output terminal of the sampling switch, a third input terminal is connected to a first clock signal, a first output terminal is used to output a first differential signal, and a second output terminal is used to output a second differential signal;

[0017] A latch comparison unit is connected to the preamplifier unit and is configured as follows: a first input terminal is connected to the first differential signal, a second input terminal is connected to the second differential signal, and an output terminal is used to output the target sampling data;

[0018] The microcontroller is configured to:

[0019] In the first clock cycle of the first clock signal, the comparator is controlled to compare the highest position of the register to 1 successively, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to the inverting input terminal of the comparator, and controlling the comparator to compare the voltage received at its inverting input terminal with the common mode voltage; if the common mode voltage is greater than the voltage received at the inverting input terminal, the comparator is controlled to output 1, otherwise, the highest position of the register is set to 0;

[0020] In the second clock cycle of the first clock signal, the second highest position of the register is set to 1, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to the inverting input terminal of the comparator, controlling the comparator to compare the received voltage and output a corresponding comparison result, so as to reduce power consumption compared with a static comparator.

[0021] In one embodiment, the acquisition front end includes a sigma-delta analog-to-digital converter; the sigma-delta analog-to-digital converter includes:

[0022] The delta-sigma modulator module is configured as follows: the input end is connected to the signal voltage, and the output end outputs the modulation and demodulation signal;

[0023] The digital downsampling filter module is connected to the delta-sigma modulator module, and is used to extract and filter the modulation and demodulation signal, and output the target sampling data. In order to reduce the quantization noise within the system frequency band, adding a low-pass filter after the delta-sigma modulator can effectively filter out the quantization noise outside the signal bandwidth, greatly improving the system performance.

[0024] In one embodiment, the delta-sigma modulator module comprises:

[0025] A subtractor, configured as follows: an input end is connected to both the signal voltage and the modulation and demodulation signal, and is used to calculate the difference between the voltage amplitude of the signal voltage and the voltage amplitude of the modulation and demodulation signal;

[0026] an integrator, configured to generate a comparison reference voltage according to the received difference;

[0027] The dynamic comparator is configured as follows: the inverting input terminal is grounded, the non-inverting input terminal is connected to the comparison reference voltage, and the output terminal outputs the modulation and demodulation signal. The delta-sigma modulator module adopts a single-loop first-order structure to reduce the speed and improve the accuracy of the delta-sigma modulator.

[0028] In one of the embodiments, the SoC architecture for arc detection further includes:

[0029] The distributed temperature sensing module is connected to the acquisition front end and is used to monitor the temperature changes at the corresponding positions of the architecture during operation to achieve temperature compensation. This is to facilitate the monitoring of the temperature changes at the corresponding positions of the system during operation and achieve quantitative output of the temperature.

[0030] In one embodiment, the distributed temperature sensing module includes: a first transistor, configured as follows: a source electrode is grounded, and a gate electrode is connected to a first DC power supply;

[0031] A second transistor is configured as follows: a source electrode is grounded, and a drain electrode is connected to a gate electrode of the first transistor;

[0032] A third transistor is configured as follows: a source electrode is grounded, and a drain electrode is connected to a second DC power source;

[0033] a fourth transistor, configured as follows: a source connected to the drain of the second transistor, a drain connected to a gate, and a gate connected to the gate of the second transistor;

[0034] a fifth transistor, configured as follows: a source connected to the drain of the third transistor, a drain connected to the gate, and a gate connected to the gate of the third transistor;

[0035] a sixth transistor, configured such that: a drain is connected to the drain of the first transistor;

[0036] a seventh transistor, configured as follows: a source connected to the source of the sixth transistor, a drain connected to the drain of the fourth transistor, and a gate connected to the gate of the sixth transistor;

[0037] The eighth transistor is configured as follows: a source connected to the source of the seventh transistor, a drain connected to the drain of the fifth transistor, and a gate connected to the gate of the seventh transistor.

[0038] In one of the embodiments, the SoC architecture for arc detection further includes:

[0039] a reset circuit, connected to the microcontroller, for resetting the microcontroller to an initial state; and / or

[0040] The phase-locked loop circuit is connected to the microcontroller and is used to set the main clock frequency of the microcontroller by configuring the frequency division ratio of the register. The reset circuit is used to restore the architecture to its original state to ensure that the architecture works stably and reliably, and the phase-locked loop circuit is used to realize a stable and high-frequency clock signal.

[0041] In one of the embodiments, the SoC architecture for arc detection further includes:

[0042] Low voltage dropout regulator is used to provide working power, so as to provide a stable DC voltage power supply.

[0043] Another aspect of the present application provides an arc detection device, comprising the architecture described in any one of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 It is a structural schematic diagram of a SoC architecture for arc detection provided in the first embodiment;

[0046] Figure 2 It is a structural schematic diagram of a SoC architecture for arc detection provided in the second embodiment;

[0047] Figure 3 A schematic diagram of the structure of a SAR ADC provided in an embodiment of the present invention;

[0048] Figure 4 It is a structural schematic diagram of a SoC architecture for arc detection provided in the third embodiment;

[0049] Figure 5 A schematic diagram of the structure of a comparator provided in an embodiment of the present invention;

[0050] Figure 6 This is a diagram of the SAR ADC power spectrum test result provided in an embodiment of the present invention;

[0051] Figure 7 It is a structural schematic diagram of a SoC architecture for arc detection provided in a fourth embodiment;

[0052] Figure 8 A schematic diagram of the structure of a delta-sigma modulator provided in an embodiment of the present invention;

[0053] Fig. 9 This is a graph of the sigma-delta ADC power spectrum test results provided in an embodiment of the present invention;

[0054] Fig.10 is a structural schematic diagram of a SoC architecture for arc detection provided in a fifth embodiment;

[0055] Fig.11 This is a schematic diagram of the structure of a distributed temperature sensing module provided in an embodiment of the present invention;

[0056] Fig.12 This is a diagram of measurement results of a distributed temperature sensing module provided in an embodiment of the present invention;

[0057] Fig.13 It is a structural schematic diagram of a SoC architecture for arc detection provided in the sixth embodiment;

[0058] Fig.14 A schematic diagram of the structure of a test system provided in an embodiment of the present invention;

[0059] Description of reference numerals:

[0060] 100, acquisition front end; 200, microcontroller; 300, memory; 120, Nyquist analog-to-digital converter; 122, sampling switch; 124, comparator; 126, capacitor array digital-to-analog converter; 1242, preamplifier unit; 1244, latch comparison unit; 140, sigma-delta analog-to-digital converter; 142, delta-sigma modulator module; 144, digital downsampling filter module; 1422, subtractor; 1424, integrator; 1426, dynamic comparator; 400, distributed temperature sensing module. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0064] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0065] When an arc fault occurs in a line, it is likely to cause a fire by spraying high-temperature particles or high-temperature gases to ignite the surrounding combustibles. Since the 1990s, the international community has begun to conduct in-depth and detailed research on the causes, damages and preventive measures of arc faults. Despite this, due to the complexity of arc faults, there is currently no reliable method that can fully realize the detection and protection of arc faults. Most of the research at home and abroad focuses on arc recognition methods, such as time domain and frequency domain characteristics, wavelet analysis, neural networks, and fault recognition based on the fusion technology of one or some characteristics of the series arc current and the overall characteristics. They are all based on the arc detection system on chip (SoC) hardware platform. With the development of nano-scale CMOS technology, large-scale integrated circuits have been rapidly developed and applied. It is of great significance to independently research and design a power-specific SoC for arc detection. The present invention designs a SoC hardware system for arc detection for arc detection. By sampling the electrical signal taken out from the power grid, the fault arc can be studied through software analysis and arc recognition processing.

[0066] The acquisition front end 100 is used to sample the electrical signals in the power grid, obtain initial sampling data, and process the initial sampling data to obtain target sampling data including fault arcs; the memory 300 is used to store programs and data, and the programs include user programs and boot programs; the microcontroller 200 is used to respond to the start instruction, control the user program in the external storage space to be stored in the first preset position in the memory 300, and control the target sampling data in the preset sampling mode to be stored in the second preset position in the memory 300 according to the program.

[0067] As an example, please refer to Figure 1The overall bus of the architecture adopts the AMBA bus (Advanced Microcontroller Bus Architecture, on-chip bus protocol). In the embodiment of the present invention, the bus adopts a two-level bus interconnection structure of AHB (Advanced High-performance Bus) and APB (Advanced Peripheral Bus). It is an early version of the AXI (Advanced eXtensible Interface) bus. Although the performance is relatively low, the power consumption is also low, which is suitable for the low power consumption requirements of this system. The microcontroller 200 adopts the CK803 32-bit CPU, and the operating frequency can reach up to 120MHz. CKCPU adopts an embedded CPU with an AMBA / AXI interface independently designed by Hangzhou Zhongtian Microsystem Co., Ltd. The performance of CK803 is similar to ARM Cortex-M3. It is a 32-bit high-energy-efficiency embedded CPU core for the control field, with the characteristics of low cost, low power consumption, high code density, etc. A 16 / 32-bit mixed encoding instruction system is adopted, and a streamlined and efficient 3-stage pipeline is designed. The memory 300 includes a 32KB SRAM (Static Random-Access Memory), an 8KB SRAM and a 2KB ROM (Read-Only Memory), wherein the SRAM can be used as a user program and data storage space, and the ROM is used to store the boot program of the SoC. When in use, the user program can be stored in the first preset position in the memory 300, and then during the architecture startup process, the user program in the first preset position in the memory 300 is loaded into the second preset position in the memory 300 through the SPI (Serial Peripheral Interface) bus. During actual debugging, the program can be directly downloaded to the SRAM through JTAG (Joint Test Action Group).

[0068] As an example, see Figure 2 In one embodiment of the present application, the acquisition front end 100 includes a Nyquist analog-to-digital converter 120, and the Nyquist analog-to-digital converter 120 includes a sampling switch 122, a comparator 124, and a capacitor array digital-to-analog converter 126. The Nyquist analog-to-digital converter 120 adopts a successive approximation analog-to-digital converter structure, and the basic structure adopted is as follows Figure 3As shown, the input end of the sampling switch 122 is connected to the common mode voltage; the inverting input end of the comparator 124 is connected to the output end of the sampling switch 122, the positive input end is connected to the common mode voltage, and the output end is used to output the target sampling data; the capacitor array digital-to-analog converter 126 includes a capacitor array and a plurality of switching switches, each of which includes an output terminal connected to a corresponding capacitor and a first input terminal, a second input terminal, and a third input terminal; the first input terminal is connected to a reference voltage, the second input terminal is connected to a signal voltage, and the third input terminal is connected to a ground wire. The capacitor array adopts a 10-bit binary single-ended structure, bottom plate sampling, and a control switch adopts a transmission gate. The successive approximation analog-to-digital converter is widely used in medium and low-speed applications due to its simple structure, few analog modules, small area, and low power consumption. In order to make the sampling rate reach 1M.

[0069] As an example, see Figure 4 In one embodiment of the present application, the second preset position includes a register, and the comparator 124 includes a preamplifier unit 1242 and a latch comparison unit 1244. Compared with the static comparator 124, the comparator 124 has low power consumption and a structure such as Figure 5As shown, the first input terminal of the preamplifier unit 1242 is connected to the common mode voltage, the second input terminal is connected to the output terminal of the sampling switch 122, the third input terminal is connected to the first clock signal, the first output terminal is used to output the first differential signal, and the second output terminal is used to output the second differential signal; the latch comparison unit 1244 is connected to the preamplifier unit 1242, the first input terminal is connected to the first differential signal, the second input terminal is connected to the second differential signal, and the output terminal is used to output the target sampling data. The gate of the ninth transistor is connected to the first input terminal; the gate of the tenth transistor is connected to the second input terminal, and the source is connected to the source of the ninth transistor; the source of the eleventh transistor is grounded, and the drain is connected to the source of the tenth transistor; the gate of the twelfth transistor is connected to the first clock signal, the source is grounded, and the drain is connected to the first output terminal; the gate of the thirteenth transistor is connected to the second output terminal, the source is grounded, and the drain is connected to the drain of the twelfth transistor; the gate of the fourteenth transistor is connected to the drain of the thirteenth transistor, the source is grounded, and the drain is connected to the gate of the thirteenth transistor; the gate of the fifteenth transistor is connected to the gate of the twelfth transistor, the source is grounded, and the drain is connected to the drain of the fourteenth transistor; the source of the sixteenth transistor is connected to the tenth transistor The gate of the fifth transistor is connected to the drain of the ninth transistor; the gate of the seventeenth transistor is connected to the gate of the sixteenth transistor, the source is connected to the source of the sixteenth transistor, and the drain is connected to the drain of the tenth transistor; the gate of the eighteenth transistor is connected to the drain of the sixteenth transistor, and the drain is connected to the gate of the fourteenth transistor; the gate of the nineteenth transistor is connected to the drain of the fifteenth transistor, and the drain is connected to the source of the eighteenth transistor; the gate of the twentieth transistor is connected to the drain of the eighteenth transistor, and the source is connected to the source of the nineteenth transistor; the gate of the twenty-first transistor is connected to the drain of the seventeenth transistor, the source is connected to the drain of the twenty-th transistor, and the drain is connected to the gate of the nineteenth transistor. The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are all PMOS transistors, and the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor are all NMOS transistors.

[0070] The microcontroller 200 is configured as follows: in the first clock cycle of the first clock signal, control the comparator 124 to compare the highest position of the register to 1 one by one, instruct the capacitor array digital-to-analog converter 126 to output the corresponding voltage to the inverting input terminal of the comparator 124, and control the comparator 124 to compare the voltage received at its inverting input terminal with the common-mode voltage; if the common-mode voltage is greater than the voltage received at the inverting input terminal, control the comparator 124 to output 1, otherwise, set the highest position of the register to 0; in the second clock cycle of the first clock signal, set the second highest position of the register to 1, instruct the capacitor array digital-to-analog converter 126 to output the corresponding voltage to the inverting input terminal of the comparator 124, control the comparator 124 to compare the voltage it receives and output the corresponding comparison result. The present invention adopts a 10-bit SAR ADC with a sampling rate of 1 MHz, and imports the test data into MATLAB for spectrum analysis to obtain the test results as shown in the figure. Figure 6 The results show that the actual number of effective bits is about 6 bits. The detailed test results are shown in Table 1.

[0071] Table 1

[0072]

[0073] As an example, see Figure 7 In one embodiment of the present application, the acquisition front end 100 includes a sigma-delta analog-to-digital converter 140, and the sigma-delta analog-to-digital converter 140 includes a delta-sigma modulator module 142 and a digital downsampling filter module 144. The input end of the delta-sigma modulator module 142 is connected to the signal voltage, and the output end outputs the modulation and demodulation signal; the digital downsampling filter module 144 is connected to the delta-sigma modulator module 142, and is used to extract and filter the modulation and demodulation signal, and output the target sampling data. The delta-sigma modulator module 142 includes a subtractor 1422, an integrator 1424 and a dynamic comparator 1426. The input end of the subtractor 1422 is connected to both the signal voltage and the modulation and demodulation signal, and is used to calculate the difference between the signal voltage and the voltage amplitude of the modulation and demodulation signal; the integrator 1424 is used to generate a comparison reference voltage according to the received difference, and the switch capacitor integrator 1424 composed of a single-ended common source and common gate operational amplifier is widely used in low-speed and high-precision delta-sigma modulators; the inverting input end of the dynamic comparator 1426 is grounded, the non-phase input end is connected to the comparison reference voltage, and the output end outputs the modulation and demodulation signal, and the same method is adopted. Figure 5Structure. Different from the above-mentioned Nyquist analog-to-digital converter 120, oversampling is to sample the input signal at a frequency much greater than the Nyquist sampling frequency, thereby reducing the quantization noise within the system frequency band. At the same time, the application of noise shaping technology greatly reduces the noise in the low-frequency band, and most of the quantization noise is pushed to a higher frequency band. In this way, adding a low-pass filter after the delta-sigma modulator can effectively filter out the quantization noise outside the signal bandwidth, greatly improving the system performance. The delta-sigma modulator module 142 adopts a single-loop first-order structure, such as Figure 8 The digital downsampling module mainly uses the hardware description language to construct a CIC decimation filter, extracts and filters the output of the modulator, and finally obtains the digital code. The digital code obtained by the test is imported into the MATLAB software for spectrum analysis and the test results are as follows Fig. 9 The effective number of bits is 8.67 bits, and the detailed test results are shown in Table 2. The test results in Tables 1 and 2 show that the accuracy of ADC can process electrical signals, thereby realizing the function of arc detection.

[0074] Table 2

[0075]

[0076] As an example, see Fig.10 In one embodiment, the SoC architecture for arc detection also includes a distributed temperature sensing module 400, which is connected to the acquisition front end 100 and is used to monitor the temperature changes at the corresponding positions of the architecture during operation to achieve temperature compensation. In order to facilitate the monitoring of the temperature changes at the corresponding positions of the system during operation and to achieve quantitative output of the temperature. Traditional temperature sensors use the temperature characteristics of bipolar transistors (BJTs) to achieve temperature sensing functions. Although they have high accuracy and good linearity, they have a large area and high power consumption. The fully digital temperature sensor based on MOSFETS has a small area and low power consumption, and is suitable for the distributed temperature sensing module 400 in this design. The structure of the distributed temperature sensing module 400 is as follows Fig.11As shown. The distributed temperature sensing module 400 includes: a first transistor, configured as: a source connected to ground, and a gate connected to a first DC power supply; a second transistor, configured as: a source connected to ground, and a drain connected to the gate of the first transistor; a third transistor, configured as: a source connected to ground, and a drain connected to a second DC power supply; a fourth transistor, configured as: a source connected to the drain of the second transistor, a drain connected to the gate, and a gate connected to the gate of the second transistor; a fifth transistor, configured as: a source connected to the drain of the third transistor, a drain connected to the gate, and a gate connected to the gate of the third transistor; a sixth transistor, configured as: a drain connected to the drain of the first transistor; a seventh transistor, configured as: a source connected to the source of the sixth transistor, a drain connected to the drain of the fourth transistor, and a gate connected to the gate of the sixth transistor; an eighth transistor, configured as: a source connected to the source of the seventh transistor, a drain connected to the drain of the fifth transistor, and a gate connected to the gate of the seventh transistor. The first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all PMOS transistors, and the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.

[0077] The distributed temperature sensing module 400 adopts differential output, which not only enhances the resistance to power supply noise, but also improves the linearity of the temperature characteristic curve. The layout of the eight temperature sensors refers to the implementation form of digital standard cells, which is compatible with the digital automatic layout and routing process. It can be embedded in any digital standard cell row of equal height. The area size is comparable to that of ordinary standard cells, and almost no static current is consumed. The temperature sensor is connected to the front end of the ADC to achieve quantized output of temperature. Fig.12 The test results show that within the range of -10℃ to 70℃, the temperature sensing unit area of ​​the temperature sensor is only 24.08 square microns, and the maximum measurement error is -1.25℃ / +2℃, which is sufficient to monitor the temperature changes at different positions of the architecture during operation, thereby achieving temperature compensation.

[0078] As an example, see Fig.13In one embodiment, the SoC architecture for arc detection further includes a reset circuit and a phase-locked loop circuit. The reset circuit is connected to the microcontroller 200 and is used to reset the microcontroller 200 to an initial state; the phase-locked loop circuit is connected to the microcontroller 200 and is used to set the main clock frequency of the microcontroller 200 by configuring the frequency division ratio of the register. The reset circuit is used to restore the architecture to its original state to ensure that the architecture works stably and reliably, and the phase-locked loop circuit is used to achieve a stable and high-frequency clock signal. In one of the embodiments, the architecture also includes four timers for single overflow trigger interrupt or cyclic overflow trigger interrupt; the debugging interface includes Watchdog, GPIO (General-purpose input / output) and JTAG debugging interface; the communication interface includes UART (Universal Asynchronous Receiver / Transmitter) interface and SPI interface, the SPI interface is used to transfer the program stored in the external FLASH architecture to SRAM when the system boots from ROM, and can be used as a normal SPI bus after the boot is completed; two PWM (Pulse width modulation) signals are used to realize motor speed regulation / inversion. In one of the embodiments, the architecture also includes a low-dropout regulator for providing working power. In order to provide a stable DC voltage power supply. In one of the embodiments, the SoC software development environment for arc detection uses Zhongtian C-SKY CPU Software Development Kit CDS Release V4.3. CDS Workbench is used to compile programs written in C language and download the compiled executable files to the CK CPU for debugging and running. CDSWorkbench is developed based on Eclipse, and its interface is similar to many ARM / Xilinx development tools. The usage is basically the same. When downloading and debugging software, you need to use the CK CPU downloader to connect to the JTAG interface of the SoC through the JTAG interface.

[0079] After completing the design of the system Register Transfer Level (RTL), IP integration and functional simulation verification, the Design Compiler tool is used to synthesize the RTL to obtain the gate-level netlist of the corresponding process and complete the post-synthesis simulation. If there is a problem with the simulation, it may be necessary to modify the constraints of the synthesis and re-synthesize or modify the RTL and then re-synthesize until the simulation verification is correct. After the post-synthesis simulation passes, the Innovus software is used to layout and route the system. First, plan the size of the architecture, determine the location and number of PADs, and the layout of each IP. Then plan the power grid, layout the digital units, design the clock tree, and finally optimize the routing and add virtual to meet the density requirements of DRC (Design Rule Check). Check the timing report to ensure that the timing meets the requirements. Finally, the design is verified. After passing the DRC, LVS (Layout Versus Schematic, the identity verification of the layout and the circuit diagram) and ANTENNA verification, the post-simulation of the timing back-annotation is performed. If there is a problem with the simulation, it is necessary to re-layout and re-verify, and deliver the tape-out after confirming that the post-simulation is correct.

[0080] As an example, see Fig.14 In one embodiment, the test system includes a PC, a JTAG downloader, a DC voltage regulator, a signal generator, and a UART-to-USB module; the PC is connected to the JTAG debugging interface of the SoC system through the JTAG downloader, and is connected to the UART interface of the SoC system through the UART-to-USB module; the DC voltage regulator is used to provide voltage to the SoC system; the signal generator is used to provide a sine wave input to the ADC of the SoC system. The test process includes: online debugging through the JTAG downloader, configuring the measurement mode of the Nyquist analog-to-digital converter and the oversampling analog-to-digital converter by writing C language, in the continuous sampling mode, the data sampled by the ADC can be stored in the SRAM of the SoC system, after a certain number of accesses, the ADC sampling results stored in the SRAM are transmitted to the PC through the UART interface through the UART-to-USB, and the data obtained by the UART interface are saved or printed through python processing, and then the saved data is imported into Matlab for spectrum analysis processing of the data.

[0081] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0082] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A SoC architecture for arc detection, characterized in that: For sampling electrical signals in a power grid and acquiring target sampling data for identifying fault arcs, the SoC architecture includes: The acquisition front end is used to sample the electrical signals in the power grid, obtain initial sampling data, and process the initial sampling data to obtain target sampling data including the fault arc; A memory, used for storing programs and data, wherein the programs include user programs and boot programs; A microcontroller is electrically connected to the memory and the acquisition front end, and is used to respond to a start instruction, control the user program in the external storage space to be stored in a first preset position in the memory; and control the target sampling data in a preset sampling mode to be stored in a second preset position in the memory according to the program; Wherein, the acquisition front end includes a sigma-delta analog-to-digital converter; the sigma-delta analog-to-digital converter includes: a delta-sigma modulator module, which is configured as follows: an input end is connected to a signal voltage, and an output end outputs a modulation and demodulation signal, and the delta-sigma modulator module is a single-loop first-order structure; A distributed temperature sensing module, connected to the acquisition front end, is used to monitor the temperature changes at corresponding positions of the architecture during operation to achieve temperature compensation; The distributed temperature sensing module includes: a first transistor, configured as follows: a source connected to ground, and a gate connected to a first DC power supply; A second transistor is configured as follows: a source electrode is grounded, and a drain electrode is connected to a gate electrode of the first transistor; A third transistor is configured as follows: a source electrode is grounded, and a drain electrode is connected to a second DC power source; a fourth transistor, configured as follows: a source connected to the drain of the second transistor, a drain connected to a gate, and a gate connected to the gate of the second transistor; a fifth transistor, configured as follows: a source connected to the drain of the third transistor, a drain connected to the gate, and a gate connected to the gate of the third transistor; a sixth transistor, configured such that: a drain is connected to the drain of the first transistor; a seventh transistor, configured as follows: a source connected to the source of the sixth transistor, a drain connected to the drain of the fourth transistor, and a gate connected to the gate of the sixth transistor; The eighth transistor is configured as follows: a source connected to the source of the seventh transistor, a drain connected to the drain of the fifth transistor, and a gate connected to the gate of the seventh transistor.

2. The SoC architecture for arc detection according to claim 1, characterized in that: The acquisition front end may be replaced by a Nyquist analog-to-digital converter.

3. The SoC architecture for arc detection according to claim 2, characterized in that: The Nyquist analog-to-digital converter comprises: The sampling switch is configured as follows: the input end is connected to the common mode voltage; A comparator is configured as follows: an inverting input terminal is connected to the output terminal of the sampling switch, a non-inverting input terminal is connected to a common mode voltage, and an output terminal is used to output the target sampling data; A capacitor array digital-to-analog converter includes a capacitor array and a plurality of switching switches, each of the switching switches includes an output terminal connected to a corresponding capacitor and a first input terminal, a second input terminal, and a third input terminal; the first input terminal is connected to a reference voltage, the second input terminal is connected to a signal voltage, and the third input terminal is connected to a ground line.

4. The SoC architecture for arc detection according to claim 3, characterized in that: The second preset location includes a register.

5. The SoC architecture for arc detection according to claim 4, characterized in that: The comparator comprises: The preamplifier unit is configured as follows: a first input terminal is connected to a common mode voltage, a second input terminal is connected to an output terminal of the sampling switch, a third input terminal is connected to a first clock signal, a first output terminal is used to output a first differential signal, and a second output terminal is used to output a second differential signal; A latch comparison unit is connected to the preamplifier unit and is configured as follows: a first input terminal is connected to the first differential signal, a second input terminal is connected to the second differential signal, and an output terminal is used to output the target sampling data; The microcontroller is configured to: In the first clock cycle of the first clock signal, the comparator is controlled to compare the highest position of the register to 1 successively, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to the inverting input terminal of the comparator, and controlling the comparator to compare the voltage received at its inverting input terminal with the common mode voltage; if the common mode voltage is greater than the voltage received at the inverting input terminal, the comparator is controlled to output 1, otherwise, the highest position of the register is set to 0; In the second clock cycle of the first clock signal, the second highest bit of the register is set to 1, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to the inverting input terminal of the comparator, controlling the comparator to compare the received voltage and output a corresponding comparison result.

6. The SoC architecture for arc detection according to claim 1, characterized in that: The sigma-delta analog-to-digital converter comprises: The digital down-sampling filter module is connected to the delta-sigma modulator module, and is used to extract and filter the modulation and demodulation signal, and output the target sampling data.

7. The SoC architecture for arc detection according to claim 1, characterized in that: The delta-sigma modulator module includes: A subtractor, configured as follows: an input end is connected to both the signal voltage and the modulation and demodulation signal, and is used to calculate the difference between the voltage amplitude of the signal voltage and the voltage amplitude of the modulation and demodulation signal; an integrator, configured to generate a comparison reference voltage according to the received difference; The dynamic comparator is configured as follows: the inverting input terminal is grounded, the non-inverting input terminal is connected to the comparison reference voltage, and the output terminal outputs the modulation and demodulation signal.

8. The SoC architecture for arc detection according to any one of claims 4 to 7, characterized in that: Also includes: A reset circuit, connected to the microcontroller, for resetting the microcontroller to an initial state; and / or The phase-locked loop circuit is connected to the microcontroller and is used to set the main clock frequency of the microcontroller by configuring the frequency division ratio of the register.

9. The SoC architecture for arc detection according to any one of claims 1 to 7, characterized in that: Also includes: Low dropout voltage regulator, used to provide working power.

10. An arc detection device, characterized in that: include: An architecture according to any one of claims 1 to 9.

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