Display device

Abstract

A display device is provided. The display device includes a substrate; a first pixel circuit on the substrate and including a first driving thin film transistor and a first storage capacitor electrically connected to the first driving thin film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second driving thin film transistor and a second storage capacitor electrically connected to the second driving thin film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit; a second initialization voltage line electrically connected to the first initialization voltage line; and a driving voltage line between the first pixel circuit and the second pixel circuit, wherein a channel region of the first driving thin film transistor or a channel region of the second driving thin film transistor is between the second initialization voltage line and the driving voltage line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0074445, filed on June 18, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Aspects of one or more example embodiments relate to a display apparatus. BACKGROUND

[0003] Among display apparatuses, an organic light emitting display apparatus has many benefits such as a relatively wide viewing angle, a relatively good contrast, and a relatively high response speed, and thus, the organic light emitting display apparatus has attracted attention as a next generation display apparatus.

[0004] In general, an organic light emitting display apparatus includes a thin film transistor and an organic light emitting device on a substrate, in which the organic light emitting device emits light. The organic light emitting display apparatus can be used as a display device for a relatively small size product such as a cellular phone or a large size product such as a television.

[0005] The organic light emitting display apparatus includes a thin film transistor, a capacitor, etc. capable of operating the organic light emitting display apparatus. The thin film transistor can include a semiconductor layer including a channel region, a source region, and a drain region, and a gate electrode electrically insulated from the semiconductor layer via a gate insulating layer.

[0006] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore, it can not necessarily be construed as the prior art that is already known to those skilled in the art. SUMMARY

[0007] Aspects of one or more example embodiments relate to a display apparatus in which a luminance difference that can occur due to a voltage line (e.g., an initialization voltage line) is improved. However, this characteristic is an example, and the scope of embodiments according to the disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings or can be learned by practice of the disclosed embodiments.

[0009] According to one or more example embodiments, a display apparatus includes a substrate; a first pixel circuit on the substrate and including a first drive thin-film transistor and a first storage capacitor electrically connected to the first drive thin-film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second drive thin-film transistor and a second storage capacitor electrically connected to the second drive thin-film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction; and a drive voltage line extending in the second direction between the first pixel circuit and the second pixel circuit, wherein a channel region of the first drive thin-film transistor or a channel region of the second drive thin-film transistor is between the second initialization voltage line and the drive voltage line.

[0010] According to some example embodiments, the first pixel circuit can further include a first operation control thin-film transistor electrically connected to the drive voltage line, the second pixel circuit can further include a second operation control thin-film transistor electrically connected to the drive voltage line, and the first operation control thin-film transistor and the second operation control thin-film transistor can be asymmetric with respect to a virtual axis passing between the first pixel circuit and the second pixel circuit.

[0011] According to some example embodiments, a semiconductor layer of the first operation control thin-film transistor can be electrically connected to the drive voltage line through a first connection electrode.

[0012] According to some example embodiments, the first connection electrode can include a 1-1 connection electrode corresponding to a portion of any one of the electrodes of the first storage capacitor and contacting the drive voltage line, and a 1-2 connection electrode contacting the 1-1 connection electrode and a semiconductor layer of the first operation control thin-film transistor.

[0013] According to some example embodiments, the first pixel circuit can further include a first compensation thin-film transistor electrically connected to the first drive thin-film transistor, and a portion of a semiconductor layer of the first compensation thin-film transistor can be superposed with a shield electrode electrically connected to the drive voltage line.

[0014] According to some example embodiments, the second pixel circuit can further include a second compensation thin-film transistor electrically connected to the second drive thin-film transistor, and a portion of a semiconductor layer of the second compensation thin-film transistor can be superposed with a shield electrode electrically connected to the second initialization voltage line.

[0015] According to some example embodiments, the second initialization voltage line can be on the same layer as the drive voltage line.

[0016] According to some example embodiments, the second initialization voltage line can be on a layer above the first initialization voltage line.

[0017] According to some example embodiments, the second initialization voltage line can be electrically connected to the first initialization voltage line through a second connection electrode integral with the second initialization voltage line.

[0018] According to some example embodiments, the first pixel circuit can further include a first initialization thin film transistor electrically connected to the first initialization voltage line, and the second connection electrode can include: a 2-1 connection electrode superposed with a portion of the first initialization voltage line and electrically connecting the first initialization voltage line with the second initialization voltage line; and a 2-2 connection electrode extending from the 2-1 connection electrode and electrically connecting the first initialization voltage line with a semiconductor layer of the first initialization thin film transistor.

[0019] According to one or more example embodiments, a display apparatus includes: a substrate; a first pixel circuit on the substrate and including a first drive thin film transistor and a first storage capacitor electrically connected to the first drive thin film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second drive thin film transistor and a second storage capacitor electrically connected to the second drive thin film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction; and a drive voltage line extending in the second direction between the first pixel circuit and the second pixel circuit, wherein the second initialization voltage line is superposed with the drive voltage line.

[0020] According to some example embodiments, the first pixel circuit and the second pixel circuit can be symmetrical with respect to a virtual axis passing through between the first pixel circuit and the second pixel circuit.

[0021] According to some example embodiments, the first pixel circuit can further include a first compensation thin film transistor electrically connected to the first drive thin film transistor, and the second pixel circuit can further include a second compensation thin film transistor electrically connected to the second drive thin film transistor, and a portion of a semiconductor layer of the first compensation thin film transistor and a portion of a semiconductor layer of the second compensation thin film transistor can be superposed with a shield electrode electrically connected to the drive voltage line.

[0022] According to some example embodiments, the drive voltage line can be on a layer above the first initialization voltage line, and the second initialization voltage line can be on a layer above the drive voltage line.

[0023] According to some example embodiments, the first initialization voltage line and the second initialization voltage line can be electrically connected to each other through a third connection electrode on a layer between the first initialization voltage line and the second initialization voltage line.

[0024] According to one or more example embodiments, a display apparatus includes a substrate including a hole, a first pixel circuit and a second pixel circuit adjacent to each other around the hole, a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction, a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction, and a driving voltage line extending in the second direction between the first pixel circuit and the second pixel circuit, wherein at least one of the first initialization voltage line, the second initialization voltage line, and the driving voltage line is disconnected around the hole.

[0025] According to some example embodiments, the first pixel circuit can include a first operation control thin film transistor electrically connected to the driving voltage line, the second pixel circuit can include a second operation control thin film transistor electrically connected to the driving voltage line, and the first operation control thin film transistor and the second operation control thin film transistor can be asymmetric with respect to the driving voltage line.

[0026] According to some example embodiments, a semiconductor layer of the first operation control thin film transistor can be electrically connected to the driving voltage line through a first connection electrode, and the first connection electrode can include a 1-1 connection electrode corresponding to a portion of any one of electrodes of a first storage capacitor in the first pixel circuit and contacting the driving voltage line, and a 1-2 connection electrode contacting the 1-1 connection electrode and the semiconductor layer of the first operation control thin film transistor.

[0027] According to some example embodiments, the first pixel circuit and the second pixel circuit can be symmetric with respect to the driving voltage line.

[0028] According to some example embodiments, the driving voltage line can be on a layer above the first initialization voltage line, and the second initialization voltage line can be on a layer above the driving voltage line.

[0029] According to some example embodiments, the first initialization voltage line and the second initialization voltage line can be electrically connected to each other through a third connection electrode on a layer between the first initialization voltage line and the second initialization voltage line. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other aspects, features, and characteristics of some embodiments of the disclosure will become more apparent from the following description with reference to the drawings, in which:

[0031] Figure 1 is a schematic perspective view of a display apparatus according to some example embodiments;

[0032] Figure 2is a schematic equivalent circuit diagram of a pixel circuit electrically connected to any one of the light emitting diodes of the display device according to some example embodiments;

[0033] Figure 3 is a plan view of pixel circuits arranged in a display area of the display device according to some example embodiments;

[0034] Figures 4 to 7 is a plan view of a process for describing forming a pixel circuit of Figure 3 according to some example embodiments;

[0035] Figure 8 is a cross-sectional view of the display device of Figure 3 taken along line I-I’ of Figure 3 ;

[0036] Figure 9 is a cross-sectional view of the display device of Figure 3 taken along line II-II’ of Figure 3 ;

[0037] Figure 10 is a plan view of pixel circuits arranged in a display area of the display device according to some example embodiments;

[0038] Figures 11 to 14 is a plan view of a process for describing forming a pixel circuit of Figure 10 according to some example embodiments;

[0039] Figure 15 is a cross-sectional view of the display device of Figure 10 taken along line III-III’ of Figure 10 ;

[0040] Figure 16 is a schematic plan view of a structure around an assembly area according to some example embodiments; and

[0041] Figure 17A and Figure 17B are schematic cross-sectional views of a portion of the display device according to some example embodiments. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to aspects of some example embodiments, one or more examples of which are illustrated in the drawings, wherein like reference numerals refer to like elements throughout. In this regard, embodiments according to the present disclosure can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely descriptive of aspects of the present disclosure and are not intended to limit the present disclosure in any manner. Thus, the example embodiments are described below by referring to the drawings, which are intended to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0043] Although embodiments according to the present disclosure can have various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will be described in detail herein. The disclosed effects and features, and implementation methods thereof will become apparent by referring to the accompanying drawings and embodiments as more fully described below. However, embodiments according to the present disclosure are not limited to the example embodiments described herein below and can be implemented in various forms.

[0044] Hereinafter, aspects of some example embodiments of the disclosure will be described in more detail by referring to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same or substantially similar components, and the description will not be repeated.

[0045] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] It will be further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0048] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. That is, for example, there can be an intervening layer, region or component.

[0049] The sizes of elements in the drawings can be exaggerated for the purpose of explanation. For example, the sizes and thicknesses of elements in the drawings are arbitrarily indicated for the purpose of explanation, and thus the disclosure is not necessarily limited to the illustrated figures.

[0050] When a certain embodiment can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0051] In this specification, the expression "A and / or B" can indicate A, B, or A and B. Also, the expression "at least one of A and B" can indicate A, B, or A and B.

[0052] In the following embodiments, it will be understood that when an element, region, or layer is referred to as being connected to another element, region, or layer, it can be directly and / or indirectly connected to the another element, region, or layer. For example, in this specification, it will be understood that when an element, region, or layer is referred to as being in contact with or electrically connected to another element, region, or layer, it can be directly and / or indirectly in contact with or electrically connected to the another element, region, or layer.

[0053] The x-axis, y-axis and z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0054] Hereinafter, aspects of some example embodiments will be described in greater detail with reference to the accompanying drawings.

[0055] Figure 1 is a schematic perspective view of a display apparatus 1 according to some example embodiments.

[0056] As Figure 1 As shown in FIG. 1, the display apparatus 1 according to some example embodiments can include a display area DA in which light is emitted and a non-display area NDA in which light is not emitted. The non-display area NDA can completely surround the display area DA. The substrate can include a first area corresponding to the display area DA and a second area corresponding to the non-display area NDA, in which the pixel circuit to be described below and the light emitting diode electrically connected to the pixel circuit, respectively, can be disposed in the first area of the substrate.

[0057] Figure 1 The display apparatus 1 including the display area DA having a square shape is illustrated. However, the display area DA can have an arbitrary shape such as a circular shape, an elliptical shape, or a polygonal shape.

[0058] In some embodiments, the display apparatus 1 can include a component area CA. The component area CA can be disposed inside the display area DA and can be completely surrounded by the display area DA. A component can be disposed in the component area CA, and the display apparatus 1 can perform various functions by using the component.

[0059] The components can include electronic elements using light and / or sound. The electronic elements can include a sensor configured to measure a distance (such as a proximity sensor), a sensor configured to identify a part of a user's body (e.g., a fingerprint, an iris, a face, etc.), a small light configured to output light, an image sensor configured to capture an image (e.g., a camera), etc. The electronic elements using light can use light of various wavelength ranges (such as visible light, infrared, ultraviolet, etc.). The electronic elements using sound can use sound of an ultrasonic band or other frequency bands.

[0060] The light and / or sound of the electronic elements can pass through or be transmitted through the component area CA, and thus, the component area CA can be a transmission area through which light and / or sound can be transmitted.

[0061] Hereinafter, an organic light emitting display apparatus including an organic light emitting diode will be described as an example of the display apparatus 1 according to some example embodiments. However, the display apparatus 1 according to embodiments of the present disclosure is not limited thereto. The light emitting diode of the display apparatus 1 can include an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode can include a PN junction diode including an inorganic semiconductor material. When a voltage is applied to the PN junction diode in a normal direction, holes and electrons can be injected into the PN junction diode, and energy generated by recombination of the holes and the electrons can be converted into light energy to emit light of a specific color. The above-described inorganic light emitting diode can have a width of several micrometers to several hundred micrometers, and in some embodiments, the inorganic light emitting diode can be referred to as a micro light emitting diode.

[0062] Figure 2 is a schematic equivalent circuit diagram of a pixel circuit PC electrically connected to any one of the light emitting diodes of the display apparatus 1 according to some example embodiments.

[0063] As Figure 2 indicated in the above-described Equation 1, the light emitting diode can include an organic light emitting diode OLED, and the organic light emitting diode OLED can be electrically connected to a pixel circuit PC including a plurality of thin film transistors and a capacitor (a plurality of capacitors).

[0064] According to some example embodiments, the pixel circuit PC can include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst can be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line 30. At least one of the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the driving voltage line 30 can be shared by adjacent pixel circuits PC.

[0065] Although Figure 2The thin film transistors T1 to T7 are shown implemented as p-channel MOS (pMOS) field effect transistors (FETs) (pMOSFETs), but one of ordinary skill in the art will recognize that at least one of the thin film transistors T1 to T7 can be implemented as n-channel MOS (nMOS) FETs (nMOSFETs) according to some example embodiments. For example, among the thin film transistors T1 to T7, the drive thin film transistor T1, the switch thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6 can be implemented as pMOSFETs, while the compensation thin film transistor T3, the initialization thin film transistor T4, and the reset thin film transistor T7 can be implemented as nMOSFETs. Embodiments according to the present disclosure are not limited thereto, and the number of transistors and the type of transistors can vary (e.g., there can be additional transistors or other electronic components or fewer transistors or other components) according to some example embodiments without departing from the spirit and scope of embodiments according to the present disclosure.

[0066] The drive gate electrode G1 of the drive thin film transistor T1 can be connected to the lower electrode CE1 of the storage capacitor Cst, the drive source electrode S1 of the drive thin film transistor T1 can be connected to the drive voltage line 30 through the operation control thin film transistor T5, and the drive drain electrode D1 of the drive thin film transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The drive thin film transistor T1 can receive the data signal Dm according to the switching operation of the switch thin film transistor T2, and supply a drive current I OLED to the organic light emitting diode OLED.

[0067] The switch gate electrode G2 of the switch thin film transistor T2 can be connected to the scan line SL, the switch source electrode S2 of the switch thin film transistor T2 can be connected to the data line DL, and the switch drain electrode D2 of the switch thin film transistor T2 can be connected to the drive source electrode S1 of the drive thin film transistor T1 while being connected to the drive voltage line 30 through the operation control thin film transistor T5. The switch thin film transistor T2 can be turned on in response to a scan signal Sn transmitted through the scan line SL, and can perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the drive source electrode S1 of the drive thin film transistor T1.

[0068] The compensation gate electrode G3 of the compensation thin film transistor T3 can be connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 can be connected to the driving drain electrode D1 of the driving thin film transistor T1, and the compensation drain electrode D3 of the compensation thin film transistor T3 can be connected to the lower electrode CE1 of the storage capacitor Cst, the initialization drain electrode D4 of the initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 can be turned on in response to a scan signal Sn received through the scan line SL, and can electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1 to diode-connect the driving thin film transistor T1.

[0069] The initialization gate electrode G4 of the initialization thin film transistor T4 can be connected to a previous scan line SL-1, the initialization source electrode S4 of the initialization thin film transistor T4 can be connected to an initialization voltage line VL, and the initialization drain electrode D4 of the initialization thin film transistor T4 can be connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The initialization thin film transistor T4 can be turned on in response to a previous scan signal Sn-1 received through the previous scan line SL-1, and can perform an initialization operation of initializing a voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting an initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0070] The operation control gate electrode G5 of the operation control thin film transistor T5 can be connected to an emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 can be connected to a driving voltage line 30, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0071] The emission control gate electrode G6 of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 can be connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the reset source electrode S7 of the reset thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0072] The operation control thin film transistor T5 and the emission control thin film transistor T6 can be simultaneously turned on in response to an emission control signal En received through the emission control line EL, so that a driving voltage ELVDD can be transmitted to the organic light emitting diode OLED and a driving current IOLED may flow in an organic light emitting diode OLED.

[0073] A reset gate electrode G7 of the reset thin film transistor T7 can be connected to a previous scan line SL-1, a reset source electrode S7 of the reset thin film transistor T7 can be connected to an emission control drain electrode D6 of the emission control thin film transistor T6 and a pixel electrode of the organic light emitting diode OLED, and a reset drain electrode D7 of the reset thin film transistor T7 can be connected to an initialization source electrode S4 of the initialization thin film transistor T4 and an initialization voltage line VL.

[0074] The scan line SL and the previous scan line SL-1 can be electrically connected to each other, and thus the same scan signal Sn can be applied to the scan line SL and the previous scan line SL-1. Accordingly, the reset thin film transistor T7 can be turned on in response to the scan signal Sn transmitted through the previous scan line SL-1, and can perform an operation of initializing the pixel electrode of the organic light emitting diode OLED.

[0075] Figure 2 It is shown that the compensation thin film transistor T3 and the initialization thin film transistor T4 have double gate electrodes. However, according to some example embodiments, the compensation thin film transistor T3 and the initialization thin film transistor T4 can have a single gate electrode.

[0076] The storage capacitor Cst can include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst can be connected to the driving gate electrode G1 of the driving thin film transistor T1, and the upper electrode CE2 of the storage capacitor Cst can be connected to the driving voltage line 30. The storage capacitor Cst can store and hold a voltage corresponding to a difference between the voltage of the driving voltage line 30 and the voltage of the driving gate electrode G1 of the driving thin film transistor T1, thereby maintaining the voltage applied to the driving gate electrode G1 of the driving thin film transistor T1.

[0077] The organic light emitting diode OLED can include a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, the intermediate layer including an emission layer. A common voltage ELVSS can be applied to the counter electrode, the counter electrode being integrally formed throughout a plurality of pixels. The organic light emitting diode OLED can emit light by receiving a driving current I OLED from the driving thin film transistor T1, so that the display apparatus 1 can display an image. For reference, the counter electrode can extend outside of the display area DA to be connected to an electrode power line, and the electrode voltage ELVSS can be applied to the electrode power line.

[0078] The signal lines SL, SL-1, EL, and DL can include a scan line SL that transmits a scan signal Sn, a previous scan line SL-1 that transmits a previous scan signal Sn-1 to the initialization thin-film transistor T4 and transmits the previous scan signal Sn-1 to the reset thin-film transistor T7, an emission control line EL that transmits an emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6, and a data line DL that crosses the scan line SL and transmits a data signal Dm. The drive voltage line 30 can transmit a drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VL can transmit an initialization voltage Vint to the initialization thin-film transistor T4 and the reset thin-film transistor T7.

[0079] Figure 2 A case where each of the pixel circuits PC includes the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the drive voltage line 30 is shown. However, the disclosure is not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the drive voltage line 30 can be shared by adjacent pixel circuits PC. For example, as will be described below Figure 3 and Figure 10 The drive voltage line 30 can be shared by adjacent pixel circuits PC, and as shown in Figure 10 at least a portion of the initialization voltage line VL can be shared by adjacent pixel circuits PC.

[0080] Figure 3 is a plan view of pixel circuits PC arranged in a display area DA of a display device 1 according to some example embodiments. For reference, Figure 3 The illustration of the organic light-emitting diode OLED is omitted. Referring to Figure 3 The pixel circuits PC can be arranged in the x-direction and the y-direction. For example, the pixel circuits PC can be arranged in the x-direction and the y-direction to form a matrix. Figure 3 A first pixel circuit PC1 and a second pixel circuit PC2 included in the arranged pixel circuits PC are shown, where the first pixel circuit PC1 and the second pixel circuit PC2 are arranged adjacent to each other in a direction (e.g., the x-direction).

[0081] According to some example embodiments, the first pixel circuit PC1 and the second pixel circuit PC2 can have a laterally asymmetric structure. That is, the first pixel circuit PC1 and the second pixel circuit PC2 can be asymmetric with respect to each other based on a virtual first axis AX1 passing between the first pixel circuit PC1 and the second pixel circuit PC2.

[0082] Each of the first and second pixel circuits PC1 and PC2 can include a thin-film transistor and a storage capacitor. For example, the first and second pixel circuits PC1 and PC2 can include the thin-film transistors T1 to T7 and the storage capacitor Cst described above with reference to FIG. 1. Figure 2 Each of the first and second pixel circuits PC1 and PC2 can include a thin-film transistor and a storage capacitor. For example, the first and second pixel circuits PC1 and PC2 can include the thin-film transistors T1 to T7 and the storage capacitor Cst described above with reference to FIG. 1.

[0083] The scan line SL can extend in the x direction. The scan line SL can be electrically connected to the pixel circuit PC arranged in the x direction, and can transmit a scan signal Sn.

[0084] The previous scan line SL-1 can extend in the x direction. The previous scan line SL-1 can be electrically connected to the pixel circuit PC arranged in the x direction, and can transmit a previous scan signal Sn-1.

[0085] The emission control line EL can extend in the x direction. The emission control line EL can be electrically connected to the pixel circuit PC arranged in the x direction, and can transmit an emission control signal En.

[0086] The initialization voltage line VL can include a first initialization voltage line 10 and a second initialization voltage line 20 electrically connected to the first initialization voltage line 10. The first initialization voltage line 10 can extend in a first direction (e.g., the x direction), and the second initialization voltage line 20 can extend in a second direction (e.g., the y direction) crossing the first direction. Accordingly, the first and second initialization voltage lines 10 and 20 can cross each other to form a mesh shape. The first initialization voltage line 10 can transmit an initialization voltage Vint to the pixel circuit PC arranged in the x direction, and the second initialization voltage line 20 can transmit the initialization voltage Vint to the pixel circuit PC arranged in the y direction. The first and second initialization voltage lines 10 and 20 can be electrically connected to each other.

[0087] The drive voltage line 30 can extend in the y direction. The drive voltage line 30 can be electrically connected to the pixel circuit PC arranged in the y direction, and can transmit a drive voltage ELVDD. According to some example embodiments, the drive voltage line 30 and the second initialization voltage line 20 can be alternately positioned in the x direction. For example, according to some example embodiments, the drive voltage line 30 and the second initialization voltage line 20 can be alternately located between the pixel circuits PC arranged in the x direction. The drive voltage line 30 arranged between the pixel circuits PC can be shared by adjacent pixel circuits PC (e.g., the first and second pixel circuits PC1 and PC2).

[0088] The data lines DL can extend in the y direction. The data lines DL can be electrically connected to the pixel circuits PC arranged in the y direction, and can transmit data signals Dm. According to some example embodiments, the data lines DL can be located between the second initialization voltage lines 20 and the drive voltage lines 30 adjacent to each other.

[0089] For ease of explanation, the pixel circuit PC will be described in more detail by more specifically referring to a first pixel circuit PC1 and a second pixel circuit PC2 that are a pair of pixel circuits PC arranged in adjacent columns in the same row among a plurality of pixel circuits PC.

[0090] Figures 4 to 7 is a plan view for describing a process of forming the pixel circuit PC according to some example embodiments, Figure 8 is a cross-sectional view of the display device 1 taken along Figure 3 Figure 3 is a cross-sectional view of the display device 1 taken along Figure 9 is a cross-sectional view of the display device 1 taken along Figure 3 is a cross-sectional view of the display device 1 taken along Figure 3 is a cross-sectional view of the display device 1 taken along

[0091] Referring to Figure 4 The semiconductor layer of the first pixel circuit PC1 and the semiconductor layer of the second pixel circuit PC2 can have substantially the same planar shape. Thin film transistors T1 to T7 of each of the first pixel circuit PC1 and the second pixel circuit PC2 can be formed along the semiconductor layer that is curved in various directions. For example, a portion of the semiconductor layer can have a curved shape such as a shape of "C", "Ω", "S", "M", or "W", and thus a large (long) channel length can be formed in a small space. With this structure, the thin film transistors T1 to T7 can have a long channel region, thereby increasing a driving range of a gate voltage applied to a gate electrode. Accordingly, light gray scales emitted from the organic light emitting diode OLED can be adjusted more finely, and display quality can be improved. However, according to some example embodiments and according to the design of the display device 1, a portion of the semiconductor layer can have a straight shape rather than a curved shape. Further, the semiconductor layer of the first pixel circuit PC1 and the semiconductor layer of the second pixel circuit PC2 can be connected to each other.

[0092] ​Each of the semiconductor layers of the first and second pixel circuits PC1 and PC2 can include a channel region of each of the thin film transistors T1 to T7 of the first and second pixel circuits PC1 and PC2, a source region located at one side of the channel region, and a drain region located at the other side of the channel region. For example, the source and drain regions of the semiconductor layer can be doped with impurities, which can include n-type impurities or p-type impurities. The source and drain regions can correspond to the source electrodes S1 to S7 and the drain electrodes D1 to D7, respectively. Hereinafter, for convenience of explanation, the source electrodes S1 to S7 and the drain electrodes D1 to D7 will be referred to as the source regions S1 to S7 and the drain regions D1 to D7, respectively.

[0093] The semiconductor layer of the driving thin film transistor T1 of the first pixel circuit PC1 can include a driving channel region A1 overlapped with a driving gate electrode G1, a driving source region S1 and a driving drain region D1 arranged at both sides of the driving channel region A1. The second pixel circuit PC2 can include a driving thin film transistor T1 arranged at the same position as the driving thin film transistor T1 of the first pixel circuit PC1, and the structure and shape of the driving thin film transistor T1 of the second pixel circuit PC2 can be the same as those of the driving thin film transistor T1 of the first pixel circuit PC1.

[0094] The semiconductor layer of the switching thin film transistor T2 of the first pixel circuit PC1 can include a switching channel region A2 overlapped with a switching gate electrode G2, a switching source region S2 and a switching drain region D2 arranged at both sides of the switching channel region A2. The second pixel circuit PC2 can include a switching thin film transistor T2 arranged at the same position as the switching thin film transistor T2 of the first pixel circuit PC1, and the structure and shape of the switching thin film transistor T2 of the second pixel circuit PC2 can be the same as those of the switching thin film transistor T2 of the first pixel circuit PC1.

[0095] The semiconductor layer of the compensation thin film transistor T3 of the first pixel circuit PC1 can include a compensation channel region A3 overlapped with a compensation gate electrode G3, a compensation source region S3 and a compensation drain region D3 arranged at both sides of the compensation channel region A3. The second pixel circuit PC2 can include a compensation thin film transistor T3 arranged at the same position as the compensation thin film transistor T3 of the first pixel circuit PC1, and the structure and shape of the compensation thin film transistor T3 of the second pixel circuit PC2 can be the same as those of the compensation thin film transistor T3 of the first pixel circuit PC1.

[0096] The semiconductor layer of the initialization thin-film transistor T4 of the first pixel circuit PC1 can include an initialization channel region A4 overlaid with an initialization gate electrode G4, an initialization source region S4 and an initialization drain region D4 arranged at both sides of the initialization channel region A4. The second pixel circuit PC2 can include an initialization thin-film transistor T4 arranged at the same position as the initialization thin-film transistor T4 of the first pixel circuit PC1, and the structure and shape of the initialization thin-film transistor T4 of the second pixel circuit PC2 can be the same as those of the initialization thin-film transistor T4 of the first pixel circuit PC1.

[0097] The semiconductor layer of the operation control thin-film transistor T5 of the first pixel circuit PC1 can include an operation control channel region A5 overlaid with an operation control gate electrode G5, an operation control source region S5 and an operation control drain region D5 arranged at both sides of the operation control channel region A5. The second pixel circuit PC2 can include an operation control thin-film transistor T5 arranged at the same position as the operation control thin-film transistor T5 of the first pixel circuit PC1, and the structure and shape of the operation control thin-film transistor T5 of the second pixel circuit PC2 can be the same as those of the operation control thin-film transistor T5 of the first pixel circuit PC1.

[0098] The semiconductor layer of the emission control thin-film transistor T6 of the first pixel circuit PC1 can include an emission control channel region A6 overlaid with an emission control gate electrode G6, an emission control source region S6 and an emission control drain region D6 arranged at both sides of the emission control channel region A6. The second pixel circuit PC2 can include an emission control thin-film transistor T6 arranged at the same position as the emission control thin-film transistor T6 of the first pixel circuit PC1, and the structure and shape of the emission control thin-film transistor T6 of the second pixel circuit PC2 can be the same as those of the emission control thin-film transistor T6 of the first pixel circuit PC1.

[0099] The semiconductor layer of the reset thin-film transistor T7 of the first pixel circuit PC1 can include a reset channel region A7 overlaid with a reset gate electrode G7, a reset source region S7 and a reset drain region D7 arranged at both sides of the reset channel region A7. The second pixel circuit PC2 can include a reset thin-film transistor T7 arranged at the same position as the reset thin-film transistor T7 of the first pixel circuit PC1, and the structure and shape of the reset thin-film transistor T7 of the second pixel circuit PC2 can be the same as those of the reset thin-film transistor T7 of the first pixel circuit PC1.

[0100] The positions of the source regions S1 to S7 and the drain regions D1 to D7 of the thin-film transistors of each of the first pixel circuit PC1 and the second pixel circuit PC2 can be the same as or different from the positions shown in FIG. 1. According to some example embodiments, Figure 4 the positions of the source regions S1 to S7 and the drain regions D1 to D7 of the thin-film transistors of each of the first pixel circuit PC1 and the second pixel circuit PC2 can be the same as or different from the positions shown in FIG. 1. According to some example embodiments, Figure 4The source regions S1 to S7 illustrated in FIG. 1A can become the drain regions D1 to D7, and the drain regions D1 to D7 can become the source regions S1 to S7.

[0101] The semiconductor layer described above can be formed over the substrate 100. The substrate 100 can include glass, metal, or a polymer resin. In the case where the substrate 100 has a flexible or bendable property, the substrate 100 can include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. However, various modifications can be possible. For example, the substrate 100 can have a multilayer structure of two (or more) layers each including the polymer resin described above and a barrier layer located between the two layers, the barrier layer including an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0102] However, one or more additional layers can be between the substrate 100 and the semiconductor layer. For example, a buffer layer 101 including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer can be between the substrate 100 and the semiconductor layer. The buffer layer 101 can improve planarization of the upper surface of the substrate 100, or prevent, reduce, or minimize penetration of impurities or contaminants from the substrate 100 or the like into the semiconductor layer or the like. The buffer layer 101 can have a single-layer structure or a multilayer structure as needed. In the case of a multilayer structure, one or more layers in the buffer layer 101 can be referred to as a barrier layer.

[0103] Further, the semiconductor layer can include a semiconductor layer including polycrystalline silicon or a semiconductor layer including an oxide. For example, the semiconductor layer can include a Zn-oxide-based material such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. However, the semiconductor layer is not limited thereto, and various modifications can be made. For example, the semiconductor layer can include an oxide semiconductor such as In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) including a metal such as In, Ga, or Sn in ZnO.

[0104] The first gate insulating layer 103 can be formed over the semiconductor layers of the first pixel circuit PC1 and the second pixel circuit PC2, and the gate electrodes G1 to G7 of the scan line SL, the previous scan line SL-1, the emission control line EL, and the thin film transistors T1 to T7 can be formed over the first gate insulating layer 103. Here, the drive gate electrode G1 of the drive thin film transistor T1 can serve not only as a control electrode of the drive thin film transistor T1 but also as a lower electrode CE1 of the storage capacitor Cst. That is, the drive gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst can be integrated with each other.

[0105] The scan line SL, the previous scan line SL-1, and the emission control line EL can extend in the x direction, and can be electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2. The scan line SL, the previous scan line SL-1, or the emission control line EL can be integrated with one or more of the gate electrodes G1 to G7 of the thin film transistors T1 to T7. For example, the previous scan line SL-1 can be integrated with the initialization gate electrode G4 of the initialization thin film transistor T4 and the reset gate electrode G7 of the reset thin film transistor T7, the scan line SL can be integrated with the switching gate electrode G2 of the switching thin film transistor T2 and the compensation gate electrode G3 of the compensation thin film transistor T3, and the emission control line EL can be integrated with the operation control gate electrode G5 of the operation control thin film transistor T5 and the emission control gate electrode G6 of the emission control thin film transistor T6. The driving gate electrode G1 (or the lower electrode CE1 of the storage capacitor Cst) can have a separate (isolated) shape.

[0106] The signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 can include the same material and the same layer structure as each other. For example, the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, or the like. However, each of the scan line SL, the previous scan line SL-1, the emission control line EL, the gate electrodes G1 to G7 of the thin film transistors T1 to T7, and the lower electrode CE1 of the storage capacitor Cst can have a single layer structure or a multi-layer structure. When each of the scan line SL, the previous scan line SL-1, the emission control line EL, the gate electrodes G1 to G7 of the thin film transistors T1 to T7, and the lower electrode CE1 of the storage capacitor Cst has a multi-layer structure, each of the scan line SL, the previous scan line SL-1, the emission control line EL, the gate electrodes G1 to G7 of the thin film transistors T1 to T7, and the lower electrode CE1 of the storage capacitor Cst can include various materials. For example, the multi-layer structure can include a double layer structure of a Mo layer / Al layer, a triple layer structure of a Mo layer / Al layer / Mo layer, or the like.

[0107] The first gate insulating layer 103, the second gate insulating layer 105, the first interlayer insulating layer 107, and the second interlayer insulating layer 109 to be described below can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. Each of the insulating layers 103, 105, 107, and 109 can have a single layer structure or a multi-layer structure as needed. In addition, a contact hole can be formed in the insulating layers 103, 105, 107, and 109, and components of different layers can be electrically connected to each other through the contact hole.

[0108] Referring toFigure 5 After the second gate insulating layer 105 is formed on the structure of the first gate insulating layer 103, the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 of the storage capacitor Cst can be formed on the second gate insulating layer 105. Figure 4 The first initialization voltage line 10 can extend in the x direction, and can be electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2.

[0109] The shield electrode 70 can have a separate shape, and can be positioned such that a portion of the shield electrode 70 overlaps the compensation thin film transistor T3. The shield electrode 70 can improve stability and reliability of a voltage value of the compensation thin film transistor T3.

[0110] The storage capacitor Cst can include the lower electrode CE1 and the upper electrode CE2, and the lower electrode CE1 and the upper electrode CE2 can overlap each other with an insulating layer therebetween, thereby forming a capacitor. In this case, the second gate insulating layer 105 between the lower electrode CE1 and the upper electrode CE2 can serve as a dielectric layer of the storage capacitor Cst. The upper electrode CE2 of the storage capacitor Cst can serve not only as the upper electrode CE2 of the storage capacitor Cst but also as the 1-1 connection electrode 41. That is, the upper electrode CE2 of the storage capacitor Cst and the 1-1 connection electrode 41 can be integrated with each other.

[0111] The first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 positioned on the second gate insulating layer 105 can include the same material as the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 positioned on the first gate insulating layer 103, and have the same layered structure as the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 positioned on the first gate insulating layer 103. For example, the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 can have a multi-layer structure such as a two-layer structure of a Mo layer / Al layer, a three-layer structure of a Mo layer / Al layer / Mo layer, etc.

[0112] Referring to FIG. 1, the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 can be positioned on the second gate insulating layer 105.

[0113] Figure 6 The first interlayer insulating layer 107 can be positioned on the structure of the first gate insulating layer 103 and the second gate insulating layer 105, and the driving voltage line 30, the second initialization voltage line 20, the 1-2 connection electrode 42, and the second connection electrode 50 can be positioned on the first interlayer insulating layer 107. Figure 5 As a reference, the contact hole shown in FIG. 1 can be formed in the first gate insulating layer 103, the second gate insulating layer 105, and / or the first interlayer insulating layer 107 to connect the 1-1 connection electrode 41 to the 1-2 connection electrode 42.

[0114] Figure 6 The contact hole shown in FIG. 1 can be formed in the first gate insulating layer 103, the second gate insulating layer 105, and / or the first interlayer insulating layer 107 to connect the 1-1 connection electrode 41 to the 1-2 connection electrode 42. Figure 6 ​​The layer shown in the middle is electrically connected to the layer below it.

[0115] The drive voltage line 30 can extend in the y direction between the first pixel circuit PC1 and the second pixel circuit PC2, and can be electrically connected to the operation control thin film transistor T5 of the first pixel circuit PC1 and the operation control thin film transistor T5 of the second pixel circuit PC2. That is, the operation control thin film transistor T5 of the first pixel circuit PC1 and the operation control thin film transistor T5 of the second pixel circuit PC2 can share one drive voltage line 30. Accordingly, the drive voltage line 30 can be electrically connected to the first pixel circuit PC1 located at one side of the drive voltage line 30 and the second pixel circuit PC2 located at the other side of the drive voltage line 30. Further, the drive voltage line 30 can supply a voltage to each of the first pixel circuit PC1 and the second pixel circuit PC2 through different paths.

[0116] A path through which the drive voltage line 30 supplies a voltage to the first pixel circuit PC1 will be described with reference to Figure 3 and Figure 8 A path through which the drive voltage line 30 supplies a voltage to the first pixel circuit PC1 will be described with reference to

[0117] The drive voltage line 30 can be electrically connected to the semiconductor layer of the operation control thin film transistor T5 of the first pixel circuit PC1 through the first connection electrode 40. The first connection electrode 40 can include a 1-1 connection electrode 41 and a 1-2 connection electrode 42. The 1-1 connection electrode 41 can correspond to a portion of any one of the electrodes of the storage capacitor Cst of the first pixel circuit PC1, and can contact the drive voltage line 30. The 1-2 connection electrode 42 can contact the 1-1 connection electrode 41 and the semiconductor layer of the operation control thin film transistor T5 of the first pixel circuit PC1.

[0118] For example, the 1-1 connection electrode 41 can correspond to a portion of the upper electrode CE2 of the storage capacitor Cst, and can be electrically connected to the drive voltage line 30 through a contact hole located in a region in which the 1-1 connection electrode 41 is overlapped with the drive voltage line 30. Further, the 1-1 connection electrode 41 can be electrically connected to the 1-2 connection electrode 42 through a contact hole located in a region in which the 1-1 connection electrode 41 is overlapped with the 1-2 connection electrode 42. The 1-2 connection electrode 42 can extend from a contact hole located at one end of the 1-2 connection electrode 42 and connected to the 1-1 connection electrode 41 in a direction toward the operation control thin film transistor T5 of the first pixel circuit PC1. In a region in which the 1-2 connection electrode 42 is overlapped with the semiconductor layer of the operation control thin film transistor T5 of the first pixel circuit PC1, the 1-2 connection electrode 42 can be electrically connected to the semiconductor layer of the operation control thin film transistor T5 of the first pixel circuit PC1 through a contact hole located at the other end of the 1-2 connection electrode 42.

[0119] Accordingly, the driving voltage ELVDD can reach the operation control source electrode S5 at the semiconductor layer of the operation control thin film transistor T5 of the first pixel circuit PC1 from the driving voltage line 30 through the first-1 connection electrode 41 and the first-2 connection electrode 42. The driving voltage ELVDD reaching the operation control source electrode S5 can reach the organic light emitting diode OLED through the driving thin film transistor T1 and the emission control thin film transistor T6 of the first pixel circuit PC1.

[0120] The path of the driving voltage line 30 along which the voltage is supplied to the second pixel circuit PC2 can be different from the path of the driving voltage line 30 along which the voltage is supplied to the first pixel circuit PC1 as described above. The path of the driving voltage line 30 along which the voltage is supplied to the second pixel circuit PC2 can not require the first connection electrode 40.

[0121] For example, the driving voltage line 30 can include a protrusion 45 that can function as a connection electrode. The protrusion 45 of the driving voltage line 30 can be integral with the driving voltage line 30 and can be superposed with the semiconductor layer of the operation control thin film transistor T5 of the second pixel circuit PC2. The driving voltage line 30 can be electrically connected to the semiconductor layer of the operation control thin film transistor T5 of the second pixel circuit PC2 through a contact hole located in the protrusion 45. Accordingly, the driving voltage ELVDD can reach the operation control source electrode S5 of the second pixel circuit PC2 from the driving voltage line 30 through the protrusion 45. The driving voltage ELVDD reaching the operation control source electrode S5 can reach the organic light emitting diode OLED through the driving thin film transistor T1 and the emission control thin film transistor T6 of the second pixel circuit PC2.

[0122] As described above, the driving voltage line 30 can supply the driving voltage ELVDD to the pixel circuits PC located at both sides of the driving voltage line 30 through different paths. Accordingly, two adjacent pixel circuits PC that are not symmetrical to each other based on the driving voltage line 30 can be connected to one driving voltage line 30.

[0123] The second initialization voltage line 20 can correspond to a portion of the initialization voltage line VL and extend in the y direction. The initialization voltage line VL can include a first initialization voltage line 10 electrically connected to the first and second pixel circuits PC1 and PC2 and extending in a first direction (e.g., the x direction), and a second initialization voltage line 20 electrically connected to the first initialization voltage line 10 and extending in a second direction (e.g., the y direction) crossing the first direction. The first and second initialization voltage lines 10 and 20 can cross each other to form a mesh shape. Also, the first and second initialization voltage lines 10 and 20 can be located on different layers and can be electrically connected to each other through the second connection electrode 50. Each of the first and second initialization voltage lines 10 and 20 can be electrically connected to the pixel circuit PC adjacent thereto and can supply the initialization voltage Vint.

[0124] The second initialization voltage line 20 and the driving voltage line 30 can extend in the second direction (e.g., the y direction) across the plurality of pixel circuits PC and can be arranged apart from each other according to a preset pattern. Here, the second initialization voltage line 20 and the driving voltage line 30 can be alternately arranged between the pixel circuits PC such that one second initialization voltage line 20 and one driving voltage line 30 can be positioned for each pair of pixel circuits PC. Also, the driving channel region A1 of the driving thin film transistor T1 of the first pixel circuit PC1 or the driving channel region A1 of the driving thin film transistor T1 of the second pixel circuit PC2 can be between the second initialization voltage line 20 and the driving voltage line 30.

[0125] Accordingly, the second initialization voltage line 20 and the driving voltage line 30 can be alternately electrically connected to the shield electrode 70 included in each of the pixel circuits PC. For example, the shield electrode 70 of the first pixel circuit PC1 can be electrically connected to the driving voltage line 30, and the shield electrode 70 of the second pixel circuit PC2 can be electrically connected to the second initialization voltage line 20. Here, a portion of the semiconductor layer of the compensation thin film transistor T3 of the first pixel circuit PC1 can be overlapped with the shield electrode 70 electrically connected to the driving voltage line 30, and a portion of the semiconductor layer of the compensation thin film transistor T3 of the second pixel circuit PC2 can be overlapped with the shield electrode 70 electrically connected to the second initialization voltage line 20. Figure 9 It is shown that the second initialization voltage line 20 is electrically connected to the shield electrode 70 in the second pixel circuit PC2 through a contact hole located in an area in which the second initialization voltage line 20 and the shield electrode 70 are overlapped with each other. Accordingly, even when the driving voltage line 30 is not positioned to correspond to each of the pixel circuits PC and two pixel circuits PC share one driving voltage line 30, the shield electrode 70 located in each of the pixel circuits PC can receive a constant voltage from the second initialization voltage line 20 or the driving voltage line 30.

[0126] As Figure 5 and Figure 6 shown in FIGS. 1 and 2, the first initialization voltage line 10 and the second initialization voltage line 20 are located on different layers from each other. The first initialization voltage line 10 and the second initialization voltage line 20 can be electrically connected to each other through the second connection electrode 50 integral with the second initialization voltage line 20. The second connection electrode 50 will be described in more detail with reference to Figure 9 FIG. 3.

[0127] The second connection electrode 50 can include a 2-1 connection electrode 51 and a 2-2 connection electrode 52. The 2-1 connection electrode 51 can be superposed with a portion of the first initialization voltage line 10 and can electrically connect the first initialization voltage line 10 to the second initialization voltage line 20. The 2-2 connection electrode 52 can extend in a direction away from the 2-1 connection electrode 51 and can electrically connect the first initialization voltage line 10 to a semiconductor layer of the initialization thin-film transistor T4 of the first pixel circuit PC1. As shown in Figure 9 FIG. 3, the 2-1 connection electrode 51 can extend from the second initialization voltage line 20 and can be electrically connected to the first initialization voltage line 10 through a contact hole located in a region in which the 2-1 connection electrode 51 is superposed with the first initialization voltage line 10. In addition, the 2-2 connection electrode 52 can extend in a direction away from the 2-1 connection electrode 51 and can be electrically connected to an initialization source electrode S4 of the first pixel circuit PC1 through a contact hole located in a region in which the 2-2 connection electrode 52 is superposed with a semiconductor layer of the initialization thin-film transistor T4 of the first pixel circuit PC1. Accordingly, the initialization thin-film transistor T4 of the first pixel circuit PC1 can receive the initialization voltage Vint from the second initialization voltage line 20 through the second connection electrode 50.

[0128] The initialization thin-film transistor T4 of the second pixel circuit PC2 can receive the initialization voltage Vint from the first initialization voltage line 10 through a bridge electrode 55 electrically connecting the initialization thin-film transistor T4 to the first initialization voltage line 10. That is, the first pixel circuit PC1 and the second pixel circuit PC2 can receive the initialization voltage Vint from the first initialization voltage line 10 or the second initialization voltage line 20 through different paths from each other.

[0129] The second initialization voltage line 20, the driving voltage line 30, the 1-2 connection electrode 42, and the second connection electrode 50 can include the same material and have the same layered structure. Accordingly, the second initialization voltage line 20 and the driving voltage line 30 can be formed simultaneously in one process, and thus process efficiency can be improved.

[0130] For example, the second initialization voltage line 20, the driving voltage line 30, the 1-2 connecting electrode 42, and the second connecting electrode 50 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. Each of the second initialization voltage line 20, the driving voltage line 30, the 1-2 connecting electrode 42, and the second connecting electrode 50 can have a single layer structure or a multi-layer structure. When each of the second initialization voltage line 20, the driving voltage line 30, the 1-2 connecting electrode 42, and the second connecting electrode 50 has a multi-layer structure, each of the second initialization voltage line 20, the driving voltage line 30, the 1-2 connecting electrode 42, and the second connecting electrode 50 can include various materials. For example, the multi-layer structure can include a two-layer structure of a Ti layer / Al layer, a three-layer structure of a Ti layer / Al layer / Ti layer, etc.

[0131] Referring to Figure 7 , the second interlayer insulating layer 109 can be positioned on the structure of Figure 6 , and the data line DL can be positioned on the second interlayer insulating layer 109.

[0132] For reference, a contact hole shown in Figure 7 may be formed in the second interlayer insulating layer 109 to electrically connect a layer shown in Figure 7 to a layer thereunder. The layer on the second interlayer insulating layer 109 can be electrically connected to a pixel electrode of the organic light emitting diode OLED located on the planarization layer 111 of the structure covering Figure 7 . Here, the planarization layer 111 can include an organic material such as acryl, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), etc. However, the disclosure is not limited thereto, and the planarization layer 111 can include an inorganic material as needed, and can have a single layer structure or a multi-layer structure.

[0133] The data line DL can extend in the y direction, and can be electrically connected to a switch source electrode S2 of the switch thin film transistor T2. For example, the data line DL can be electrically connected to a layer between the switch source electrode S2 and the data line DL through a contact hole located in an area in which the data line DL and the switch source electrode S2 overlap. Here, the layer between the switch source electrode S2 and the data line DL can be electrically connected to the switch source electrode S2 through a contact hole located in an area in which the layer and the switch source electrode S2 overlap.

[0134] The data line DL can include the same material or the same single-layer structure or the same multi-layer structure as the second initialization voltage line 20, the driving voltage line 30, the 1-2 connecting electrode 42, and the second connecting electrode 50. For example, the data line DL can include a two-layer structure of a Ti layer / Al layer, a three-layer structure of a Ti layer / Al layer / Ti layer, or the like.

[0135] Figure 10 is a plan view of a pixel circuit PC arranged in a display area DA of a display device 1 according to some example embodiments. For reference, Figure 10 The illustration of the organic light emitting diode OLED is omitted.

[0136] According to some example embodiments, the first pixel circuit PC1 and the second pixel circuit PC2 can have a laterally symmetrical structure. That is, the first pixel circuit PC1 and the second pixel circuit PC2 can be symmetrical with respect to each other based on a virtual second axis AX2 passing between the first pixel circuit PC1 and the second pixel circuit PC2.

[0137] The aspects described above with reference to Figures 1 to 9 may equally apply to the present embodiments. In the following, the same aspects will not be described and different aspects will mainly be described. With reference to Figure 10 , the pixel circuits PC can be arranged in the x direction and the y direction to form a matrix. For example, Figure 10 shows a first pixel circuit PCI and a second pixel circuit PC2 arranged adjacent to each other in one direction (e.g., the x direction).

[0138] The first pixel circuit PC1 and the second pixel circuit PC2 according to some example embodiments can include the thin film transistors T1 to T7, the storage capacitor Cst, and the signal lines SL, SL-1, EL, and DL described above with reference to Figure 2 .

[0139] The first initialization voltage line 10 and the signal lines SL, SL-1, and EL can extend in the x direction and can be arranged to be separated from each other. Each of the first initialization voltage line 10 and the signal lines SL, SL-1, and EL can be electrically connected to the pixel circuits PC arranged in the x direction.

[0140] The second initialization voltage line 20 and the driving voltage line 30 can extend in the y direction between the first pixel circuit PC1 and the second pixel circuit PC2. The second initialization voltage line 20 can be superposed with the driving voltage line 30. Based on this structure, a space for the second initialization voltage line 20 and the driving voltage line 30 can not be needed, and thus, the spatial availability of the display area DA can be improved.

[0141] The data lines DL can extend in the y direction. The data lines DL can be positioned at both sides of the second initialization voltage line 20 or the driving voltage line 30.

[0142] Figures 11 to 14 is a plan view for describing a process of forming the pixel circuit PC according to some example embodiments.

[0143] Referring to Figure 11 The semiconductor layer of the first pixel circuit PC1 and the semiconductor layer of the second pixel circuit PC2 can be positioned in various directions on the substrate 100 in a curved shape. Here, the semiconductor layer of the first pixel circuit PC1 and the semiconductor layer of the second pixel circuit PC2 can be connected to each other and can be symmetrical to each other based on a virtual second axis AX2 therebetween.

[0144] The semiconductor layer can include the same material as the semiconductor layer according to the above-described embodiments. For example, the semiconductor layer can include a semiconductor layer including polysilicon or a semiconductor layer including an oxide.

[0145] The first gate insulating layer 103 can be positioned on the semiconductor layers of the first pixel circuit PC1 and the second pixel circuit PC2, and the scan line SL, the previous scan line SL-1, the emission control line EL, and the gate electrodes G1 to G7 of the thin film transistors T1 to T7 can be positioned on the first gate insulating layer 103. Here, the driving gate electrode G1 of the driving thin film transistor T1 can not only serve as a control electrode of the driving thin film transistor T1 but also serve as a lower electrode CE1 of the storage capacitor Cst. That is, the driving gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst can be integrated with each other.

[0146] As with the above-described embodiments, at least one of the signal lines SL, SL-1, and EL can be integrated with at least one of the gate electrodes G1 to G7. In addition, the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 can include the same material and the same layer structure as each other. For example, the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 can have a two-layer structure of a Mo layer / Al layer, a three-layer structure of a Mo layer / Al layer / Mo layer, etc.

[0147] Referring to Figure 12 The second gate insulating layer 105 can be positioned on the structure of Figure 11 The first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 of the storage capacitor Cst can be positioned on the second gate insulating layer 105. Here, the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 of the first pixel circuit PC1 and the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 of the second pixel circuit PC2 can be symmetrical to each other based on the virtual second axis AX2.

[0148] The first initialization voltage line 10 can extend in the x direction, and can be electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2.

[0149] The shield electrode 70 can have a separate shape. The shield electrode 70 can be integrated throughout the first pixel circuit PC1 and the second pixel circuit PC2. Further, a portion of the shield electrode 70 can be superposed with the compensation thin film transistor T3 of the first pixel circuit PC1 and the compensation thin film transistor T3 of the second pixel circuit PC2.

[0150] The storage capacitor Cst can include a lower electrode CE1 and an upper electrode CE2, and the lower electrode CE1 and the upper electrode CE2 can be superposed with each other with an insulating layer therebetween, thereby forming a capacitor. In this case, the second gate insulating layer 105 between the lower electrode CE1 and the upper electrode CE2 can function as a dielectric layer of the storage capacitor Cst.

[0151] The first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 located on the second gate insulating layer 105 can include the same material as the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 located on the first gate insulating layer 103, and have the same layered structure as the signal lines SL, SL-1, and EL, the gate electrodes G1 to G7, and the lower electrode CE1 located on the first gate insulating layer 103. For example, the first initialization voltage line 10, the shield electrode 70, and the upper electrode CE2 can have a multi-layer structure such as a two-layer structure of a Mo layer / Al layer, a three-layer structure of a Mo layer / Al layer / Mo layer, etc.

[0152] Referring to Figure 13 , the first interlayer insulating layer 107 can be positioned on the structure of Figure 12 , and the drive voltage line 30 and the third connection electrode 60 can be positioned on the first interlayer insulating layer 107. Here, the drive voltage line 30 can be superposed with the virtual second axis AX2, and can be symmetrical with respect to the virtual second axis AX2. The third connection electrode 60 of the first pixel circuit PC1 and the third connection electrode 60 of the second pixel circuit PC2 can also be symmetrical with each other based on the virtual second axis AX2.

[0153] As a reference, the contact hole shown in Figure 13 may be formed in the first gate insulating layer 103, the second gate insulating layer 105, and / or the first interlayer insulating layer 107 to electrically connect the layer shown in Figure 13 to a layer thereunder.

[0154] The driving voltage line 30 can extend in the y direction between the first pixel circuit PCI and the second pixel circuit PC2, and can be electrically connected to the operation control thin film transistor T5 of the first pixel circuit PCI and the operation control thin film transistor T5 of the second pixel circuit PC2. That is, the operation control thin film transistor T5 of the first pixel circuit PCI and the operation control thin film transistor T5 of the second pixel circuit PC2 can share one driving voltage line 30. Accordingly, the driving voltage line 30 can be electrically connected to the first pixel circuit PCI located at one side of the driving voltage line 30 and the second pixel circuit PC2 located at the other side of the driving voltage line 30. According to some example embodiments, because the first pixel circuit PCI and the second pixel circuit PC2 are symmetrical to each other based on the virtual second axis AX2, the driving voltage line 30 can supply a voltage to each of the first pixel circuit PCI and the second pixel circuit PC2 through the same path.

[0155] For example, the driving voltage line 30 can be electrically connected to the upper electrode CE2 through a contact hole located in a region in which the driving voltage line 30 is overlaid with the upper electrode CE2 of the first pixel circuit PCI and the second pixel circuit PC2. Also, each of the upper electrodes CE2 can be electrically connected to the operation control thin film transistor T5 through a connection electrode located on the same layer as the driving voltage line 30 and having a separate shape. Accordingly, the driving voltage ELVDD can pass through the upper electrode CE2, the operation control thin film transistor T5, the driving thin film transistor T1, and the emission control thin film transistor T6 in sequence from the driving voltage line 30 to the organic light emitting diode OLED.

[0156] The driving voltage line 30 can include the same material as the driving voltage line 30 according to the above-described embodiments. For example, the driving voltage line 30 can include a two-layer structure of a Ti layer / Al layer, a three-layer structure of a Ti layer / Al layer / Ti layer, etc.

[0157] Referring to Figure 14 The second interlayer insulating layer 109 can be positioned on the structure of Figure 13 The second initialization voltage line 20 and the data line DL can be positioned on the second interlayer insulating layer 109, and here, the second initialization voltage line 20 and the data line DL can be symmetrical to each other based on the virtual second axis AX2.

[0158] The second initialization voltage line 20 can extend in the y direction between the first pixel circuit PCI and the second pixel circuit PC2, and can be overlaid with the driving voltage line 30.

[0159] The second initialization voltage line 20 can be positioned on a layer above the driving voltage line 30, and the driving voltage line 30 can be positioned on a layer above the first initialization voltage line 10. As described above, the first initialization voltage line 10 and the second initialization voltage line 20 positioned on different layers can be electrically connected to each other through the third connection electrode 60 positioned on a layer between the first initialization voltage line 10 and the second initialization voltage line 20.

[0160] Reference will be made to Figure 15 The third connection electrode 60 will be described in more detail. Figure 15 is a cross-sectional view of the display apparatus 1 of Figure 10 is a cross-sectional view of the display apparatus 1 of Figure 10

[0161] The third connection electrode 60 can be positioned on a layer between a layer on which the first initialization voltage line 10 is positioned and a layer on which the second initialization voltage line 20 is positioned. One end of the third connection electrode 60 can be electrically connected to the second initialization voltage line 20, and the other end of the third connection electrode 60 can be electrically connected to the first initialization voltage line 10. For example, the second initialization voltage line 20 can extend in a direction toward the third connection electrode 60, and can be electrically connected to the third connection electrode 60 through a contact hole positioned in a region in which the second initialization voltage line 20 and the third connection electrode 60 are overlapped. The third connection electrode 60 can extend from one end to the other end, and can be electrically connected to the first initialization voltage line 10 through a contact hole positioned in a region in which the third connection electrode 60 and the first initialization voltage line 10 are overlapped. Accordingly, the first initialization voltage line 10 and the second initialization voltage line 20 can maintain a constant voltage.

[0162] In addition, in addition to the contact hole connected to the second initialization voltage line 20 positioned on a layer above the third connection electrode 60, a contact hole connected to a semiconductor layer of the initialization thin film transistor T4 positioned on a layer below the third connection electrode 60 can be positioned at one end of the third connection electrode 60. Accordingly, the initialization thin film transistor T4 of the first pixel circuit PC1 and the initialization thin film transistor T4 of the second pixel circuit PC2 can receive an initialization voltage Vint from the first initialization voltage line 10 or the second initialization voltage line 20 through the third connection electrode 60.

[0163] Figure 16 is a schematic plan view of a structure around the assembly area CA, Figure 17A and Figure 17B is a cross-sectional view of a portion of the display apparatus 1 according to some example embodiments. Figure 16 The first initialization voltage line 10, the second initialization voltage line 20, and the driving voltage line 30 on the substrate 100 as a structure around the assembly area CA are shown. ​

[0164] Figure 16 An example in which the first pixel circuit PC1 and the second pixel circuit PC2 positioned adjacent to each other according to some example embodiments are not symmetrical to each other is shown. However, embodiments according to the present disclosure are not limited thereto. That is, the present embodiment can be equally applied to the example of the asymmetrical structure and the example of the symmetrical structure described above. In addition, the above aspects can be applied to the present embodiment, and some identical aspects will not be described again.

[0165] In the display device 1 including the component area CA included in the display area DA, Figure 1 ) when the component area CA is biased toward one side of the display area DA rather than being located in the center of the display area DA, overcharging (overload) can occur due to the initialization voltage line VL connected in parallel with respect to the pixel in the area where the distance from the component area CA to the edge of the display area DA is large, and thus a brightness difference can occur. According to some example embodiments, the above problem can be solved based on a structure including a first initialization voltage line 10 connected in parallel and a second initialization voltage line 20 electrically connected to the first initialization voltage line 10. Accordingly, regardless of the position of the component area CA in the display area DA, a high-quality image can be provided.

[0166] As Figure 16 shown in the above, the first initialization voltage line 10 can extend in a first direction (for example, an x direction) across a plurality of pixel circuits PC and can be electrically connected to the pixel circuits PC located in a row direction. In addition, the second initialization voltage line 20 and the driving voltage line 30 can extend in a second direction (for example, a y direction) across a plurality of pixel circuits PC and can be alternately electrically connected to the pixel circuits PC located in a column direction. Here, the first initialization voltage line 10, the second initialization voltage line 20, and / or the driving voltage line 30 can be disconnected around the component area CA.

[0167] According to some example embodiments, the substrate 100 of the display device 1 can include a hole 100H located in the component area CA. For example, as Figure 17A shown in the above, the display device 1 can include a substrate 100, a display layer DPL located on the substrate 100 and including the pixel circuit PC and the light emitting diode described above, and a thin film encapsulation layer TFE on the display layer DPL, in which the substrate 100, the display layer DPL, and the thin film encapsulation layer TFE can include holes 100H, DPL-H, and TFE-H, respectively, corresponding to the component area CA. According to some example embodiments, as Figure 17B shown in the above, the substrate 100, the display layer DPL, and the thin film encapsulation layer TFE can not include holes corresponding to the component area CA as Figure 17A shown in the above.

[0168] The middle area MA can be located between the component area CA and the display area DA. The middle area MA can be a non-emitting non-display area, and lines (wirings) and internal circuits bypassing the component area CA can be located in the middle area MA.

[0169] The above description is mainly given with respect to a display apparatus. However, the disclosure is not limited thereto. That is, a method of manufacturing a display apparatus can also be included in the scope of the disclosure.

[0170] According to one or more of the above-described embodiments, a display apparatus capable of realizing a high-quality image and improving a luminance difference can be provided. However, the scope of the disclosure is not limited thereto.

[0171] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be apparent to those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims and their equivalents.

Claims

1. A display device comprising: a substrate; a first pixel circuit on the substrate and including a first drive thin-film transistor and a first storage capacitor electrically connected to the first drive thin-film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second drive thin-film transistor and a second storage capacitor electrically connected to the second drive thin-film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line, extending in a second direction crossing the first direction, and crossing the first initialization voltage line in a display region and arranging the first initialization voltage line and the second initialization voltage line in a grid structure; and a drive voltage line extending in the second direction between the first pixel circuit and the second pixel circuit, wherein a channel region of the first drive thin-film transistor or a channel region of the second drive thin-film transistor is between the second initialization voltage line and the drive voltage line.

2. The display device of claim 1, wherein, the first pixel circuit further includes a first operation control thin-film transistor electrically connected to the drive voltage line, the second pixel circuit further includes a second operation control thin-film transistor electrically connected to the drive voltage line, and the first operation control thin-film transistor and the second operation control thin-film transistor are asymmetric with respect to a virtual axis passing between the first pixel circuit and the second pixel circuit.

3. The display device of claim 2, wherein, a semiconductor layer of the first operation control thin-film transistor is electrically connected to the drive voltage line through a first connection electrode.

4. The display device of claim 3, wherein, the first connection electrode includes: a 1-1 connection electrode corresponding to a portion of any one of electrodes of the first storage capacitor and contacting the drive voltage line; and a 1-2 connection electrode contacting the 1-1 connection electrode and the semiconductor layer of the first operation control thin-film transistor.

5. The display device of claim 1, wherein, the first pixel circuit further includes a first compensation thin-film transistor electrically connected to the first drive thin-film transistor, and a portion of a semiconductor layer of the first compensation thin-film transistor is superposed with a shield electrode electrically connected to the drive voltage line.

6. The display device of claim 5, wherein, the second pixel circuit further includes a second compensation thin-film transistor electrically connected to the second drive thin-film transistor, and a portion of a semiconductor layer of the second compensation thin-film transistor is superposed with a shield electrode electrically connected to the second initialization voltage line.

7. The display device of claim 1, wherein, the second initialization voltage line is on the same layer as the drive voltage line.

8. The display device of claim 1, wherein, the second initialization voltage line is on a layer above the first initialization voltage line.

9. The display device of claim 8, wherein, the second initialization voltage line is electrically connected to the first initialization voltage line through a second connection electrode integral with the second initialization voltage line.

10. The display device of claim 9, wherein, the first pixel circuit further includes a first initialization thin-film transistor electrically connected to the first initialization voltage line, and the second connection electrode includes: a second-1 connection electrode overlapping with a part of the first initialization voltage line and electrically connecting the first initialization voltage line and the second initialization voltage line; and a second-2 connection electrode extending from the second-1 connection electrode and electrically connecting the first initialization voltage line and a semiconductor layer of the first initialization thin film transistor.

11. A display device comprising: a substrate; a first pixel circuit on the substrate and including a first drive thin film transistor and a first storage capacitor electrically connected to the first drive thin film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second drive thin film transistor and a second storage capacitor electrically connected to the second drive thin film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction; and a drive voltage line extending in the second direction between the first pixel circuit and the second pixel circuit and shared by the first pixel circuit and the second pixel circuit, wherein the second initialization voltage line overlaps with the drive voltage line.

12. The display device of claim 11, wherein, The first pixel circuit and the second pixel circuit are symmetrical with respect to a virtual axis passing between the first pixel circuit and the second pixel circuit.

13. The display device of claim 12, wherein, The first pixel circuit further includes a first compensation thin film transistor electrically connected to the first drive thin film transistor, and The second pixel circuit further includes a second compensation thin film transistor electrically connected to the second drive thin film transistor, and a part of a semiconductor layer of the first compensation thin film transistor and a part of a semiconductor layer of the second compensation thin film transistor overlap with a shield electrode electrically connected to the drive voltage line.

14. The display device of claim 12, wherein, The drive voltage line is on a layer above the first initialization voltage line, and The second initialization voltage line is on a layer above the drive voltage line.

15. The display device of claim 14, wherein, The first initialization voltage line and the second initialization voltage line are electrically connected to each other by a third connection electrode on a layer between the first initialization voltage line and the second initialization voltage line.

16. A display device comprising: a substrate including a hole; a first pixel circuit and a second pixel circuit adjacent to each other around the hole; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line, extending in a second direction crossing the first direction, and crossing the first initialization voltage line in a display area and arranging the first initialization voltage line and the second initialization voltage line in a grid structure; and a drive voltage line extending in the second direction between the first pixel circuit and the second pixel circuit, wherein at least one of the first initialization voltage line, the second initialization voltage line, and the drive voltage line is broken around the hole.

17. The display device of claim 16, wherein, The first pixel circuit includes a first operation control thin film transistor electrically connected to the drive voltage line, The second pixel circuit includes a second operation control thin film transistor electrically connected to the drive voltage line, and The first operation control thin film transistor and the second operation control thin film transistor are asymmetric with respect to the drive voltage line.

18. The display device of claim 17, wherein, The semiconductor layer of the first operation control thin film transistor is electrically connected to the drive voltage line through a first connection electrode, and The first connection electrode includes: a 1-1 connection electrode corresponding to a portion of any one of the electrodes of the first storage capacitor in the first pixel circuit, and contacting the drive voltage line; and a 1-2 connection electrode contacting the 1-1 connection electrode and the semiconductor layer of the first operation control thin film transistor.

19. The display device of claim 16, wherein, The first pixel circuit and the second pixel circuit are symmetric with respect to the drive voltage line.

20. The display device of claim 19, wherein, The drive voltage line is on a layer above the first initialization voltage line, and the second initialization voltage line is on a layer above the drive voltage line, and The first initialization voltage line and the second initialization voltage line are electrically connected to each other by a third connection electrode on a layer between the first initialization voltage line and the second initialization voltage line.

Images