Optical receiver device, pulse width modulator circuit system and sensitivity control method

Abstract

The optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuit system. The boost converter circuit is used to convert a power supply voltage according to a pulse width modulation signal to generate an output voltage. The optical receiver circuit is used to set a gain according to the output voltage to convert an optical signal into a data signal according to the gain. The pulse width modulation controller circuit system is used to perform digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage, and compare the output voltage with a reference voltage to generate a pulse width modulation signal.

Description

Technical Field

[0001] The present invention relates to an optical receiver device, and more particularly to a pulse width modulator circuit system with digital-to-analog conversion operation in the optical receiver device and a sensitivity control method. Background Art

[0002] In the application of optical fiber network, photodiodes can be used to convert optical signals into electrical signals for subsequent data processing. In actual long-distance communication, if the sensitivity of the photodiode to light is not high enough or unstable, the signal-to-noise ratio of the received data may be low, resulting in a high bit error rate. Summary of the invention

[0003] In some embodiments, the optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuit system. The boost converter circuit is used to convert a power supply voltage according to a pulse width modulation signal to generate an output voltage. The optical receiver circuit is used to set a gain according to the output voltage to convert the optical signal into a data signal according to the gain. The pulse width modulation controller circuit system is used to perform digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage, and compare the output voltage with a reference voltage to generate a pulse width modulation signal.

[0004] In some embodiments, the pulse width modulation controller circuit system includes a feedback circuit, a digital analog converter circuit system and a modulator circuit system. The feedback circuit is used to generate a feedback voltage according to an output voltage, wherein the output voltage is generated according to a pulse width modulation signal via a boost converter circuit. The digital analog converter circuit system is used to perform digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage. The modulator circuit system is used to generate a pulse width modulation signal according to the feedback voltage.

[0005] In some embodiments, the sensitivity control method includes the following operations: converting a power supply voltage according to a pulse width modulation signal to generate an output voltage; performing digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage; comparing the output voltage with a reference voltage to generate a pulse width modulation signal; and setting a gain of an optical receiver circuit according to the output voltage to control the sensitivity of the optical receiver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The technical solution, actual operation and technical effects of the present invention are now described in detail as follows as a preferred embodiment with reference to the accompanying drawings.

[0007] Figure 1 A schematic diagram of an optical receiver device according to some embodiments of the present invention is drawn;

[0008] Figure 2AAccording to some embodiments of the present invention, Figure 1 A schematic diagram of a digital-to-analog converter circuit;

[0009] Figure 2B According to some embodiments of the present invention, Figure 2A Schematic diagram of the current source array circuit;

[0010] Figure 2C According to some embodiments of the present invention, Figure 2B A schematic diagram of the waveform of the current in; and

[0011] Figure 3 A flowchart of a sensitivity control method according to some embodiments of the present invention is drawn.

[0012] Description of reference numerals:

[0013] 100: Optical receiver device

[0014] 120:Boost Converter Circuit

[0015] 140: Optical receiver circuit

[0016] 142: Transimpedance Amplifier Circuit

[0017] 144: Post-amplifier circuit

[0018] 160: Pulse Width Modulation Controller Circuit System

[0019] 162: Feedback Circuit

[0020] 164: Digital to Analog Converter Circuit

[0021] 165: Latch circuit

[0022] 166: Error amplifier circuit

[0023] 168: Comparator circuit

[0024] C1: Capacitor

[0025] D1,D2: diodes

[0026] FSW: Control code

[0027] I DAC :Current

[0028] L1: Inductor

[0029] N1, N2: nodes

[0030] RF1,RF2:Resistance

[0031] S1,S 2P ,S 2N:Signal

[0032] S D :Data signal

[0033] S L :Light signal

[0034] S PWM : Pulse Width Modulation Signal

[0035] S R :Reset signal

[0036] S S :Set signal

[0037] TN: Transistor

[0038] V DD :Power supply voltage

[0039] V E :Error signal

[0040] V F :Feedback voltage

[0041] V OUT :Output voltage

[0042] V REF :Reference voltage

[0043] V SAW :Sawtooth signal

[0044] 220,222,224: Encoder circuit

[0045] 240: Current Source Array Circuit

[0046] B1~B9,T11~T17,T21~T81:bit

[0047] 2421~242 17 :Current Source Circuit

[0048] S W1 ~S W17 :switch

[0049] 0I~8I,64I,507I~511I: Current

[0050] 300: Sensitivity control method

[0051] S310, S320, S330, S340: Operation DETAILED DESCRIPTION

[0052] All words used in this application have their usual meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope of protection of the present invention. Similarly, the present invention is not limited to the various embodiments shown in the specification.

[0053] As used in this application, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used in this application, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device composed of at least one transistor and / or at least one active and passive component connected in a certain manner to process signals.

[0054] As used in this application, the term "and / or" includes any combination of one or more of the listed associated items. In this application, the words first, second, third, etc. are used to describe and identify each component, and there is no particular order. Therefore, the first component in this application can also be referred to as the second component without departing from the original intention of the present invention. For ease of understanding, similar components in the drawings will be designated with the same reference numerals.

[0055] Figure 1 A schematic diagram of an optical receiver device 100 is drawn according to some embodiments of the present invention. In some embodiments, the optical receiver device 100 can be used in (but not limited to) optical fiber network applications.

[0056] The optical receiver device 100 includes a boost converter circuit 120, an optical receiver circuit 140, and a pulse width modulation (PWM) controller circuit system 160 (hereinafter referred to as the PWM controller circuit system 160). The boost converter circuit 120 is used to generate a pulse width modulation signal S PWM (hereinafter referred to as PWM signal S PWM )Convert the power supply voltage V DD , to generate an output voltage V from node N1 OUT For example, the boost converter circuit 120 includes an inductor L1, a transistor TN, a diode D1, and a capacitor C1. A first terminal of the inductor L1 receives a power supply voltage V DD , and the second end of the inductor L1 is coupled to the first end (e.g., the drain) of the transistor TN and the anode of the diode D1. The second end (e.g., the source) of the transistor TN is coupled to the ground, and the control end (e.g., the gate) of the transistor TN is used to receive the PWM signal S PWM The transistor TN can be switched according to the PWM signal S PWMThe cathode of the diode D1 is coupled to the node N1 and the first end of the capacitor C1 to generate an output voltage V OUT , and the second end of the capacitor C1 is coupled to the ground. In this example, the diode D1 may be (but is not limited to) a Schottky diode. When the transistor TN is switched on according to the PWM signal S PWM When conducting, the inductor L1 is based on the power supply voltage V DD The longer the transistor TN is turned on, the higher the energy stored in the inductor L1. PWM When turned off, the inductor L1 transfers the previously stored energy to the capacitor C1 through the diode D1 to generate the output voltage V OUT .

[0057] The optical receiver circuit 140 is a receiver optical sub-assembly (ROSA), which can output a voltage V OUT Set a gain and convert the optical signal S according to the gain L is the data signal S D For example, the optical receiver circuit 140 includes a diode D2, a transimpedance amplifier circuit 142, and a post-amplifier circuit 144. The cathode of the diode D2 is coupled to the node N1 to receive the output voltage V OUT , and the anode of the diode D2 is used to generate the signal S1. In this embodiment, the diode D2 may be (but is not limited to) an avalanche photodiode, which generates a photodiode according to the output voltage V OUT is reverse biased. If the output voltage V OUT The higher the reverse bias voltage is, the greater the gain of the diode D2 is. L Generates a signal S1 with a higher power. On the contrary, if the output voltage V OUT The lower the reverse bias voltage is, the lower the gain of the diode D2 is. L In other words, the diode D2 can generate a signal S1 with less power based on the output voltage V OUT Set the light signal S L The transimpedance amplifier circuit 142 can convert the signal S1 into a signal S 2P With signal S 2N , and the post-amplifier circuit 144 can be based on the signal S 2P With signal S 2N Generate data signal S D .

[0058] The PWM controller circuit system 160 is used to perform digital-to-analog conversion according to a frequency switching control code FSW (hereinafter referred to as control code FSW) to gradually adjust the frequency corresponding to the output voltage V OUT The current I DAC , and compare the output voltage V OUT With reference voltage V REF To generate a PWM signal S PWM In some embodiments, the control code FSW can be used to set the output voltage V OUT For example, as described later, the current I DAC- can be adjusted in response to the control code FSW to adjust the output voltage V OUT .

[0059] Specifically, the PWM controller circuit system 160 may include a feedback circuit 162, a digital to analog converter (DAC) circuit 164 (hereinafter referred to as DAC circuit 164), an error amplifier circuit 166, a comparator circuit 168, and a latch circuit 165. The feedback circuit 162 is coupled to the node N1 and is used to generate a voltage signal according to the output voltage V OUT Generate feedback voltage V F For example, the feedback circuit 162 includes a resistor RF1 and a resistor RF2. The resistor RF1 is coupled between the node N1 and the node N2, and the resistor RF2 is coupled between the node N2 and the ground. The resistor RF1 and the resistor RF2 have a positive effect on the output voltage V OUT Divide the voltage to generate the feedback voltage V F In some embodiments, the resistor RF1 may be an off-chip resistor, and the resistor RF2 may be an on-chip resistor, but the present invention is not limited thereto. The output terminal of the DAC circuit 164 is coupled to the node N2 to generate (eg, to draw) the current I DAC In some embodiments, the current I DAC Flows through at least a portion of the feedback circuit 162 (eg, the resistor RF1). In some embodiments, the DAC circuit 164 performs digital-to-analog conversion according to the control code FSW to adjust the current I DAC , to adjust the output voltage V OUT (As shown in equation (1) described later). The detailed operation of the DAC circuit 164 will be referred to later. FIG. 2A to FIG. 2C illustrate.

[0060] In some embodiments, the error amplifier circuit 166, the comparator circuit 168, and the latch circuit 165 operate as a modulator circuit system for modulating the feedback voltage V F Generate PWM signal S PWMFor example, the error amplifier circuit 166 is based on the feedback voltage V F With reference voltage V REF Generate error signal V E The comparator circuit 168 compares the error signal V E With sawtooth wave signal V SAW To generate a reset signal S R The latch circuit 165 may be (but is not limited to) an SR (set-reset) latch, which may be reset according to a reset signal S R and set signal S S Generate PWM signal S PWM Through the above setting method, the output voltage V OUT It can be expressed as the following formula (1):

[0061]

[0062] From the above formula (1), we can know that if the current I DAC The higher the output voltage V OUT The higher the current I DAC The lower the output voltage V OUT In other words, by adjusting the current I DAC , the boost converter circuit 120 can adjust the output voltage V accordingly OUT .

[0063] In some related technologies, if the output voltage needs to be adjusted (for example, increased or decreased) to another target level in a short period of time, due to the influence of the capacitance of the internal node of the PWM controller and the response time of the negative feedback mechanism, the output voltage may experience a voltage overshoot or voltage undershoot phenomenon, causing the gain of the photodiode to be unstable within a certain period of time.

[0064] Compared with the above-mentioned related art, in some embodiments of the present invention, through the digital analog operation of the DAC circuit 164, the current I DAC-- In this way, the boost converter circuit 120 can gradually and linearly increase or decrease the output voltage V OUT , to avoid problems such as voltage overshoot or voltage undershoot.

[0065] Figure 2A According to some embodiments of the present invention, Figure 1Schematic diagram of a DAC circuit 164. The DAC circuit 164 includes a plurality of encoder circuits 220, 222 and 224 and a current source array circuit 240. The plurality of encoder circuits 220, 222 and 224 generate a plurality of sets of digital codes according to the control code FSW. In detail, the encoder circuit 220 generates a plurality of bits B1 to B9 according to the control code FSW, wherein the first part of the plurality of bits B1 to B9 (e.g., bits B1 to B3) is a first set of digital codes. The encoder circuit 222 generates a plurality of bits T11 to T17 (hereinafter referred to as a second set of digital codes) according to the second part of the plurality of bits B1 to B9 (e.g., bits B4 to B6). The encoder circuit 224 generates a plurality of bits T21 to T81 (hereinafter referred to as a third set of digital codes) according to the third part of the plurality of bits B1 to B9 (e.g., bits B7 to B9). In some embodiments, each of the control code FSW, the second set of digital codes, and the third set of digital codes is a thermometer code, and the plurality of bits B1 - B9 are binary codes.

[0066] like Figure 2A As shown, the current source array circuit 240 is used to selectively conduct according to the above-mentioned multiple sets of digital codes to generate a current I DAC To facilitate the description of the current source array circuit 240, refer to Figure 2B , Figure 2B According to some embodiments of the present invention, Figure 2A Schematic diagram of a current source array circuit 240. The current source array circuit 240 includes a plurality of switches S W1 ~S W17 With multiple current source circuits 2421-242 17 . Multiple switches S W1 ~S W3 is the first set of switches, multiple switches S W4 ~S W10 is the second set of switches, and multiple switches S W11 ~S W17 The plurality of current source circuits 2421 to 2423 are the first group of current source circuits, and the plurality of current source circuits 2424 to 2425 are the third group of switches. 10 is a second set of current source circuits, and the plurality of current source circuits 242 11 ~242 17 This is the third set of current source circuits.

[0067] The first switch S W1 ~S W3 , the second set of switches S W4 ~S W10 And the third group S W11 ~S W17The switches S are controlled by the first set of digital codes, the second set of digital codes and the third set of digital codes. W1 ~S W3 The multiple switches S are selectively turned on according to the multiple bits B1 to B3. W4 ~S W10 The switches S are selectively turned on according to the bits T11 to T17. W11 ~S W17 The plurality of bits T21 to T81 are selectively turned on respectively.

[0068] The first group of current source circuits 2421-2423 and the second group of current source circuits 2424-242 10 and a plurality of current source circuits 242 11 ~242 17 are respectively coupled to the first set of switches S W1 ~S W3 , the second set of switches S W4 ~S W10 And the third switch S W11 ~S W17 The currents of the multiple current source circuits 2421 to 2423 are I, 2I, and 4I respectively. 10 The current of each of them is 8I. Multiple current source circuits 242 11 ~242 17 In other words, in the third current source circuit 242 11 ~242 17 The current of one current source circuit (i.e., 64I) is higher than that of the second group of current source circuits 2424-242 10 The total current (ie, 56I), and the second group of current source circuits 2424-242 10 The current of one of the current source circuits 2421 to 2423 (ie, 8I) is higher than the total current of the first group of current source circuits 2421 to 2423 (ie, 7I).

[0069] Explained in another way, the first set of digital codes (i.e., multiple bits B1-B3) are generated based on bits with lower weights in the control code FSW, the second set of digital codes (i.e., multiple bits T11-T17) are generated based on bits with the second highest weights in the control code FSW, and the third set of digital codes (i.e., multiple bits T21-T81) are generated based on bits with the highest weights in the control code FSW. W1 ~S W3 The total current of the first set of current source circuits 2421-2423 (which are controlled by the first set of digital codes) is relatively low. W4 ~S W10The second group of current source circuits 2424-242 (which are controlled by the second group of digital codes) 10 The total current is the second highest. Coupled to the third set of switches S W11 ~S W17 The third current source circuit 242 (which is controlled by the third digital code) 11 ~242 17 The total current is the highest.

[0070] By the above setting method, when the first group of switches S W1 ~S W3 , the second set of switches S W4 ~S W10 And the third switch S W11 ~S W17 When at least one switch in the circuit is turned on (ie, the switch is closed) according to the first set of digital codes, the second set of digital codes, and the third set of digital codes, at least one current source circuit coupled to the at least one switch can generate a current I from the node N2. DAC For example, the current I DAC The relationship with multiple bits B0 to B9 can be expressed as the following table:

[0071]

[0072]

[0073] As can be seen from the table above, when multiple bits B1 to B9 are all logic 0, all switches S W1 ~S W17 Under this condition, all current source circuits 2421 to 242 17 are not connected to node N2, so the current I DAC If bit B1 is logic 1 and the remaining bits B2 to B9 are logic 0, switch S W1 The remaining switch S is turned on W2 ~S W17 Under this condition, the current source circuit 2421 is connected to the node N2 and the remaining current source circuits 2422 to 242 17 are not connected to node N2, so the current I DAC =1I (current source circuit 2421 generates a current of 1I). If bit B4 is a logic value of 1 and the remaining bits B1-B3 and B5-B9 are all logic values ​​of 0, switch S W4 The remaining switch S is turned on W1 ~S W3 With S W5 ~S W17Under this condition, the current source circuit 2424 is connected to the node N2 and the remaining current source circuits 2421-2423 and 2425-242 17 are not connected to node N2, so the current I DAC =8I (the current source circuit 2424 generates a current of 8I). If the bits B1 to B6 are logic 1 and the remaining bits B7 to B9 are logic 0, the switches S W1 ~S W10 The remaining switch S is turned on W11 ~S W17 Under this condition, the multiple current source circuits 2421-242 10 The current source circuit 242 connected to the node N2 and the remaining 11 ~242 17 is not connected to node N2, so the current I DAC is 63I (current source circuits 2421 to 2423 generate a current of 7I, current source circuits 2424 to 242 10 Produces a current of 56I).

[0074] If bit B7 is logic 1 and the remaining bits B1-B6 and B8-B9 are all logic 0, switch S W11 The remaining switch S is turned on W1 ~S W10 With S W12 ~S W17 Under this condition, the current source circuit 242 11 Connected to the node N2 and the remaining current source circuits 2421-242 10 With 242 12 ~242 17 is not connected to node N2, so the current I DAC =64I (Please follow the above analogy and will not be repeated in the following text). If bit B8 is logic 1 and the remaining bits B1 to B7 and B9 are all logic 0, multiple switches S W11 ~S W12 The remaining switch S is turned on W1 ~S W10 With S W13 ~S W17 Under this condition, the multiple current source circuits 242 11 ~242 12 Connected to the node N2 and the remaining current source circuits 2421-242 10 With 242 13 ~242 17 is not connected to node N2, so the current I DACis 128I. Similarly, when all bits B1 to B9 are logic 1, all switches S W1 ~S W17 Under this condition, all current source circuits 2421 to 242 17 connected to node N2, so the current I DAC It is 511I.

[0075] Figure 2B The configuration of the current source array circuit 240 in the embodiment is for example only, and the present invention is not limited thereto. According to actual design requirements, any current source circuit in the current source array circuit 240 can be implemented by a plurality of unit current source circuits connected in parallel. For example, in some embodiments, the plurality of current source circuits 242 11 ~242 17 Each of them can be formed by 8 current source circuits with a current of 8I (generating a total current of 64I) connected in parallel.

[0076] Figure 2C According to some embodiments of the present invention, Figure 2B The current I DAC Waveform diagram of . Figure 2C As shown, through the above configuration, the current source array circuit 240 can turn on a corresponding number of current source circuits in response to the control code FSW to gradually adjust the current I DAC (For example, from 0I to 511I, a total of 512 steps). In this way, according to the above formula (1), the boost converter circuit 120 can gradually and linearly increase the output voltage V OUT , to avoid voltage overshoot or voltage undershoot, thereby keeping the sensitivity of the diode D2 stable, improving the defects of the aforementioned related technology.

[0077] Figure 3 A flow chart of a sensitivity control method 300 is drawn according to some embodiments of the present invention. In some embodiments, the sensitivity control method 300 may be (but not limited to) Figure 1 The boost converter circuit 120 and the PWM controller circuit system 160 are implemented.

[0078] In operation S310, a power supply voltage is converted according to a pulse width modulation signal to generate an output voltage. In operation S320, a digital-to-analog conversion is performed according to a control code to gradually adjust a current associated with the output voltage. In operation S330, the output voltage is compared with a reference voltage to generate a pulse width modulation signal. In operation S340, a gain of an optical receiver circuit is set according to the output voltage to control the sensitivity of the optical receiver circuit.

[0079] The description of the multiple operations of the sensitivity control method 300 can refer to the aforementioned multiple embodiments, so it will not be repeated here. The above multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present invention, the various operations under the sensitivity control method 300 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the sensitivity control method 300 can be performed simultaneously or partially simultaneously.

[0080] In summary, through the optical receiver device, PWM controller circuit system and sensitivity control method in some embodiments of the present invention, the boost converter can gradually and linearly increase the output voltage for controlling the optical receiver circuit based on the operation of digital-to-analog conversion. In this way, voltage overshoot and voltage undershoot can be avoided to stabilize the sensitivity of the optical receiver circuit.

[0081] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All such changes fall within the scope of protection sought by the present invention.

Claims

1. An optical receiver device, comprising: a boost converter circuit for converting a power supply voltage according to a pulse width modulation signal to generate an output voltage; an optical receiver circuit, configured to set a gain according to the output voltage, so as to convert an optical signal into a data signal according to the gain; as well as A pulse width modulation controller circuit system, for performing a digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage, and comparing the output voltage with a reference voltage to generate the pulse width modulation signal, wherein the higher the current, the higher the output voltage, wherein the pulse width modulation controller circuit system comprises: a feedback circuit, used for generating a feedback voltage according to the output voltage; a digital-to-analog converter circuit, configured to perform the digital-to-analog conversion according to the control code to generate the current; an error amplifier circuit, used for generating an error signal according to the feedback voltage and a reference voltage; a comparator circuit for comparing the error signal with a sawtooth wave signal to generate a reset signal; and a latch circuit, for generating the pulse width modulation signal according to a setting signal and the reset signal, Wherein, the digital-to-analog converter circuit comprises: a plurality of encoder circuits, for generating a plurality of sets of digital codes according to the control code; and a current source array circuit, configured to selectively conduct according to the plurality of sets of digital codes to generate the current, Wherein, the current source array circuit comprises: A plurality of sets of switches, each of which is controlled by the plurality of sets of digital codes; and A plurality of current source circuits are respectively coupled to the plurality of switches. When at least one switch in the plurality of sets of switches is turned on according to the plurality of sets of digital codes, at least one current source circuit in the plurality of sets of current source circuits coupled to the at least one switch generates the current.

2. The optical receiver device according to claim 1, characterized in that The multiple groups of current source circuits include: a first set of current source circuits coupled to a first set of switches among the plurality of sets of switches, wherein the first set of switches is controlled by a first set of digital codes among the plurality of sets of digital codes; a second set of current source circuits coupled to a second set of switches among the plurality of sets of switches, wherein the second set of switches is controlled by a second set of digital codes among the plurality of sets of digital codes; and a third current source circuit coupled to a third set of switches among the plurality of switches, wherein the third set of switches is controlled by a third set of digital codes among the plurality of digital codes, A current of a current source circuit in the third group of current source circuits is higher than a total current of the second group of current source circuits, and a current of a current source circuit in the second group of current source circuits is higher than a total current of the first group of current source circuits.

3. The optical receiver device according to claim 1, characterized in that The plurality of encoder circuits include: a first encoder circuit for generating a plurality of bits according to the control code, wherein a first portion of the plurality of bits is a first group of digital codes among the plurality of groups of digital codes; a second encoder circuit for generating a second set of digital codes from a second portion of the plurality of bits; and A third encoder circuit is used to generate a third group of digital codes among the multiple groups of digital codes according to a third part of the multiple bits.

4. A pulse width modulation controller circuit system, comprising: a feedback circuit for generating a feedback voltage according to an output voltage, wherein the output voltage is generated by a boost converter circuit according to a pulse width modulation signal; a digital-to-analog converter circuit for performing a digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage, wherein the higher the current, the higher the output voltage; as well as a modulator circuit system for generating the pulse width modulation signal according to the feedback voltage, wherein the digital-to-analog converter circuit comprises: a plurality of encoder circuits, for generating a plurality of sets of digital codes according to the control code; and a current source array circuit, configured to selectively conduct according to the plurality of sets of digital codes to generate the current, Wherein, the current source array circuit comprises: A plurality of sets of switches, each of which is controlled by the plurality of sets of digital codes; and A plurality of current source circuits are respectively coupled to the plurality of switches, wherein when at least one switch in the plurality of switches is turned on according to the plurality of digital codes, the plurality of current source circuits are coupled to At least one current source circuit to the at least one switch generates the current.

5. A sensitivity control method, applied to the pulse width modulation controller circuit system according to claim 4, comprising: Converting a power supply voltage according to a pulse width modulation signal to generate an output voltage; Performing a digital-to-analog conversion according to a control code to gradually adjust a current associated with the output voltage, wherein when the current is higher, the output voltage is higher; comparing the output voltage with a reference voltage to generate the pulse width modulation signal; as well as A gain of an optical receiver circuit is set according to the output voltage to control a sensitivity of the optical receiver circuit.

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