Semiconductor device for a battery protection switch

Abstract

The present disclosure provides a semiconductor device for a battery protection switch, including: a first cell region in which a first MOS transistor is formed, the first MOS transistor receiving a first control signal to turn on or off the first MOS transistor; a second cell region in which a second MOS transistor is formed, the second MOS transistor receiving a second control signal to turn on or off the second MOS transistor, the first cell region and the second cell region being disposed adjacent to each other; and a third cell region disposed adjacent to the second cell region, a switch being formed in the third cell region, the switch receiving a third control signal to perform the following control: when the first MOS transistor performs a turn-off operation, the switch turns on to cause the second MOS transistor to turn off before the first MOS transistor turns off or to turn off simultaneously with the first MOS transistor turning off.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and particularly relates to a semiconductor device for a battery protection switch. Background Art

[0002] In a battery system, overcharging and over-discharging of a battery not only reduce the service life of the battery, but may also cause safety accidents such as explosion and fire in severe cases. The battery is, for example, a lithium battery pack or the like.

[0003] In the existing battery system, the device for controlling battery charging and discharging often cannot completely cut off the charging current or the discharging circuit in the case of overcharging or over-discharging of the battery, presenting a safety hazard. Summary of the Invention

[0004] To solve one of the above technical problems, the present disclosure provides a semiconductor device for a battery protection switch.

[0005] The semiconductor device for a battery protection switch of the present disclosure is realized by the following technical solutions.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device for a battery protection switch, including: a first cell region in which a first MOS transistor is formed, the first MOS transistor receiving a first control signal to turn on or off the first MOS transistor; a second cell region in which a second MOS transistor is formed, the second MOS transistor receiving a second control signal to turn on or off the second MOS transistor, the first cell region and the second cell region being disposed adjacent to each other; and a third cell region disposed adjacent to the second cell region, the third cell region forming a switch that receives a third control signal to perform the following control: when the first MOS transistor performs a turn-off operation, the switch turns on to cause the second MOS transistor to turn off before the first MOS transistor turns off or to turn off simultaneously with the first MOS transistor turning off.

[0007] For the semiconductor device according to at least one embodiment of the present disclosure, the first cell region includes a first gate region, a first source region, and a first drain region, and a first parasitic diode is formed in the first cell region between the first source region and the first drain region.

[0008] For the semiconductor device according to at least one embodiment of the present disclosure, the second cell region includes a second gate region, a second source region, and a first drain region, and a second parasitic diode is formed in the second cell region between the second source region and the first drain region.

[0009] A semiconductor device according to at least one embodiment of the present disclosure, wherein the first parasitic diode and the second parasitic diode form an inverse series structure, and the first cell region and the second cell region share the first drain region.

[0010] A semiconductor device according to at least one embodiment of the present disclosure further includes a fourth cell region disposed adjacent to the first cell region. A protection diode is formed in the fourth cell region. The fourth cell region includes a first source region and a second drain region. The fourth cell region and the first cell region share the first source region. The first drain region of the first cell region and the second drain region of the fourth cell region can be connected such that the protection diode is in parallel with the first parasitic diode, so that when it is necessary to turn off the second MOS transistor, the second MOS transistor is quickly turned off by the voltage formed on the protection diode.

[0011] A semiconductor device according to at least one embodiment of the present disclosure, wherein the third cell region includes a third gate region, a second source region, and a third drain region. The third cell region and the second cell region share the second source region. The third drain region of the third cell region and the second gate region of the second cell region can be connected.

[0012] The protection diode of the semiconductor device according to at least one embodiment of the present disclosure is a high-voltage diode.

[0013] A semiconductor device according to at least one embodiment of the present disclosure further includes a substrate electrode region. The first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate.

[0014] A semiconductor device according to at least one embodiment of the present disclosure, wherein the first MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the first cell region includes a first gate region, a first source region, and a first drain region, and the first cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a first P-type well region is formed in the N-type drift region, at least a first P-type highly doped region and a first N-type highly doped region are formed in the first P-type well region, the first P-type well region is spaced from the P-type substrate by the N-type drift region, and a second N-type highly doped region is formed in the N-type drift region; the first source region is formed on the dielectric layer, and at least a part of the first source region passes through the dielectric layer to contact the first N-type highly doped region and the first P-type highly doped region; the first drain region is formed on the dielectric layer, and at least a part of the first drain region passes through the dielectric layer to contact the second N-type highly doped region; the first gate region is formed in the dielectric layer.

[0015] A semiconductor device according to at least one embodiment of the present disclosure, wherein the second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the second cell region includes a second gate region, a second source region, and a first drain region, and the second cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a second P-type well region is formed in the N-type drift region, at least a third P-type highly doped region and a third N-type highly doped region are formed in the second P-type well region, the second P-type well region is spaced from the P-type substrate by the N-type drift region, and a second N-type highly doped region is formed in the N-type drift region; the second source region is formed on the dielectric layer, and at least a part of the second source region passes through the dielectric layer to contact the third N-type highly doped region and the third P-type highly doped region; the first drain region is formed on the dielectric layer, and at least a part of the first drain region passes through the dielectric layer to contact the second N-type highly doped region; the second gate region is formed in the dielectric layer.

[0016] A semiconductor device according to at least one embodiment of the present disclosure, the third cell region includes a third gate region, a second source region, and a third drain region, the third cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a third P-type well region is formed in the N-type drift region, at least a fourth P-type highly doped region and a fourth N-type highly doped region are formed in the third P-type well region, the third P-type well region is spaced from the P-type substrate by the N-type drift region, and a fifth N-type highly doped region is formed in the N-type drift region; the second source region is formed on the dielectric layer, at least a part of the second source region passes through the dielectric layer and contacts the fourth N-type highly doped region and contacts the fourth P-type highly doped region; the third drain region is formed on the dielectric layer, at least a part of the third drain region passes through the dielectric layer and contacts the fifth N-type highly doped region; the third gate region is formed in the dielectric layer.

[0017] A semiconductor device according to at least one embodiment of the present disclosure, the fourth cell region includes a first source region and a second drain region; the fourth cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a fourth P-type well region is formed in the N-type drift region, at least a sixth P-type highly doped region is formed in the fourth P-type well region, the fourth P-type well region is spaced from the P-type substrate by the N-type drift region, and a sixth N-type highly doped region is formed in the N-type drift region; the first source region is formed on the dielectric layer, at least a part of the first source region passes through the dielectric layer and contacts the sixth P-type highly doped region; the second drain region is formed on the dielectric layer, at least a part of the second drain region passes through the dielectric layer and contacts the sixth N-type highly doped region.

[0018] A semiconductor device according to at least one embodiment of the present disclosure, a fifth P-type highly doped region is further formed on the substrate, the substrate electrode region is formed on the dielectric layer, and at least a part of the substrate electrode region passes through the dielectric layer and contacts the fifth P-type highly doped region.

[0019] A semiconductor device according to at least one embodiment of the present disclosure, wherein the first MOS transistor is a PMOS transistor and the substrate is an N-type substrate; the first cell region includes a first gate region, a first source region, and a first drain region, and the first cell region includes an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a first N-type well region is formed in the P-type drift region, at least a first N-type highly doped region and a first P-type highly doped region are formed in the first N-type well region, the first N-type well region is spaced from the N-type substrate by the P-type drift region, and a second P-type highly doped region is formed in the P-type drift region; the first source region is formed on the dielectric layer, and at least a part of the first source region passes through the dielectric layer to contact the first P-type highly doped region and the first N-type highly doped region; the first drain region is formed on the dielectric layer, and at least a part of the first drain region passes through the dielectric layer to contact the second P-type highly doped region; the first gate region is formed in the dielectric layer.

[0020] A semiconductor device according to at least one embodiment of the present disclosure, wherein the second MOS transistor is a PMOS transistor and the substrate is an N-type substrate; the second cell region includes a second gate region, a second source region, and a first drain region, and the second cell region includes an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a second N-type well region is formed in the P-type drift region, at least a third N-type highly doped region and a third P-type highly doped region are formed in the second N-type well region, the second N-type well region is spaced from the N-type substrate by the P-type drift region, and a second P-type highly doped region is formed in the P-type drift region; the second source region is formed on the dielectric layer, and at least a part of the second source region passes through the dielectric layer to contact the third P-type highly doped region and the third N-type highly doped region; the first drain region is formed on the dielectric layer, and at least a part of the first drain region passes through the dielectric layer to contact the second P-type highly doped region; the second gate region is formed in the dielectric layer.

[0021] A semiconductor device according to at least one embodiment of the present disclosure, the third cell region includes a third gate region, a second source region, and a third drain region, the third cell region includes an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a third N-type well region is formed in the P-type drift region, at least a fourth N-type highly doped region and a fourth P-type highly doped region are formed in the third N-type well region, the third N-type well region is spaced from the N-type substrate by the P-type drift region, and a fifth P-type highly doped region is formed in the P-type drift region; the second source region is formed on the dielectric layer, and at least a part of the second source region passes through the dielectric layer to contact the fourth P-type highly doped region and contact the fourth N-type highly doped region; the third drain region is formed on the dielectric layer, and at least a part of the third drain region passes through the dielectric layer to contact the fifth P-type highly doped region; the third gate region is formed in the dielectric layer.

[0022] A semiconductor device according to at least one embodiment of the present disclosure, the fourth cell region includes a first source region and a second drain region; the fourth cell region includes an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a fourth N-type well region is formed in the P-type drift region, at least a sixth N-type highly doped region is formed in the fourth N-type well region, the fourth N-type well region is spaced from the N-type substrate by the P-type drift region, and a sixth P-type highly doped region is formed in the P-type drift region; the first source region is formed on the dielectric layer, and at least a part of the first source region passes through the dielectric layer to contact the sixth N-type highly doped region; the second drain region is formed on the dielectric layer, and at least a part of the second drain region passes through the dielectric layer to contact the sixth P-type highly doped region.

[0023] On the substrate of a semiconductor device according to at least one embodiment of the present disclosure, a fifth N-type highly doped region is further formed, the substrate electrode region is formed on the dielectric layer, and at least a part of the substrate electrode region passes through the dielectric layer to contact the fifth N-type highly doped region.

[0024] For a semiconductor device according to at least one embodiment of the present disclosure, the region between the dielectric layer and the substrate of the first cell region and the region between the dielectric layer and the substrate of the fourth cell region are isolated by a PN junction; the region between the dielectric layer and the substrate of the second cell region and the region between the dielectric layer and the substrate of the third cell region are isolated by a PN junction; the region between the dielectric layer and the substrate of the third cell region and the doped region between the substrate electrode region and the substrate are isolated by a PN junction.

[0025] In a semiconductor device according to at least one embodiment of the present disclosure, the region between the dielectric layer of the first cell region and the substrate is isolated from the region between the dielectric layer of the fourth cell region and the substrate by an isolation dielectric; the region between the dielectric layer of the second cell region and the substrate is isolated from the region between the dielectric layer of the third cell region and the substrate by an isolation dielectric; the region between the dielectric layer of the third cell region and the substrate is isolated from the doped region between the substrate electrode region and the substrate by an isolation dielectric.

[0026] In a semiconductor device according to at least one embodiment of the present disclosure, the first cell region includes a first source region, a drain region, and a first gate region. An N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region. The first cell region further includes a dielectric layer. At least a part of the first source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region; two isolation dielectric regions are symmetrically formed in the P-type well region, and one of the first gate regions is formed in each of the isolation dielectric regions.

[0027] In a semiconductor device according to at least one embodiment of the present disclosure, the second cell region includes a second source region, a drain region, and a second gate region. An N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region. The second cell region further includes a dielectric layer. At least a part of the second source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region; two isolation dielectric regions are symmetrically formed in the P-type well region, and one of the second gate regions is formed in each of the isolation dielectric regions.

[0028] In a semiconductor device according to at least one embodiment of the present disclosure, the first cell region and the second cell region share the dielectric layer, the drain region, and the N-type highly doped region.

[0029] In a semiconductor device according to at least one embodiment of the present disclosure, at least one isolation dielectric region is formed between at least the P-type well region of the first cell region and the P-type well region of the second cell region, and a metal floating region is formed in the isolation dielectric region.

[0030] In a semiconductor device according to at least one embodiment of the present disclosure, at least one isolation dielectric region is formed between at least the P-type well region of the first cell region and the P-type well region of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

[0031] A semiconductor device according to at least one embodiment of the present disclosure, wherein both the first gate region and the second gate region are trench gate structures.

[0032] A semiconductor device according to at least one embodiment of the present disclosure, wherein both the first gate region and the second gate region are isolated trench gate structures.

[0033] A semiconductor device according to at least one embodiment of the present disclosure, wherein both the first cell region and the second cell region adopt a superjunction structure.

[0034] A semiconductor device according to at least one embodiment of the present disclosure, wherein the first cell region includes a first source region, a drain region, and a first gate region. A P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region. The first cell region further includes a dielectric layer. At least a part of the first source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts the N-type highly doped region. Two isolation dielectric regions are symmetrically formed in the N-type well region, and one of the first gate regions is formed in each of the isolation dielectric regions.

[0035] A semiconductor device according to at least one embodiment of the present disclosure, wherein the second cell region includes a second source region, a drain region, and a second gate region. A P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region. The second cell region further includes a dielectric layer. At least a part of the second source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts the N-type highly doped region. Two isolation dielectric regions are symmetrically formed in the N-type well region, and one of the second gate regions is formed in each of the isolation dielectric regions.

[0036] A semiconductor device according to at least one embodiment of the present disclosure, wherein the first cell region and the second cell region share the dielectric layer, the drain region, and the P-type highly doped region.

[0037] A semiconductor device according to at least one embodiment of the present disclosure, wherein at least one isolation dielectric region is formed between at least the N-type well region of the first cell region and the N-type well region of the second cell region, and a metal floating region is formed in the isolation dielectric region.

[0038] A semiconductor device according to at least one embodiment of the present disclosure has at least one isolation dielectric region formed at least between the N-type well regions of the first cell region and the N-type well regions of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

[0039] For a semiconductor device according to at least one embodiment of the present disclosure, both the first gate region and the second gate region are trench gate structures.

[0040] For a semiconductor device according to at least one embodiment of the present disclosure, both the first gate region and the second gate region are separated trench gate structures.

[0041] For a semiconductor device according to at least one embodiment of the present disclosure, the thickness of the drift region of the first cell region is less than the thickness of the drift region of the second cell region, so that the first MOS transistor formed in the first cell region has low breakdown voltage performance, and the second MOS transistor formed in the second cell region has high breakdown voltage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are included in this specification and form a part of this specification.

[0043] Figure 1 It is a schematic structural diagram when the circuit structure corresponding to the semiconductor device for a battery protection switch according to an embodiment of the present disclosure is used in a charge and discharge control device.

[0044] Figure 2 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

[0045] Figure 3 It is a schematic structural diagram of each cell region of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

[0046] Figure 4 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0047] Figure 5 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0048] Figure 6 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0049] Figure 7It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0050] Figure 8 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0051] Figure 9 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure. Specific Embodiments

[0052] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the sake of description, only the parts related to the present disclosure are shown in the drawings.

[0053] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and embodiments.

[0054] Unless otherwise specified, the exemplary embodiments / Examples shown will be understood to provide exemplary features of various details of some ways that can implement the technical concept of the present disclosure in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / Examples can be additionally combined, separated, interchanged, and / or rearranged.

[0055] In the drawings, cross-hatching and / or shading are generally used to make the boundaries between adjacent components clear. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the components may be exaggerated. When the exemplary embodiments can be implemented differently, the specific process sequences can be performed in a different order than described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order. Moreover, the same reference numerals represent the same components.

[0056] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. For this reason, the term "connected" can refer to physical connection, electrical connection, etc., and can have or not have intervening components.

[0057] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "lower", "above", "on", "over", "upper", and "side (e.g., as in "sidewall")" etc., so as to describe the relationship between one component and another (other) component as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the drawings is flipped, a component described as "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both the "above" and "under" orientations. In addition, the device can be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0058] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. In addition, when the terms "comprise" and / or "include" and their variants are used in this specification, it is stated that there are the stated features, integers, steps, operations, components, assemblies, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, assemblies, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as degree terms, so they are used to explain the inherent deviations of measured values, calculated values, and / or provided values that would be recognized by those of ordinary skill in the art.

[0059] Figure 1 FIG. is a schematic structural diagram of a circuit structure corresponding to a semiconductor device for a battery protection switch in an embodiment of the present disclosure when used in a charge and discharge control device. Among them, 50 is the circuit structure corresponding to the semiconductor device for the battery protection switch.

[0060] As Figure 1As shown, the charge and discharge control device may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a drive unit 40, and a charge and discharge control switch 50 (which may be implemented by a semiconductor device for a battery protection switch according to the present disclosure).

[0061] The VDD generator 10 may be connected to the highest voltage of the battery / battery pack so as to generate the voltage VDD required inside the charge and discharge control device according to the highest voltage.

[0062] The voltage acquisition unit 20 may be used to acquire the voltage of the battery / battery pack. When it is a battery pack, the voltage acquisition unit 20 may be used to acquire the voltage of each battery.

[0063] The logic control circuit 30 may generate a control signal according to the acquired voltage of the battery / battery pack. Of course, additionally, the logic control circuit 30 may generate a control signal according to the charging current and the discharging current.

[0064] The drive unit 40 provides a signal for driving the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

[0065] The charge and discharge control switch 50 then controls the charging current and the discharging current according to the received switch control signal.

[0066] Taking an NMOS transistor as an example, among them, the charge and discharge control switch 50 may include a low-voltage withstand NMOS transistor 100 serving as a discharge switch, a high-voltage withstand NMOS transistor 200 serving as a charging switch, and a switching NMOS transistor 300.

[0067] The low-voltage withstand NMOS transistor 100 and the high-voltage withstand NMOS transistor 200 may be connected in series on the high-voltage side of the battery / battery pack or may also be connected in series to the low-voltage side of the battery / battery pack, and the series connection order of the two is not limited.

[0068] In this embodiment, taking the low-voltage withstand NMOS transistor 100 and the high-voltage withstand NMOS transistor 200 being connected in series to the low-voltage side of the battery / battery pack as an example for description, and taking the source S1 of the low-voltage withstand NMOS transistor 100 being connected to the low-voltage end of the battery / battery pack as an example for description.

[0069] The gate G1 of the low-voltage withstand NMOS transistor 100 receives the discharge control signal OD from the drive unit 40, the gate G2 of the high-voltage withstand NMOS transistor 200 receives the charge control signal OC from the drive unit 40, and the drain D1 of the low-voltage withstand NMOS transistor 100 is connected to the drain D2 of the high-voltage withstand NMOS transistor 200. The low-voltage withstand NMOS transistor 100 has a first parasitic diode D1, and the high-voltage withstand NMOS transistor 200 has a second parasitic diode D2.

[0070] The positive terminal of the first high-voltage protection diode D1 is connected to the source of the low-voltage withstand NMOS transistor 100, and the negative terminal of the first high-voltage protection diode D1 is connected to the drain of the low-voltage withstand NMOS transistor 100.

[0071] The drain of the switching NMOS transistor 300 is connected to the gate of the high-voltage withstand NMOS transistor 200, and the source of the switching NMOS transistor 300 is connected to the source of the high-voltage withstand NMOS transistor 200. A first resistor R1 may be connected between the source and the drain of the switching NMOS transistor 300.

[0072] The gate of the switching NMOS transistor 300 receives the current signal OB from the driving unit 40, and the gate of the switching NMOS transistor 300 is connected to the source of the high-voltage withstand NMOS transistor 200 through a second resistor R2. The switching NMOS transistor 300 may be in a low-voltage withstand form and can be made very small in size.

[0073] The source of the low-voltage withstand NMOS transistor 100 is connected to the low-voltage terminal B- of the battery / battery pack, and the source of the high-voltage withstand NMOS transistor 200 is connected to the low-voltage terminal P- of the external load or charger. Those skilled in the art should also understand that connecting the source of the high-voltage withstand NMOS transistor 200 to the low-voltage terminal B- of the battery / battery pack and the source of the first low-voltage withstand NMOS transistor 100 to the low-voltage terminal P- of the external load or charger can also achieve the same function. Similarly, connecting it to the high-voltage side of the battery / battery pack can also achieve the same function.

[0074] The voltage withstand value of the low-voltage withstand NMOS transistor 100 can be 1.8 - 7V, that is, V GS 、V GD 、V DS can be in the range of 1.8 - 7V. The voltage withstand value of the high-voltage withstand NMOS transistor 200 is related to the voltage of the battery. It is usually 1.5 - 2 times the sum of the voltages of each battery. For example, in the case of a battery pack with 16 batteries, the voltage of each battery is usually 4.5V, and its voltage withstand value needs to be 4.5 * 16 * (1.5 - 2)V. For example, its voltage withstand value should be greater than 108V, that is, V GS 、V GD 、V DS greater than 108V. According to the previous description, the on-resistance is related to the voltage withstand value. Therefore, the on-resistance of the low-voltage withstand NMOS transistor 100 will be significantly smaller than that of the high-voltage withstand NMOS transistor 200. And the voltage withstand value of the switching NMOS transistor 300 can be in the range of 10 - 20V.

[0075] The low-voltage NMOS transistor 100 is a transistor of the low-voltage type. If so, when the low-voltage NMOS transistor 100 is turned off, if the high-voltage NMOS transistor 200 cannot be turned off in time during the turn-off process (for example, before or at the same time as the low-voltage NMOS transistor 100 is turned off), the high-voltage NMOS transistor 200 remains in the on state, and thus the voltage at the P- terminal will be applied to the drain of the low-voltage NMOS transistor 100. Since during the turn-off process of the low-voltage NMOS transistor 100 and the high-voltage NMOS transistor 200, the voltage at the P- terminal will rise to the voltage value of the P+ terminal.

[0076] Since the high-voltage NMOS transistor 200 cannot be turned off in time, the rising voltage value at the P- terminal will be applied to the drain of the low-voltage NMOS transistor 100. At the same time, since the low-voltage NMOS transistor 100 is a transistor of the low-voltage type, if a high voltage is applied to its drain, it will inevitably cause damage to the low-voltage NMOS transistor 100.

[0077] By setting a switch (in the form of a switch NMOS transistor 300), the high-voltage NMOS transistor 200 can be turned off in time during the turn-off process (for example, before or at the same time as the low-voltage NMOS transistor 100 is turned off). As a result, the rising voltage value at the P- terminal will not be applied to the drain of the low-voltage NMOS transistor 100, but to the drain of the high-voltage NMOS transistor 200 (because the high-voltage NMOS transistor 200 is a transistor of the high-voltage type, so the high voltage will not cause damage to the high-voltage NMOS transistor 200).

[0078] For the actual high-voltage NMOS transistor 200, there is a parasitic capacitance between its gate G and source S. Due to the existence of this parasitic capacitance, even when V GS is less than the threshold voltage, the high-voltage NMOS transistor 200 cannot be turned off quickly because the charge release of the capacitor requires a certain amount of time. Thus, even when the voltage of the control signal at the gate is less than the threshold voltage, the high-voltage NMOS transistor 200 cannot be turned off quickly. The parasitic capacitance of the high-voltage NMOS transistor 200 needs to be discharged through the circuit of the first resistor R1. In this case, there will inevitably be a situation of turn-off delay of the high-voltage NMOS transistor 200.

[0079] By connecting a switch in series between the gate and source of the high-voltage NMOS transistor 200, so that when the high-voltage NMOS transistor 200 needs to be turned off, it can be turned off quickly (enabling the parasitic capacitance to discharge quickly).

[0080] When the high-voltage withstand NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB. The current OB flows through the second resistor R2, and a voltage is formed across the second resistor R2. This voltage is greater than the gate-source voltage V of the switching NMOS transistor 300. GS , the switching NMOS transistor 300 conducts rapidly. In this way, a path is formed between the gate and the source of the high-voltage withstand NMOS transistor 200, enabling the parasitic capacitance between the gate and the source of the high-voltage withstand NMOS transistor 200 to discharge rapidly, thereby quickly turning off the high-voltage withstand NMOS transistor 200. In this way, the rising P-terminal voltage will not be applied to the drain of the first low-voltage withstand NMOS transistor 100, and the low-voltage withstand NMOS transistor 100 will not be damaged.

[0081] In addition, a high-voltage protection diode D3 is connected in series between the source and the drain of the low-voltage withstand NMOS transistor 100. The purpose is that when the low-voltage withstand NMOS transistor 100 is turned off and the high-voltage withstand NMOS transistor 200 is not turned off in time, the high voltage at the P-terminal will be applied to the drain of the low-voltage withstand NMOS transistor 100. The high-voltage protection diode D3 will play a protective role here. The high voltage will cause the high-voltage protection diode D3 to break down reversely, thereby avoiding damage to the low-voltage withstand NMOS transistor 100. This is because the high-voltage protection diode D3 is broken down reversely, so as to prevent the drain voltage of the low-voltage withstand NMOS transistor 100 from being too high.

[0082] The on-resistance value of the series NMOS transistors from the B-terminal to the P-terminal is:

[0083] R on = R DS,on (100) + R DS,on (200), where R on is the sum of the on-resistances of the low-voltage withstand NMOS transistor 100 and the high-voltage withstand NMOS transistor 200, R DS,on (100) is the on-resistance of the low-voltage withstand NMOS transistor 100, and R DS,on (200) is the on-resistance of the high-voltage withstand NMOS transistor 200.

[0084] Also, since the low-voltage withstand NMOS transistor 100 is a low-voltage withstand NMOSFET, the physical structure of the low-voltage withstand NMOSFET does not require a low-doped breakdown drift region. That is to say, for the low-voltage withstand NMOSFET, R DS,on (100) = R s,metal + R source + R channel + R drain + R d,metal .

[0085] Therefore, for NMOSFETs with the same physical size, R DS,on (100) is much smaller than R DS,on (200), so R on ≈R DS,on (200). Therefore, by using series-connected high- and low-voltage NMOSFETs, the on-resistance of the series-connected MOSFETs can be reduced by a factor of 1, and thus the heat loss caused by the on-resistance is reduced by a factor of 2.

[0086] Figure 2 is a schematic structural diagram of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

[0087] Figure 3 is a schematic structural diagram of each cell region of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

[0088] As shown in Figure 2 and Figure 3 , a semiconductor device for a battery protection switch includes: a first cell region (MNLV1), where a first MOS transistor is formed in the first cell region (MNLV1), and the first MOS transistor receives a first control signal to turn on or off the first MOS transistor;

[0089] a second cell region (MNHV2), where a second MOS transistor is formed in the second cell region (MNHV2), and the second MOS transistor receives a second control signal to turn on or off the second MOS transistor, and the first cell region and the second cell region are disposed adjacent to each other; and

[0090] a third cell region (MN3), which is disposed adjacent to the second cell region, and a switch is formed in the third cell region. The switch receives a third control signal to perform the following control: when the first MOS transistor performs a turn-off operation, the switch turns on so that the second MOS transistor turns off before the first MOS transistor turns off or turns off simultaneously with the first MOS transistor turning off.

[0091] According to a preferred embodiment of the present disclosure, the first cell region includes a first gate region G1, a first source region S1, and a first drain region D. A first parasitic diode D1 is formed in the first cell region, and the first parasitic diode D1 is formed between the first source region S1 and the first drain region D.

[0092] According to a preferred embodiment of the present disclosure, the second cell region includes a second gate region G2, a second source region S2, and a first drain region D. A second parasitic diode D2 is formed in the second cell region, and the second parasitic diode D2 is formed between the second source region S2 and the first drain region D.

[0093] As shown in Figure 2and Figure 3 As shown, the first parasitic diode D1 and the second parasitic diode D2 form an anti-series structure, and the first cell region (MNLV1) and the second cell region (MNHV2) share the first drain region D.

[0094] As Figure 3 shown, the semiconductor device further includes a fourth cell region (D3). The fourth cell region (D3) is disposed adjacent to the first cell region (MNLV1). A protection diode D3 is formed in the fourth cell region. The fourth cell region includes a first source region S1 and a second drain region D. The fourth cell region and the first cell region share the first source region S1. The first drain region D of the first cell region and the second drain region D of the fourth cell region can be connected, such that the protection diode D3 is in parallel with the first parasitic diode D1, so that when it is necessary to turn off the second MOS transistor, the second MOS transistor is quickly turned off by the voltage formed on the protection diode D3.

[0095] As Figure 3 shown, the third cell region (MN3) includes a third gate region G3, a second source region S2, and a third drain region G2. The third cell region and the second cell region share the second source region S2. The third drain region G2 of the third cell region and the second gate region G2 of the second cell region can be connected.

[0096] In each of the above embodiments, the protection diode D3 is a high-voltage diode.

[0097] As Figure 2 and Figure 3 shown, the semiconductor device further includes a substrate electrode region B. The first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate (Psub).

[0098] According to an embodiment of the present disclosure, the first MOS transistor of the semiconductor device is an NMOS transistor, and the substrate is a P-type substrate (Psub); the first cell region (MNLV1) includes a first gate region G1, a first source region S1, and a first drain region D. The first cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer. A first P-type well region PW is formed in the N-type drift region ND. At least a first P-type highly doped region P+ and a first N-type highly doped region N+ are formed in the first P-type well region PW. The first P-type well region PW is spaced apart from the P-type substrate by the N-type drift region ND. A second N-type highly doped region N+ is formed in the N-type drift region ND; the first source region S1 is formed on the dielectric layer, and at least a part of the first source region S1 passes through the dielectric layer to contact the first N-type highly doped region N+ and the first P-type highly doped region P+; the first drain region D is formed on the dielectric layer, and at least a part of the first drain region D passes through the dielectric layer to contact the second N-type highly doped region N+; the first gate region G1 is formed in the dielectric layer.

[0099] The second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the second cell region (MNHV2) includes a second gate region G2, a second source region S2, and a first drain region D. The second cell region includes a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer. A second P-type well region PW is formed in the N-type drift region ND. At least a third P-type highly doped region P+ and a third N-type highly doped region N+ are formed in the second P-type well region PW. The second P-type well region PW is spaced apart from the P-type substrate by the N-type drift region ND. A second N-type highly doped region N+ is formed in the N-type drift region ND; the second source region S2 is formed on the dielectric layer, and at least a part of the second source region S2 passes through the dielectric layer to contact the third N-type highly doped region N+ and the third P-type highly doped region P+; the first drain region D is formed on the dielectric layer, and at least a part of the first drain region D passes through the dielectric layer to contact the second N-type highly doped region N+; the second gate region G2 is formed in the dielectric layer.

[0100] The third cell region (MN3) includes a third gate region G3, a second source region S2, and a third drain region (G2). The third cell region includes a P-type substrate and a dielectric layer. At least an N-type drift region ND is formed between the P-type substrate and the dielectric layer. A third P-type well region PW is formed in the N-type drift region ND. At least a fourth P-type highly doped region P+ and a fourth N-type highly doped region N+ are formed in the third P-type well region PW. The third P-type well region PW and the P-type substrate are separated by the N-type drift region ND. A fifth N-type highly doped region N+ is formed in the N-type drift region ND. The second source region S2 is formed on the dielectric layer. At least a part of the second source region S2 passes through the dielectric layer to contact the fourth N-type highly doped region N+ and the fourth P-type highly doped region P+. The third drain region G2 is formed on the dielectric layer. At least a part of the third drain region G2 passes through the dielectric layer to contact the fifth N-type highly doped region N+. The third gate region G3 is formed in the dielectric layer.

[0101] The fourth cell region (D3) includes a first source region S1 and a second drain region D. The fourth cell region includes a P-type substrate and a dielectric layer. At least an N-type drift region ND is formed between the P-type substrate and the dielectric layer. A fourth P-type well region PW is formed in the N-type drift region ND. At least a sixth P-type highly doped region P+ is formed in the fourth P-type well region PW. The fourth P-type well region PW and the P-type substrate are separated by the N-type drift region ND. A sixth N-type highly doped region N+ is formed in the N-type drift region ND. The first source region S1 is formed on the dielectric layer. At least a part of the first source region S1 passes through the dielectric layer to contact the sixth P-type highly doped region P+. The second drain region D is formed on the dielectric layer. At least a part of the second drain region D passes through the dielectric layer to contact the sixth N-type highly doped region N+.

[0102] Among them, the doping concentration of the N+ region is greater than that of the ND region, and the doping concentration of the P+ region is greater than that of the PW region.

[0103] Among them, the source region can be a metal material, the dielectric layer is an oxide layer, the substrate electrode region is a metal material, the gate region can be polysilicon, the P-type highly doped region is silicon doped with P-type, the P-type well region is silicon doped with P-type, the N-type highly doped region is silicon doped with N-type, the N-type well region is silicon doped with N-type, the N-type drift region ND is silicon doped with N-type, and the drain region can be a metal material.

[0104] As Figure 2 and Figure 3 shown, in the first cell region, a first parasitic diode D1 is formed between the PW region and the ND region. In the second cell region, a second parasitic diode D2 is formed between the PW region and the ND region. In the fourth cell region, a protection diode D3 is formed between the PW region and the ND region.

[0105] In each of the above embodiments, a fifth P-type highly doped region P+ is further formed on the substrate (Psub), and a substrate electrode region B is formed on the dielectric layer. At least a part of the substrate electrode region B passes through the dielectric layer and contacts the fifth P-type highly doped region P+.

[0106] In each of the above embodiments, the MOS transistors of the semiconductor device are all NMOS transistors. Those skilled in the art should understand that the MOS transistors can also be designed as PMOS transistors. If the MOS transistors are designed as PMOS transistors, the "P-type" and "N-type" in each of the above embodiments are interchanged, and semiconductor devices using PMOS transistors for battery protection switches in multiple embodiments can be formed.

[0107] Figure 2 and Figure 3 In the illustrated embodiment, the region between the dielectric layer and the substrate in the first cell region is isolated from the region between the dielectric layer and the substrate in the fourth cell region by an isolation dielectric; the region between the dielectric layer and the substrate in the second cell region is isolated from the region between the dielectric layer and the substrate in the third cell region by an isolation dielectric; the region between the dielectric layer and the substrate in the third cell region is isolated from the doped region between the substrate electrode region and the substrate by an isolation dielectric.

[0108] Among them, the isolation dielectric can be an oxide layer.

[0109] Figure 4 is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0110] Figure 4 In, the region between the dielectric layer and the substrate in the first cell region is isolated from the region between the dielectric layer and the substrate in the fourth cell region by a PN junction; the region between the dielectric layer and the substrate in the second cell region is isolated from the region between the dielectric layer and the substrate in the third cell region by a PN junction; the region between the dielectric layer and the substrate in the third cell region is isolated from the doped region between the substrate electrode region and the substrate by a PN junction.

[0111] By the region extending from the substrate (Psub) extending in the drift region and extending to the dielectric layer, a PN junction is formed between the region between the dielectric layer and the substrate in the first cell region and the region between the dielectric layer and the substrate in the fourth cell region; a PN junction is formed between the region between the dielectric layer and the substrate in the second cell region and the region between the dielectric layer and the substrate in the third cell region; a PN junction is formed between the region between the dielectric layer and the substrate in the third cell region and the doped region between the substrate electrode region and the substrate.

[0112] Figure 5It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0113] Figure 5 The device structure in [[ ]] adopts the Loscos structure design.

[0114] Figure 6 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0115] Figure 6 The device structure in [[ ]] adopts the RESURF structure design.

[0116] Figure 7 It is a schematic structural diagram of a semiconductor device for a battery protection switch according to another embodiment of the present disclosure.

[0117] Figure 7 The partial structure of a semiconductor device for a battery protection switch according to an embodiment is shown in [[ ]], including the structures of a first cell region (MNLV1) and a second cell region (MNHV2).

[0118] Figure 8 The partial structure of a semiconductor device for a battery protection switch according to an embodiment is shown in [[ ]], including the structures of a first cell region (MNLV1) and a second cell region (MNHV2).

[0119] Figure 9 The partial structure of a semiconductor device for a battery protection switch according to an embodiment is shown in [[ ]], including the structures of a first cell region (MNLV1) and a second cell region (MNHV2).

[0120] As Figure 7 shown, the first cell region (MNLV1) and the second cell region (MNHV2) adopt the VDMOS design.

[0121] As Figure 7 shown, the first cell region includes a first source region S1, a drain region D, and a first gate region G1. An N-type highly doped region N+ is formed on the drain region D. An N-type drift region is formed on the N-type highly doped region N+. A P-type well region is formed in the N-type drift region. A P-type highly doped region is formed in the P-type well region. An N-type highly doped region is formed on the P-type well region. The first cell region further includes a dielectric layer. At least a part of the first source region S1 sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region. Two isolation dielectric regions are symmetrically formed in the P-type well region, and a first gate region G1 is formed in each isolation dielectric region.

[0122] The second cell region includes a second source region S2, a drain region D, and a second gate region G2. An N-type highly doped region N+ is formed on the drain region D, an N-type drift region is formed on the N-type highly doped region N+, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, and an N-type highly doped region is formed on the P-type well region. The second cell region further includes a dielectric layer. At least a part of the second source region S2 sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region. Two isolation dielectric regions are symmetrically formed in the P-type well region, and a second gate region G2 is formed in each isolation dielectric region.

[0123] As Figure 7 shown, the first cell region and the second cell region share the dielectric layer, the drain region, and the N-type highly doped region N+.

[0124] Preferably, at least one isolation dielectric region is formed between the P-type well region PW of the first cell region and the P-type well region PW of the second cell region, and a metal floating region is formed in the isolation dielectric region.

[0125] Preferably, at least one isolation dielectric region is formed between the P-type well region PW of the first cell region and the P-type well region PW of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

[0126] Preferably, the thickness of the drift region ND of the first cell region (MNLV1) is less than the thickness of the drift region ND of the second cell region (MNHV2), so that the first MOS transistor formed by the first cell region has low breakdown voltage performance, and the second MOS transistor formed by the second cell region has high breakdown voltage performance.

[0127] Figure 7 The first gate region G1 and the second gate region G2 in

[0128] Figure 8 are both trench gate structures.

[0129] Figure 9 In

[0130] Figures 7 to 9 the illustrated embodiment, the MOS transistors of the semiconductor device are all NMOS transistors. Those skilled in the art should understand that the MOS transistors can also be designed as PMOS transistors. If the MOS transistors are designed as PMOS transistors, Figures 7 to 9 by interchanging the "P-type" and "N-type" in the illustrated embodiment, semiconductor devices using PMOS transistors for battery protection switches in multiple embodiments can be formed.

[0131] Those skilled in the art should understand that in each of the above embodiments, the sizes and shapes of the D region, N+ region, ND region, PW region, G region, S region, B region, N region, N+ region, P+ region, dielectric layer, isolation dielectric, etc. are all exemplary. Appropriate adjustments to the sizes and shapes by those skilled in the art all fall within the protection scope of the present disclosure.

[0132] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A semiconductor device for a battery protection switch, characterized in that, Comprising: A first cell region in which a first MOS transistor is formed, the first MOS transistor receiving a first control signal to turn on or off the first MOS transistor; A second cell region in which a second MOS transistor is formed, the second MOS transistor receiving a second control signal to turn on or off the second MOS transistor, the first cell region and the second cell region being disposed adjacent to each other; And A third cell region disposed adjacent to the second cell region, a switch being formed in the third cell region, the switch receiving a third control signal to perform the following control: when the first MOS transistor performs a turn-off operation, the switch turns on so that the second MOS transistor turns off before the first MOS transistor turns off or turns off simultaneously with the first MOS transistor turning off; The first cell region includes a first gate region, a first source region, and a first drain region, and a first parasitic diode is formed in the first cell region, the first parasitic diode being formed between the first source region and the first drain region; The second cell region includes a second gate region, a second source region, and a first drain region, and a second parasitic diode is formed in the second cell region, the second parasitic diode being formed between the second source region and the first drain region; The first parasitic diode and the second parasitic diode form a reverse series structure, and the first cell region and the second cell region share the first drain region; The third cell region includes a third gate region, a second source region, and a third drain region, the third cell region and the second cell region sharing the second source region, and the third drain region of the third cell region and the second gate region of the second cell region can be connected.

2. The semiconductor device according to claim 1, wherein Further included is a fourth cell region disposed adjacent to the first cell region, a protection diode being formed in the fourth cell region, the fourth cell region including a first source region and a second drain region, the fourth cell region and the first cell region sharing the first source region, and the first drain region of the first cell region and the second drain region of the fourth cell region can be connected, such that the protection diode is connected in parallel with the first parasitic diode, so that when it is necessary to turn off the second MOS transistor, the second MOS transistor is quickly turned off by the voltage formed on the protection diode.

3. The semiconductor device according to claim 2, wherein, The protection diode is a high-voltage diode.

4. The semiconductor device according to claim 2, characterized in that, Further included is a substrate electrode region, and the first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate.

5. The semiconductor device according to claim 1, wherein The first MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; The first cell region includes a first gate region, a first source region, and a first drain region, and the first cell region includes a P-type substrate and a dielectric layer; At least an N-type drift region is formed between the P-type substrate and the dielectric layer. A first P-type well region is formed in the N-type drift region. At least a first P-type highly doped region and a first N-type highly doped region are formed in the first P-type well region. The first P-type well region is spaced from the P-type substrate by the N-type drift region. A second N-type highly doped region is formed in the N-type drift region; The first source region is formed on the dielectric layer. At least a part of the first source region passes through the dielectric layer to contact the first N-type highly doped region and the first P-type highly doped region; The first drain region is formed on the dielectric layer. At least a part of the first drain region passes through the dielectric layer to contact the second N-type highly doped region; The first gate region is formed in the dielectric layer.

6. The semiconductor device according to claim 1, wherein The second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; The second cell region includes a second gate region, a second source region, and a first drain region. The second cell region includes a P-type substrate and a dielectric layer; At least an N-type drift region is formed between the P-type substrate and the dielectric layer. A second P-type well region is formed in the N-type drift region. At least a third P-type highly doped region and a third N-type highly doped region are formed in the second P-type well region. The second P-type well region is spaced from the P-type substrate by the N-type drift region. A second N-type highly doped region is formed in the N-type drift region; The second source region is formed on the dielectric layer. At least a part of the second source region passes through the dielectric layer to contact the third N-type highly doped region and the third P-type highly doped region; The first drain region is formed on the dielectric layer. At least a part of the first drain region passes through the dielectric layer to contact the second N-type highly doped region; The second gate region is formed in the dielectric layer.

7. The semiconductor device according to claim 4, characterized in that, The third cell region includes a third gate region, a second source region, and a third drain region. The third cell region includes a P-type substrate and a dielectric layer; At least an N-type drift region is formed between the P-type substrate and the dielectric layer. A third P-type well region is formed in the N-type drift region. At least a fourth P-type highly doped region and a fourth N-type highly doped region are formed in the third P-type well region. The third P-type well region is spaced from the P-type substrate by the N-type drift region. A fifth N-type highly doped region is formed in the N-type drift region; The second source region is formed on the dielectric layer. At least a part of the second source region passes through the dielectric layer to contact the fourth N-type highly doped region and the fourth P-type highly doped region; The third drain region is formed on the dielectric layer. At least a part of the third drain region passes through the dielectric layer to contact the fifth N-type highly doped region; The third gate region is formed in the dielectric layer.

8. The semiconductor device according to claim 2, wherein The fourth cell region includes a first source region and a second drain region. The fourth cell region includes a P-type substrate and a dielectric layer; At least an N-type drift region is formed between the P-type substrate and the dielectric layer. A fourth P-type well region is formed in the N-type drift region. At least a sixth P-type highly doped region is formed in the fourth P-type well region. The fourth P-type well region is spaced apart from the P-type substrate by the N-type drift region. A sixth N-type highly doped region is formed in the N-type drift region; The first source region is formed on the dielectric layer. At least a part of the first source region passes through the dielectric layer and contacts the sixth P-type highly doped region; The second drain region is formed on the dielectric layer. At least a part of the second drain region passes through the dielectric layer and contacts the sixth N-type highly doped region.

9. The semiconductor device according to claim 7, wherein A fifth P-type highly doped region is further formed on the substrate. The substrate electrode region is formed on the dielectric layer. At least a part of the substrate electrode region passes through the dielectric layer and contacts the fifth P-type highly doped region.

10. The semiconductor device according to claim 2, wherein, The first MOS transistor is a PMOS transistor, and the substrate is an N-type substrate; The first cell region includes a first gate region, a first source region, and a first drain region. The first cell region includes an N-type substrate and a dielectric layer; At least a P-type drift region is formed between the N-type substrate and the dielectric layer. A first N-type well region is formed in the P-type drift region. At least a first N-type highly doped region and a first P-type highly doped region are formed in the first N-type well region. The first N-type well region is spaced apart from the N-type substrate by the P-type drift region. A second P-type highly doped region is formed in the P-type drift region; The first source region is formed on the dielectric layer. At least a part of the first source region passes through the dielectric layer and contacts the first P-type highly doped region and contacts the first N-type highly doped region; The first drain region is formed on the dielectric layer. At least a part of the first drain region passes through the dielectric layer and contacts the second P-type highly doped region; The first gate region is formed in the dielectric layer.

11. The semiconductor device according to claim 2, wherein The second MOS transistor is a PMOS transistor, and the substrate is an N-type substrate; The second cell region includes a second gate region, a second source region, and a first drain region. The second cell region includes an N-type substrate and a dielectric layer; At least a P-type drift region is formed between the N-type substrate and the dielectric layer. A second N-type well region is formed in the P-type drift region. At least a third N-type highly doped region and a third P-type highly doped region are formed in the second N-type well region. The second N-type well region is spaced apart from the N-type substrate by the P-type drift region. A second P-type highly doped region is formed in the P-type drift region; The second source region is formed on the dielectric layer. At least a part of the second source region passes through the dielectric layer and contacts the third P-type highly doped region and contacts the third N-type highly doped region; The first drain region is formed on the dielectric layer. At least a part of the first drain region passes through the dielectric layer and contacts the second P-type highly doped region; The second gate region is formed in the dielectric layer.

12. The semiconductor device according to claim 4, wherein, The third cell region includes a third gate region, a second source region, and a third drain region. The third cell region includes an N-type substrate and a dielectric layer; At least a P-type drift region is formed between the N-type substrate and the dielectric layer. A third N-type well region is formed in the P-type drift region. At least a fourth N-type highly doped region and a fourth P-type highly doped region are formed in the third N-type well region. The third N-type well region and the N-type substrate are spaced apart by the P-type drift region. A fifth P-type highly doped region is formed in the P-type drift region; The second source region is formed on the dielectric layer. At least a part of the second source region passes through the dielectric layer to contact the fourth P-type highly doped region and the fourth N-type highly doped region; The third drain region is formed on the dielectric layer. At least a part of the third drain region passes through the dielectric layer to contact the fifth P-type highly doped region; The third gate region is formed in the dielectric layer.

13. The semiconductor device according to claim 2, wherein The fourth cell region includes a first source region and a second drain region; the fourth cell region includes an N-type substrate and a dielectric layer; At least a P-type drift region is formed between the N-type substrate and the dielectric layer. A fourth N-type well region is formed in the P-type drift region. At least a sixth N-type highly doped region is formed in the fourth N-type well region. The fourth N-type well region and the N-type substrate are spaced apart by the P-type drift region. A sixth P-type highly doped region is formed in the P-type drift region; The first source region is formed on the dielectric layer. At least a part of the first source region passes through the dielectric layer to contact the sixth N-type highly doped region; The second drain region is formed on the dielectric layer. At least a part of the second drain region passes through the dielectric layer to contact the sixth P-type highly doped region.

14. The semiconductor device according to claim 12, wherein, A fifth N-type highly doped region is further formed on the substrate. The substrate electrode region is formed on the dielectric layer. At least a part of the substrate electrode region passes through the dielectric layer to contact the fifth N-type highly doped region.

15. The semiconductor device according to any one of claims 9 to 14, characterized in that, The region between the dielectric layer and the substrate of the first cell region and the region between the dielectric layer and the substrate of the fourth cell region are isolated by a PN junction; The region between the dielectric layer and the substrate of the second cell region and the region between the dielectric layer and the substrate of the third cell region are isolated by a PN junction; The region between the dielectric layer and the substrate of the third cell region and the doped region between the substrate electrode region and the substrate are isolated by a PN junction.

16. The semiconductor device according to any one of claims 9 to 14, characterized in that, The region between the dielectric layer and the substrate of the first cell region and the region between the dielectric layer and the substrate of the fourth cell region are isolated by an isolation dielectric; The region between the dielectric layer and the substrate of the second cell region and the region between the dielectric layer and the substrate of the third cell region are isolated by an isolation dielectric; The region between the dielectric layer and the substrate of the third cell region and the doped region between the substrate electrode region and the substrate are isolated by an isolation dielectric.

17. The semiconductor device according to claim 2, wherein, The first cell region includes a first source region, a drain region, and a first gate region. An N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region. The first cell region further includes a dielectric layer. At least a part of the first source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region; Two isolation dielectric regions are symmetrically formed in the P-type well region, and one of the first gate regions is formed in each of the isolation dielectric regions.

18. The semiconductor device according to claim 17, wherein The second cell region includes a second source region, a drain region, and a second gate region. An N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region. The second cell region further includes a dielectric layer. At least a part of the second source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region; Two isolation dielectric regions are symmetrically formed in the P-type well region, and one of the second gate regions is formed in each of the isolation dielectric regions.

19. The semiconductor device according to claim 18, wherein, The first cell region and the second cell region share the dielectric layer, the drain region, and the N-type highly doped region.

20. The semiconductor device according to claim 19, wherein, At least one isolation dielectric region is formed at least between the P-type well regions of the first cell region and the second cell region, and a metal floating region is formed in the isolation dielectric region.

21. The semiconductor device according to claim 20, wherein, At least one isolation dielectric region is formed at least between the P-type well regions of the first cell region and the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

22. The semiconductor device according to any one of claims 18 to 21, characterized in that, Both the first gate region and the second gate region are trench gate structures.

23. The semiconductor device according to any one of claims 18 to 21, characterized in that, Both the first gate region and the second gate region are separated trench gate structures.

24. The semiconductor device according to any one of claims 18 to 21, characterized in that, Both the first cell region and the second cell region adopt a super junction structure.

25. The semiconductor device according to claim 2, wherein, The first cell region includes a first source region, a drain region, and a first gate region. A P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region. The first cell region further includes a dielectric layer. At least a part of the first source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts the N-type highly doped region; Two isolation dielectric regions are symmetrically formed in the N-type well region, and one of the first gate regions is formed in each of the isolation dielectric regions.

26. The semiconductor device according to claim 25, wherein, The second cell region includes a second source region, a drain region, and a second gate region. A P-type highly doped region is formed on the drain region. A P-type drift region is formed on the P-type highly doped region. An N-type well region is formed in the P-type drift region. An N-type highly doped region is formed in the N-type well region. A P-type highly doped region is formed on the N-type well region. The second cell region further includes a dielectric layer. At least a part of the second source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts the N-type highly doped region; Two isolation dielectric regions are symmetrically formed in the N-type well region, and one of the second gate regions is formed in each of the isolation dielectric regions.

27. The semiconductor device according to claim 26, wherein The first cell region shares the dielectric layer, the drain region, and the P-type highly doped region with the second cell region.

28. The semiconductor device according to claim 27, wherein, At least one isolation dielectric region is formed at least between the N-type well region of the first cell region and the N-type well region of the second cell region, and a metal floating region is formed in the isolation dielectric region.

29. The semiconductor device according to claim 28, wherein At least one isolation dielectric region is formed at least between the N-type well region of the first cell region and the N-type well region of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

30. The semiconductor device according to any one of claims 26 to 29, characterized in that, Both the first gate region and the second gate region are trench gate structures.

31. The semiconductor device according to any one of claims 26 to 29, characterized in that, Both the first gate region and the second gate region are separated trench gate structures.

32. The semiconductor device according to any one of claims 1 to 14, 17 to 21, and 25 to 29, characterized in that, The thickness of the drift region of the first cell region is less than the thickness of the drift region of the second cell region, so that the first MOS transistor formed by the first cell region has low breakdown voltage performance, and the second MOS transistor formed by the second cell region has high breakdown voltage performance.

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