Image sensing device and electronic device including the same

Abstract

An image sensing device includes a pixel circuit, a readout circuit, and a row driver. The pixel circuit is configured to output a pixel signal in response to a select signal. The readout circuit is configured to output a digital signal corresponding to the pixel signal, generate a gain control signal based on a first pixel signal received from the pixel circuit, provide the gain control signal to the pixel circuit, receive a second pixel signal output by the pixel circuit using the gain control signal, and output a digital signal corresponding to the second pixel signal. The row driver is configured to provide the select signal to the pixel circuit while the readout circuit provides the gain control signal to the pixel circuit and the pixel circuit outputs the second pixel signal to the readout circuit, while maintaining the select signal at a first level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0074074 filed on June 18, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an image sensing device and / or an electronic device including the image sensing device. Background Art

[0004] Image sensing devices may include semiconductor elements that convert light information into electrical signals. Such image sensing devices may include charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices.

[0005] A CMOS image sensor can be abbreviated as CIS. A CIS can include multiple pixels arranged in a two-dimensional manner. Each pixel can include, for example, a photodiode (PD). A photodiode can be used to convert incident light into an electrical signal.

[0006] Recently, with the development of the computer industry and the communications industry, the demand for image sensors with improved performance has continued to increase in various fields such as providing digital cameras, video cameras, smartphones, game consoles, security cameras, medical micro cameras, and robots. In addition, as semiconductor devices become highly integrated, image sensors are also becoming highly integrated. Summary of the Invention

[0007] Aspects of the present disclosure provide an image sensing device capable of high-speed operation.

[0008] Aspects of the present disclosure also provide an electronic device capable of performing a high-speed image sensing operation.

[0009] According to an embodiment, an image sensing device may include a pixel circuit including a floating diffusion, a photoelectric element, a drive transistor, a dual conversion gain DCG transistor, a selection transistor, and a column line connected to the selection transistor. The floating diffusion may be a region in the pixel circuit. The floating diffusion may be configured to store charge generated by the photoelectric element. The drive transistor may be configured to generate a pixel signal based on the charge stored in the floating diffusion. The selection transistor may be configured to output the pixel signal generated by the drive transistor to the column line in response to the selection transistor receiving a selection signal. The selection transistor may be configured to output a first pixel signal to the column line based on the charge stored in the floating diffusion when the DCG transistor is turned off. The DCG transistor may be configured to change the capacitance of the floating diffusion in response to the DCG transistor receiving a gain control signal. The pixel circuit may be configured to perform operations in which the selection transistor outputs the first pixel signal to the column line and the DCG transistor receives the gain control signal while the selection transistor receives the selection signal maintained at a first level.

[0010] According to an embodiment, an image sensing device may include a pixel circuit, a readout circuit, and a row driver. The pixel circuit may be configured to output a pixel signal in response to a selection signal. The readout circuit may be configured to output a digital signal corresponding to the pixel signal provided from the pixel circuit. The readout circuit may be configured to receive a first pixel signal from the pixel circuit, generate a gain control signal based on the first pixel signal, and provide the gain control signal to the pixel circuit. The readout circuit may be configured to receive a second pixel signal output by the pixel circuit using the gain control signal, and output a digital signal corresponding to the second pixel signal. The row driver may be configured to provide the selection signal to the pixel circuit while maintaining the selection signal at a first level during the operation of the readout circuit providing the gain control signal to the pixel circuit and the operation of the pixel circuit outputting the second pixel signal to the readout circuit.

[0011] According to an embodiment, an image sensing device may include a pixel circuit, a row driver, a ramp signal generator, and a readout circuit. The pixel circuit may be configured to output a pixel signal in response to a selection signal. The row driver may be configured to generate a selection signal and provide the selection signal to the pixel circuit. The ramp signal generator may be configured to generate a ramp signal. The readout circuit may be configured to receive a pixel signal from the pixel circuit, compare the pixel signal with a ramp signal provided by the ramp signal generator, and output a digital signal corresponding to the pixel signal. The ramp signal generator may be configured to provide the ramp signal to the readout circuit. The ramp signal may include a first pulse that drops from a reference voltage to a first level, a second pulse that drops from the reference voltage to a second level different from the first level, and a third pulse that drops from the reference voltage to a third level different from the second level. The ramp signal generator may be configured to provide the first pulse, the second pulse, and the third pulse to the readout circuit while the row driver provides the selection signal to the pixel circuit and maintains the selection signal at the first level.

[0012] According to an embodiment, an electronic device may include an image sensor and a processor. The image sensor may include a plurality of sensing units, and the image sensor may be configured to output an image signal based on light sensed by the plurality of sensing units. The image signal may include conversion gain information for each of the plurality of sensing units. The processor may be configured to receive the image signal from the image sensor and perform image processing on the image signal using the conversion gain information for each of the plurality of sensing units included in the image signal.

[0013] However, the aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of an image sensing device according to some example embodiments;

[0016] Figure 2 It shows Figure 1 A diagram showing the conceptual layout of an image sensor;

[0017] Figure 3 Is used to illustrate Figure 1 A diagram of an example of a pixel array;

[0018] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA';

[0019] Figure 5 yes Figure 1 A unit pixel circuit diagram included in a pixel array;

[0020] Figure 6 It shows Figure 1 A block diagram of the pixel array and readout circuitry;

[0021] Figure 7 is a timing diagram for explaining the operation of an image sensing device according to some example embodiments;

[0022] Figure 8 Is used to illustrate the Figure 6 FIG. 1 is a diagram showing a structure of a digital signal output by a readout circuit;

[0023] Figure 9 is a diagram for explaining effects of an image sensing device according to some example embodiments;

[0024] Figure 10 is a block diagram of an image sensing device according to some example embodiments;

[0025] Figure 11 yes Figure 10 Example circuit diagram of the timing controller;

[0026] Figure 12 is a timing diagram for explaining the operation of an image sensing device according to some example embodiments;

[0027] Figure 13 is an exemplary diagram for explaining a pixel array of an image sensing device according to an example embodiment;

[0028] Figure 14 is a circuit diagram illustrating a pixel circuit of an image sensing device according to example embodiments;

[0029] Figure 15 is an exemplary diagram for explaining a pixel array of an image sensing device according to an example embodiment;

[0030] Figure 16 is a block diagram of an electronic device including a multi-camera module; and

[0031] Figure 17 yes Figure 16 Detailed block diagram of the camera module. DETAILED DESCRIPTION

[0032] Hereinafter, example embodiments according to the inventive concept will be described with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram of an image sensing device according to some example embodiments.

[0034] Reference Figure 1 , the image sensing device 1 may include an image sensor 100 and an image processor 900 .

[0035] The image sensor 100 may generate an image signal IMS by sensing an image of a sensing target using light. In some example embodiments, the generated image signal IMS may be, for example, a digital signal, but example embodiments are not limited thereto.

[0036] The image signal IMS may be provided to and processed in the image processor 900. The image processor 900 receives the image signal IMS output from the buffer 170 of the image sensor 100 and may process the received image signal IMS to facilitate display thereof.

[0037] In some example embodiments, the image processor 900 may perform digital binning on the image signal IMS output from the image sensor 100. In this case, the image signal IMS output from the image sensor 100 may be a raw image signal from the pixel array 140 that has not been subjected to analog binning, or may be an image signal IMS that has been subjected to analog binning.

[0038] In some example embodiments, the image sensor 100 and the image processor 900 may be placed separately from each other, as shown. For example, the image sensor 100 may be mounted on a first chip and the image processor 900 may be mounted on a second chip, and they may communicate with each other via a predetermined interface, or alternatively, may communicate with each other via a desired interface. However, example embodiments are not limited thereto, and the image sensor 100 and the image processor 900 may be implemented as a single package, such as an MCP (Multi-Chip Package).

[0039] The image sensor 100 may include a control register block 110 , a timing generator 120 , a row driver 130 , a pixel array 140 , a readout circuit 150 , a ramp signal generator 160 , and a buffer 170 .

[0040] The control register block 110 may generally control the operation of the image sensor 100. Specifically, the control register block 110 may directly transmit an operating signal to the timing generator 120, the ramp signal generator 160, and the buffer 170.

[0041] The timing generator 120 may generate a signal used as a reference for operation timing of components of the image sensor 100. The operation timing reference signal generated by the timing generator 120 may be transmitted to the row driver 130, the readout circuit 150, the ramp signal generator 160, and the like.

[0042] The ramp signal generator 160 may generate and transmit a ramp signal used in the readout circuit 150. For example, the readout circuit 150 may include a correlated double sampler (CDS), a comparator, etc., and the ramp signal generator 160 may generate and transmit a ramp signal used in the correlated double sampler (CDS), the comparator, etc.

[0043] The buffer 170 may include, for example, a latch unit. The buffer 170 may temporarily store the image signal IMS to be provided to the outside, and may transmit the image signal IMS to an external memory or an external device.

[0044] The pixel array 140 may sense an external image. The pixel array 140 may include a plurality of pixels (or unit pixels). The row driver 130 may selectively activate rows of the pixel array 140.

[0045] The readout circuit 150 samples the pixel signal provided from the pixel array 140 , compares the pixel signal with the ramp signal, and may then convert the analog image signal (data) into a digital image signal (data) based on the comparison result.

[0046] Figure 2 It shows Figure 1 Diagram of the conceptual layout of an image sensor.

[0047] Reference Figure 2 , the image sensor 100 may include a first region S1 and a second region S2 stacked in a first direction Z (eg, a vertical direction). As shown in the figure, the first region S1 and the second region S2 may extend in a second direction X and a third direction Y, and Figure 1 The blocks shown may be placed in a first region S1 and a second region S2. The first region S1 and the second region S2 may be regions included in a semiconductor substrate such as a silicon substrate, which may also include an underlying organic plastic substrate, but is not limited thereto.

[0048] Although not shown in the drawings, a third area containing a memory device may be placed below the second area S2. In this case, the memory device placed in the third area receives image data from the first and second areas S1 and S2, stores or processes the image data, and can resend the image data to the first and second areas S1 and S2. The memory device may include storage elements such as DRAM (dynamic random access memory) elements, SRAM (static random access memory) elements, STT-MRAM (spin transfer torque magnetic random access memory) elements, and flash memory elements. When the memory device includes, for example, DRAM elements, it can receive and process image data at a relatively high speed. Furthermore, in some example embodiments, the memory device may be placed in the second area S2.

[0049] The first region S1 may include a pixel array region PA and a first peripheral region PH1, and the second region S2 may include a logic circuit region LC and a second peripheral region PH2. The first region S1 and the second region S2 may be sequentially stacked and positioned vertically.

[0050] In the first area S1, the pixel array area PA may be where the reference Figure 1 The pixel array described ( Figure 1 The pixel array region PA may include a plurality of unit pixels ( Figure 3 Each pixel may include a photodiode and a transistor. A more detailed description will be provided later.

[0051] The first peripheral area PH1 may include a plurality of pads and may be positioned around the pixel array area PA. The plurality of pads may transmit and receive electrical signals to and from an external device or the like.

[0052] In the second region S2 , the logic circuit region LC may include electronic components including a plurality of transistors. The electronic components included in the logic circuit region LC may be electrically connected to the pixel array region PA to provide signals to each unit pixel PX of the pixel array region PA or control output signals.

[0053] For example, the reference above Figure 1 The control register block 110, timing generator 120, row driver 130, readout circuit 150, ramp signal generator 160, buffer 170, etc. described above can be placed in the logic circuit region LC. For example, Figure 1 Blocks other than the pixel array 140 among the blocks may be placed in the logic circuit region LC.

[0054] The second peripheral region PH2 may also be placed in a region of the first region S1 corresponding to the first peripheral region PH1 , but example embodiments are not limited thereto.

[0055] Figure 3 Is used to illustrate Figure 1 FIG. 1 is a diagram of an example of a pixel array.

[0056] Reference Figure 3 , the pixels PX(i,j) of the pixel array 140 may be arranged, for example, in a Bayer pattern. However, example embodiments are not limited thereto, and the pixels PX(i,j) may also be arranged, for example, in a tetra pattern or a nona pattern.

[0057] exist Figure 3In the figure, although only sixteen filters in four rows and four columns are shown to illustrate the Bayer pattern, for the sake of illustration, this only shows some filter areas, and example embodiments are not limited thereto. That is, the number of filters in the Bayer pattern can be modified and implemented as many times as needed.

[0058] The Bayer pattern may include filters of three colors: red, green, and blue. The R filter (R) is a filter that transmits only red, the G filters (Gr and Gb) are filters that transmit only green, and the B filter (B) is a filter that transmits only blue. As a Bayer pattern, Figure 3 As shown, each of the R, G, and B filters (R, Gb, Gr, and B) can be placed while having a constant pattern. Figure 3 As shown, according to human visual characteristics, the G filter may include a Gr filter (Gr) located next to the R filter (R) and a Gb filter (Gb) located next to the B filter (B).

[0059] As shown in the drawing, a Bayer pattern may be formed by forming a region in which each color filter (eg, R, Gb, Gr, or B) is formed in a 1×1 matrix.

[0060] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'.

[0061] Reference Figure 4 The image sensor includes substrates 146R and 146Gr, phototransistors 148R and 148Gr, an anti-reflection film 147, a side anti-reflection film 144, a color filter 143, an upper planarization film 142, a lower planarization film 145, and microlenses 141-1 and 141-2. The color filter 143 may include a red color filter R for selectively transmitting light in a red wavelength region and a green color filter Gr for selectively transmitting light in a green wavelength region, but example embodiments are not limited thereto. The color filter 143 may be formed of a photosensitive resin or other suitable color filter material.

[0062] Since the substrates 146R and 146Gr can be a P-type or N-type bulk substrate, for example, a P-type or N-type epitaxial layer can be used by growing it on a P-type bulk substrate, or a P-type or N-type epitaxial layer can be used by growing it on an N-type bulk substrate. In addition, as the substrates 146R and 146Gr, a substrate such as an organic plastic substrate can be used in addition to a semiconductor substrate.

[0063] The phototransistors 148R and 148Gr may be photodiodes, phototransistors, photogates, pinned photodiodes, or a combination thereof. Hereinafter, photodiodes will be described as an example of photoelectric elements, but example embodiments are not limited thereto.

[0064] The anti-reflection film 147 and the side anti-reflection film 144 may reduce or prevent light entering the microlenses 141-1 and 141-2 from the outside from penetrating the region R and the region Gr. Although the anti-reflection film 147 and the side anti-reflection film 144 may be made of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin, and a combination thereof, or a laminate thereof, example embodiments are not limited thereto.

[0065] The upper and lower planarizing films 142 and 145 may be formed to be flat with the color filters R and Gr interposed therebetween. Although the upper and lower planarizing films 142 and 145 may include at least one of a silicon oxide film-based material, a silicon nitride film-based material, a resin, or a combination thereof, example embodiments are not limited thereto.

[0066] Figure 5 yes Figure 1 A unit pixel circuit diagram included in a pixel array.

[0067] Reference Figure 5 The pixel PX may include a photoelectric element PD, a charge transfer transistor CT, a reset transistor RT, a floating diffusion FD, a drive transistor DT, a selection transistor ST, and a DCG (dual conversion gain) transistor GT. The features of the pixel PX may be formed in a semiconductor substrate such as a silicon substrate.

[0068] The photoelectric element PD may generate charges by sensing an external image (or light), a cathode of the photoelectric element PD may be connected to a floating node of the floating diffusion FD through a charge transfer transistor CT, and an anode of the photoelectric element PD may be grounded.

[0069] Although the photoelectric element PD may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof, example embodiments are not limited thereto.

[0070] In some embodiments, the photoelectric element PD may include an organic photodiode.

[0071] When the photoelectric element PD is an organic photodiode, the photoelectric element PD may include a first electrode and a second electrode arranged in parallel with each other, and an organic light conversion layer disposed between the first electrode and the second electrode. The organic light conversion layer may receive light of a predetermined wavelength band, or alternatively, light of a desired wavelength band, to generate charges.

[0072] The charge transfer transistor CT is provided by, for example, a row driver ( Figure 1 The transfer signal TG provided by 130) is turned on, and the charges generated by the photoelectric element PD can be transferred to the floating diffusion portion FD.

[0073] The floating diffusion FD may function as a kind of capacitor C1 having a predetermined capacitance or, alternatively, a desired capacitance, and may store charges generated by the photoelectric element PD.

[0074] The gate terminal of the drive transistor DT can be connected to the floating diffusion FD. The drive transistor DT can operate as a source follower buffer amplifier by using the charge stored in the floating diffusion FD. That is, the drive transistor DT can use the power supply voltage VDD to amplify the charge generated in the photoelectric element PD and transferred to the floating diffusion FD, and can transfer the charge to the select transistor ST.

[0075] For example, the row driver ( Figure 1 The selection signal SEL provided by the row driver (130) turns on the selection transistor ST, and the selection transistor ST can perform switching operations and addressing operations. Figure 1 When the selection signal SEL is applied to the 130) of the CMOS circuit, the pixel signal VO can be output to the column line connected to the selection transistor ST. Such a pixel signal VO can be output by the readout circuit ( Figure 1 150) detection.

[0076] The reset transistor RT can be reset, for example, by a row driver ( Figure 1 When the reset transistor RT is turned on by the reset signal RG, the floating diffusion FD and the capacitor C2 can be reset to the power supply voltage VDD.

[0077] The DCG transistor GT can be read out by, for example, a readout circuit ( Figure 1 Specifically, the DCG transistor GT can be turned on by, for example, a gain control signal CGCS provided by the row driver ( Figure 1 130) provides a reset signal RG and a readout circuit ( Figure 1 To this end, for example, the gate of the DCG transistor GT is connected to the output of the OR gate ORG, and the OR gate ORG can perform an OR operation on the reset signal RG and the gain control signal CGCS to provide the OR operation result to the gate of the DCG transistor GT.

[0078] When the DCG transistor GT is turned on, the floating diffusion FD can be reset to the power supply voltage VDD, and the capacitance of the floating diffusion FD can be increased to the sum of the capacitances of capacitors C1 and C2. That is, when the DCG transistor GT is turned off, the floating diffusion FD has the capacitance of capacitor C1, so the image sensor 100 generates an image signal in a high conversion gain mode. When the DCG transistor GT is turned on, the capacitance of the floating diffusion FD increases by the capacitance of capacitor C2, so the image sensor 100 can generate an image signal in a low conversion gain mode.

[0079] In some example embodiments, although the ratio of the capacitance of the capacitor C1 to the capacitance of the capacitor C2 may be about 1:3, example embodiments are not limited thereto.

[0080] In some example embodiments, although the reset transistor RT and the drive transistor DT are shown as receiving the power supply voltage VDD, example embodiments are not limited thereto. If desired, the voltages supplied to the reset transistor RT and the drive transistor DT may be modified to be different from the illustrated form. For example, in some example embodiments, a first voltage may be supplied to the reset transistor RT, and a second voltage different from the first voltage may be applied to the drive transistor DT.

[0081] Figure 6 It shows Figure 1 Block diagram of the pixel array and readout circuitry.

[0082] refer to Figure 6 , the pixel array 140 may include a plurality of pixels PX(i, j). The plurality of pixels PX(i, j) may be arranged into a plurality of rows i and a plurality of columns j. A row line may be provided for each of the plurality of rows i, and a column line may be provided for each of the plurality of columns j. Each pixel PX(i, j) may be selected by transmission signals TG(i), TG(i+1), and TG(i+2) and selection signals SEL(i), SEL(i+1), and SEL(i+2) to output pixel signals VO(j), VO(j+1), and VO(j+2).

[0083] The readout circuit 150 may include a plurality of comparators COMP 152(j), 152(j+1), and 152(j+2) (collectively referred to as 152) and a plurality of counters CNT 154(j), 154(j+1), and 154(j+2) (collectively referred to as 154) connected to a plurality of columns (j) of the pixel array 140. The readout circuit 150 may perform correlated double sampling operations and analog-to-digital conversion operations using, for example, the plurality of comparators 152(j), 152(j+1), and 152(j+2) and the plurality of counters 154(j), 154(j+1), and 154(j+2).

[0084] The ramp signal generator 160 may generate a ramp signal VR. The ramp signal VR is a signal for converting the pixel signals VO(j), VO(j+1), and VO(j+2), which are analog signals, into digital signals OD(j), OD(j+1), and OD(j+2), and may have a shape of, for example, a triangular wave.

[0085] The ramp signal generator 160 may generate the ramp signal VR, for example, in response to the ramp enable signal R_EN generated in the control register block 110. In some example embodiments, although the ramp signal generator 160 may control the ramp signal VR by generating a pulse according to a voltage drop on the ramp signal VR during a portion in which the ramp enable signal R_EN is enabled, example embodiments are not limited thereto.

[0086] The ramp signal VR generated by the ramp signal generator 160 can be provided to each comparator 152(j), 152(j+1), and 152(j+2). Each of the comparators 152(j), 152(j+1), and 152(j+2) can correspond one-to-one to the column line (j) of one pixel PX(i, j).

[0087] Comparators 152(j), 152(j+1), and 152(j+2) can compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2). Specifically, comparators 152(j), 152(j+1), and 152(j+2) first compare the ramp signal VR with the reset voltages of the pixel signals VO(j), VO(j+1), and VO(j+2), then compare the ramp signal VR with the signal voltages of the pixel signals VO(j), VO(j+1), and VO(j+2), and finally compare the ramp signal VR with the signal voltages of the pixel signals VO(j), VO(j+1), and VO(j+2). A detailed description will be provided later.

[0088] In some example embodiments, the comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2), and output a comparison signal based on the comparison result. Such a comparison signal may indicate which of the ramp signal VR and the pixel signals VO(j), VO(j+1), and VO(j+2) is larger using a binary signal. For example, when the ramp signal VR is larger, the comparator outputs "1," and when the pixel signals VO(j), VO(j+1), and VO(j+2) are larger, the comparator may output "0." Alternatively, the comparator may be configured to have an inverted output.

[0089] The counters 154(j), 154(j+1), and 154(j+2) may correspond one-to-one to the comparators 152(j), 152(j+1), and 152(j+2), respectively. That is, one comparison signal may be counted by one counter. However, example embodiments are not limited thereto.

[0090] The counters 154(j), 154(j+1), and 154(j+2) can count how long the comparison signals output by the comparators 152(j), 152(j+1), and 152(j+2) maintain the same value, for example, based on the time point when the ramp enable signal R_EN is enabled (or based on the time point when other counter signals are enabled). In addition, the counters can output digital signals OD(j), OD(j+1), and OD(j+2) of the pixel signals VO(j), VO(j+1), and VO(j+2) as analog signals based on the counting results.

[0091] Control signal generators CSG 156(j), 156(j+1), and 156(j+2) (collectively referred to as 156) can generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2), respectively. Specifically, control signal generators 156(j), 156(j+1), and 156(j+2) can generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of comparators 152(j), 152(j+1), and 152(j+2). A more detailed description will be provided later.

[0092] The gain control signals CGCS(j), CGCS(j+1) and CGCS(j+2) generated from the control signal generators 156(j), 156(j+1) and 156(j+2) may be provided to a plurality of pixels PX(i, j) through column lines.

[0093] although Figure 6 In the example, the control signal generators 156(j), 156(j+1), and 156(j+2) generate the gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of the comparators 152(j), 152(j+1), and 152(j+2), but example embodiments are not limited thereto. In some example embodiments, the control signal generators CSG 156(j), 156(j+1), and 156(j+2) (collectively referred to as 156) may generate the gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of the counters 154(j), 154(j+1), and 154(j+2).

[0094] In the following, reference will be made to Figures 5 to 8Operations of an image sensing device according to some example embodiments are described.

[0095] Figure 7 is a timing diagram for explaining operations of an image sensing device according to some example embodiments. Figure 8 Is used to illustrate the Figure 6 Diagram of the structure of the digital signal output by the readout circuit.

[0096] Figure 7 The illustrated ramp signal VR is a signal provided to the comparator 152 during one sensing period 1H, over which the selection signal SEL maintains a logic high level (hereinafter referred to as level H).

[0097] That is, the ramp signal generator 160 can provide the ramp signal VR to the comparator 152 during a sensing period 1H in which the selection signal SEL maintains the level H. For the ramp signal VR, the first pulse P1, the second pulse P2 and the third pulse P3 are applied in sequence, the first pulse P1 drops from the reference voltage by the first level dV1 to the ramp reset voltage V1, the second pulse P2 drops from the reference voltage by the second level dV2 to the ramp reference voltage REF, and the third pulse P3 drops from the reference voltage by the third level dV3 to the ramp signal voltage V3.

[0098] Specifically, the ramp signal generator 160 responds to the ramp enable signal R_EN during a sensing period 1H, and sequentially generates a first pulse P1 having a first amplitude, a second pulse P2 having a second amplitude greater than the first amplitude, and a third pulse P3 having a third amplitude greater than the second amplitude using the ramp signal VR, and can provide the pulses to the comparator 152.

[0099] Here, the ramp reference voltage REF may be determined between the ramp reset voltage V1 and the ramp signal voltage V3. That is, the second pulse P2 of the ramp signal VR may further drop from the reference voltage by more than the first level dV1 and less than the third level dV3.

[0100] In some example embodiments, although the ramp reference voltage REF may be determined as a saturation voltage of an analog-to-digital converter included in the readout circuit 150 , example embodiments are not limited thereto.

[0101] Although it is possible to obtain the data from, for example, the control register block ( Figure 1 110) controlled timing generator ( Figure 1 120) provides Figure 7 A selection signal SEL, a reset signal RG, a transmission signal TG, etc. are shown, but example embodiments are not limited thereto.

[0102] Reference Figures 5 to 7In the first section T1, the reset signal RG becomes level H, and the reset transistor RT is turned on. Since the reset signal RG of level H is also supplied to the OR gate ORG connected to the gate of the DCG transistor GT, the output of the OR gate ORG also becomes level H. Therefore, the DCG transistor GT is also turned on.

[0103] Therefore, the reset voltage is supplied to the floating diffusion FD and the capacitor C2, and the floating diffusion FD and the capacitor C2 are reset. In some example embodiments, the reset voltage may be, for example, the power supply voltage VDD. Hereinafter, the case where the reset voltage is the power supply voltage VDD will be described as an example.

[0104] Next, when the reset signal RG changes from the H level to the logic low level (hereinafter referred to as the L level), the reset transistor RT and the DCG transistor GT are turned off. On the other hand, the drive transistor DT generates the pixel signal VO based on the charge stored in the floating diffusion FD (charge reset by the power supply voltage VDD), and since the select transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0105] The readout circuit 150 supplied with the pixel signal VO compares the supplied pixel signal VO with the first pulse P1 and converts a reset signal of the pixel PX into a digital signal OD.

[0106] Next, when the transfer signal TG transitions from level L to level H in the second portion T2, the charge transfer transistor CT is turned on. When the charge transfer transistor CT is turned on, the charge generated by the photoelectric element PD is supplied to the floating diffusion FD (or the amount of charge stored in the floating diffusion FD is changed by light incident on the photoelectric element PD).

[0107] The drive transistor DT generates a pixel signal VO based on the charges stored in the floating diffusion FD (charges generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0108] If the optical power of the sensed image is low (for example, in a dark environment), the voltage level of the pixel signal VO changes to a voltage level lower than the reset signal, like the low pixel signal VOL. However, if the optical power of the generated image is high (for example, in a bright environment), the voltage level of the pixel signal VO changes to a voltage level higher than the reset signal, like the high pixel signal VOH.

[0109] The low pixel signal VOL can preferably generate an image signal with a high conversion gain HCG without increasing the capacitance of the floating diffusion part FD to maximize the sensing efficiency, and the high pixel signal VOH can preferably generate an image signal with a low conversion gain LCG by increasing the capacitance of the floating diffusion part FD to maximize the sensing saturation.

[0110] To determine this, the readout circuit 150 to which the pixel signal VO is supplied may compare the supplied pixel signal VO with the second pulse P2 to determine the signal level of the gain control signal CGCS.

[0111] After the second pulse P2 falls to the ramp reference voltage REF in the second section T2, the second pulse P2 maintains the ramp reference voltage REF in the third section T3.

[0112] At this time, the control signal generator 156 monitors the signal of the comparator 152 to determine whether the pixel signal VO provided from the pixel PX in the second section T2 is the low pixel signal VOL or the high pixel signal VOH.

[0113] For example, if the pixel signal VO provided from the pixel PX is a low pixel signal VOL, it can be known that the comparator 152 outputs 0, indicating that the pixel signal VO is greater than the ramp signal VR, and the control signal generator 156 is provided with 0, and it is necessary to generate an image signal with a high conversion gain in this sensing period 1H. In addition, if the pixel signal VO provided from the pixel PX is a high pixel signal VOH, it can be known that the comparator 152 outputs 1, indicating that the pixel signal VO is less than the ramp signal VR, and the control signal generator 156 is provided with 1, and it is necessary to generate an image signal with a low conversion gain in this sensing period 1H.

[0114] Next, in the fourth section T4, the control signal generator 156 generates and outputs the gain control signal CGCS of the H level or the L level.

[0115] If the pixel signal VO provided from the pixel PX is a low pixel signal VOL, the control signal generator 156 outputs a gain control signal CGCS of level L, so that the DCG transistor GT remains in an off state. Since the reset signal RG maintains a level L in the fourth section T4, the turn-on or turn-off of the DCG transistor GT is determined by the signal level of the gain control signal CGCS.

[0116] The drive transistor DT generates a pixel signal VO based on the charges stored in the floating diffusion FD (charges generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0117] The readout circuit 150 supplied with the pixel signal VO compares the supplied pixel signal VO with the third pulse P3 and converts the image signal of the pixel PX into a digital signal OD.

[0118] Specifically, the comparator 152 compares the ramp signal VR with the pixel signal VO starting from a specific time point (e.g., a time point when the comparator 152 is enabled), and may output the comparison result as a comparison signal to the counter 154. The counter 154 may count the comparison signal and convert the pixel signal VO into a digital signal OD.

[0119] On the other hand, if the pixel signal VO provided from the pixel PX is a high pixel signal VOH, the control signal generator 156 outputs a gain control signal CGCS of level H to turn on the DCG transistor GT. As a result, due to the influence of the capacitor C2, the capacitance of the floating diffusion portion FD increases, and the signal level of the pixel signal VO can be changed according to the change in the capacitance of the floating diffusion portion FD.

[0120] The drive transistor DT generates a pixel signal VO based on the charges stored in the floating diffusion FD (charges generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0121] The readout circuit 150 supplied with the pixel signal VO compares the supplied pixel signal VO with the third pulse P3 and converts the image signal of the pixel PX into a digital signal OD.

[0122] Specifically, the comparator 152 compares the ramp signal VR with the pixel signal VO starting from a specific time point (e.g., a time point when the comparator 152 is enabled), and may output the comparison result as a comparison signal to the counter 154. The counter 154 may count the comparison signal and convert the pixel signal VO into a digital signal OD.

[0123] Reference Figure 8 , the digital signal OD output from the readout circuit 150 at each sensing period 1H may include digital image data DID and conversion gain information GI.

[0124] The digital image data DID may be data generated, for example, based on the difference between the image signal of the pixel PX and the reset signal of the pixel PX, and the conversion gain information GI may be information indicating whether the digital image data DID is data generated with a low conversion gain or data generated with a high conversion gain.

[0125] The digital signal OD thus generated can be used as an image signal ( Figure 1The digital image data DID is provided to the image processor 900 outside the image sensor 100 in the form of the conversion gain information GI. The image processor 900 can determine the required processing for the digital image data DID based on the conversion gain information GI and perform the processing.

[0126] Figure 9 is a diagram for explaining effects of an image sensing device according to some example embodiments.

[0127] Reference Figure 8 and Figure 9 In the image sensing device according to this exemplary embodiment, by comparing the optical power of the sensed image with the ramp reference voltage REF during one sensing period 1H in which the selection signal SEL maintains a level H, the digital signal OD can be generated in gain modes different from each other.

[0128] If the optical power of the sensed image is lower than the ramp reference voltage REF, the digital signal OD is generated with a high conversion gain to maximize the sensing efficiency, as optical efficiency is more important than dynamic range. Conversely, if the optical power of the sensed image is higher than the ramp reference voltage REF, the digital signal OD is generated with a low conversion gain to maximize the dynamic range.

[0129] In some example embodiments, the high conversion gain or the low conversion gain is not determined based on an image of a previous frame or an image signal of another sensing cycle, and the operations of determining the high conversion gain or the low conversion gain and generating the digital signal OD are performed within one sensing cycle 1 H. Thus, high-speed operation of the image sensor can be achieved.

[0130] In the following, reference will be made to Figures 10 and 11 An image sensing device according to some example embodiments is described. Hereinafter, descriptions of configurations identical to those of the above-described example embodiments will be omitted, and differences will be mainly described.

[0131] Figure 10 is a block diagram of an image sensing device according to some example embodiments. Figure 11 yes Figure 10 Example circuit diagram of a timing controller.

[0132] Reference Figure 10 The readout circuit 150 of the image sensor 200 may further include timing controllers 158 ( j ), 158 ( j+1), and 158 ( j+2).

[0133] The timing controllers 158(j), 158(j+1), and 158(j+2) are provided with the first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) from the control signal generators 156(j), 156(j+1), and 156(j+2), and may provide the second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2) to the DCG transistors ( Figure 5 Depending on the signal levels of the second gain control signals CGCS2(j), CGCS2(j+1) and CGCS2(j+2), the DCG transistors ( Figure 5 The GT) can be turned on or off.

[0134] The timing controllers 158(j), 158(j+1), and 158(j+2) may adjust the timing of the first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) generated by the control signal generators 156(j), 156(j+1), and 156(j+2), and provide them to the DCG transistors ( Figure 5 That is, the first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) and the second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2) have the same signal levels as each other, but conversion timings of the signals may be different from each other.

[0135] Such timing controllers 158(j), 158(j+1) and 158(j+2) can be implemented in various forms. Figure 11 Examples of the timing controllers 158 ( j ), 158 ( j+1 ), and 158 ( j+2 ) are described.

[0136] Reference Figure 11 , the timing controller 158 may include a first switch 158 a , a storage unit 158 ​​b (eg, a capacitor), and a second switch 158 c .

[0137] The first switch 158 a is controlled by the first switching signal SW1 , and, for example, when the first switch 158 a is turned on, the gain control signal CGCS provided from the control signal generator 156 may be stored in the storage unit 158 ​​b .

[0138] The second switch 158c is controlled by the second switching signal SW2, and when the second switch 158c is turned on, the gain control signal CGCS stored in the storage unit 158b may be provided to, for example, the DCG transistor ( Figure 5GT).

[0139] Therefore, the gain control signal CGCS provided to the timing controller 158 may be provided to the outside after its timing is adjusted (eg, delayed).

[0140] Figure 12 is a timing diagram for explaining operations of an image sensing device according to some example embodiments. Hereinafter, descriptions of operations identical to those of the described example embodiments will be omitted, and differences will be mainly described.

[0141] Reference Figures 10 to 12 , while the control signal generator 156 generates the first gain control signal CGCS1 in the third section T3, the first switch signal SW1 changes to the H level, and the second switch signal SW2 maintains the L level. Therefore, the first gain control signal CGCS1 can be stored in the storage unit 158b of the timing controller 158. At this time, since the second switch 158c is in the off state, the first gain control signal CGCS1 is not provided to the DCG transistor ( Figure 5 GT).

[0142] Next, the first switching signal SW1 transitions to level L, and the second switching signal SW2 transitions to level H. As a result, the first gain control signal CGCS1 stored in the storage unit 158b of the timing controller 158 is supplied to the DCG transistor ( Figure 5 GT) as the second gain control signal CGCS2.

[0143] In this way, by adjusting the timing of generating the gain control signal CGCS and providing the gain control signal CGCS to the DCG transistor ( Figure 5 By separating the timings of GT) from each other, the negative feedback caused by the readout circuit 150 in the pixel PX can be reduced or prevented.

[0144] While the above description describes an example in which a unit sensing unit that generates and outputs a pixel signal corresponds to a single pixel PX in an image sensor, example embodiments are not limited thereto. Alternatively, the present inventive concept may be implemented in a form in which a unit sensing unit of an image sensor corresponds to a plurality of pixels PX. Hereinafter, some example embodiments will be described, but example embodiments are not limited thereto.

[0145] Figure 13 is an exemplary diagram for explaining a pixel array of an image sensing device according to example embodiments.

[0146] Reference Figure 13 , the pixel array of the image sensor 300 can be configured as a tetra pattern. Figure 13The tetra pattern is shown as having only sixteen filters in four rows and four columns, but for convenience, this only shows a portion of the filter area, and example embodiments are not limited thereto. That is, the number of filters in the tetra pattern can be applied as differently as possible.

[0147] The tetra pattern may include filters of three colors: red, green, and blue. That is, the R filter (R) may be a filter that transmits only red, the G filters (Gr and Gb) may be filters that transmit only green, and the B filter (B) may be a filter that transmits only blue.

[0148] In the tetra pattern, such as Figure 13 As shown, each of the R, G, and B filters R, Gb, Gr, and B may be arranged in a specific pattern. Figure 13 As shown, considering the visual characteristics of humans, the G filter may include a Gr filter (Gr) located next to the R filter (R) and a Gb filter (Gb) located next to the B filter (B).

[0149] A tetra pattern can be formed by forming a unit sensing cell in which each color filter (e.g., each of R, Gr, Gb, or B) is arranged in a 2×2 matrix. In the tetra pattern, since each of the same color filters (e.g., R, Gr, Gb, or B) is adjacent to each other, spatial similarity can be increased. As a result, noise associated with, for example, performing binning can be effectively reduced.

[0150] Figure 14 is a circuit diagram illustrating a pixel circuit of an image sensing device according to example embodiments.

[0151] refer to Figure 14 , in reference Figure 13 In the tetra pattern described, for example, four photoelectric elements PD1, PD2, PD3, and PD4 can share one floating diffusion FD. In addition, as shown in the figure, the four photoelectric elements PD1, PD2, PD3, and PD4 can also share a reset transistor RT, a drive transistor DT, and a select transistor ST.

[0152] When the transmission signal TG(i) becomes level H, the charge transfer transistor TG is turned on, and the photoelectric element PD1 can be connected to the floating diffusion portion FD. When the transmission signal TG(i+1) becomes level H, the charge transfer transistor TG is turned on, and the photoelectric element PD2 can be connected to the floating diffusion portion FD. When the transmission signal TG(i+2) becomes level H, the charge transfer transistor TG is turned on, and the photoelectric element PD3 can be connected to the floating diffusion portion FD. When the transmission signal TG(i+3) becomes level H, the charge transfer transistor TG is turned on, and the photoelectric element PD4 can be connected to the floating diffusion portion FD.

[0153] By adjusting the timing of the transmission signals TG(i), TG(i+1), TG(i+2) and TG(i+3), the conversion gain mode is determined for each unit sensing unit including the four photoelectric elements PD1, PD2, PD3 and PD4, and image data according to the determined conversion gain mode can be generated.

[0154] On the other hand, unlike the example embodiments described above, the sensor array of the image sensor can be implemented as follows: by modifying the sensor array of the image sensor so that N*N (N is a natural number of 3 or greater) pixels form a unit sensing unit with the same color filter, and an independent image signal is generated for each unit sensing unit.

[0155] Figure 15 1 is an exemplary diagram for explaining a pixel array of an image sensing device according to an example embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

[0156] Reference Figure 15 , the pixel circuit PC and the readout circuit ROC can be placed in each pixel of the image sensor 400.

[0157] Here, the pixel circuit PC placed in each pixel may include, for example Figure 5 The pixel circuit PX shown, and the readout circuit ROC may include Figure 6 The comparator circuit 152, the counter 154 and the control signal generator 156 are shown. Moreover, in some example embodiments, the readout circuit ROC may include Figure 10 A comparator 152 , a counter 154 , a control signal generator 156 and a timing controller 158 are shown.

[0158] In some example embodiments, since the readout circuit ROC is placed in each pixel, each pixel may output a digital signal OD instead of an analog signal. At this time, the digital signal OD output from each pixel may include the digital image data ( Figure 8 The conversion gain information corresponding to the DID) Figure 8 As a result, the digital signal OD output from each pixel may include different types of conversion gain information ( Figure 8 GI).

[0159] For example, when sensing an image of one frame, the pixel PX(a, b) may output conversion gain information ( Figure 8 GI) and digital image data sensed with low conversion gain ( Figure 8 The digital signal OD including the DID) of the pixel PX (c, d) can output the conversion gain information ( Figure 8 GI) and digital image data sensed with high conversion gain ( Figure 8 Digital signal OD including DID).

[0160] In some example embodiments, when the image sensor 400 includes an upper substrate and a lower substrate stacked on each other, the readout circuit ROC included in each pixel may be placed on the lower substrate, but example embodiments are not limited thereto.

[0161] Figure 16 is a block diagram of an electronic device including a multi-camera module. Figure 17 yes Figure 16 Detailed block diagram of the camera module.

[0162] Reference Figure 16 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0163] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the accompanying drawings illustrate an example in which three camera modules 1100a, 1100b, and 1100c are disposed, example embodiments are not limited thereto. In some example embodiments, the camera module group 1100 may be implemented by modifying the camera module group 1100 to include only two camera modules. Furthermore, in some example embodiments, the camera module group 1100 may be implemented by modifying the camera module group 1100 to include n (n is a natural number of 4 or greater) camera modules.

[0164] In the following, reference will be made to Figure 17 A detailed configuration of the camera module 1100 b is described in more detail, but the following description may also be similarly applied to other camera modules 1100 a and 1100 c according to example embodiments.

[0165] Reference Figure 17, the camera module 1100 b may include a prism 1105 , an optical path folding element (hereinafter referred to as “OPFE”) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage unit 1150 .

[0166] The prism 1105 can deform the path of light L incident from the outside by using the reflective surface 1107 including a light-reflecting material.

[0167] In some example embodiments, the prism 1105 may change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. Furthermore, the prism 1105 may rotate a reflective surface 1107 of the light-reflecting material in a direction A around a central axis 1106, or in a direction B around the central axis 1106, thereby changing the path of light L incident in the first direction X to a vertical second direction Y. In this case, the OPFE 1110 may also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0168] In some example embodiments, as shown in the figure, although the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and may be greater than 15 degrees in the negative (-) A direction, example embodiments are not limited thereto.

[0169] In some example embodiments, the prism 1105 may be movable by approximately 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees in the positive (+) or negative (-) B direction. Here, the moving angle may be movable by the same angle in the positive (+) or negative (-) B direction, or may be movable by an almost similar angle within a range of approximately 1 degree.

[0170] In some example embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, direction Z) parallel to the extension direction of the central axis 1106 .

[0171] The OPFE 1110 may include, for example, m (where m is a natural number) optical lenses. The m lenses may be moved in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is set to Z, if the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b may be changed to an optical zoom ratio of 3Z or 5Z or greater.

[0172] The actuator 1130 can move the OPFE 1110 or the optical lens (hereinafter collectively referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0173] The image sensing device 1140 may include an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. In some example embodiments, the image sensor 1142 may include at least one of the aforementioned image sensors 100, 200, 300, and 400.

[0174] The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

[0175] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 may include, for example, information regarding the degree of rotation, information regarding the focal length, information regarding the aforementioned optical axis, and the like. When the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 may include a focal length value for each position (or each state) of the optical lens, as well as information regarding autofocus.

[0176] The storage unit 1150 may store image data sensed by the image sensor 1142. The storage unit 1150 may be placed outside the image sensing device 1140 and may be implemented in a form stacked with a sensor chip constituting the image sensing device 1140. In some example embodiments, although the storage unit 1150 may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), example embodiments are not limited thereto.

[0177] Reference together Figure 16 and Figure 17 In some example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 depending on the operation of the actuator 1130 included therein.

[0178] In some example embodiments, one camera module (e.g., 1100b) among the multiple camera modules 1100a, 1100b, and 1100c may be a folded lens camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a and 1100c) may be vertical camera modules that do not include the prism 1105 and OPFE 1110, but example embodiments are not limited thereto.

[0179] In some example embodiments, one camera module (e.g., 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c may be, for example, a vertical depth camera that extracts depth information using IR (infrared rays). In some example embodiments, the application processor 1200 may combine image data provided from such a depth camera with image data provided from other camera modules (e.g., 1100a or 1100b) to generate a 3D depth image.

[0180] In some example embodiments, at least two camera modules (e.g., 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view from each other. In some example embodiments, although the optical lenses of at least two camera modules (e.g., 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, example embodiments are not limited thereto.

[0181] Furthermore, in some example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may have a different field of view from each other. In some example embodiments, the optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different from each other, but example embodiments are not limited thereto.

[0182] In some example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be physically separated from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c do not divide and use the sensing area of ​​one image sensor 1142, but an independent image sensor 1142 may be placed inside each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0183] Reference again Figure 16, the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented separately using separate semiconductor chips.

[0184] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , and 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0185] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , and 1212 c corresponding to the number of camera modules 1100 a , 1100 b , and 1100 c .

[0186] Image data generated from each of the camera modules 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c via image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated from the camera module 1100a can be provided to the sub-image processor 1212a via the image signal line ISLa, the image data generated from the camera module 1100b can be provided to the sub-image processor 1212b via the image signal line ISLb, and the image data generated from the camera module 1100c can be provided to the sub-image processor 1212c via the image signal line ISLc. Although such image data transmission can be performed using, for example, a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), example embodiments are not limited thereto.

[0187] In some example embodiments, the image data generated from each of the camera modules 1100a, 1100b, and 1100c may include the conversion gain information ( Figure 8 This conversion gain information ( Figure 8 The GI) is provided to the sub-image processors 1212a, 1212b and 1212c or the image generator 1214 and used for image processing.

[0188] In some example embodiments, each of the camera modules 1100a, 1100b, and 1100c may generate a first image signal and a second image signal forming one frame of image, provide the first image signal including the first conversion gain information to the sub-image processors 1212a, 1212b, and 1212c or the image generator 1214, and provide the second image signal including second conversion gain information different from the first conversion gain information to the sub-image processors 1212a, 1212b, and 1212c or the image generator 1214. That is, the first image signal and the second image signal forming one frame of image may include different types of conversion gain information from each other.

[0189] The sub-image processors 1212a, 1212b, and 1212c or the image generator 1214 may perform first image processing using first conversion gain information included in the first image signal, and may perform second image processing using second conversion gain information included in the second image signal.

[0190] Meanwhile, in some exemplary embodiments, one sub-image processor may be positioned to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are not implemented separately as shown in the figure, but may be combined and implemented as one sub-image processor, and the image data provided from the camera modules 1100a and 1100c may be provided to the combined sub-image processor after being selected by a selection element (e.g., a multiplexer).

[0191] The image data provided to the corresponding sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c according to image generation information or a mode signal.

[0192] Specifically, the image generator 1214 may combine at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view based on the image generation information or the mode signal to generate an output image. Furthermore, the image generator 1214 may select any one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view based on the image generation information or the mode signal to generate an output image.

[0193] In some example embodiments, the image generation information may include a zoom signal (or a zoom factor).Also, in some example embodiments, the mode signal may be a signal based on a mode selected from a user, for example.

[0194] When the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has a different field of view (angle of view), the image generator 1214 may perform different operations depending on the type of the zoom signal. For example, when the zoom signal is a first signal, after combining the image data output from the camera module 1100a and the image data output from the camera module 1100c, the output image may be generated using the combined image signal and the image data output from the camera module 1100b that is not used for the combination. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not combine the image data and may select any one of the image data output from each of the camera modules 1100a, 1100b, and 1100c to generate the output image. However, example embodiments are not limited thereto, and the method of processing image data may be modified and implemented as needed.

[0195] In some example embodiments, the image generator 1214 receives image data of different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and performs HDR (high dynamic range) processing on the plurality of image data, thereby generating combined image data with an increased dynamic range.

[0196] The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. The control signal generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

[0197] According to image generation information including a zoom signal or a mode signal, any one of the plurality of camera modules 1100a, 1100b, and 1100c is designated as a master camera (e.g., 1100b), and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. Such information is included in a control signal and can be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

[0198] Depending on the zoom factor or mode signal, the camera module that serves as the master camera or the slave camera can be changed. For example, when the viewing angle of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b can operate as the master camera and camera module 1100a can operate as the slave camera. Conversely, when the zoom factor indicates a high zoom ratio, camera module 1100a can operate as the master camera and camera module 1100b can operate as the slave camera.

[0199] In some example embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is the master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit the synchronization enable signal to the camera module 1100b. The camera module 1100b, upon receiving the synchronization enable signal, generates a synchronization signal based on the synchronization enable signal and may provide the generated synchronization signal to the camera modules 1100a and 1100c via a synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may transmit image data to the application processor 1200 in synchronization with the synchronization signal.

[0200] In some example embodiments, the control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode with respect to the sensing speed.

[0201] In a first operating mode, the plurality of camera modules 1100a, 1100b, and 1100c generate image signals at a first speed (e.g., generate image signals at a first frame rate), encode the image signals at a second speed higher than the first speed (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second speed may be equal to or less than 30 times the first speed.

[0202] The application processor 1200 stores the received image signal (i.e., the encoded image signal) in the internal memory 1230 provided within the application processor 1200 or in the external memory 1400 provided outside the application processor 1200. Thereafter, the application processor 1200 can read and decode the encoded image signal from the internal memory 1230 or the external memory 1400 and can display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the multiple sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 can perform decoding and can perform image processing on the decoded image signal.

[0203] In the second operating mode, the plurality of camera modules 1100a, 1100b, and 1100c generate image signals at a third speed lower than the first speed (e.g., generate image signals at a third frame rate lower than the first frame rate), and may transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be unencoded signals. The application processor 1200 may perform image processing on the received image signals, or may store the image signals in the internal memory 1230 or the external memory 1400.

[0204] The PMIC 1300 may provide power, such as a power supply, to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may provide a first power to the camera module 1100a via a power signal line PSLa, provide a second power to the camera module 1100b via a power signal line PSLb, and provide a third power to the camera module 1100c via a power signal line PSLc.

[0205] The PMIC 1300 responds to the power control signal PCON from the application processor 1200 to generate power corresponding to each of the multiple camera modules 1100a, 1100b, and 1100c, and can adjust the power level. The power control signal PCON may include a power adjustment signal for each operating mode of the multiple camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, and in this case, the power control signal PCON may include information about the camera module operating in the low power mode and the power level to be set. The power level supplied to each of the multiple camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Similarly, the power level can be dynamically changed.

[0206] In an example embodiment, Figure 1 and / or Figure 6The image sensor 100 (eg, the control register block 110, the timing generator 120, the row driver 130, the ramp signal generator 160) and / or the image processor 900, Figure 16 and Figure 17 Features of the electronic device 1000 (e.g., the application processor 1200, the sub-image processors 1212a to 1212c of the image processing device 1210 and the camera module controller 1216, the storage controller 1220, the internal memory 1230, the actuator 1130, the control logic 1144, the image sensor 1142, the memory 1146, etc.) may include: processing circuits, such as hardware including logic circuits; hardware / software combinations, such as a processor that executes software; memory; or combinations thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The memory may include a nonvolatile memory such as a flash memory, a phase-change random access memory (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM), or a volatile memory such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory), but example embodiments are not limited thereto.

[0207] While the present disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. An image sensing device comprising: A pixel circuit includes a floating diffusion portion, a photoelectric element, a drive transistor, a dual conversion gain DCG transistor, a selection transistor, and a column line connected to the selection transistor. The floating diffusion is a region in the pixel circuit. The floating diffusion is configured to store charges generated by the photoelectric element, The driving transistor is configured to generate a pixel signal based on the charge stored in the floating diffusion, The selection transistor is configured to output the pixel signal generated by the drive transistor to the column line in response to the selection transistor receiving a selection signal. The selection transistor is configured to output a first pixel signal to the column line based on the charge stored in the floating diffusion when the DCG transistor is turned off. The DCG transistor is configured to change the capacitance of the floating diffusion in response to the DCG transistor receiving a gain control signal, and The pixel circuit is configured to perform an operation in which the selection transistor outputs the first pixel signal to the column line and the DCG transistor receives the gain control signal during a period in which the selection transistor receives a selection signal maintained at a first level. The image sensing device further includes a readout circuit configured to receive the first pixel signal from the pixel circuit, generate the gain control signal based on a comparison of the first pixel signal and a ramp signal, and provide the gain control signal to the pixel circuit.

2. The image sensing device according to claim 1, wherein The pixel circuit further includes a reset transistor and a capacitor, The reset transistor is configured to provide a reset voltage to the floating diffusion in response to a reset signal. The capacitor is connected between the reset transistor and the DCG transistor, and The DCG transistor is configured to change a capacitance of the floating diffusion using the capacitor.

3. The image sensing device according to claim 2, wherein: The capacitance of the capacitor is greater than the capacitance of the floating diffusion.

4. The image sensing device according to claim 2, wherein: The reset transistor and the DCG transistor are configured to be turned on simultaneously in response to the reset signal.

5. The image sensing device according to claim 2, wherein The pixel circuit further includes an OR gate, and The OR gate is configured to receive the gain control signal and the reset signal, perform an OR operation based on the gain control signal and the reset signal, and provide a result of the OR operation to the DCG transistor. The image sensing device according to claim 1 , wherein The pixel circuit further includes a charge transfer transistor configured to provide the charge generated by the photoelectric element to the floating diffusion portion in response to a transmission signal. The photoelectric element includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that are separated from each other, and The charge transfer transistors include a first charge transfer transistor, a second charge transfer transistor, a third charge transfer transistor and a fourth charge transfer transistor, The first charge transfer transistor is connected to the first photoelectric element and the floating diffusion. the second charge transfer transistor being connected to the second photoelectric element and the floating diffusion; The third charge transfer transistor is connected to the third photoelectric element and the floating diffusion, and The fourth charge transfer transistor is connected to the fourth photoelectric element and the floating diffusion.

7. An image sensing device comprising: a pixel circuit configured to output a pixel signal in response to a selection signal; a readout circuit configured to output a digital signal corresponding to a pixel signal supplied from the pixel circuit, The readout circuit is configured to receive a first pixel signal from the pixel circuit, generate a gain control signal based on a comparison of the first pixel signal and a ramp signal, and provide the gain control signal to the pixel circuit, The readout circuit is configured to receive a second pixel signal output by the pixel circuit using the gain control signal and output a digital signal corresponding to the second pixel signal; as well as The row driver is configured to provide the selection signal to the pixel circuit while maintaining the selection signal at a first level during an operation in which the readout circuit provides the gain control signal to the pixel circuit and an operation in which the pixel circuit outputs the second pixel signal to the readout circuit.

8. The image sensing device according to claim 7, wherein The readout circuit includes a comparator and a control signal generator, The comparator is configured to output a comparison signal based on a comparison between the ramp signal and the first pixel signal, The control signal generator is configured to generate the gain control signal based on the comparison signal.

9. The image sensing device according to claim 8, wherein The readout circuit further includes a timing controller, The timing controller is configured to receive a first gain control signal generated by the control signal generator, and The timing controller is configured to provide the pixel circuit with a second gain control signal generated by adjusting the timing of the first gain control signal.

10. The image sensing device according to claim 9, wherein The timing controller includes a storage unit, a first switch and a second switch. The storage unit is configured to store the first gain control signal by turning on the first switch to provide a stored first gain control signal, and The timing controller is configured to output the stored first gain control signal as the second gain control signal by turning on the second switch.

11. The image sensing device according to claim 7, wherein The digital signal corresponding to the second pixel signal includes conversion gain information corresponding to the gain control signal generated based on the first pixel signal.

12. The image sensing device according to claim 11, further comprising: A pixel array comprising a plurality of pixels, wherein The plurality of pixels include a first pixel and a second pixel, The first pixel is configured to output a third pixel signal, The second pixel is configured to output a fourth pixel signal, The third pixel signal and the fourth pixel signal constitute an image of the same frame, the readout circuit being configured to output a first digital signal corresponding to the third pixel signal and to output a second digital signal corresponding to the fourth pixel signal; and The first digital signal and the second digital signal include different types of conversion gain information from each other.

13. The image sensing device according to claim 7, further comprising: A pixel array comprising a plurality of pixels, wherein Each pixel of the pixel array includes the pixel circuitry and the readout circuitry.

14. An image sensing device comprising: a pixel circuit configured to output a pixel signal in response to a selection signal; a row driver configured to generate the selection signal and provide the selection signal to the pixel circuit; a ramp signal generator configured to generate a ramp signal; as well as a readout circuit configured to receive the pixel signal from the pixel circuit, generate a gain control signal based on comparing the pixel signal with a ramp signal provided from the ramp signal generator, provide the gain control signal to the pixel circuit, and output a digital signal corresponding to the pixel signal, The ramp signal generator is configured to provide the ramp signal to the readout circuit, The ramp signal includes a first pulse falling from a reference voltage to a first level, a second pulse falling from the reference voltage to a second level different from the first level, and a third pulse falling from the reference voltage to a third level different from the second level, and The ramp signal generator is configured to provide the first pulse, the second pulse, and the third pulse to the readout circuit while the row driver provides the selection signal to the pixel circuit and maintains the selection signal at a first level.

15. The image sensing device according to claim 14, wherein The first level is less than the second level, and The second level is lower than the third level.

16. The image sensing device according to claim 14, wherein The readout circuit includes a comparator and a control signal generator, The comparator is configured to output a comparison signal based on a comparison between the ramp signal and the pixel signal, The control signal generator is configured to generate a gain control signal based on the comparison signal and provide the gain control signal to the pixel circuit, and The control signal generator is configured to generate the gain control signal based on a comparison result of the pixel signal and the second pulse.

17. The image sensing device according to claim 16, wherein the pixel circuit comprises: Optoelectronic components, a floating diffusion configured to store charges generated by the photoelectric element, the floating diffusion being a region in the pixel circuit; a reset transistor configured to provide a reset voltage to the floating diffusion in response to a reset signal, capacitor, connected to the reset transistor, a dual conversion gain DCG transistor connected to the capacitor, the DCG transistor being configured to change the capacitance of the floating diffusion using the capacitance of the capacitor in response to the gain control signal, a driving transistor configured to generate the pixel signal based on the charge stored in the floating diffusion, and A selection transistor is configured to output the pixel signal generated by the drive transistor to the readout circuit in response to the selection signal.

18. The image sensing device according to claim 14, wherein The first pulse drops from the reference voltage to a ramp reset voltage, The second pulse falls from the reference voltage to a ramp reference voltage, The third pulse drops from the reference voltage to the ramp signal voltage, and The second pulse has a sustain portion in which the ramp reference voltage is maintained for a specific time.

19. The image sensing device according to claim 18, wherein The readout circuit includes a comparator, a control signal generator and a timing controller, The comparator is configured to output a comparison signal based on a comparison between the ramp signal and the pixel signal, The control signal generator is configured to generate a first gain control signal based on the comparison signal, The timing controller is configured to receive a first gain control signal generated by the control signal generator, generate a second gain control signal by adjusting a timing of the first gain control signal during the sustain section, and provide the second gain control signal to the pixel circuit.

20. The image sensing device according to claim 19, wherein The timing controller includes a first switch, a storage unit, and a second switch connected in series. The storage unit is configured to store the first gain control signal at a first time point in the maintaining section when the first switch is turned on and the second switch is turned off, and The timing controller is configured to provide a second gain control signal based on the first gain control signal stored in the storage unit at a second time point after the first time point of the sustaining section when the first switch is turned off and the second switch is turned on.

21. The image sensing device according to claim 14, wherein The readout circuit is configured to output a digital signal corresponding to the pixel signal based on comparing the pixel signal with a ramp signal provided from the ramp signal generator.

Images