camera device

Abstract

A first imaging device according to an embodiment of the present application includes a first substrate, a second substrate, and a through wiring. The first substrate includes a photoelectric conversion section and a first transistor for constituting a sensor pixel provided in a first semiconductor substrate. The second substrate is layered on the first substrate and includes a second transistor for constituting the sensor pixel provided in a second semiconductor substrate having one surface opposite to the first substrate and an opening penetrating the second semiconductor substrate in a layer direction. The second substrate has an adjustment section for adjusting a threshold voltage of the second transistor, the adjustment section being formed on a side surface of the opening located in a vicinity of a gate of the second transistor and / or on a region of the one surface of the second semiconductor substrate opposite to the first transistor. The through wiring is provided in the opening for electrically connecting the first substrate and the second substrate.

Description

Technical Field

[0001] This invention relates to a camera device with a three-dimensional structure. Background Technology

[0002] In the past, miniaturization of the area of ​​each pixel in two-dimensional camera devices has been achieved due to the introduction of miniaturization processes and increased mounting density. In recent years, to achieve even greater miniaturization of camera devices and higher pixel density, three-dimensional camera devices have been developed. In a three-dimensional camera device, for example, a semiconductor substrate including multiple sensor pixels and a semiconductor substrate including signal processing circuitry are stacked. The signal processing circuitry processes the signals obtained using each sensor pixel.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-245506 Summary of the Invention

[0006] Incidentally, higher image quality is expected for camera devices with three-dimensional structures.

[0007] People expect to be able to provide a camera device that can improve image quality.

[0008] A first imaging device according to an embodiment of the present invention includes a first substrate, a second substrate, and a through wiring. The first substrate includes a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor constituting a sensor pixel. A second substrate is stacked on the first substrate. The second substrate includes a second transistor and an opening disposed in a second semiconductor substrate having a surface opposite to the first substrate. The second transistor constituting the sensor pixel. The opening penetrates the second semiconductor substrate in the stacking direction. The second substrate has an adjustment portion for adjusting the threshold voltage of the second transistor, the adjustment portion being formed on a side of the opening near the gate of the second transistor and / or on the region of the one surface of the second semiconductor substrate opposite to the first transistor. The through wiring is disposed within the opening. The through wiring electrically connects the first substrate and the second substrate.

[0009] A second imaging device according to an embodiment of the present invention includes a first substrate, a second substrate, a through wiring, and a second transistor. The first substrate includes a photoelectric conversion portion and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion portion and the first transistor constituting a sensor pixel. The second substrate is stacked on the first substrate. The second substrate has an opening disposed in the second semiconductor substrate, the opening penetrating the second semiconductor substrate in the stacking direction, and the opening is filled with an insulating film. The through wiring penetrates the insulating film. The through wiring electrically connects the first substrate and the second substrate. The second transistor in the second semiconductor substrate constituting the sensor pixel. The second transistor includes a gate, at least one end of the gate adjacent to the through wiring being embedded in the insulating film.

[0010] A third imaging device according to an embodiment of the present invention includes a first substrate, a second substrate, and a through wiring. The first substrate includes a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor constituting a sensor pixel. The second substrate is stacked on the first substrate. The second substrate includes a second transistor disposed in a second semiconductor substrate and an opening, the second transistor constituting the sensor pixel, the opening penetrating the second semiconductor substrate in the stacking direction. The through wiring is disposed within the opening. The through wiring electrically connects the first substrate and the second substrate. The through wiring has a second center line at a position different from a first center line in a plan view, the first center line equally dividing the gate of the second transistor along its extension direction, and the second center line equally dividing the through wiring in the same direction as the first center line.

[0011] In a first imaging device according to an embodiment of the present invention, an adjustment portion for adjusting the threshold voltage of the second transistor is provided on the side of the opening near the gate of the second transistor and / or in the region of the second semiconductor substrate opposite to the first transistor. In a second imaging device according to an embodiment of the present invention, the end of the gate of the second transistor disposed in the second semiconductor substrate adjacent to the through wiring for electrically connecting the first substrate and the second substrate is embedded in the insulating film filling the opening, the opening penetrating the second semiconductor substrate, and the through wiring penetrating the opening. In a third imaging device according to an embodiment of the present invention, the opening is provided through the second semiconductor substrate, and the through wiring penetrating the opening in the stacking direction and for electrically connecting the first substrate and the second substrate is provided at a position offset from the center line that equally divides the gate of the second transistor disposed in the second semiconductor substrate along the extension direction. This reduces the influence of the electric field of the through wiring on the adjacent second transistor and the influence of the electric field of the first transistor on the adjacent second transistor. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example of the functional structure of a camera device according to a first embodiment of the present invention.

[0013] Figure 2 It shows Figure 1 A schematic plan view of the general structure of the camera device shown.

[0014] Figure 3 It shows along Figure 2 A schematic diagram of the cross-sectional structure taken from line III-III′ is shown.

[0015] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0016] Figure 5 This is a diagram illustrating an example of the connection pattern between multiple pixel shared units and multiple vertical signal lines.

[0017] Figure 6 It shows Figure 3 A cross-sectional schematic diagram illustrating an example of the specific construction of the camera device shown.

[0018] Figure 7A It shows Figure 6 A schematic diagram illustrating an example of the planar structure of the main portion of the first substrate.

[0019] Figure 7BIt shows Figure 7A A schematic diagram of the planar structure of the main part of the first substrate plus the pad portion.

[0020] Figure 8 It shows Figure 6 A schematic diagram of an example of a planar structure of the second substrate (semiconductor layer).

[0021] Figure 9 It shows Figure 6 The diagram shows an example of a planar structure of the first wiring layer plus the pixel circuitry and the main part of the first substrate.

[0022] Figure 10 It shows Figure 6 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0023] Figure 11 It shows Figure 6 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0024] Figure 12 It shows Figure 6 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0025] Figure 13 It is used for explanation Figure 1 A three-dimensional diagram showing the structure of the main parts of the camera device.

[0026] Figure 14A It shows along Figure 13 A schematic diagram of the cross-section structure taken from line II in the diagram.

[0027] Figure 14B It shows along Figure 13 A schematic diagram of the cross-section structure taken from line II-II.

[0028] Figure 15A This diagram illustrates the change in pixel transistor characteristics due to whether or not a bias voltage is applied to the through wiring, serving as a comparative example.

[0029] Figure 15B It is used to illustrate that in having Figure 14A The diagram shows the characteristic changes of the pixel transistors in the semiconductor device with the shown structure due to whether or not a bias voltage is applied to the through wiring.

[0030] Figure 16A It is used for explanation Figure 14A A cross-sectional schematic diagram illustrating an example of the manufacturing steps for the adjustment section.

[0031] Figure 16B It shows Figure 16A A cross-sectional diagram of the subsequent steps.

[0032] Figure 16C It shows Figure 16B A cross-sectional diagram of the subsequent steps.

[0033] Figure 16D It shows Figure 16C A cross-sectional diagram of the subsequent steps.

[0034] Figure 16E It shows Figure 16D A cross-sectional diagram of the subsequent steps.

[0035] Figure 16F It shows Figure 16E A cross-sectional diagram of the subsequent steps.

[0036] Figure 17A It is used for explanation Figure 14A A cross-sectional schematic diagram of another example of the manufacturing steps of the adjustment part shown.

[0037] Figure 17B It is used for explanation Figure 17A A cross-sectional diagram of the subsequent steps.

[0038] Figure 18 It is used to describe the input signal to Figure 3 A schematic diagram of the path of the camera device shown.

[0039] Figure 19 It is used for explanation Figure 3 A schematic diagram of the signal path of the pixel signal of the camera device shown.

[0040] Figure 20A This is a schematic diagram showing the cross-sectional structure of the main part of the camera device according to a modified example 1 of the present invention.

[0041] Figure 20B It shows Figure 20A A schematic diagram of another cross-sectional structure of the camera device shown.

[0042] Figure 21 It shows Figure 20A The diagram shows a planar structure of the camera device in the horizontal direction.

[0043] Figure 22A It is used for explanation Figure 20A A cross-sectional schematic diagram illustrating an example of the manufacturing steps of the camera device.

[0044] Figure 22B It shows Figure 22A A cross-sectional diagram of the subsequent steps.

[0045] Figure 23A It is used for explanation Figure 20A A cross-sectional schematic diagram of another example of the manufacturing steps of the camera device shown.

[0046] Figure 23B It shows Figure 23A A schematic diagram of the subsequent construction.

[0047] Figure 23C It shows Figure 23B A cross-sectional diagram of the subsequent steps.

[0048] Figure 23D It shows Figure 23C A cross-sectional diagram of the subsequent steps.

[0049] Figure 23E It shows Figure 23C A plan view of the subsequent steps.

[0050] Figure 24 This is a schematic diagram illustrating an example of the cross-sectional structure of the main part of the camera device according to a second embodiment of the present invention.

[0051] Figure 25 It shows Figure 24 The diagram shows a schematic of the planar shape of the selection transistor.

[0052] Figure 26 This is a schematic diagram showing another example of the cross-sectional structure of the main part of the camera device according to a second embodiment of the present invention.

[0053] Figure 27 It shows Figure 26 A cross-sectional schematic diagram of a specific example of the gate shape shown.

[0054] Figure 28 It shows Figure 26 A cross-sectional schematic diagram of a specific example of the gate shape shown.

[0055] Figure 29 It shows Figure 26 A cross-sectional schematic diagram of a specific example of the gate shape shown.

[0056] Figure 30 It shows Figure 26 A cross-sectional schematic diagram of a specific example of the gate shape shown.

[0057] Figure 31A It is used for explanation Figure 24 A cross-sectional schematic diagram illustrating an example of the manufacturing steps of the camera device.

[0058] Figure 31B It shows Figure 31A A cross-sectional diagram of the subsequent steps.

[0059] Figure 31C It shows Figure 31B A cross-sectional diagram of the subsequent steps.

[0060] Figure 31D It shows Figure 31C A cross-sectional diagram of the subsequent steps.

[0061] Figure 31E It shows Figure 31D A cross-sectional diagram of the subsequent steps.

[0062] Figure 31F It shows Figure 31E A cross-sectional diagram of the subsequent steps.

[0063] Figure 32A It is used for explanation Figure 26 A cross-sectional schematic diagram illustrating an example of the manufacturing steps of the camera device.

[0064] Figure 32B It shows Figure 32A A cross-sectional diagram of the subsequent steps.

[0065] Figure 32C It shows Figure 32B A cross-sectional diagram of the subsequent steps.

[0066] Figure 32D It shows Figure 32C A cross-sectional diagram of the subsequent steps.

[0067] Figure 32E It shows Figure 32D A cross-sectional diagram of the subsequent steps.

[0068] Figure 33A It is used for explanation Figure 26 A cross-sectional schematic diagram of another example of the manufacturing steps of the camera device shown.

[0069] Figure 33B It shows Figure 33A A cross-sectional diagram of the subsequent steps.

[0070] Figure 33C It shows Figure 33B A cross-sectional diagram of the subsequent steps.

[0071] Figure 33D It shows Figure 33C A cross-sectional diagram of the subsequent steps.

[0072] Figure 33E It shows Figure 33D A cross-sectional diagram of the subsequent steps.

[0073] Figure 33F It shows Figure 33E A cross-sectional diagram of the subsequent steps.

[0074] Figure 34 This is a planar schematic diagram illustrating the active region of a pixel transistor in the context of mitigating the effects of through wiring through ion implantation.

[0075] Figure 35 This is a schematic diagram illustrating an example of the planar structure of the main part of the camera device according to a third embodiment of the present invention.

[0076] Figure 36 yes Figure 35 A schematic cross-sectional view of the planar camera device shown.

[0077] Figure 37 This is a schematic diagram illustrating another example of the planar structure of the main part of the camera device according to a third embodiment of the present invention.

[0078] Figure 38 yes Figure 37 A schematic cross-sectional view of the planar camera device shown.

[0079] Figure 39 This is a characteristic graph showing the relationship between the distance between the through wiring and the gate and the threshold voltage of the pixel transistor.

[0080] Figure 40 This is a characteristic diagram showing the relationship between the offset of the through-wire center relative to the gate center and the threshold voltage of the pixel transistor.

[0081] Figure 41 It is a plan view used to illustrate the location of the through wiring.

[0082] Figure 42 It shows Figure 8 A schematic diagram of a modified example of the planar structure of the second substrate (semiconductor layer) shown.

[0083] Figure 43 It shows Figure 42 The diagram shows a planar structure of the pixel circuit plus the main part of the first wiring layer and the first substrate.

[0084] Figure 44 It shows Figure 43 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0085] Figure 45 It shows Figure 44A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0086] Figure 46 It shows Figure 45 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0087] Figure 47 It shows Figure 7A A schematic diagram of a modified example of the planar structure of the first substrate shown.

[0088] Figure 48 It shows the layering in Figure 47 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0089] Figure 49 It shows Figure 48 The diagram shows an example of a planar structure for a pixel circuit plus a first wiring layer.

[0090] Figure 50 It shows Figure 49 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0091] Figure 51 It shows Figure 50 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0092] Figure 52 It shows Figure 51 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0093] Figure 53 It shows Figure 47 A schematic diagram of another example of the planar structure of the first substrate shown.

[0094] Figure 54 It shows the layering in Figure 53 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0095] Figure 55 It shows Figure 54 The diagram shows an example of a planar structure for a pixel circuit plus a first wiring layer.

[0096] Figure 56 It shows Figure 55 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0097] Figure 57It shows Figure 56 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0098] Figure 58 It shows Figure 57 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0099] Figure 59 It shows Figure 3 A cross-sectional schematic diagram of another example of the camera device shown.

[0100] Figure 60 It is used to describe the input signal to Figure 59 A schematic diagram of the path of the camera device shown.

[0101] Figure 61 It is used for explanation Figure 59 A schematic diagram of the signal path of the pixel signal of the camera device shown.

[0102] Figure 62 It shows Figure 6 A cross-sectional schematic diagram of another example of the camera device shown.

[0103] Figure 63 It shows Figure 4 A diagram of another example of the equivalent circuit shown.

[0104] Figure 64 It shows Figure 7A A planar schematic diagram of another example of the pixel separation section shown.

[0105] Figure 65 This is a cross-sectional view in the thickness direction showing a construction example of a camera device according to a variation 9 of the present invention.

[0106] Figure 66 This is a cross-sectional view in the thickness direction showing a construction example of a camera device according to a variation 9 of the present invention.

[0107] Figure 67 This is a cross-sectional view in the thickness direction showing a construction example of a camera device according to a variation 9 of the present invention.

[0108] Figure 68 This is a cross-sectional view in the horizontal direction showing an example of the layout of multiple pixel units according to a variation 9 of the present invention.

[0109] Figure 69 This is a cross-sectional view in the horizontal direction showing an example of the layout of multiple pixel units according to a variation 9 of the present invention.

[0110] Figure 70This is a cross-sectional view in the horizontal direction showing an example of the layout of multiple pixel units according to a variation 9 of the present invention.

[0111] Figure 71 This is a diagram illustrating an example of a schematic structure of a camera system equipped with a camera device according to any of the above embodiments and variations.

[0112] Figure 72 It shows Figure 71 A diagram illustrating an example of the recording process of the camera system shown.

[0113] Figure 73 This is a block diagram illustrating an example of a schematic structure of a vehicle control system.

[0114] Figure 74 This is an example diagram used to illustrate the installation locations of the vehicle exterior information detection unit and the camera unit.

[0115] Figure 75 This is a diagram illustrating an example of the general structure of an endoscopic surgical system.

[0116] Figure 76 This is a block diagram illustrating an example of the functional structure of a camera head and a camera control unit (CCU). Detailed Implementation

[0117] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The following description illustrates specific examples of the invention, but the invention is not limited to the following model. Furthermore, the invention is not limited to the arrangement, dimensions, or aspect ratios of the constituent elements shown in the various drawings. It should be noted that the description is given in the following order.

[0118] 1. First embodiment (an example having a stacked structure of three substrates, wherein adjustment portions are provided on the side of the second semiconductor substrate on which a channel of a pixel transistor adjacent to a through wiring is formed, and on the back side of the second substrate opposite to the transistor disposed in the first substrate)

[0119] 2. Modified Example 1 (Another example of the manufacturing method of the adjusting part)

[0120] 3. Second embodiment (example in which the end of the gate of the pixel transistor adjacent to the through wiring is buried in the component separation region)

[0121] 4. Third embodiment (regarding the positional relationship between pixel transistors and through wiring)

[0122] 5. Variation Example 2 (Example 1 of planar construction)

[0123] 6. Variation Example 3 (Example 2 of planar construction)

[0124] 7. Variation Example 4 (Example 3 of planar construction)

[0125] 8. Modification 5 (Example of a central portion of the pixel array having a junction between substrates)

[0126] 9. Variation 6 (including an example of a planar transmission transistor)

[0127] 10. Variation Example 7 (Example of a pixel connected to a pixel circuit)

[0128] 11. Variation Example 8 (Structure Example of Pixel Separation Section)

[0129] 12. Variation 9 (Example of setting up a trap wiring for each plurality of sensor pixels)

[0130] 13. Application Example (Camera System)

[0131] 14. Application Examples

[0132] <1. First Embodiment>

[0133] [Functional Structure of the Camera Device]

[0134] Figure 1 This is a block diagram illustrating an example of the functional structure of a camera device (camera device 1) according to a first embodiment of the present invention.

[0135] For example, Figure 1 The camera device 1 includes an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0136] In the pixel array section 540, pixels 541 are arranged repeatedly in an array. More specifically, pixel sharing units 539, comprising multiple pixels, are repeated units. These pixel sharing units 539 are arranged repeatedly in an array having a row direction and a column direction. It should be noted that, for convenience, this specification sometimes refers to the row direction as the H direction and the column direction, which is orthogonal to the row direction, as the V direction. Figure 1 In the example, a pixel shared unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of pixels 541A, 541B, 541C, and 541D includes a photodiode PD (described below). Figure 6 (as shown below). Pixel sharing unit 539 shares a single pixel circuit (described below). Figure 4The pixel array 540 is a unit of pixel circuit 210. In other words, every four pixels (pixels 541A, 541B, 541C, and 541D) includes one pixel circuit (pixel circuit 210 as described below). By operating the pixel circuit in a time-division manner, the pixel signals of each of the pixels 541A, 541B, 541C, and 541D are read out sequentially. For example, pixels 541A, 541B, 541C, and 541D are arranged in two rows × two columns. In addition to pixels 541A, 541B, 541C, and 541D, the pixel array 540 also includes multiple row drive signal lines 542 and multiple vertical signal lines (column readout lines) 543. Each row drive signal line 542 drives the pixels 541 included in each of the multiple pixel sharing units 539 arranged in the row direction in the pixel array 540. The individual pixels arranged in the row direction in the pixel sharing unit 539 are driven. (See below for further details.) Figure 4 In detail, the pixel sharing unit 539 is provided with multiple transistors. To drive these multiple transistors respectively, multiple row drive signal lines 542 are provided for each pixel sharing unit 539. The pixel sharing unit 539 is connected to vertical signal lines (column readout lines) 543. Pixel signals are read from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal lines (column readout lines) 543.

[0137] For example, the row driving unit 520 includes: a row address control unit or a row decoder unit that determines the row position of the driven pixel; and a row driving circuit unit that generates signals for driving pixels 541A, 541B, 541C and 541D.

[0138] For example, the column signal processing unit 550 is connected to the vertical signal line 543. The column signal processing unit 550 includes a load circuit section that forms a source follower circuit together with pixels 541A, 541B, 541C, and 541D (pixel shared unit 539). The column signal processing unit 550 may include an amplification circuit section that amplifies the signal read from the pixel shared unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing section. For example, in the noise processing section, the system noise level is removed, for example, from the signal read from the pixel shared unit 539 as a result of photoelectric conversion.

[0139] For example, the column signal processing unit 550 includes an analog-to-digital converter (ADC). In the ADC, the signal read from the pixel sharing unit 539 or the analog signal after the aforementioned noise processing is converted into a digital signal. For example, the ADC includes a comparator section and a counter section. In the comparator section, the analog signal to be converted is compared with a reference signal to be compared. In the counter section, the time until the comparison result in the comparator section is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit section for controlling the scanning of the readout column.

[0140] The timing control unit 530 supplies signals for controlling timing to the row drive unit 520 and the column signal processing unit 550, respectively, based on the reference clock signal or timing control signal input to the camera device.

[0141] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion or as a result of the imaging operation of the imaging device 1. For example, the image signal processing unit 560 includes an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0142] Examples of signal processing performed by the image signal processing unit 560 include tone curve correction processing, that is, when the camera data after AD (analog-to-digital) conversion is obtained by capturing images of darker subjects, it is made to have more gray levels, while when the camera data is obtained by capturing images of brighter subjects, the gray levels are reduced. In this case, it is preferable to pre-store tone curve characteristic data in the data holding unit of the image signal processing unit 560. The tone curve characteristic data relates to which tone curve is used to correct the gray levels of the camera data.

[0143] For example, the input unit 510A is used to input the aforementioned reference clock signal, timing control signal, characteristic data, etc., from outside the device to the imaging device 1. Examples of timing control signals include vertical synchronization signals and horizontal synchronization signals. Characteristic data is stored, for example, in the data holding unit of the image signal processing unit 560. For example, the input unit 510A includes an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0144] Input terminal 511 is an external terminal for inputting data. Input circuit section 512 is used to capture the signal input to input terminal 511 into the imaging device 1. Input amplitude conversion section 513 converts the amplitude of the signal captured by input circuit section 512 into an amplitude easily usable inside the imaging device 1. Input data conversion circuit section 514 changes the arrangement of the data string of the input data. For example, input data conversion circuit section 514 includes a serial-to-parallel conversion circuit. This serial-to-parallel conversion circuit converts the serial signal received as input data into a parallel signal. It should be noted that input section 510A may omit input amplitude conversion section 513 and input data conversion circuit section 514. Power supply section supplies power to various voltages required inside the imaging device 1 based on the power supplied from the outside to the imaging device 1.

[0145] When the camera device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. Examples of external memory devices include flash memory, SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), etc.

[0146] The output unit 510B outputs image data to an external device. Examples of such image data include image data captured by the camera device 1 and image data processed by the image signal processing unit 560. For example, the output unit 510B includes an output data conversion circuit unit 515, an output amplitude conversion unit 516, an output circuit unit 517, and an output terminal 518.

[0147] For example, the output data conversion circuit 515 includes a parallel-to-serial conversion circuit. The output data conversion circuit 515 converts parallel signals used inside the camera device 1 into serial signals. The output amplitude changing unit 516 changes the amplitude of the signal used inside the camera device 1. This makes the amplitude-changed signal easier to use in external devices connected to the camera device 1. The output circuit 517 is a circuit for outputting data from inside the camera device 1 to the outside of the device. The output circuit 517 drives the wiring connected to the output terminal 518 outside the camera device 1. The output terminal 518 outputs data from the camera device 1 to the outside of the device. The output unit 510B can omit the output data conversion circuit 515 and the output amplitude changing unit 516.

[0148] When the camera device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device. Examples of external memory devices include flash memory, SRAM, DRAM, etc.

[0149] [Brief Structure of Camera Device 1]

[0150] Figure 2 and Figure 3 Examples of the schematic structure of the camera device 1 are shown. The camera device 1 includes three substrates (first substrate 100, second substrate 200 and third substrate 300). Figure 2 The planar structures of the first substrate 100, the second substrate 200, and the third substrate 300 are schematically shown, and Figure 3 The cross-sectional structure of the first substrate 100, the second substrate 200 and the third substrate 300 stacked on top of each other is schematically shown. Figure 3 Corresponding to along Figure 2 The cross-sectional structure shown is taken from line III-III′. The imaging device 1 is a three-dimensional structure formed by bonding three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the wiring included in each of the first substrate 100, second substrate 200, and third substrate 300, as well as the interlayer insulating film surrounding the wiring, are collectively referred to as the wiring layers (100T, 200T, and 300T) provided in each of the substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, second substrate 200, and third substrate 300 are stacked in this order. Semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S are arranged sequentially along the stacking direction. The specific structures of the first substrate 100, the second substrate 200, and the third substrate 300 will be described below. Figure 3 The arrows shown indicate the incident direction of light L into the imaging device 1. For convenience, this specification sometimes refers to the light incident side of the imaging device 1 as "lower part," "lower side," and "below," and the opposite side as "upper part," "upper side," and "above." Furthermore, for convenience, regarding the substrate including the semiconductor layer and the wiring layer, this specification sometimes refers to the substrate side near the wiring layer as the front side, and the substrate side near the semiconductor layer as the back side. It should be noted that the description in this specification is not limited to the above designations. For example, the imaging device 1 is a back-illuminated type imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0151] Both the pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each of these pixels 541 includes a photodiode (hereinafter referred to as a photodiode PD) and a transmission transistor (hereinafter referred to as a transmission transistor TR). The second substrate 200 is provided with pixel circuitry (hereinafter referred to as pixel circuitry 210) included in the pixel sharing unit 539. The pixel circuitry reads out or resets the photodiodes from the photodiodes of pixels 541A, 541B, 541C, and 541C via the transmission transistors. In addition to including such pixel circuitry, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes power lines 544 extending in the row direction. For example, the third substrate 300 includes an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. For example, the row driving section 520 is disposed in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the second substrate 200. More specifically, the row driving section 520 is disposed in a region that overlaps with a region near the end of the pixel array section 540 in the H direction in the stacking direction. Figure 2 For example, the column signal processing unit 550 is disposed in a region that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is disposed in a region that overlaps with a region near the end of the pixel array unit 540 in the V direction in the stacking direction. Figure 2 Although not shown, the input section 510A and the output section 510B can be arranged in a portion other than the third substrate 300. For example, the input section 510A and the output section 510B can be arranged in the second substrate 200. Alternatively, the input section 510A and the output section 510B can be provided on the back side (light incident surface) of the first substrate 100. It should be noted that the pixel circuit provided in the second substrate 200 described above can be alternatively referred to in some cases as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. The term pixel circuit is used in this specification.

[0152] For example, the first substrate 100 and the second substrate 200 are connected by a through electrode (described below). Figure 6The through electrodes 120E and 121E are electrically connected to each other. For example, the second substrate 200 and the third substrate 300 are electrically connected to each other through contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. Contact areas 201R and 301R are positioned between the pixel array section 540 and the row drive section 520 in the stacking direction. Figure 3 In other words, for example, contact regions 201R and 301R are disposed in or near a region in which the row drive unit 520 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap each other in the stacking direction. For example, each of contact regions 201R and 301R is arranged at the end of this region in the H direction. Figure 2 For example, contact region 301R is provided at a position on the third substrate 300 that overlaps with a portion of the horizontal drive unit 520. Specifically, for example, contact region 301R is provided at a position on the third substrate 300 that overlaps with the end of the horizontal drive unit 520 in the H direction. Figure 2 and Figure 3 For example, contact portions 201 and 301 connect the row drive unit 520 disposed in the third substrate 300 to the row drive signal line 542 disposed in the second substrate 200. For example, contact portions 201 and 301 can also connect the input unit 510A disposed in the third substrate 300 to the power supply line 544 and the reference potential line (hereinafter referred to as the reference potential line VSS). Contact regions 202R and 302R are disposed between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction. Figure 3 In other words, for example, contact regions 202R and 302R are disposed in or near a region in which the signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap each other in the stacking direction. For example, each of contact regions 202R and 302R is arranged at the end of this region in the V direction. Figure 2For example, contact region 302R is provided at a position on the third substrate 300 that overlaps with a portion of the column signal processing unit 550. Specifically, for example, contact region 302R is provided at a position on the third substrate 300 that overlaps with the end of the column signal processing unit 550 in the V direction. Figure 2 and Figure 3 For example, contacts 202 and 302 are used to connect pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion of photodiodes) output from each of the plurality of pixel sharing units 539 included in the pixel array unit 540 to a column signal processing unit 550 provided in the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0153] As mentioned above, Figure 3 This is an example of a cross-sectional view of the imaging device 1. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact portions 201, 202, 301, and 302 are formed using electrodes made of a conductive material. For example, the conductive material includes metallic materials such as copper (Cu), aluminum (Al), or gold (Au). For example, contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly joining wiring formed as electrodes, thereby enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0154] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, such as Figure 3 As shown, electrical connection portions such as contact areas 201R, 202R, 301R, and 302R can be provided in areas overlapping with the pixel array portion 540 in the stacking direction. Alternatively, electrical connection portions can also be provided in areas not overlapping with the pixel array portion 540 in the stacking direction. Specifically, electrical connection portions can be provided in areas overlapping with the peripheral portion in the stacking direction. The peripheral portion is arranged on the outer side of the pixel array portion 540.

[0155] For example, connection holes H1 and H2 are provided in the first substrate 100 and the second substrate 200. Connection holes H1 and H2 penetrate through the first substrate 100 and the second substrate 200. Figure 3 The connecting holes H1 and H2 are located on the outer side of the pixel array portion 540 (or the portion overlapping with the pixel array portion 540). Figure 2For example, the connection hole H1 is arranged outside the pixel array portion 540 in the H direction, and the connection hole H2 is arranged outside the pixel array portion 540 in the V direction. For example, the connection hole H1 reaches the input portion 510A provided in the third substrate 300, and the connection hole H2 reaches the output portion 510B provided in the third substrate 300. Each of the connection holes H1 and H2 may be a cavity or may at least partially include conductive material. For example, there is a configuration in which each electrode formed as the input portion 510A and / or the output portion 510B is connected to a bonding wire. Alternatively, there is a configuration in which the electrode formed as the input portion 510A and / or the output portion 510B is connected to the conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be embedded in a part or the entirety of the connection holes H1 and H2, or the conductive material may be formed on the sidewalls of the connection holes H1 and H2.

[0156] It should be noted that Figure 3 The diagram shows a structure in which the third substrate 300 is provided with an input section 510A and an output section 510B, but this is not limiting. For example, the input section 510A and / or the output section 510B can also be provided in the second substrate 200 in such a way that signals from the third substrate 300 are transmitted to the second substrate 200 via wiring layers 200T and 300T. Similarly, the input section 510A and / or the output section 510B can also be provided in the first substrate 100 in such a way that signals from the second substrate 200 are transmitted to the first substrate 100 via wiring layers 100T and 200T.

[0157] Figure 4 This is an equivalent circuit diagram showing a construction example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 4The diagram illustrates four pixels 541 (541A, 541B, 541C, and 541D), a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. For example, the pixel circuit 210 includes four transistors. Specifically, the pixel circuit 210 includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates the pixel circuit 210 in a time-division manner, sequentially outputting the pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The mode in which a pixel circuit 210 is connected to a plurality of pixels 541, and the pixel signals of each of the plurality of pixels 541 are output from the pixel circuit 210 in a time-division manner, is referred to as "multiple pixels 541 sharing a pixel circuit 210".

[0158] Pixels 541A, 541B, 541C, and 541D each contain the same constituent elements. To distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D, identification number 1 is assigned to the end of the symbol of the constituent elements of pixel 541A, identification number 2 is assigned to the end of the symbol of the constituent elements of pixel 541B, identification number 3 is assigned to the end of the symbol of the constituent elements of pixel 541C, and identification number 4 is assigned to the end of the symbol of the constituent elements of pixel 541D. When it is not necessary to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the symbols of the constituent elements of pixels 541A, 541B, 541C, and 541D are omitted.

[0159] For example, pixels 541A, 541B, 541C, and 541D each include: a photodiode PD; a transmission transistor TR electrically connected to the photodiode PD; and a floating diffuser FD electrically connected to the transmission transistor TR. Each photodiode PD (PD1, PD2, PD3, and PD4) has: a cathode electrically connected to the source of the transmission transistor TR; and an anode electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light to generate a charge corresponding to the amount of light received. For example, the transmission transistor TR (each transmission transistor TR1, TR2, TR3, and TR4) is an n-type CMOS (complementary metal-oxide-semiconductor) transistor. The transmission transistor TR has: a drain electrically connected to the floating diffuser FD; and a gate electrically connected to a drive signal line. This drive signal line is a plurality of row drive signal lines 542 connected to a pixel shared unit 539 (see [link to relevant documentation]). Figure 1Part of the process. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion section FD. Each floating diffusion section FD (floating diffusion sections FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in the p-type semiconductor layer. The floating diffusion section FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD, and a charge-to-voltage conversion device that generates a voltage corresponding to the amount of charge.

[0160] The four floating diffusers FD (FD1, FD2, FD3, and FD4) included in a pixel shared unit 539 are electrically connected to each other and to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The gate of the amplifying transistor AMP is connected to the floating diffuser FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 543, and the gate of the select transistor SEL is connected to the drive signal line. The drive signal line is part of a plurality of row drive signal lines 542 connected to a pixel shared unit 539.

[0161] When the transfer transistor TR is in the ON state, it transfers the charge of the photodiode PD to the floating diffuser FD. For example, as described below. Figure 6 As shown, the gate (transfer gate TG) of the transfer transistor TR includes a so-called vertical electrode and is configured to be connected from the semiconductor layer (described below). Figure 6 The semiconductor layer 100S extends from the front side to the depth reaching the PD. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. When the reset transistor RST is in the ON state, it resets the potential of the floating diffuser FD to the potential of the power supply line VDD. The select transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifying transistor AMP generates a voltage signal corresponding to the level of charge held in the floating diffuser FD as a pixel signal. The amplifying transistor AMP is connected to the vertical signal line 543 via the select transistor SEL. The amplifying transistor AMP and the load circuit section in the column signal processing unit 550 connected to the vertical signal line 543 (see [link to relevant documentation]) Figure 1 Together, they form a source follower. When the select transistor SEL is turned on, the amplifying transistor AMP outputs the voltage of the floating diffuser FD to the column signal processing unit 550 via the vertical signal line 543. For example, the reset transistor RST, the amplifying transistor AMP, and the select transistor SEL are N-type CMOS transistors.

[0162] The FD conversion gain switching transistor FDG is used to change the gain of the charge-to-voltage conversion performed by the floating diffuser FD. Typically, in low-light conditions, the pixel signal is smaller. When the charge-to-voltage conversion is based on Q=CV, if the floating diffuser FD has a large capacitance (FD capacitance C), the voltage V obtained when converted to voltage by the amplifying transistor AMP will be small. On the other hand, brighter areas provide a larger pixel signal. Therefore, if the FD capacitance C is small, the floating diffuser FD will not be able to receive all the charge from the photodiode PD. Furthermore, the FD capacitance C must be large to prevent the voltage V obtained when converted to voltage by the amplifying transistor AMP from being too large (i.e., to make V smaller). Considering these factors, when the FD conversion gain switching transistor FDG is turned on, the FD capacitance C increases by an amount equivalent to the gate capacitance of the FDG. This results in an overall increase in the FD capacitance C. Conversely, when the FD conversion gain switching transistor FDG is turned off, the FD capacitance C decreases overall. Thus, the FD capacitance C is variable by switching the FD conversion gain switching transistor FDG on / off. This allows for switching conversion efficiency. For example, the FD conversion gain switching transistor FDG is an N-type CMOS transistor.

[0163] It should be noted that a configuration can also be adopted in which the FD conversion gain switching transistor FDG is not provided. In this case, for example, pixel circuit 210 includes three transistors, such as amplifying transistor AMP, selecting transistor SEL, and resetting transistor RST. For example, pixel circuit 210 includes at least one of pixel transistors such as amplifying transistor AMP, selecting transistor SEL, resetting transistor RST, and FD conversion gain switching transistor FDG.

[0164] The select transistor SEL can also be positioned between the power supply line VDD and the amplifying transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to both the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifying transistor AMP, and the gate of the select transistor SEL is electrically connected to the horizontal drive signal line 542 (see [link to relevant documentation]). Figure 1The source of the amplifying transistor AMP (output of pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that, although not shown, the number of pixels 541 sharing a single pixel circuit 210 is not necessarily four. For example, two or eight pixels 541 may share a single pixel circuit 210.

[0165] Figure 5 An example of the connection pattern between multiple pixel shared units 539 and vertical signal lines 543 is shown. For example, four pixel shared units 539 arranged in a column direction are divided into four groups, and each vertical signal line 543 is connected to a corresponding one of these four groups. For the sake of simplicity, Figure 5 An example is shown in which each of the four groups includes one pixel sharing unit 539, but each of the four groups may also include multiple pixel sharing units 539. Thus, in the imaging device 1, the multiple pixel sharing units 539 arranged in the column direction can be divided into groups, each including one or more pixel sharing units 539. For example, each vertical signal line 543 and each column signal processing unit 550 are connected to a corresponding one of these groups, thereby allowing pixel signals to be read out simultaneously from each corresponding group. Alternatively, in the imaging device 1, a vertical signal line 543 can be connected to the multiple pixel sharing units 539 arranged in the column direction. Then, pixel signals are sequentially read out from the multiple pixel sharing units 539 connected to a vertical signal line 543 in a time-division manner.

[0166] [Detailed Structure of Camera Device 1]

[0167] Figure 6 An example of the cross-sectional structure of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 in a direction perpendicular to the main surface is shown. For ease of understanding, Figure 6 The positional relationship between the constituent elements is schematically shown, and the cross-section shown may differ from the actual cross-section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 also includes a light-receiving lens 401 disposed on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may also be disposed between the light-receiving lens 401 and the first substrate 100. For example, the light-receiving lens 401 is disposed on each of pixels 541A, 541B, 541C, and 541D. For example, the imaging device 1 is a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 disposed in the central portion and a peripheral portion 540B disposed outside the pixel array portion 540.

[0168] The first substrate 100, starting from the light-receiving lens 401 side, sequentially includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. For example, the semiconductor layer 100S is formed from a silicon substrate. For example, the semiconductor layer 100S includes a p-well layer 115 in a portion of its front side (the surface on the side of the wiring layer 100T) and its vicinity, and the semiconductor layer 100S includes an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0169] Figure 7A An example of a planar structure of the first substrate 100 is shown. Figure 7A The planar structure of the pixel separation section 117, photodiode PD, floating diffusion section FD, VSS contact region 118, and transmission transistor TR of the first substrate 100 is mainly shown. (Refer to...) Figure 7A In addition Figure 6 The structure of the first substrate 100 will be explained below.

[0170] The floating diffuser FD and VSS contact region 118 are disposed near the front side of the semiconductor layer 100S. The floating diffuser FD is formed from an n-type semiconductor region disposed in the p-well layer 115. For example, the floating diffusers FD (floating diffusers FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D are disposed close to each other in the central portion of the pixel common unit 539. Figure 7A As will be described in detail below, the four floating diffusion sections (floating diffusion sections FD1, FD2, FD3, and FD4) included in the pixel common unit 539 are electrically connected to each other in the first substrate 100 (more specifically, in the wiring layer 100T) via an electrical connection member (the pad section 120 described below). Furthermore, each floating diffusion section FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical member (the through electrode 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion sections FD are electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via this electrical member.

[0171] VSS contact area 118 is the area electrically connected to the reference potential line VSS. VSS contact area 118 is arranged away from the floating diffuser FD. For example, in pixels 541A, 541B, 541C, and 541D, the floating diffuser FD is arranged at one end of the pixel in the V direction, and the VSS contact area 118 is arranged at the other end of the pixel in the V direction. Figure 7A For example, the VSS contact region 118 is formed of a p-type semiconductor region. For example, the VSS contact region 118 is connected to a ground potential or a fixed potential. This provides a reference potential to the semiconductor layer 100S.

[0172] In addition to photodiodes PD, floating diffusers FD, and VSS contact regions 118, the first substrate 100 also includes a transmission transistor TR. These photodiodes PD, floating diffusers FD, VSS contact regions 118, and transmission transistor TR are disposed in individual pixels 541A, 541B, 541C, and 541D. The transmission transistor TR is disposed on the front side of the semiconductor layer 100S (the side opposite to the light incident surface, or the side of the second substrate 200). The transmission transistor TR includes a transmission gate TG. For example, the transmission gate TG includes a horizontal portion TGb facing the front side of the semiconductor layer 100S and a vertical portion TGa disposed in the semiconductor layer 100S. The vertical portion TGa extends along the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end is disposed in the n-type semiconductor region 114. The transmission transistor TR is constructed using this vertical transistor configuration. This makes it less prone to pixel signal transmission defects and improves the readout efficiency of the pixel signal.

[0173] The horizontal portion TGb of the transmission gate TG extends from a position opposite to the vertical portion TGA (e.g., in the H direction) toward the central portion of the pixel common unit 539. Figure 7A This allows the position of the through electrode reaching the transmission gate TG (hereinafter referred to as the through electrode TGV) in the H direction to be close to the position of the through electrodes (hereinafter referred to as the through electrodes 120E and 121E) connected to the floating diffusion portion FD and the VSS contact region 118 in the H direction. For example, the multiple pixel shared units 539 disposed in the first substrate 100 have the same structure. Figure 7A ).

[0174] The semiconductor layer 100S is provided with a pixel separation portion 117 that separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction (the direction perpendicular to the front surface of the semiconductor layer 100S) of the semiconductor layer 100S. The pixel separation portion 117 is configured to separate pixels 541A, 541B, 541C, and 541D from each other. For example, the pixel separation portion 117 has a grid-like planar shape (…). Figure 7A and Figure 7B For example, pixel separation unit 117 electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other. For example, pixel separation unit 117 includes a light-shielding film 117A and an insulating film 117B. For example, the light-shielding film 117A is formed using tungsten (W) or the like. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. For example, the insulating film 117B is formed of silicon oxide (SiO). For example, pixel separation unit 117 has a full trench isolation (FTI) structure and extends through the semiconductor layer 100S. Although not shown, pixel separation unit 117 is not limited to an FTI structure extending through the semiconductor layer 100S. For example, pixel separation unit 117 may have a deep trench isolation (DTI) structure in which the semiconductor layer 100S is not extended. The pixel separation portion 117 extends along the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0175] For example, the semiconductor layer 100S is provided with a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back side of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side of the pixel separation portion 117. Specifically, the second pinning region 116 is disposed between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. For example, both the first pinning region 113 and the second pinning region 116 are formed of a p-type semiconductor region.

[0176] A fixed-charge film 112 with a negative fixed charge is disposed between the semiconductor layer 100S and the insulating film 111. The electric field induced by the fixed-charge film 112 forms a first pinning region 113 of the hole accumulation layer at the interface on the light-receiving surface (back side) side of the semiconductor layer 100S. This suppresses the generation of dark current caused by the interface energy level on the light-receiving surface side of the semiconductor layer 100S. For example, the fixed-charge film 112 is formed using an insulating film with a negative fixed charge. Examples of materials for such an insulating film with a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

[0177] A light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be continuously disposed from the light-shielding film 117A constituting the pixel separation section 117. For example, the light-shielding film 117A between the fixed charge film 112 and the insulating film 111 may be selectively disposed at a position opposite to the pixel separation section 117 in the semiconductor layer 100S. The insulating film 111 is configured to cover the light-shielding film 117A. For example, the insulating film 111 may be formed of silicon oxide.

[0178] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 sequentially includes, starting from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, the horizontal portion TGb of the transmission gate TG is disposed in this wiring layer 100T. The interlayer insulating film 119 is disposed across the entire front side of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. For example, the interlayer insulating film 119 is formed of a silicon oxide film. It should be noted that the wiring layer 100T is not limited to the above structure, but it is sufficient as long as the wiring layer 100T has a structure including wiring and an insulating film.

[0179] Figure 7B It shows Figure 7A The planar structure shown includes pads 120 and 121. Each pad 120 and 121 is disposed in a selective region on the interlayer insulating film 119. Pad 120 is used to interconnect the floating diffusers FD (floating diffusers FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D. For example, a pad 120 is provided for each pixel common unit 539, and the pad 120 is arranged in the central portion of the pixel common unit 539 in the planar view. Figure 7B The pad portion 120 is provided to span the pixel separation portion 117. The pad portion 120 is arranged to overlap at least a portion of each of the floating diffuser portions FD1, FD2, FD3 and FD4. Figure 6 and Figure 7BSpecifically, the pad portion 120 is formed in a region that overlaps with at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) sharing the pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) sharing the pixel circuit 210 in a direction perpendicular to the front side of the semiconductor layer 100S. A coupling via 120C for electrically connecting the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4 is provided in the interlayer insulating film 119. For example, the coupling via 120C is provided in each of pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 120 is buried in the coupling via 120C, thereby electrically connecting the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4.

[0180] The pad portion 121 is used to interconnect a plurality of VSS contact regions 118. For example, for two adjacent pixel sharing units 539 in the V direction, the VSS contact regions 118 of pixels 541C and 541D disposed in one of the pixel sharing units 539 and the VSS contact regions 118 of pixels 541A and 541B disposed in the other pixel sharing unit 539 are electrically connected to each other via the pad portion 121. For example, the pad portion 121 is configured to span the pixel separation portion 117. The pad portion 121 is arranged to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front side of the semiconductor layer 100S. Interlayer insulating film 119 has a connection via 121C for electrically connecting pad portion 121 to VSS contact area 118. For example, connection via 121C is provided in each of pixels 541A, 541B, 541C, and 541D. For example, a portion of pad portion 121 is buried in connection via 121C, thereby electrically connecting pad portion 121 to VSS contact area 118. For example, the pad portions 120 and 121 of multiple pixel shared units 539 arranged in the V direction are arranged at approximately the same position in the H direction. Figure 7B ).

[0181] By providing pads 120, the wiring for connecting each floating diffuser FD to the pixel circuit 210 (e.g., the gate electrode of the amplifying transistor AMP) is reduced. Similarly, by providing pads 121, the wiring for supplying potential to each VSS contact region 118 is reduced. For example, this can reduce the overall chip area, suppress electrical interference between wirings of miniaturized pixels, and / or reduce costs by reducing the number of components.

[0182] Pad portions 120 and 121 can be disposed at desired locations in the first substrate 100 and the second substrate 200. Specifically, pad portions 120 and 121 can be disposed in either the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S. When pad portions 120 and 121 are disposed in the wiring layer 100T, pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, each of pad portions 120 and 121 can be configured to be directly connected to at least a portion of the floating diffusion portion FD and / or at least a portion of the VSS contact region 118. Alternatively, a configuration can be adopted in which corresponding connection vias 120C and 121C are provided from each of the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 are disposed at desired locations in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0183] Specifically, when pads 120 and 121 are provided in wiring layer 100T, the wiring in insulating region 212 of semiconductor layer 200S that connects to floating diffusion region FD and / or VSS contact region 118 can be reduced. This reduces the area of ​​insulating region 212 in the second substrate 200 where pixel circuit 210 is formed, which is used to form through wiring (connecting from floating diffusion region FD to pixel circuit 210). Therefore, a larger area of ​​the second substrate 200 where pixel circuit 210 is formed can be ensured. For example, by ensuring a larger area of ​​pixel circuit 210, larger pixel transistors can be formed, and image quality can be improved by reducing noise, etc.

[0184] In particular, when the FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion section FD and / or a VSS contact area 118 for each pixel 541. In this way, by using the construction of the pad sections 120 and 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0185] In addition, such as Figure 7BAs shown, for example, pad portions 120 connected to multiple floating diffusers FD and pad portions 121 connected to multiple VSS contact regions 118 are arranged alternately in a straight line in the V direction. Furthermore, pad portions 120 and 121 are formed at locations surrounded by multiple photodiodes PD, multiple transmission gates TG, and multiple floating diffusers FD. This allows for the free arrangement of components other than the floating diffusers FD and VSS contact regions 118 in the first substrate 100 where multiple components are formed. Therefore, efficient layout of the entire chip can be achieved. Additionally, the layout symmetry of components formed in the shared pixel units 539 can be ensured, and thus characteristic variations in each pixel 541 can be suppressed.

[0186] For example, pads 120 and 121 are each formed of polysilicon. More specifically, pads 120 and 121 are each formed of doped polysilicon with added impurities. Preferably, pads 120 and 121 are each formed of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This allows the pixel circuit 210 to be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason for this will be explained later. It should be noted that in the following description, the method of forming the pixel circuit 210 after the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0187] Here, it is also conceivable to form the pixel circuit 210 in the second substrate 200 and then bond the second substrate 200 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the front side of the first substrate 100 (the front side of the wiring layer 100T) and the front side of the second substrate 200 (the front side of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the front side of the first substrate 100 and the front side of the second substrate 200 come into contact with each other. Thereby, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, the structure of the imaging device 1 using the second manufacturing method allows it to be manufactured, for example, using appropriate processes according to the structure of each of the first substrate 100 and the second substrate 200. Therefore, it is possible to manufacture a high-quality and high-performance imaging device.

[0188] In this second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, alignment errors may occur due to the manufacturing apparatus used for bonding. Furthermore, for example, both the first substrate 100 and the second substrate 200 have a diameter of approximately tens of centimeters. When the first substrate 100 and the second substrate 200 are bonded together, substrate expansion and contraction may occur in the microscopic regions of each portion of the first substrate 100 and the second substrate 200. This expansion and contraction is caused by a slight deviation in the timing of the substrates contacting each other. This expansion and contraction of the first substrate 100 and the second substrate 200 can sometimes lead to positional errors in the electrodes formed on the front surface of the first substrate 100 and the front surface of the second substrate 200 for electrical connection. In the second manufacturing method, it is preferable to pre-treat the substrates so that the electrodes of the first substrate 100 and the second substrate 200 can contact each other despite such errors. Specifically, by taking the aforementioned errors into account, at least one of the first substrate 100 and the second substrate 200 can have a larger electrode. More preferably, both the first substrate 100 and the second substrate 200 have larger electrodes. Therefore, if the second manufacturing method is used, the size (size in the substrate plane direction) of the electrode formed on the front side of the first substrate 100 or the second substrate 200 is larger than the size of the internal electrode extending from the interior of the first substrate 100 or the second substrate 200 to the front side along the thickness direction.

[0189] On the other hand, the first manufacturing method described above can be used by using a heat-resistant conductive material to construct each pad portion 120 and 121. In the first manufacturing method, after forming a first substrate 100 including a photodiode PD, a transmission transistor TR, etc., the first substrate 100 and a second substrate 200 (semiconductor layer 200S) are bonded together. At this time, the second substrate 200 has not yet formed a pattern for the active element and wiring layer for constituting the pixel circuit 210. Since the second substrate 200 is in a state where no pattern has been formed, even if there is an error in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause a positional alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. It should be noted that when forming the pattern of the second substrate, for example in an exposure apparatus for forming a pattern, the pattern is formed simultaneously with the pattern formed on the first substrate as the object of positional alignment. For this reason, the misalignment error between the first substrate 100 and the second substrate 200 will not be a problem when manufacturing the imaging device 1 in the first manufacturing method. For the same reason, the error caused by the expansion and contraction of the substrates in the second manufacturing method will not be a problem when manufacturing the imaging device 1 in the first manufacturing method.

[0190] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, an active element is formed on the second substrate 200. Subsequently, through electrodes 120E and 121E, and a through electrode TGV ( Figure 6 To form these through electrodes 120E and 121E and TGV, for example, the pattern of the through electrodes is formed by using a reduced-projection exposure implemented by an exposure apparatus from above the second substrate 200. Because of the use of reduced-projection exposure, even if there is a positional alignment error between the second substrate 200 and the exposure apparatus, the magnitude of this error in the second substrate 200 is at most a fraction of the error magnitude in the second manufacturing method described above (the reciprocal of the reduced-projection magnification). Therefore, by using the first manufacturing method to obtain the structure of the imaging device 1, the components formed on each of the first substrate 100 and the second substrate 200 are easily aligned with each other in position, and a high-quality and high-performance imaging device can be manufactured.

[0191] The imaging device 1 manufactured using this first manufacturing method has features different from those of the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, each of the through electrodes 120E, 121E, and TGV has a substantially constant thickness (dimension in the plane of the substrate) from the second substrate 200 to the first substrate 100. Alternatively, when each of the through electrodes 120E, 121E, and TGV has a tapered shape, each of the through electrodes 120E, 121E, and TGV has a tapered shape with a constant slope. The imaging device 1 including such through electrodes 120E, 121E, and TGV facilitates the miniaturization of the pixels 541.

[0192] Here, when the imaging device 1 is manufactured in the first manufacturing method, the active element is formed in the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together. Therefore, the heat treatment required to form the active element also affects the first substrate 100. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided in the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200 for each pad portion 120 and 121. For example, conductive materials with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, are used for the pad portions 120 and 121. In this way, the imaging device 1 can be manufactured by using the first manufacturing method described above.

[0193] For example, the passivation film 122 is disposed across the entire front side of the semiconductor layer 100S and covers the pad portions 120 and 121. Figure 6 For example, the passivation film 122 is formed of a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pad portions 120 and 121 across the passivation film 122. This interlayer insulating film 123 is provided across the entire front side of the semiconductor layer 100S. For example, the interlayer insulating film 123 is formed of a silicon oxide (SiO) film. A bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. In other words, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided across the entire main surface of the first substrate 100. For example, the bonding film 124 is formed of a silicon nitride film or a silicon oxide film.

[0194] For example, the light-receiving lens 401 is opposite to the semiconductor layer 100S through the fixed charge film 112 and the insulating film 111. Figure 6For example, each light-receiving lens 401 is disposed at a position opposite to the photodiode PD of each of pixels 541A, 541B, 541C and 541D.

[0195] The second substrate 200 sequentially includes a semiconductor layer 200S and a wiring layer 200T, starting from the side of the first substrate 100. The semiconductor layer 200S is formed of a silicon substrate. The semiconductor layer 200S has a well region 211 spanning the thickness direction. For example, the well region 211 is a p-type semiconductor region. The second substrate 200 is provided with pixel circuits 210 arranged for each pixel common unit 539. For example, the pixel circuits 210 are provided on the front side of the semiconductor layer 200S (the wiring layer 200T side of the semiconductor layer 200S). In the imaging device 1, the second substrate 200 is attached to the first substrate 100, and the back side of the second substrate 200 (the semiconductor layer 200S side) faces the front side of the first substrate 100 (the wiring layer 100T side). In other words, the second substrate 200 and the first substrate 100 are attached in a face-to-back manner.

[0196] Figures 8 to 12 An example of the planar structure of the second substrate 200 is schematically shown. Figure 8 The structure of the pixel circuit 210 disposed near the front side of the semiconductor layer 200S is shown. Figure 9 The structure of the wiring layer 200T (specifically, the first wiring layer W1 described below), the semiconductor layer 200S connected to the wiring layer 200T, and various portions of the first substrate 100 are schematically shown. Figures 10 to 12 Examples of planar constructions for wiring layers 200T are shown below. Figures 8 to 12 In addition Figure 6 The structure of the second substrate 200 will be explained below. Figure 8 and Figure 9 The outline of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is shown in dashed lines, and the boundary between the semiconductor layer 200S and the element separation region 213 or the insulating region 212 at the portion overlapping with the gate electrodes of the individual transistors constituting the pixel circuit 210 is shown in dotted lines. In the portion overlapping with the gate electrode of the amplifying transistor AMP, the boundary between the semiconductor layer 200S and the element separation region 213, and the boundary between the element separation region 213 and the insulating region 212 are provided at one of the locations in the channel width direction.

[0197] The second substrate 200 is provided with: an insulating region 212 dividing the semiconductor layer 200S and an element separation region 213 disposed in a portion of the semiconductor layer 200S in the thickness direction. Figure 6For example, an insulating region 212 is disposed between two adjacent pixel circuits 210 in the H direction. The through electrodes 120E and 121E of the two pixel shared units 539 connected to these two pixel circuits 210, as well as the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4), are arranged in the insulating region 212. Figure 9 ).

[0198] The insulating region 212 has a thickness approximately the same as that of the semiconductor layer 200S. Figure 6 The semiconductor layer 200S is divided by the insulating region 212. Through electrodes 120E and 121E, as well as through electrode TGV, are arranged in the insulating region 212. For example, the insulating region 212 is formed of silicon oxide.

[0199] Through electrodes 120E and 121E are disposed to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wiring in the wiring layer 200T (hereinafter referred to as the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). These through electrodes 120E and 121E are disposed to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122. The lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121 (…). Figure 6 The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210 to each other. In other words, the through electrode 120E electrically connects the floating diffusion portion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200. The through electrode 121E is used to electrically connect the pad portion 121 to the reference potential line VSS of the wiring layer 200T to each other. In other words, the through electrode 121E electrically connects the VSS contact area 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0200] A through-electrode TGV is disposed to penetrate the insulating region 212 in the thickness direction. The upper end of the through-electrode TGV is connected to the wiring in the wiring layer 200T. The through-electrode TGV is disposed to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119. The lower end of the through-electrode TGV is connected to the transmission gate TG ( Figure 6 This through-electrode TGV is used to connect the transmission gates TG (transmission gates TG1, TG2, TG3, and TG4) of pixels 541A, 541B, 541C, and 541D to the wiring layer 200T (part of the row drive signal line 542, or more specifically, as described below). Figure 11The wirings TRG1, TRG2, TRG3, and TRG4 in the first substrate 100 are electrically connected to each other. In other words, the through electrode TGV electrically connects the transmission gate TG of the first substrate 100 to the wiring TRG of the second substrate 200, and transmits drive signals to each of the transmission transistors TR (transmission transistors TR1, TR2, TR3, and TR4).

[0201] The insulating region 212 is a region provided to insulate the aforementioned through electrodes 120E and 121E and through electrode TGV from the semiconductor layer 200S. Through electrodes 120E and 121E and through electrode TGV are used to electrically connect the first substrate 100 and the second substrate 200 to each other. For example, the insulating region 212 is provided between two adjacent pixel circuits 210 (pixel sharing unit 539) in the H direction, and the through electrodes 120E and 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to these two pixel circuits 210 are arranged in the insulating region 212. For example, the insulating region 212 is provided to extend along the V direction (…). Figure 8 and Figure 9 Here, the horizontal portion TGb of the transfer gate TG is cleverly arranged such that the position of the through electrode TGV in the H direction is closer to the positions of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGA. Figure 7A and Figure 9For example, the through electrode TGV is arranged in the H direction at a position approximately the same as that of the through electrodes 120E and 121E. This allows the through electrodes 120E and 121E, as well as the through electrode TGV, to be disposed together in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to provide the horizontal portion TGb only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa. For example, the through electrode TGV is arranged in the approximately central portion of each pixel 541 in both the H and V directions. In this case, the position of the through electrode TGV in the H direction is significantly offset from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate the through electrodes TGV and the through electrodes 120E and 121E from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is far from the positions of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide an insulating region 212 around each of the through electrodes 120E, 121E, and TGV. This allows for finer segmentation of the semiconductor layer 200S. In contrast, when the through electrodes 120E and 121E and the through electrode TGV are arranged together in the insulating region 212 extending along the V direction, the size of the semiconductor layer 200S in the H direction can be increased. This ensures a larger area for semiconductor element formation in the semiconductor layer 200S. For example, this allows for an increase in the size of the amplification transistor AMP and noise suppression.

[0202] For reference Figure 4 As described, the pixel sharing unit 539 has the following structure: the floating diffusion portions FD disposed in each of the plurality of pixels 541 are electrically connected to each other, and the plurality of pixels 541 share a single pixel circuit 210. Furthermore, the electrical connection between the aforementioned floating diffusion portions FD is achieved through pad portions 120 disposed in the first substrate 100. Figure 6 and Figure 7BThis is achieved by providing an electrical connection portion (pad portion 120) in the first substrate 100 and a pixel circuit 210 in the second substrate 200 via a through electrode 120E. As another construction example, it is also conceivable to provide an electrical connection portion between floating diffusers FD in the second substrate 200. In this case, four through electrodes connected to each of the floating diffusers FD1, FD2, FD3, and FD4 are provided in the pixel common unit 539. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the size of the insulating region 212 used to insulate the area around these through electrodes becomes larger. In contrast, the construction with a pad portion 120 in the first substrate 100... Figure 6 and Figure 7B This reduces the number of through electrodes and the size of the insulating region 212. This ensures a larger area for the semiconductor element formation region in the semiconductor layer 200S. For example, this allows the amplifying transistor AMP to have a larger size and to suppress noise.

[0203] Component separation region 213 is disposed on the front side of semiconductor layer 200S. Component separation region 213 has a shallow trench isolation (STI) structure. In this component separation region 213, semiconductor layer 200S is recessed in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in the recessed portion. For example, the insulating film is formed of silicon oxide. Component separation region 213 performs component separation among multiple transistors constituting pixel circuit 210 according to the layout of pixel circuit 210. Semiconductor layer 200S (specifically, well region 211) extends below component separation region 213 (deep within semiconductor layer 200S).

[0204] Here, refer to Figure 7A , Figure 7B and Figure 8 To illustrate the difference between the shape (shape in the plane direction of the substrate) of the pixel sharing unit 539 in the first substrate 100 and the shape of the pixel sharing unit 539 in the second substrate 200.

[0205] In the imaging device 1, the pixel sharing unit 539 is disposed across both the first substrate 100 and the second substrate 200. For example, the shape of the pixel sharing unit 539 disposed in the first substrate 100 and the shape of the pixel sharing unit 539 disposed in the second substrate 200 are different from each other.

[0206] exist Figure 7A and Figure 7BIn each of these, the outlines of pixels 541A, 541B, 541C, and 541D are shown with a single-dotted line, and the outline of the pixel sharing unit 539 is shown with a thick line. For example, the pixel sharing unit 539 in the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to them in the V direction. In other words, the pixel sharing unit 539 in the first substrate 100 includes four adjacent pixels 541 arranged in two rows × two columns. The pixel sharing unit 539 of the first substrate 100 has a generally square shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541).

[0207] exist Figure 8 and Figure 9 In each of these examples, the outlines of pixels 541A, 541B, 541C, and 541D are shown with a single-dotted line, and the outline of the pixel sharing unit 539 is shown with a thick line. For example, the outline of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and larger in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction and a size equivalent to four pixels in the V direction. In other words, the pixel sharing unit 539 of the second substrate 200 is formed to have a size equivalent to pixels arranged adjacently in one row × four columns. The pixel sharing unit 539 of the second substrate 200 has a generally rectangular outline.

[0208] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in a line in the V direction in this order. Figure 8 By setting the shape of each pixel circuit 210 to approximately rectangular as described above, it is possible to achieve this in one direction ( Figure 8 Four transistors (select transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) are arranged in a line along the V direction. This allows the drains of the amplification transistor AMP and the reset transistor RST to be shared within a single diffusion region (a diffusion region connected to the power supply line VDD). Alternatively, the formation regions of each pixel circuit 210 can be set to approximately square (see below). Figure 48In this case, with two transistors arranged in one direction, it is difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST within a diffusion region. Therefore, setting the formation region of the pixel circuit 210 to a roughly rectangular shape facilitates the arrangement of the four transistors close together and reduces the size of the formation region of the pixel circuit 210. In other words, pixel miniaturization can be achieved. Furthermore, without needing to reduce the size of the formation region of the pixel circuit 210, the size of the formation region of the amplification transistor AMP can be increased, thereby suppressing noise.

[0209] For example, near the front side of semiconductor layer 200S, in addition to the selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is also provided. For example, VSS contact region 218 is formed of a p-type semiconductor region. VSS contact region 218 is electrically connected to VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) through wiring of wiring layer 200T and through electrode 121E. For example, this VSS contact region 218 is located adjacent to the source of FD conversion gain switching transistor FDG across component separation region 213. Figure 8 ).

[0210] Next, refer to Figure 7B and Figure 8 This will be used to illustrate the positional relationship between the pixel sharing unit 539 disposed in the first substrate 100 and the pixel sharing unit 539 disposed in the second substrate 200. For example, one of the two pixel sharing units 539 arranged in the V direction on the first substrate 100 (e.g., Figure 7B The pixel sharing unit 539 on the paper side) is connected to one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, on the paper side). Figure 8 (Left side of the paper) Pixel shared unit 539. For example, one of the two pixel shared units 539 arranged in the V direction on the first substrate 100 (for example, Figure 7B The pixel sharing unit 539 on the lower side of the paper is connected to another of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, on the lower side of the paper). Figure 8 (The right side of the paper) Pixel shared unit 539.

[0211] For example, in the two pixel sharing units 539 arranged in the H direction on the second substrate 200, the internal layout (transistor arrangement, etc.) of one pixel sharing unit 539 is approximately equal to the layout obtained by reversing the internal layout of the other pixel sharing unit 539 in the V and H directions. The effect provided by this layout will be explained below.

[0212] In the two pixel sharing units 539 arranged in the V direction on the first substrate 100, each pad portion 120 is disposed at the central portion of the outer shape of the pixel sharing unit 539. In other words, each pad portion 120 is disposed at the central portion of the pixel sharing unit 539 in both the V and H directions. Figure 7B On the other hand, as described above, the pixel sharing unit 539 of the second substrate 200 has a generally rectangular shape that is longer in the V direction. Therefore, for example, the amplifying transistor AMP connected to the pad portion 120 is arranged at a position offset from the center of the pixel sharing unit 539 in the V direction towards the upper side of the paper. For example, if two pixel sharing units 539 arranged in the H direction of the second substrate 200 have the same internal layout, then the amplifying transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., Figure 7B The distance between the pad portion 120 of the pixel shared unit 539 on the upper side of the paper is relatively short. However, the distance between the amplification transistor AMP of the other pixel shared unit 539 and the pad portion 120 (e.g., Figure 7B The distance between the pad portions 120 of the pixel sharing unit 539 on the underside of the paper is relatively long. This increases the wiring area required when there is a connection between the amplifying transistor AMP and the pad portion 120. The wiring layout of the pixel sharing unit 539 may become complex. This may affect the miniaturization of the imaging device 1.

[0213] In contrast, by reversing the internal layout of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplification transistor AMP and the pad portion 120 of both pixel-sharing units 539 can be reduced. This makes it easier to miniaturize the imaging device 1 than a structure in which the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 have the same internal layout. It should be noted that... Figure 8 The planar layout of the multiple pixel-sharing units 539 of the second substrate 200 is shown to be symmetrical from left to right, but includes the following description Figure 9 In the case of the layout of the first wiring layer W1 shown, it becomes asymmetrical from left to right.

[0214] Furthermore, preferably, the internal layout of the two pixel-shared units 539 arranged in the H direction on the second substrate 200 is also reversed relative to each other in the H direction. The reason for this will be explained below. Figure 9 As shown, two pixel-sharing units 539 arranged in the H direction on the second substrate 200 are respectively connected to pad portions 120 and 121 on the first substrate 100. For example, pad portions 120 and 121 are arranged at the central portion in the H direction of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200 (between the two pixel-sharing units 539 arranged in the H direction). Therefore, by additionally reversing the internal layout of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200, the distance between each of the multiple pixel-sharing units 539 on the second substrate 200 and the pad portions 120 and 121 can be reduced. In other words, this further facilitates the miniaturization of the imaging device 1.

[0215] Furthermore, the position of the outline of the pixel sharing unit 539 of the second substrate 200 is not necessarily aligned with the position of the outline of either of the pixel sharing units 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Figure 9 (Left side of the paper) Pixel shared unit 539 on one side in the V direction (e.g., Figure 9 The outline of the outer frame at the upper side of the paper surface is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the outline line on one side in the V direction (on the upper side of the paper). Additionally, one of the two pixel-shared units 539 arranged in the H direction in the second substrate 200 (for example, Figure 9 (On the right side of the paper) Pixel shared unit 539 on the other side in the V direction (e.g., Figure 9 The outline of the outer frame at the lower side of the paper is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 7B The outer edge of the outline at the other location in the V direction (on the underside of the paper). By arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 in this way, the distance between the amplifying transistor AMP and the pad portion 120 can be reduced. This facilitates the miniaturization of the imaging device 1.

[0216] Furthermore, the outlines of the multiple pixel-sharing units 539 on the second substrate 200 do not need to be aligned. For example, two pixel-sharing units 539 arranged in the H direction on the second substrate 200 can be arranged such that the outlines in the V direction are offset. This reduces the distance between the amplifying transistor AMP and the pad portion 120. This facilitates miniaturization of the imaging device 1.

[0217] Reference Figure 7B and Figure 9 To illustrate the repeated arrangement of the pixel sharing unit 539 in the pixel array section 540. The pixel sharing unit 539 of the first substrate 100 has the size of two pixels 541 in the H direction and the size of two pixels 541 in the V direction. Figure 7B For example, in the pixel array portion 540 of the first substrate 100, these pixel sharing units 539, each having a size equivalent to the four pixels 541, are arranged adjacently in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541). Alternatively, in the pixel array portion 540 of the first substrate 100, a pair of pixel sharing units 539, including two pixel sharing units 539 arranged adjacent to each other in the V direction, may be provided. For example, in the pixel array portion 540 of the first substrate 100, these paired pixel sharing units 539 are arranged adjacently in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 4-pixel pitch (equivalent to the pitch of four pixels 541). The pixel sharing units 539 of the second substrate 200 have a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction. Figure 9 For example, in the pixel array section 540 of the second substrate 200, a pair of pixel sharing units 539, each including two pixel sharing units 539, are provided, and each pixel sharing unit 539 has a size equivalent to the four pixels 541. These pixel sharing units 539 are arranged to be adjacent in the H direction and offset in the V direction. For example, in the pixel array section 540 of the second substrate 200, these paired pixel sharing units 539 are arranged adjacently without gaps in the H direction at a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction at a 4-pixel pitch (equivalent to the pitch of four pixels 541). By repeating this arrangement of pixel sharing units 539, the pixel sharing units 539 can be arranged without gaps. This facilitates the miniaturization of the imaging device 1.

[0218] For example, the amplifying transistor AMP can have a planar structure, but preferably, for example, the amplifying transistor AMP has a three-dimensional structure such as a fin (e.g., Fin-FET, tri-gate FET, or dual-gate FET). Figure 6 In the aforementioned three-dimensional configuration, the channel region has a concave-convex structure. This increases the effective gate width and can suppress noise. For example, the select transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG all have planar configurations. The amplifier transistor AMP can also have a planar configuration. Alternatively, the select transistor SEL, reset transistor RST, or FD conversion gain switching transistor FDG can have a three-dimensional configuration.

[0219] For example, Figure 13 Examples of main components of the camera device 1 according to this embodiment include, for instance. Figure 6 A three-dimensional diagram of the structure in region X shown. Figure 14A It shows along Figure 13 The cross-sectional structure shown is taken from line II, and Figure 14B It shows along Figure 13 The cross-sectional structure shown is taken from line II-II. For example, the semiconductor layer 200S is provided with four transistors as described above for constituting the pixel circuit 210 (hereinafter, without special distinction between them, the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG will be referred to as pixel transistors). In addition, the semiconductor layer 200S is provided with an insulating region 212 that divides the semiconductor layer 200S into multiple blocks. This insulating region 212 is provided with multiple through-wires (through electrodes 120E and 121E and through electrode TGV) that electrically connect the first substrate 100 and the second substrate 200 to each other and penetrate the insulating region 212 in the thickness direction.

[0220] According to this embodiment, the semiconductor layer 200S has adjustment portions 220 (adjustment portions 220A and 220B) respectively provided on its side surface and back surface (surface S2): on the side surface, the pixel transistor is adjacent to the aforementioned through wiring; and on the back surface (surface S2), it faces a transistor (e.g., a transmission transistor TR) disposed in the first substrate 100. As an example, Figure 13 , Figure 14A and Figure 14B The selection transistor SEL and the through electrode TGV arranged adjacent to it are shown respectively.

[0221] Each adjustment unit 220 is used to reduce the characteristic variation of the pixel transistor by increasing the threshold voltage of the parasitic transistor generated when a bias voltage is applied to a through wiring arranged adjacent to the pixel transistor or to a transistor disposed in the first substrate.

[0222] Specifically, for example, the adjustment portion 220A provided on the side surface of the semiconductor layer 200S is used to increase the threshold voltage of the parasitic transistor generated in the select transistor SEL arranged adjacent to the through electrode TGV, for example, when a bias voltage is applied to the through electrode TGV, and thus reduce the occurrence of leakage current. For example, the adjustment portion 220B provided on the back surface (surface S2) of the semiconductor layer 200S is used to increase the threshold voltage of the parasitic transistor generated in the select transistor SEL arranged opposite to the through transistor TR, for example, when a bias voltage is applied to the transfer transistor TR provided in the first substrate 100, and thus reduce the occurrence of leakage current.

[0223] Figure 15A The changes in the characteristics of the select transistor SEL are shown when the adjustment unit 220A is not provided, in the state where no bias voltage is applied to the through electrode TGV (off state) and in the state where a bias voltage is applied to the through electrode TGV (on state). Figure 15B The changes in the characteristics of the select transistor SEL are shown when the adjustment unit 220A is provided (in the imaging device 1) in a state where no bias voltage is applied to the through electrode TGV (off state) and a state where a bias voltage is applied to the through electrode TGV (on state).

[0224] Without the adjustment section 220A, when a bias voltage is applied to the through electrode TGV (on state), the threshold voltage Vth of the select transistor SEL shifts in the negative direction compared to the off state. On the other hand, with the adjustment section 220A, no change in the threshold voltage Vth of the select transistor SEL is observed in either the off or on state. In other words, because the adjustment section 220A is provided on the side of the semiconductor layer 200S that forms the channel of the select transistor SEL arranged adjacent to the through electrode TGV, leakage current caused by the bias voltage applied to the through electrode TGV can be prevented.

[0225] It should be noted that the leakage current occurring when a bias voltage is applied to the through electrode TGV is caused by carrier concentration in the semiconductor layer 200S near the gate of the select transistor SEL. Therefore, Figure 13An example is shown in which the adjustment portion 220A is disposed on the entire surface of the side of the semiconductor layer 200S opposite to the through electrode TGV. However, leakage current can be reduced by forming the adjustment portion 220A at least at and near the contact surface between the gate of the select transistor SEL and the semiconductor layer 200S.

[0226] This also applies to the adjustment section 220B. Figure 13 An example is shown in which the adjustment portion 220B is formed on the entire back side (surface S2) of the semiconductor layer 200S. However, the effect of the bias voltage applied to the transmission transistor TR and the occurrence of leakage current can be reduced by forming the adjustment portion 220B at least in the region opposite to the transistor (e.g., the transmission transistor TR) disposed in the first substrate 100.

[0227] For example, each of the adjustment portions 220A and 220B is formed from an impurity region doped with an impurity. Preferably, each adjustment portion 220A and 220B formed from the impurity region has the same conductivity type as the well of the semiconductor layer 200S. For example, each of the adjustment portions 220A and 220B can be formed as a p-type semiconductor region doped with boron (B) as a p-type impurity. In addition, for example, the impurity concentration of the p-type semiconductor region can be equal to or greater than that of the p-well layer (e.g., p-well layer 215, and see, for example) formed in the semiconductor layer 200S. Figure 20A The impurity concentration. For example, adjustment units 220A and 220B can each be formed using a metal oxide film. Specific examples include: aluminum oxide (Al2O3) film, hafnium oxide (HfO2) film, yttrium oxide (Y2O3) film, lanthanum oxide (La2O3) film, etc.

[0228] It should be noted that this embodiment has been described using the through electrode TGV and the selection transistor SEL located near the through electrode TGV as examples. However, this technique is also applicable to situations where other through wirings (e.g., through electrodes 120E and 121E) are arranged adjacent to other pixel transistors (e.g., amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG). Moreover, the same effect can be obtained.

[0229] For example, adjustment parts 220A and 220B can be manufactured in the following manner. Figures 16A to 16F Each example illustrates the manufacturing steps of the semiconductor layer 200S.

[0230] First, such as Figure 16A As shown, for example, an adjustment portion 220B is formed in the semiconductor layer 200S by ion implantation. Subsequently, as... Figure 16BAs shown, for example, a silicon oxide film is formed on the adjustment part 220B as a bonding film 124, and then the bonding film 124 is used as a bonding surface to be bonded to the first substrate 100 (interlayer insulating film 123) that has been separately fabricated.

[0231] Next, as Figure 16C As shown, the thickness of the semiconductor layer 200S is reduced as needed. In this case, the thickness of the semiconductor layer 200S is set to the film thickness required when forming the pixel circuit 210. The thickness of the semiconductor layer 200S is typically about several hundred nanometers. However, depending on the concept of the pixel circuit 210, a fully depleted (FD) type can also be used. In this case, the thickness of the semiconductor layer 200S can range from several nanometers to several micrometers.

[0232] Subsequently, as Figure 16D As shown, an opening H is provided that penetrates the semiconductor layer 200S and the adjustment section 220B, thereby appropriately separating the semiconductor layer 200S. Next, as... Figure 16E As shown, a resist film PR is formed at a predetermined location, and then an adjustment portion 220A is formed by ion implantation. Specifically, the resist film PR is patterned on the semiconductor layer 200S and on the bonding film 124 exposed through the opening H, except at the location where the adjustment portion 220A will be formed. Then, boron (B) is implanted into the semiconductor layer 200S exposed from the resist film PR by ion implantation. This forms the adjustment portion 220A on the side of the opening H.

[0233] Subsequently, as Figure 16F As shown, the resist film PR is removed, and a silicon oxide film, for example, is formed to fill the opening H. This forms an insulating region 212. Then, a pixel circuit 210, including an amplifying transistor AMP, is formed in the semiconductor layer 200S. Thus, an imaging device 1 including adjustment units 220 (adjustment units 220A and 220B) is manufactured.

[0234] For example, wiring layer 200T includes a passivation film 221, an interlayer insulating film 222, and multiple wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). For example, the passivation film 221 is in contact with the front side of the semiconductor layer 200S and covers the entire front side of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of each of the select transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 separates the multiple wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). For example, the interlayer insulating film 222 is formed of silicon oxide.

[0235] For example, the wiring layer 200T, starting from the semiconductor layer 200S side, sequentially comprises a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202. All of these are electrically insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 has multiple connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to their respective underlying layers. Each connection portion is obtained by filling the connection holes provided in the interlayer insulating film 222 with a conductive material. For example, the interlayer insulating film 222 has a connection portion 218V for connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of this connection portion for interconnecting components in the second substrate 200 is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, preferably, the aperture of the connecting holes used to interconnect the components in the second substrate 200 is smaller than the aperture of each of the through electrodes 120E and 121E and the through electrode TGV. The reason for this is explained below. The depth of the connecting portions (such as connecting portion 218V) provided in the wiring layer 200T is smaller than the depth of each of the through electrodes 120E and 121E and the through electrode TGV. Therefore, it is easier to fill the connecting holes with conductive material to obtain the aforementioned connecting portions compared to the through electrodes 120E and 121E and the through electrode TGV. Since the connecting portions have apertures smaller than the apertures of each of the through electrodes 120E and 121E and the through electrode TGV, it is easier to achieve miniaturization of the imaging device 1.

[0236] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaching the source of the FD conversion gain switching transistor FDG). For example, the first wiring layer W1 connects the through electrode 121E to the connection portion 218V. In this way, the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S are electrically connected to each other.

[0237] Next, refer to Figures 10 to 12 To illustrate the planar structure of the 200T wiring layer. Figure 10 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 11 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 12 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0238] For example, the third wiring layer W3 includes wiring TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Figure 11 These wirings correspond to the reference. Figure 4 The multiple row drive signal lines 542 are described. Lines TRG1, TRG2, TRG3, and TRG4 are used to transmit drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. Lines TRG1, TRG2, TRG3, and TRG4 are each connected to the transmission gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E. Lines SELL, RSTL, and FDGL are used to transmit drive signals to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, respectively. Lines SELL, RSTL, and FDGL are each connected to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and the connecting portion, respectively.

[0239] For example, the fourth wiring layer W4 includes a power line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction). Figure 12The power line VDD is connected to the drain of the amplifying transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Additionally, the reference potential line VSS is connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0240] Contact portions 201 and 202 can be positioned at locations overlapping with the pixel array portion 540 in the plan view (e.g., Figure 3 Alternatively, it can be located in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 6 Contact portions 201 and 202 are disposed on the front side of the second substrate 200 (the surface on the side of the wiring layer 200T). For example, each of contact portions 201 and 202 is formed of a metal such as Cu (copper) or Al (aluminum). Contact portions 201 and 202 are exposed from the front side of the wiring layer 200T (the surface on the side of the third substrate 300). Each of contact portions 201 and 202 is used to electrically connect the second substrate 200 and the third substrate 300 to each other and to bond the second substrate 200 and the third substrate 300 together.

[0241] Figure 6 An example is shown in which peripheral circuitry is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuitry may include a portion of the row driving unit 520, or a portion of the column signal processing unit 550, etc. Additionally, as... Figure 3 As shown, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, but the connection holes H1 and H2 may be arranged near the pixel array portion 540.

[0242] For example, the third substrate 300 sequentially includes a wiring layer 300T and a semiconductor layer 300S starting from the second substrate 200 side. For example, the front side of the semiconductor layer 300S is disposed on the second substrate 200 side. The semiconductor layer 300S is formed from a silicon substrate. Circuitry is disposed in the front side portion of the semiconductor layer 300S. Specifically, for example, at least a portion of each of an input section 510A, a row drive section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B is disposed in the front side portion of the semiconductor layer 300S. For example, the wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. Contact portions 301 and 302 are exposed from the front side (the surface on the second substrate 200 side) of the wiring layer 300T. Contact portions 301 and 302 are in contact with contact portions 201 and 202 of the second substrate 200, respectively. Contact portions 301 and 302 are each electrically connected to a circuit formed in the semiconductor layer 300S (e.g., at least one of the input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B). For example, contact portions 301 and 302 are each formed of a metal such as Cu (copper) or aluminum (Al). For example, external terminal TA is connected to input portion 510A via connection hole H1, and external terminal TB is connected to output portion 510B via connection hole H2.

[0243] Here, the features of camera device 1 will be explained.

[0244] Generally, a camera device includes photodiodes and pixel circuits as its main components. Here, when the photodiode has a larger area, the charge generated as a result of photoelectric conversion increases, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal and allowing the camera device to output better image data (image information). On the other hand, when the transistors (especially amplifying transistors) included in the pixel circuit have a larger size, the noise generated in the pixel circuit decreases, thus improving the signal-to-noise ratio of the captured signal and allowing the camera device to output better image data (image information).

[0245] However, in a camera device, if a photodiode and pixel circuit are disposed on the same semiconductor substrate, and the photodiode occupies a large area within the limited area of ​​the semiconductor substrate, then the transistors included in the pixel circuit must have a small size. Furthermore, if the transistors included in the pixel circuit have a large size, then the photodiode must have a small area.

[0246] To address the aforementioned problems, for example, the imaging device 1 according to this embodiment uses a structure in which multiple pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap with a photodiode PD. This allows for maximizing the area of ​​the photodiode PD and the size of the transistors included in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the signal-to-noise ratio (S / N) of the pixel signal and enables the imaging device 1 to output better image data (image information).

[0247] In a structure where multiple pixels 541 share a single pixel circuit 210 and the single pixel circuit 210 is arranged to overlap with the photodiode PD, multiple wirings extend from the floating diffuser portions FD of each of the multiple pixels 541 and connect to the single pixel circuit 210. To ensure that the semiconductor layer 200S has a large area for forming the pixel circuit 210, for example, connecting wirings can be formed to interconnect these multiple extending wirings and integrate them into a single unit. This also applies to the multiple wirings extending from the VSS contact region 118; that is, connecting wirings can be formed to interconnect these multiple extending wirings and integrate them into a single unit.

[0248] For example, when a connecting wire is formed in the semiconductor layer 200S on which the pixel circuit 210 is formed to interconnect multiple wirings extending from the floating diffusion portions FD of each of the multiple pixels 541, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 can be reduced. Similarly, when a connecting wire is formed in the semiconductor layer 200S on which the pixel circuit 210 is formed to interconnect multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and to combine them into one, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 can be reduced.

[0249] To solve the above problems, for example, the camera device 1 according to this embodiment may have the following structure: multiple pixels 541 share a pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. Furthermore, the first substrate 100 is provided with a connecting wire for interconnecting the floating diffusion portions FD of each of the multiple pixels 541 and assembling them into one, and a connecting wire for interconnecting the VSS contact areas 118 of each of the multiple pixels 541 and assembling them into one.

[0250] Here, as a manufacturing method for providing a connection wiring in the first substrate 100 for interconnecting and assembling the floating diffuser portions FD of each of the plurality of pixels 541 into a single connection wiring, and for interconnecting and assembling the VSS contact areas 118 of each of the plurality of pixels 541 into a single connection wiring, the aforementioned second manufacturing method allows for manufacturing using appropriate processes, for example, based on the structure of the first substrate 100 and the second substrate 200. This enables the manufacture of a high-quality and high-performance imaging device. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed using a simple process. Specifically, when using the aforementioned second manufacturing method, electrodes connected to the floating diffuser portions FD and electrodes connected to the VSS contact areas 118 are respectively provided on the front surface of the first substrate 100 and the front surface of the second substrate 200, which will serve as the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, preferably, the electrodes formed on the front surfaces of the two substrates are relatively large, so that when the first substrate 100 and the second substrate 200 are bonded together, the electrodes formed on the front surfaces of the two substrates can still contact each other even if their positions are offset from each other. In this case, it is conceivable that it would be difficult to arrange such electrodes within the limited area of ​​each pixel included in the imaging device 1.

[0251] For example, to address the problem of requiring a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, the imaging device 1 according to this embodiment can utilize the aforementioned first manufacturing method, which allows multiple pixels 541 to share a single pixel circuit 210 and arranges the shared pixel circuit 210 to overlap with the photodiode PD. This facilitates the alignment of components formed on both the first substrate 100 and the second substrate 200, thereby enabling the manufacture of a high-quality and high-performance imaging device. Furthermore, an inherent structure produced using this manufacturing method can be achieved. In other words, a structure can be obtained by sequentially stacking the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200. In other words, a structure can be achieved by stacking the first substrate 100 and the second substrate 200 in a face-to-back manner. Additionally, through electrodes 120E and 121E may be provided, which penetrate the semiconductor layer 200S of the second substrate 200 and the wiring layer 100T of the first substrate 100 from the front side and reach the front side of the semiconductor layer 100S of the first substrate 100.

[0252] Regarding the structure obtained by providing a connection wiring in the first substrate 100 for interconnecting the floating diffuser portions FD of each of the plurality of pixels 541 and assembling them into a single connection wiring for interconnecting the VSS contact regions 118 of each of the plurality of pixels 541 and assembling them into a single connection wiring, when the structure and the second substrate 200 are stacked using the aforementioned first manufacturing method and a pixel circuit 210 is formed in the second substrate 200, the heat treatment required to form the active element included in the pixel circuit 210 may affect the connection wiring already formed in the first substrate 100.

[0253] Therefore, in order to solve the problem that heat treatment during the formation of the aforementioned active element affects the aforementioned connection wiring, it is preferable that the imaging device 1 according to this embodiment uses a conductive material with high heat resistance in the following two types of connection wiring: a connection wiring for interconnecting the floating diffuser portions FD of each of the plurality of pixels 541 and assembling them into one; and a connection wiring for interconnecting the VSS contact regions 118 of each of the plurality of pixels 541 and assembling them into one. Specifically, as a conductive material with high heat resistance, a material having a melting point higher than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200 can be used.

[0254] Thus, for example, the camera device 1 according to this embodiment includes the following structure: (1) a structure obtained by stacking the first substrate 100 and the second substrate 200 in a face-to-back manner (specifically, a structure obtained by sequentially stacking the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200); (2) a structure obtained by providing through electrodes 120E and 121E that penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 200 and reach the front side of the semiconductor layer 100S of the first substrate 100; and (3) a structure obtained by using a conductive material with high heat resistance to form a connecting wire for interconnecting the floating diffuser portions FD of a plurality of pixels 541 and assembling them into one wire, and a connecting wire for interconnecting the VSS contact areas 118 of a plurality of pixels 541 and assembling them into one wire. With this structure, it is possible to not have a large electrode at the interface between the first substrate 100 and the second substrate 200, and to provide in the first substrate 100 a connecting wire for interconnecting the floating diffuser portions FD of the plurality of pixels 541 and assembling them into a single wire, and a connecting wire for interconnecting the VSS contact areas 118 of the plurality of pixels 541 and assembling them into a single wire.

[0255] [Operation of Camera Device 1]

[0256] Next, refer to Figure 18 and Figure 19 To explain the operation of camera device 1. Figure 18 and Figure 19 Towards Figure 3 Arrows have been added. The arrows indicate the paths of the individual signals. Figure 18 Arrows are used to show the path from the external input to the input signal, power supply potential, and reference potential of the camera device 1. Figure 19Arrows indicate the signal path of pixel signals output from the imaging device 1 to the outside. For example, input signals (e.g., pixel clock and synchronization signals) input to the imaging device 1 via input unit 510A are transmitted to the row drive unit 520 of the third substrate 300, and a row drive signal is generated in the row drive unit 520. This row drive signal is transmitted to the second substrate 200 via contact units 301 and 201. Furthermore, this row drive signal reaches each pixel common unit 539 of the pixel array unit 540 via the row drive signal line 542 in the wiring layer 200T. The signals of the row drive signals that have reached the pixel common unit 539 of the second substrate 200, except for the drive signal of the transmission gate TG, are input to the pixel circuit 210, and drive each transistor included in the pixel circuit 210. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and drives pixels 541A, 541B, 541C and 541D. Figure 18 Additionally, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contacts 301 and 201, and supplied to the pixel circuit 210 of each pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, the pixel signals obtained by photoelectric conversion of each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 for each pixel common unit 539 via the through electrode 120E. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and contacts 202 and 302. After being processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, the pixel signal is output to the outside via the output unit 510B.

[0257] [Effect]

[0258] In this embodiment, adjustment portions 220A and 220B are respectively provided on the side and bottom surfaces of the semiconductor layer 200S. Pixel transistors (e.g., amplification transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) are arranged adjacent to through-wires (e.g., through electrodes 120E and 121E and through electrode TGV) and transistors (e.g., transmission transistor TR) disposed in the first substrate 100. This reduces, for example, the influence of the electric field from the through electrode TGV and the transmission transistor TR on the adjacent pixel transistors, thereby suppressing changes in transistor characteristics.

[0259] In an imaging device having a three-dimensional structure obtained by stacking a semiconductor substrate comprising multiple sensor pixels and a semiconductor substrate comprising signal processing circuitry for processing signals obtained from each sensor pixel, if the distance between the channel portion of a transistor formed in the upper semiconductor substrate and the adjacent through-line (TCS) is arranged to be relatively close (e.g., less than 0.25 μm), there is a concern that parasitic current paths may be generated in the transistor channel due to the bias applied to the TCS, potentially leading to degradation of transistor characteristics. Specifically, as... Figure 15A As shown, the threshold voltage Vth is offset in the negative direction.

[0260] To reduce the threshold voltage Vth offset, the distance between the through-line (TCS) and the transistor needs to be sufficiently ensured. As an example, the TCS needs to be approximately 100nm to 250nm separate from the transistor. This becomes a design constraint on pixel cell design (e.g., cell size less than 1μm). As mentioned above, by ensuring the distance between the TCS and the transistor, for example, if the cell size is set to 0.7μm, the area of ​​the semiconductor substrate that can be used to form the pixel circuit is reduced to approximately half.

[0261] In contrast, in the imaging device 1 according to this embodiment, for example, when the through electrode TGS is arranged near the select transistor SEL, an adjustment portion 220A is formed on the side of the semiconductor layer 200S that forms the channel of the select transistor SEL. Furthermore, for example, when the transmission transistor TR is arranged in the first substrate 100 near, for example, the select transistor SEL, an adjustment portion 220B is formed on the back side (surface S2) of the semiconductor layer 200S. For example, both adjustment portions 220A and 220B are formed from a p-type semiconductor region or a metal oxide film. This reduces the impact on the select transistor SEL when a bias voltage is applied to the through electrode TGS and the transmission transistor TR. Specifically, it increases the threshold voltage Vth of the parasitic transistor generated when a bias voltage is applied to the through electrode TGS and the transmission transistor TR, and reduces leakage current.

[0262] As described above, in this embodiment, adjustment portions 220A and 220B are provided on the sidewalls of the channels of pixel transistors (e.g., select transistors SEL) arranged adjacent to the through wiring (e.g., through electrode TGS) that forms a through-wire that penetrates the insulating region 212 along the thickness direction in the semiconductor layer 200S, and on the back surface (surface S2) of the semiconductor layer 200S, thereby reducing the impact on adjacent transistors when a bias voltage is applied to the aforementioned components. This reduces transistor characteristic degradation, such as leakage current in the transistors used to form the pixel circuit 210. Consequently, image quality can be improved. Furthermore, reliability can be improved.

[0263] Furthermore, in this embodiment, as described above, it is not necessary to ensure the distance between each through electrode 120E, 121E and through electrode TGS and the pixel transistors (e.g., amplification transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) in order to reduce the impact from adjacent through wirings (TCS). This improves area efficiency in the pixel cell design.

[0264] In this embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200). Compared to the case where pixels 541A, 541B, 541C, 541D and pixel circuit 210 are formed on the same substrate, this increases the area of ​​pixels 541A, 541B, 541C, 541D and pixel circuit 210. As a result, the amount of pixel signal obtained by photoelectric conversion can be increased, and the transistor noise of pixel circuit 210 can be reduced. Thereby, the signal-to-noise ratio of pixel signal can be improved, and the imaging device 1 can output better pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the imaging device 1 can be miniaturized). By reducing the pixel size, the imaging device 1 can increase the number of pixels per unit area and output images with high image quality.

[0265] Furthermore, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other via through electrodes 120E and 121E disposed in the insulating region 212. For example, methods such as connecting the first substrate 100 and the second substrate 200 to each other by bonding pad electrodes, and connecting the first substrate 100 and the second substrate 200 to each other using through wiring through the semiconductor layer (e.g., through-silicon via (TSV)). Compared to these methods, by providing through electrodes 120E and 121E in the insulating region 212, the area required to connect the first substrate 100 and the second substrate 200 to each other can be reduced. This allows for a reduction in pixel size, and thus a smaller size for the imaging device 1. Additionally, the area of ​​each pixel becomes finer. This allows for further improvement in resolution. Without requiring chip size miniaturization, the size of the areas forming pixels 541A, 541B, 541C, and 541D, as well as the area forming the pixel circuit 210, can be increased. As a result, the amount of pixel signal obtained through photoelectric conversion can be increased, and the noise of the transistors included in the pixel circuit 210 can be reduced. This improves the signal-to-noise ratio of the pixel signal and enables the imaging device 1 to output better pixel data (image information).

[0266] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are disposed on different substrates (the second substrate 200 and the third substrate 300). Compared to the case where the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the areas of the column signal processing unit 550 and the image signal processing unit 560 can be increased. This reduces noise generated in the column signal processing unit 550 and allows for the mounting of higher-performance image processing circuitry in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0267] Furthermore, in the imaging device 1, a pixel array section 540 is disposed in the first substrate 100 and the second substrate 200, and a column signal processing section 550 and an image signal processing section 560 are disposed in the third substrate 300. Additionally, contact sections 201, 202, 301, and 302, which connect the second substrate 200 and the third substrate 300, are formed above the pixel array section 540. This allows the contact sections 201, 202, 301, and 302 to be freely arranged without interference from the various wiring included in the pixel array. Therefore, contact sections 201, 202, 301, and 302 can be used when electrically connecting the second substrate 200 and the third substrate 300. Due to the use of contact sections 201, 202, 301, and 302, the degree of freedom in the layout of, for example, the column signal processing section 550 and the image signal processing section 560 is increased. This reduces noise generated in the column signal processing unit 550 and allows for the installation of a higher-performance image processing circuit in the image signal processing unit 560. Consequently, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0268] Furthermore, in the imaging device 1, the pixel separation section 117 penetrates the semiconductor layer 100S. Therefore, even when adjacent pixels (pixels 541A, 541B, 541C, and 541D) are closer together due to the miniaturization of each pixel area, color mixing between pixels 541A, 541B, 541C, and 541D can be suppressed. This improves the signal-to-noise ratio of the pixel signal and allows the imaging device 1 to output better pixel data (image information).

[0269] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel using a shared unit 539. Compared to the case where pixel circuits 210 are provided for each of pixels 541A, 541B, 541C, and 541D, this allows for a larger size of the forming region of the transistors (amplifier transistor AMP, reset transistor RST, select transistor SEL, and FD conversion gain switching transistor FDG) included in the pixel circuit 210. For example, by increasing the size of the forming region of the amplifier transistor AMP, noise can be suppressed. This improves the signal-to-noise ratio of the pixel signal and allows the imaging device 1 to output better pixel data (image information).

[0270] Furthermore, in the imaging device 1, the first substrate 100 is provided with pad portions 120 for electrically connecting the floating diffuser portions FD (floating diffuser portions FD1, FD2, FD3, and FD4) of four pixels (pixels 541A, 541B, 541C, and 541D) to each other. Compared to the case where such pad portions 120 are provided in the second substrate 200, this reduces the number of through electrodes (through electrodes 120E) used to connect the first substrate 100 and the second substrate 200. Therefore, the insulating region 212 can be reduced in size, and the formation region (semiconductor layer 200S) of the transistors included in the pixel circuit 210 can be ensured to be of sufficient size. This reduces the noise of the transistors included in the pixel circuit 210 and improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0271] Furthermore, in this embodiment, an example has been described regarding the second substrate 200 in which the amplifying transistor AMP, the reset transistor RST, and the select transistor SEL included in the pixel circuit 210 are formed in a single semiconductor layer 200S. However, at least one transistor may be formed in semiconductor layer 200S-1, and the remaining transistors may be formed in semiconductor layer 200S-2, which is different from semiconductor layer 100S and semiconductor layer 200S-1. Although semiconductor layer 200S-2 is not shown, for example, an insulating layer, a connection portion, and a connection wiring may be formed on semiconductor layer 200S-1 (equivalent to semiconductor layer 200S), and then semiconductor layer 200S-2 may be stacked. This new semiconductor layer 200S-2 may be stacked on the surface of the interlayer insulating film 123 opposite to the surface stacked on semiconductor layer 100S, and thereby the desired transistors can be formed. As an example, an amplification transistor AMP can be formed in semiconductor layer 200S-1, and a reset transistor RST and / or a selection transistor SEL can be formed in semiconductor layer 200S-2.

[0272] Additionally, multiple new semiconductor layers can be provided, and each of them can contain the transistors required for the pixel circuit 210. As an example, an amplification transistor AMP can be formed in semiconductor layer 200S-1. Furthermore, if an insulating layer, a connection portion, and a connection wiring are stacked on semiconductor layer 200S, and then a semiconductor layer 200S-2 is further stacked, a reset transistor RST can be formed in semiconductor layer 200S-2. Moreover, if an insulating layer, a connection portion, and a connection wiring are stacked on semiconductor layer 200S-2, and then a semiconductor layer 200S-3 is further stacked, a selection transistor SEL can be formed in semiconductor layer 200S-3. The transistors formed in semiconductor layers 200S-1, 200S-2, and 200S-3 can be any of the transistors included in the pixel circuit 210.

[0273] In this way, by constructing multiple semiconductor layers in the second substrate 200, the area occupied by a pixel circuit 210 in the semiconductor layer 200S can be reduced. The chip area can be reduced by miniaturizing the area of ​​each pixel circuit 210 or each transistor. Furthermore, the area of ​​the desired transistors, such as the amplifying transistor, reset transistor, and select transistor that may be included in the pixel circuit 210, can be increased. In particular, by increasing the area of ​​the amplifying transistor, a noise reduction effect can be expected.

[0274] It should be noted that even when the pixel circuit 210 is formed separately in multiple semiconductor layers (e.g., semiconductor layers 200S-1, 200S-2, and 200S-3) as described above, if the through electrode (e.g., through electrode TGS) is arranged near the pixel transistor provided in each semiconductor layer, adjustment portions 220A and 220B can be provided on the side of the channel of the semiconductor layer that forms the pixel transistor and on the back of the semiconductor layer, respectively.

[0275] The second and third embodiments, as well as variations 1 to 8, will be described below. Hereinafter, elements similar to those in the first embodiment described above will be given the same reference numerals, and their descriptions will be omitted as appropriate.

[0276] <2. Variation Example 1>

[0277] Figure 20A The diagram schematically illustrates the cross-sectional structure of the electrical connection portion and its surrounding area, taken through the through wiring, in the main parts of the imaging device (imaging device 1A) according to the modified example (modified example 1) of the first embodiment described above, namely the first substrate 100 and the second substrate 200. Figure 20B Schematic illustration along with Figure 20AThe structure of the camera device 1A, which is cut from different cross sections. Figure 21 An example of the planar structure in the horizontal direction of the second substrate 200 of the imaging device 1A is schematically shown. It should be noted that... Figure 20A It shows along Figure 21 The cross-section shown is taken from line III-III, and Figure 20B It shows along Figure 21 The cross-section shown is taken from line IV-IV. The imaging device 1A according to this modified example is obtained by providing an adjustment part 220A on the side of the semiconductor layer 200S where a component separation region 213 having, for example, an STI structure is formed.

[0278] For example, the adjustment section 220A according to this modification can be formed by ion implantation using the gate of a pixel transistor, such as an amplifying transistor AMP and a reset transistor RST, as a mask. Therefore, for example, as... Figure 21 As shown, the adjustment section 220A is continuously provided in a manner that surrounds the semiconductor layer 200S.

[0279] Additionally, for example, the adjustment section 220A according to this modification is electrically connected to the ground (GND) electrode and is connected to the p-well layer 215 formed in the semiconductor layer 200S. This reduces the impact on the pixel transistor when a bias voltage is applied to a transistor (e.g., a transmission transistor TR) formed in the first substrate 100.

[0280] For example, the camera device 1A according to this modified example can be manufactured in the following manner. Figure 22A and Figure 22B Each example shows the manufacturing steps of the adjustment section 220A.

[0281] First, as described in the first embodiment above, the semiconductor layer 200S bonded to the first substrate 100 is divided to form an insulating region 212 and a component separation region 213. Subsequently, as... Figure 22A As shown, the gate 210G of the pixel transistor is formed on the front side (surface S1) of the semiconductor layer 200S, and ion implantation is performed using the gate 210G as a mask. Thus, as... Figure 22B As shown, adjustment portions 220A are formed at both ends of the gate 210G in the planar view by self-alignment.

[0282] Alternatively, for example, the camera device 1A according to this modified example can also be manufactured in the following manner. Figures 23A to 23C Each shows another example of the manufacturing process of the adjustment section 220A.

[0283] First, as described in the first embodiment above, the semiconductor layer 200S bonded to the first substrate 100 is divided to form an insulating region 212 and a component separation region 213. Subsequently, as... Figure 23A As shown, a conductive film 210X, which will become the gate 210G, is formed on the semiconductor layer 200S, the insulating region 212, and the component separation region 213. Then, for example, as... Figure 23B As shown, a patterned resist film PR1 is formed on the conductive film 210X.

[0284] Next, as Figure 23C As shown, for example, the conductive film 210X was etched, and then ion implantation was performed using the conductive film 210X and the resist film PR1 on the conductive film 210X as a mask. Thus, as... Figure 23D As shown, adjustment portions 220A are formed at both ends of the gate 210G in the plan view through self-alignment.

[0285] Subsequently, for example, after removing the resist film PR1, such as Figure 23E As shown, a resist film PR2 corresponding to the gate 210G of each pixel transistor is formed on the conductive film 210X. For example, the conductive film 210X is patterned by etching to form the gate 210G.

[0286] As described above, the adjustment section 220A is formed using the conductive film 210X and the resist film PR used to form the gate 210G as masks, thereby making it easy to adjust the depth of ion implantation.

[0287] Thus, in this modified example, the adjustment portion 220A is formed by ion implantation using the gate 210G of the pixel transistor (e.g., amplifying transistor AMP, reset transistor RST, select transistor SEL, and FD conversion gain switching transistor FDG) disposed in the semiconductor layer 200S as a mask. Therefore, in addition to the effects of the first embodiment described above, the adjustment portion 220A can be locally formed within a narrow range between the gate 210G and the element separation region 213.

[0288] <3. Second Embodiment>

[0289] Figure 24 An example of the cross-sectional structure of the electrical connection portion cut through the through wiring is shown schematically in the main parts of the imaging device (imaging device 2) according to the second embodiment of the present invention, namely the first substrate 100 and the second substrate 200. Figure 25 schematically shown Figure 24 The planar shape of the selection transistor SEL is shown. Figure 26Another example of the cross-sectional structure of the imaging device 2 according to a second embodiment of the present invention is shown schematically. It should be noted that... Figure 24 and Figure 26 Each of them showed along Figure 25 The image capture device 2 shown is a cross-section of the camera device 2 as captured by the VV line. In the camera device 2 according to this embodiment, the end of the gate 210G of the pixel transistor (e.g., the select transistor SEL) located on the through-wire side, or the two opposite ends of the gate 210G, which are arranged adjacent to the through-wire (e.g., the through electrode TGV), is buried in an insulating film (e.g., the element separation region 213) disposed around the pixel transistor. The through-wire (e.g., the through electrode TGV) electrically connects the first substrate 100 and the second substrate 200 to each other.

[0290] The cross-sectional shape of the gate 210G, for example, the width (W) of the gate 210G facing the front side (Table S1) of the semiconductor layer 200S and the height (H) of the end of the gate 210G buried in the element separation region 213 (buried portion 210B), can also extend to the back side of the semiconductor layer 200S, for example, through the semiconductor layer 200S. Specifically, the cross-sectional shape of the gate 210G can adopt the pattern described below according to the structure of the pixel transistor.

[0291] For example, when the pixel transistor has a planar structure, in order to adjust the threshold voltage Vth, in most cases a channel injection (n) is formed at the corresponding location in the semiconductor layer 200S. - or p - (Active region 214) and p-well injection (p-well layer 215). In this case, for example, as Figure 27 As shown, preferably, the cross-sectional shape of the gate 210G conforms to the condition that width (W) > height (H). In the above configuration, preferably, the bottom surface of the buried portion 210B is formed at the channel injection (n - or p - The injection peak (Rp) of the p-well is located below the p-well. This allows the channel (current path or electron channel) to be partially surrounded by the gate 210G, and the gate 210G to act as a shield. Therefore, the effect of the bias voltage applied to the through electrode TGV is reduced. Additionally, as... Figure 28 As shown, the cross-sectional shape of the gate 210G can also conform to the condition that width (W) ≤ height (H).

[0292] For example, such as Figure 29As shown, when an undoped layer 216 is formed on the p-well layer 215, it is preferable that the cross-sectional shape of the gate 210G conforms to, for example, width (W) ≤ height (H). In the above configuration, preferably, the bottom surface of the buried portion 210B is formed above the bottom surface of the undoped layer 216 and the implantation peak position (Rp) of the p-well. This improves transconductance gm and noise characteristics. It should be noted that the p-well layer 215 may not exist below the bottom surface of the buried portion 210B. Furthermore, as... Figure 30 As shown, the cross-sectional shape of the gate 210G can conform to the condition that width (W) > height (H).

[0293] For example, Figure 24 The camera device 2 shown can be manufactured in the following manner. Figures 31A to 31F Examples of manufacturing steps for pixel transistors (e.g., selection transistors SELs) and through wiring according to this embodiment are shown.

[0294] First, the semiconductor layer 200S is bonded to the first substrate 100 (interlayer insulating film 123) through the bonding film 124, and the thickness of the semiconductor layer 200S is reduced as needed. Then, as... Figure 31A As shown, the semiconductor layer 200S is divided to form an insulating region 212 and a device separation region 213. Subsequently, a p-well layer 215 is formed in the semiconductor layer 200S, and then channel implantation is performed to form an active region 214.

[0295] Subsequently, as Figure 31B As shown, a resist film PR is patterned on the semiconductor layer 200S, the insulating region 212, and the device separation region 213. Then, for example, the implantation permeation film (e.g., a silicon oxide film not shown) used during channel implantation is removed by wet etching using hydrofluoric acid. At the same time, a portion of the device separation region 213 extending from the resist film PR is also removed, thereby forming an opening 213H.

[0296] Next, remove the resist film PR, and then, as... Figure 31C As shown, for example, thermal oxidation is used to oxidize the front side (surface S1) and the side surface within the opening 213H of the semiconductor layer 200S exposed due to the removal of the implantation permeation film and the element separation region 213, thereby forming an insulating film 223.

[0297] Subsequently, as Figure 31D As shown, for example, a polysilicon (Poly Si) film to be the gate 210G is formed on the insulating region 212, the device separation region 213, and the insulating film 223 in a manner that fills the opening 213H using chemical vapor deposition (CVD). Next, as... Figure 31EAs shown, a resist film PR is patterned on polysilicon and then etched. This forms a gate 210G with one end buried in the device separation region 213.

[0298] Subsequently, as Figure 31F As shown, for example, a passivation film 221 and an interlayer insulating film 222 are formed on the insulating region 212, the device separation region 213, and the gate 210G using CVD. Then, the front side of the interlayer insulating film 222 is planarized, for example, by chemical mechanical polishing (CMP). Afterwards, through-holes, for example, reaching the semiconductor layer 100S, are formed at predetermined locations on the interlayer insulating film 222, and these through-holes are filled, for example, with tungsten (W). In this way, a through-wire is formed (e.g., Figure 24 The through-electrode TGV is shown.

[0299] For example, Figure 26 The camera device 2 shown can also be manufactured in the following manner. Figures 32A to 32E Examples of manufacturing steps for pixel transistors (e.g., selection transistors SELs) and through wiring according to this embodiment are shown.

[0300] First, following the manufacturing method of the imaging device 2 described above, a p-well layer 215 is formed in the semiconductor layer 200S, and then channel implantation is performed to form an active region 214. Subsequently, as... Figure 32A As shown, a photoresist film PR is patterned on the semiconductor layer 200S, the insulating region 212, and the device separation region 213. Then, for example, the implantation permeation film (e.g., a silicon oxide film not shown) used during channel implantation and a portion of the device separation region 213 extending from the photoresist film PR are removed by wet etching using hydrofluoric acid.

[0301] Next, remove the resist film PR, and then, as... Figure 32B As shown, for example, thermal oxidation is used to oxidize the front side (surface S1) and the side surface within the opening 213H of the semiconductor layer 200S exposed due to the removal of the implantation permeation film and the element separation region 213, thereby forming an insulating film 223.

[0302] Subsequently, as Figure 32C As shown, for example, a polysilicon (Poly Si) film to become the gate 210G is formed on the insulating region 212, the component separation region 213, and the insulating film 223 by CVD in a manner that fills the opening 213H. Then, for example, a 1×10⁻⁶ polysilicon film is applied using phosphorus (P), arsenic (As), or boron (B). 15 cm -2 Up to 5×10 15 cm -2The doping level is used for channel implantation to make the polysilicon (PolySi) n-type or p-type, thereby forming the gate 210G. Next, as Figure 32D As shown, a resist film PR is patterned on polysilicon and then etched. This forms a gate 210G with its two ends buried in the device separation region 213.

[0303] Subsequently, as Figure 32E As shown, for example, a passivation film 221 and an interlayer insulating film 222 are formed on the insulating region 212, the device separation region 213, and the gate 210G by CVD. Then, for example, the front side of the interlayer insulating film 222 is planarized by CMP. Afterwards, for example, a through-hole reaching the semiconductor layer 100S is formed at a predetermined location on the interlayer insulating film 222, and the through-hole is filled, for example, with tungsten (W). Herein, a through-wire is formed (e.g., Figure 26 The through-electrode TGV is shown.

[0304] For example, Figure 26 The camera device 2 shown can also be manufactured in the manner described below. Figures 33A to 33F Each illustrates another example of the manufacturing steps for the pixel transistor (e.g., the selection transistor SEL) and the through wiring according to this embodiment.

[0305] First, following the manufacturing method of the imaging device 2 described above, a p-well layer 215 is formed in the semiconductor layer 200S. Then, as described above... Figure 33A As shown, channel injection is performed to form active region 214. Subsequently, as... Figure 33B As shown, for example, the implantation permeable membrane (e.g., silicon oxide film not shown) used during channel implantation, as well as the device separation region 213 and the insulating region 212, are removed by wet etching using hydrofluoric acid up to a predetermined depth.

[0306] Next, as Figure 33C As shown, for example, thermal oxidation is used to oxidize the front side (surface S1) of the semiconductor layer 200S exposed due to the removal of the implantation permeation film and the element separation region 213, as well as the side side of the semiconductor layer 200S exposed due to wet etching, thereby forming an insulating film 223.

[0307] Subsequently, as Figure 33D As shown, for example, a polysilicon (Poly Si) film to be the gate 210G is formed on the insulating region 212, the device separation region 213, and the insulating film 223 by CVD. Next, as... Figure 33E As shown, a resist film PR is patterned on polysilicon and then etched. This forms a gate 210G whose two ends are buried in the device separation region 213.

[0308] Subsequently, as Figure 33F As shown, for example, a passivation film 221 and an interlayer insulating film 222 are formed on the insulating region 212, the device separation region 213, and the gate 210G by CVD. Then, for example, the front side of the interlayer insulating film 222 is planarized by CMP. Afterwards, for example, a through-hole reaching the semiconductor layer 100S is formed at a predetermined location on the interlayer insulating film 222, and the through-hole is filled with tungsten (W) for example. This forms a through-wire (e.g., Figure 26 The through-electrode TGV is shown.

[0309] As described above, in this embodiment, the end of the gate 210G of a pixel transistor (e.g., an amplifying transistor AMP, a reset transistor RST, a select transistor SEL, and an FD conversion gain switching transistor FDG) adjacent to the through-wire (e.g., through electrodes 120E and 121E and through electrode TGV) that is arranged near the through-wire (e.g., through electrodes 120E and 121E and through electrode TGV) is buried in an insulating film (e.g., element separation region 213) disposed around the pixel transistor. This reduces, for example, the influence of the electric field from the through-wire such as the through electrode TGV, and suppresses variations in the transistor characteristics of the pixel transistor.

[0310] As described above, in a camera device having a three-dimensional structure obtained by stacking a semiconductor substrate comprising a plurality of sensor pixels and a semiconductor substrate comprising signal processing circuitry for processing signals obtained from each sensor pixel, transistors formed in the upper semiconductor substrate may generate leakage current due to the application of a bias voltage to the through wiring.

[0311] The leakage current is caused by the front side of the semiconductor substrate adjacent to the through wiring entering a reverse state, thus forming a current leakage path. The leakage current caused by the above reason is particularly significant in select transistors such as SELs, which are generally constructed as depletion-type transistors with a large doping level in transistors (pixel transistors) used to form signal processing circuits.

[0312] In contrast, in the imaging device 2 according to this embodiment, for example, the select transistor SEL arranged adjacent to the through electrode TGV employs a generally Fin-type transistor structure. That is, it is a structure obtained by burying the end of the gate 210G adjacent to the through electrode TGV, or both ends of the gate 210G (including the end adjacent to the through electrode TGV and the end opposite to the gate end) in the element separation region 213. This reduces the impact on the select transistor SEL when a bias voltage is applied to the through electrode TGV, and reduces transistor characteristic degradation such as leakage current. Therefore, image quality can be improved. Furthermore, reliability can also be improved.

[0313] Furthermore, to reduce the impact on adjacent pixel transistors caused by applying bias voltage to the through wiring, this can be achieved, for example, by placing a bias voltage in the active region of the pixel transistor, such as... Figure 34 As shown, for example, a p-type semiconductor region (adjustment portion 220A) is formed on the side of the semiconductor layer 200S opposite to the through electrode TGV, as in the first embodiment described above. However, due to the formation of this p-type semiconductor region, the width of the active region (channel width (W)) will correspondingly become narrower. Therefore, when considering the design of the transistor's channel width (W) / channel length (L), concerns may arise about the resulting increase in transistor size.

[0314] In contrast, in this embodiment, the end of the gate 210G is buried in an insulating film formed around the semiconductor layer 200S, such as the element separation region 213. This reduces the impact on the pixel transistor when a bias voltage is applied to adjacent through-wires without changing the occupied area. Therefore, area efficiency in the pixel unit design can be improved.

[0315] It should be noted that even when the pixel circuit 210 is separately formed on multiple semiconductor layers (e.g., semiconductor layers 200S-1, 200S-2, and 200S-3) as described in the first embodiment above, the ends of the gates of each pixel transistor can be buried in an insulating film (element separation region) formed around each semiconductor layer. This further improves the area efficiency in the pixel unit design.

[0316] <4. Third Embodiment>

[0317] Figure 35 This is a plan view schematically illustrating an example of the positional relationship between a through wiring (e.g., a through electrode TGV) that is a major part of the imaging device 1 according to a third embodiment of the present invention and the gate 210G of a pixel transistor arranged adjacent to the through electrode TGV. Figure 36Schematic illustration along Figure 35 The cross-sectional structure of the camera device 1, as shown by the VI-VI line, is illustrated. For example, as... Figure 35 As shown, a through-wire (e.g., through electrodes 120E and 121E and through electrode TGV) that penetrates the insulating region 212 along the thickness direction and serves to electrically connect the first substrate 100 and the second substrate 200 to each other is arranged such that, in the plan view, the center line B of the through-wire has a position different from that of the center line A. The center line A equally divides the gate 210G of the pixel transistor along its extension direction. The center line B equally divides the through electrode TGV. The positional relationship between the through-wire (e.g., through electrode TGV) and the gate 210G of the pixel transistor arranged adjacent to the through electrode TGV will be described in detail below.

[0318] Figure 37 This is a plan view schematically illustrating another example of the positional relationship between the through electrode TGV and the gate 210G of the pixel transistor in this embodiment. Figure 38 Schematic illustration along Figure 37 The cross-sectional structure of the camera device 1 shown is taken along line VII-VII. Figure 39 The relationship between the distance between the through electrode TGV and the gate 210G and the threshold voltage ΔVth of the pixel transistor is shown when the center line of the through wiring (e.g., the center line B of the through electrode TGV) and the center line A of the gate 210G of the pixel transistor coincide with each other. Figure 40 The relationship between the offset of the center line B of the through electrode TGV relative to the center line A of the gate 210G and the threshold voltage ΔVth of the pixel transistor is shown when the gate length is 500 nm and the direct distance between the through electrode TGV and the gate 210G is 100 nm.

[0319] like Figure 39 As shown, for example, the effect of a bias applied to the through electrode TGV on a pixel transistor arranged nearby can be reduced by offsetting the center line B of the through electrode TGV relative to the center line A of the gate 210G of the pixel transistor.

[0320] However, as Figure 40 As shown, depending on whether the center line B of the through electrode TGV is offset relative to the center line A of the gate 210G in the direction of the source 210S side of the pixel transistor or in the direction of the drain 210D side of the pixel transistor, the effect is very different.

[0321] For example, when the center line B of the through electrode TGV is offset between the center of the gate 210G in the extending direction and the end face of the gate 210G on the source 210S side, the threshold voltage ΔVth of the pixel transistor is less than the threshold voltage ΔVth when the center line A of the gate 210G and the center line B of the through electrode TGV coincide. On the other hand, when the center line B of the through electrode TGV is offset between the center of the gate 210G in the extending direction and the end face of the gate 210G on the drain 210D side, the threshold voltage ΔVth of the pixel transistor is greater than the threshold voltage ΔVth when the center line A of the gate 210G and the center line B of the through electrode TGV coincide.

[0322] In other words, preferably, the through electrode TGV is offset in a way that reduces the effect of the electric field on pixel transistors arranged in adjacent locations. Specifically, preferably, the through electrode TGV is offset in a way that reduces the effect of the electric field on the channel of the pixel transistors arranged in adjacent locations. For example, as Figure 41 As shown, the area surrounding the pixel transistor is divided into five regions, and the influence of the electric field on the channel of the pixel transistor is reduced by arranging the through electrode TGV in regions X2, X3, X4, and X5, excluding region X1. Furthermore, among regions X2, X3, X4, and X5, region X3 is more preferred than region X2, region X4 is more preferred than region X3, and region X5 is the most preferred on the extension line of the source 210S or drain 210D of the pixel transistor.

[0323] As described above, in the pixel transistors used to form the pixel circuit 210 in the second substrate 200 and the through wiring used to electrically connect the first substrate 100 and the second substrate 200 to each other, the through wiring is preferably arranged in a way that can reduce the influence of the electric field on the pixel transistors arranged nearby. Specifically, the through wiring is preferably arranged away from the channel of the pixel transistor.

[0324] As an example, as described below Figure 49 In the illustrated layout, for example, the through electrode TGV3 is preferably offset closer to the drain side of the select transistor SEL. For example, in the select transistor SEL, a 10% concentration is formed on the side of the semiconductor layer 200S adjacent to the through electrode TGV3. 15 cm -3 Above and 10 17 cm -3In the case of the following impurity regions (e.g., adjustment section 220A), it is preferable to arrange the transistor in such a way that the shortest distance between the center line B of the through electrode TGV3 and the center line A of the gate of the select transistor SEL is 100 nm or more. Furthermore, it is preferable to arrange the transistor in such a way that the shortest distance between the gate of the select transistor SEL and the through electrode TGV3 is 250 nm or more. This reduces the impact on the select transistor SEL when a bias voltage is applied to the through electrode TGV3. Moreover, by arranging the through electrode TGV3 on the extension lines of the source and drain of the select transistor SEL, the n-type diffusion region constituting the source or drain becomes a barrier, thereby substantially negligible the impact on the select transistor SEL when a bias voltage is applied to the through electrode TGV3.

[0325] As described above, in this embodiment, the through wiring (e.g., through electrodes 120E and 121E and through electrode TGV) that penetrates the insulating region 212 along the thickness direction and electrically connects the first substrate 100 and the second substrate 200 to each other is offset in position to reduce the electric field on the channels of the adjacently arranged pixel transistors, or more specifically, to reduce the influence of the electric field on the channels of the adjacently arranged pixel transistors. Specifically, it is arranged such that, in a plan view, the center line B that equally divides the through electrode TGV is located at a position different from the center line A that equally divides the gate 210G of the pixel transistors along the extension direction. This reduces the influence on the adjacently arranged pixel transistors when a bias voltage is applied to the through wiring and prevents changes in transistor characteristics. Therefore, image quality can be improved. Furthermore, reliability can be improved.

[0326] It should be noted that even in the case where the pixel circuit 210 is separately formed in multiple semiconductor layers (e.g., semiconductor layers 200S-1, 200S-2 and 200S-3) as described in the first embodiment above, the position of the through wiring can be offset, thereby reducing the influence of the electric field on the channel of the pixel transistor disposed in each semiconductor layer.

[0327] It should be noted that this embodiment has been described using the case where the pixel transistor is NMOS as an example, but this technology is also applicable to the case where the pixel transistor is PMOS. Similar effects can be obtained.

[0328] <5. Variation Example 2>

[0329] Figures 42 to 46 Each example shows a variation of the planar structure of the camera device 1 according to the foregoing embodiment. Figure 42The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 43 The diagram schematically illustrates the structure of the first wiring layer W1 and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 44 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to that described in the foregoing embodiments. Figure 10 . Figure 45 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 46 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0330] In this variation, such as Figure 43 As shown, the internal layout of one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (e.g., the right side of the paper in this figure) is constructed by reversing the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper in this figure) only in the H direction. Furthermore, the offset in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is greater than that in the aforementioned embodiment (…). Figure 9 The offset described in the diagram is larger. Thus, by increasing the offset in the V direction, the amplifying transistor AMP of the other pixel shared unit 539 and the pad portion 120 connected to it are made larger. Figure 7B The distance between the pad portion 120 of the other pixel-shared unit (the lower side of the paper in the figure) in the two pixel-shared units arranged in the V direction as described in the figure is reduced. Using this layout, in Figures 42 to 46 In the modified example 2 of the imaging device 1 shown, it is not necessary to reverse the planar layout of the two pixel sharing units 539 arranged in the H direction relative to each other in the V direction to make the pixel sharing units 539 have the same area as the pixel sharing units 539 of the second substrate 200 described in the previous embodiment. It should be noted that the planar layout of the pixel sharing units 539 of the first substrate 100 is the same as the planar layout described in the previous embodiment (…). Figure 7A and Figure 7BThe same applies. This allows the camera device 1 according to this variation to achieve an effect similar to that of the camera device 1 described in the foregoing embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the foregoing embodiments and this variation.

[0331] <6. Variation Example 3>

[0332] Figures 47 to 52 Each example shows a variation of the planar structure of the camera device 1 according to the foregoing embodiment. Figure 47 The planar structure of the first substrate 100 is schematically shown, and corresponds to that described in the foregoing embodiments. Figure 7A . Figure 48 The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 49 The diagram schematically illustrates the structure of the first wiring layer W1 and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 50 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to that described in the foregoing embodiments. Figure 10 . Figure 51 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 52 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0333] In this modified example, each pixel circuit 210 has a roughly square planar shape. Figure 48 (etc.). In this respect, the planar structure of the camera device 1 according to this modification is different from the planar structure of the camera device 1 described in the foregoing embodiments.

[0334] For example, the pixel sharing unit 539 of the first substrate 100 is formed as described in the foregoing embodiments, spanning a pixel region of two rows × two columns. This pixel sharing unit 539 has a generally square planar shape. Figure 47For example, in each pixel sharing unit 539, the horizontal portions TGb of the transmission gates TG1 and TG3 of pixels 541A and 541C in one pixel column extend in the H direction toward the central portion of the pixel sharing unit 539 from the position where they overlap with the vertical portions TGa (more specifically, toward the outer edges of pixels 541A and 541C, and toward the central portion of the pixel sharing unit 539). Similarly, the horizontal portions TGb of the transmission gates TG2 and TG4 of pixels 541B and 541D in another pixel column extend in the H direction toward the outer side of the pixel sharing unit 539 from the position where they overlap with the vertical portions TGa (more specifically, toward the outer edges of pixels 541B and 541D, and toward the outer side of the pixel sharing unit 539). The pad portion 120 connected to the floating diffuser FD is provided at the central portion of the pixel common unit 539 (the central portion of the pixel common unit 539 in the H direction and V direction), and the pad portion 121 connected to the VSS contact area 118 is at least in the H direction ( Figure 47 In the middle, it is located at the end of the pixel sharing unit 539 in both the H and V directions.

[0335] As another arrangement example, it is also possible to arrange the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 only in the region opposite to the vertical portion TGA. In this case, as explained in the previous embodiment, the semiconductor layer 200S is easily divided into finer segments. Therefore, it is difficult to form the transistors in the pixel circuit 210 to be large. On the other hand, if the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 extend along the H direction from the position overlapping with the vertical portion TGA as in the above-described variation, the width of the semiconductor layer 200S can be increased as explained in the previous embodiment. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transmission gates TG1 and TG3 in the H direction can be arranged close to the position of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transmission gates TG2 and TG4 in the H direction can be arranged close to the position of the through electrode 121E in the H direction. Figure 49 Therefore, as explained in the foregoing embodiments, the width (dimension in the H direction) of the semiconductor layer 200S extending along the V direction can be increased. Consequently, the size of the transistors in the pixel circuit 210 can be increased, especially the size of the amplifying transistor AMP. As a result, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0336] For example, the pixel common unit 539 of the second substrate 200 has approximately the same dimensions as the pixel common unit 539 of the first substrate 100 in both the H and V directions. For example, the pixel common unit 539 of the second substrate 200 is configured to span a region corresponding to approximately two rows × two columns of pixel regions. For example, in each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged in the V direction within a semiconductor layer 200S extending in the V direction. The FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the V direction within a semiconductor layer 200S extending in the V direction. The semiconductor layer 200S containing the selection transistor SEL and the amplification transistor AMP, and the semiconductor layer 200S containing the FD conversion gain switching transistor FDG and the reset transistor RST, are arranged in the H direction separated by an insulating region 212. This insulating region 212 extends in the V direction ( Figure 48 ).

[0337] Here, refer to Figure 48 and Figure 49 To illustrate the shape of the pixel sharing unit 539 of the second substrate 200, for example, Figure 47 The pixel sharing unit 539 of the first substrate 100 shown is connected to one side of the pad portion 120 located in the H direction. Figure 49 The amplifying transistor AMP and the selecting transistor SEL are located on the left side of the paper, and are connected to the other side of the pad portion 120 in the H direction. Figure 49 The FD conversion gain switching transistor FDG and the reset transistor RST are located on the right side of the paper. The shape of the pixel common unit 539 of the second substrate 200, which includes the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST, is determined by the following four outer edges.

[0338] The first outer edge is one end of the semiconductor layer 200S containing the selection transistor SEL and the amplification transistor AMP in the V direction. Figure 49 The outer edge is located at the upper end of the paper surface. This first outer edge is provided at the amplifying transistor AMP that constitutes the pixel sharing unit 539 and the side of the pixel sharing unit 539 in the V direction ( Figure 49 On the upper side of the paper, between the selection transistors SEL of adjacent pixel shared units 539. More specifically, the first outer edge is located at the central portion of the element separation region 213 between the amplifying transistor AMP and the selection transistor SEL in the V direction. The second outer edge is the other end of the semiconductor layer 200S containing the selection transistor SEL and the amplifying transistor AMP in the V direction. Figure 49The outer edge is located at the lower end of the paper surface. This second outer edge is disposed on the selection transistor SEL for constituting the pixel common unit 539 and on the other side in the V direction for constituting the pixel common unit 539. Figure 49 The second outer edge is located between the amplifying transistors AMP of adjacent pixel-shared units 539 (on the underside of the paper). More specifically, the second outer edge is located at the central portion of the element separation region 213 between the select transistor SEL and the amplifying transistor AMP in the V direction. The third outer edge is the other end of the semiconductor layer 200S containing the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction. Figure 49 The outer edge is located at the lower end of the paper. This third outer edge is provided at the FD conversion gain switching transistor FDG used to form the pixel shared unit 539 and the other side in the V direction used to form the pixel shared unit 539. Figure 49 The third outer edge is located between the reset transistors RST of adjacent pixel shared units 539 (on the underside of the paper). More specifically, the third outer edge is located at the central portion of the component separation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST in the V direction. The fourth outer edge is one end of the semiconductor layer 200S containing the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction. Figure 49 The fourth outer edge is located at the outer edge of the end on the upper side of the paper surface. This fourth outer edge is provided at the reset transistor RST for constituting the pixel common unit 539 and the side (in the V direction) for constituting the pixel common unit 539. Figure 49 The fourth outer edge is located between the FD conversion gain switching transistor FDG (not shown) of adjacent pixel shared units 539 on the upper side of the paper. More specifically, the fourth outer edge is located at the central portion of the element separation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction.

[0339] In the pixel common unit 539 of the second substrate 200, which includes such first, second, third, and fourth outer edges, the third and fourth outer edges are arranged in a manner offset to one side in the V direction relative to the first and second outer edges (i.e., offset to one side in the V direction). Using this arrangement, the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close as possible to the pad portion 120. This reduces the area of ​​the wiring used to connect them and facilitates miniaturization of the imaging device 1. It should be noted that the VSS contact region 218 is disposed between the semiconductor layer 200S containing the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S containing the reset transistor RST and the FD conversion gain switching transistor FDG. For example, multiple pixel circuits 210 have the same arrangement.

[0340] The imaging device 1 equipped with this second substrate 200 can also achieve effects similar to those described in the foregoing embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the foregoing embodiments and this variation.

[0341] <7. Variation Example 4>

[0342] Figures 53 to 58 Each example shows a variation of the planar structure of the camera device 1 according to the foregoing embodiment. Figure 53 The planar structure of the first substrate 100 is schematically shown, and corresponds to that described in the foregoing embodiments. Figure 7B . Figure 54 The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 55 The diagram schematically illustrates the structure of the first wiring layer W1 and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 56 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to that described in the foregoing embodiments. Figure 10 . Figure 57 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 58 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0343] In this modified example, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( Figure 55 In other words, this roughly corresponds to making the above... Figure 48 The structure is obtained by rotating the planar structure of the camera device 1 shown by 90 degrees.

[0344] For example, the pixel sharing unit 539 of the first substrate 100 is formed as described in the foregoing embodiments, spanning a pixel region of two rows × two columns. This pixel sharing unit 539 has a generally square planar shape. Figure 53For example, in each pixel shared unit 539, the transmission gates TG1 and TG2 of pixels 541A and 541B in one pixel row extend toward the central portion of the pixel shared unit 539 in the V direction. The transmission gates TG3 and TG4 of pixels 541C and 541D in another pixel row extend toward the outer direction of the pixel shared unit 539 in the V direction. The pad portion 120 connected to the floating diffuser FD is provided at the central portion of the pixel shared unit 539, and the pad portion 121 connected to the VSS contact area 118 extends at least in the V direction ( Figure 53 In this case, the positions of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 in the V direction are closer to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 of the transmission gates TG3 and TG4 in the V direction are closer to the position of the through electrode 121E in the V direction. Figure 55 For reasons similar to those described in the foregoing embodiments, the width (dimension in the V direction) of the semiconductor layer 200S extending along the H direction can be increased. This allows the amplifying transistor AMP to have a larger size and enables noise suppression.

[0345] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL in the V direction, separated by an insulating region 212. Figure 54 The FD conversion gain switching transistor FDG and the reset transistor RST are arranged in a symmetrical configuration along the H direction. The VSS contact region 218 is arranged in an island-like configuration within the insulating region 212. For example, the third wiring layer W3 extends along the H direction (…). Figure 57 ), and the fourth wiring layer W4 extends along the V direction ( Figure 58 ).

[0346] The imaging device 1 equipped with this second substrate 200 can also achieve effects similar to those described in the foregoing embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangements described in the foregoing embodiments and this variation. For example, the semiconductor layer 200S described in the foregoing embodiments and variation 1 can extend along the H direction.

[0347] <8. Variation Example 5>

[0348] Figure 59 A modified example of the cross-sectional structure of the camera device 1 according to the foregoing embodiment is shown schematically. Figure 59 Corresponding to the embodiments described above Figure 3In this modified example, the imaging device 1, in addition to having contact portions 201, 202, 301, and 302, also has contact portions 203, 204, 303, and 304 at positions opposite to the central portion of the pixel array portion 540. In this respect, the imaging device 1 according to this modified example differs from the imaging device 1 described in the foregoing embodiments.

[0349] Contact portions 203 and 204 are disposed on the second substrate 200 and exposed from the bonding surface between the second substrate 200 and the third substrate 300. Contact portions 303 and 304 are disposed on the third substrate 300 and exposed from the bonding surface between the third substrate 300 and the second substrate 200. Contact portions 203 and 304 are in contact with each other. In other words, in this imaging device 1, the second substrate 200 and the third substrate 300 are connected not only by means of contact portions 201, 202, 301 and 302, but also by means of contact portions 203, 204, 303 and 304.

[0350] Next, refer to Figure 60 and Figure 61 To illustrate the operation of the camera device 1. Figure 60 Arrows are used to show the path from the external input to the input signal, power supply potential, and reference potential of the camera device 1. Figure 61Arrows indicate the signal path of pixel signals output from the imaging device 1 to the outside. For example, the input signal input to the imaging device 1 via the input unit 510A is transmitted to the row driving unit 520 of the third substrate 300, and the row driving unit 520 generates a row driving signal. This row driving signal is transmitted to the second substrate 200 via the contact units 303 and 203. Then, this row driving signal reaches each pixel common unit 539 of the pixel array unit 540 via the row driving signal line 542 in the wiring layer 200T. The row driving signals that have reached the pixel common unit 539 of the second substrate 200, except for the drive signal of the transmission gate TG, are input to the pixel circuit 210, and drive each transistor included in the pixel circuit 210. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and drives pixels 541A, 541B, 541C and 541D. Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contacts 303 and 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via through electrode 121E. On the other hand, the pixel signals obtained by photoelectric conversion of each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 for each pixel common unit 539. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via vertical signal line 543 and contacts 204 and 304. After being processed in the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, the pixel signal is output to the outside via the output unit 510B.

[0351] The camera device 1, including these contact portions 203, 204, 303, and 304, can also achieve effects similar to those described in the aforementioned embodiments. The position and number of contact portions can be changed according to the design of the connection destination (i.e., the circuitry of the third substrate 300, etc.) via the contact portions 303 and 304.

[0352] <9. Variation Example 6>

[0353] Figure 62 A modified example of the cross-sectional structure of the camera device 1 according to the foregoing embodiment is shown. Figure 62 Corresponding to the embodiments described above Figure 6In this modified example, a transmission transistor TR with a planar structure is provided in the first substrate 100. In this respect, the imaging device 1 according to this modified example differs from the imaging device 1 described in the foregoing embodiments.

[0354] The transfer gate TG of the transfer transistor TR consists only of the horizontal portion TGb. In other words, the transfer gate TG does not include the vertical portion TGa and is positioned opposite the semiconductor layer 100S.

[0355] The imaging device 1, including the transmission transistor TR with this planar structure, can also achieve effects similar to those described in the aforementioned embodiments. Furthermore, it is conceivable that, since a planar transmission gate TG is provided in the first substrate 100, compared to the case where a vertical transmission gate TG is provided in the first substrate 100, the photodiode PD can be formed closer to the front side of the semiconductor layer 100S, thereby increasing the saturation signal quantity (Qs). Additionally, it is conceivable that, compared to the method of forming a vertical transmission gate TG in the first substrate 100, the method of forming a planar transmission gate TG in the first substrate 100 requires fewer manufacturing steps, and it is considered less likely to produce adverse effects on the photodiode PD due to manufacturing steps.

[0356] <10. Variation Example 7>

[0357] Figure 63 A modified example of the pixel circuit of the camera device 1 according to the foregoing embodiment is shown. Figure 63 Corresponding to the embodiments described above Figure 4 In this variation, a pixel circuit 210 is provided for each pixel (pixel 541A). In other words, the pixel circuit 210 is not shared by multiple pixels. In this respect, the imaging device 1 according to this variation differs from the imaging device 1 described in the foregoing embodiments.

[0358] According to this modification, the imaging device 1 places the pixel 541A and the pixel circuit 210 on different substrates (first substrate 100 and second substrate 200), which is the same as the imaging device 1 described in the previous embodiment. Therefore, the imaging device 1 according to this modification can also achieve effects similar to those described in the previous embodiment.

[0359] <11. Variation Example 8>

[0360] Figure 64A modified example of the planar structure of the pixel separation portion 117 described in the foregoing embodiment is shown. Gaps may be provided in the pixel separation portion 117 surrounding each of pixels 541A, 541B, 541C, and 541D. In other words, the entire circumferential surface of pixels 541A, 541B, 541C, and 541D may not be surrounded by the pixel separation portion 117. For example, gaps in the pixel separation portion 117 may be provided near each pad portion 120 and 121 (see [link to documentation]). Figure 7B ).

[0361] In the foregoing embodiments, an example has been described of the pixel separation section 117 having an FTI structure that penetrates the semiconductor layer 100S (see [link]). Figure 6 However, the pixel separation section 117 can have a structure other than the FTI structure. For example, the pixel separation section 117 can be configured not to completely penetrate the semiconductor layer 100S, but can have a so-called DTI structure.

[0362] <12. Variation Example 9>

[0363] In the first embodiment described above, the following configuration was explained: each of the plurality of sensor pixels is provided with a wiring electrically connected to the floating diffuser FD (i.e., a wiring for the floating diffuser) and a wiring electrically connected to the well layer WE (i.e., a wiring for the well). However, embodiments of the present invention are not limited thereto. In embodiments of the present invention, one wiring for the floating diffuser may be provided for each plurality of sensor pixels. For example, four adjacent sensor pixels may share one wiring for the floating diffuser. Similarly, one wiring for the well may be provided for each plurality of sensor pixels. For example, four adjacent sensor pixels may share one wiring for the well.

[0364] Figures 65 to 67 Each of these is a cross-sectional view in the thickness direction showing a construction example of the imaging device 1A according to a modified example 9 of the present invention. Figures 68 to 70 Each of these is a cross-sectional view in the horizontal direction showing an example of the layout of a plurality of pixel units PU according to a variation 9 of the present invention. It should be noted that... Figures 65 to 67 The cross-sectional views shown are schematic diagrams only and are not intended to strictly and accurately depict the actual construction. Figures 65 to 67 In the cross-sectional view shown, in order to facilitate the illustration of the structure of the camera device 1A in the figure, the horizontal positions of the transistor and the impurity diffusion layer at positions sec1 to sec3 have been intentionally changed.

[0365] Specifically, in Figure 65 In the pixel unit PU of the camera device 1A shown, the cross section at position sec1 is obtained through the... Figure 68The cross section obtained by cutting along line A1-A1′, the cross section at position sec2 is obtained by cutting along line A1-A1′. Figure 69 The cross section obtained by cutting along line B1-B1′, and the cross section at position sec3 is obtained by cutting along line B1-B1′. Figure 70 The cross-section obtained by cutting along line C1-C1′. Similarly, in Figure 66 In the camera device 1A shown, the cross-section at position sec1 is obtained through... Figure 68 The cross section obtained by cutting along line A2-A2′, the cross section at position sec2 is obtained by cutting along line A2-A2′. Figure 69 The cross section obtained by cutting along line B2-B2′, and the cross section at position sec3 is obtained by cutting along line B2-B2′. Figure 70 The cross-section obtained by cutting along line C2-C2′. Figure 67 In the camera device 1A shown, the cross-section at position sec1 is obtained through... Figure 68 The cross section obtained by cutting along line A3-A3′, the cross section at position sec2 is obtained by cutting along line A3-A3′. Figure 69 The cross section obtained by cutting along line B3-B3′, and the cross section at position sec3 is obtained by cutting along line B3-B3′. Figure 70 The cross section is obtained by cutting along the C3-C3′ line.

[0366] like Figure 66 and Figure 70 As shown, the imaging device 1A shares a common pad electrode 1102 arranged across multiple sensor pixels 1012 and a wiring L1002 disposed on the common pad electrode 1102. For example, the imaging device 1A has a region in which, in a plan view, the floating diffusers FD1 to FD4 of each of the four sensor pixels 1012 are adjacent to each other across the element separation layer 1016. The common pad electrode 1102 is disposed in this region. The common pad electrode 1102 is disposed across the four floating diffusers FD1 to FD4 and is electrically connected to each of the four floating diffusers FD1 to FD4. For example, the common pad electrode 1102 is formed of a polycrystalline silicon film doped with n-type or p-type impurities.

[0367] A wiring L1002 (i.e., a wiring for the floating diffusion section) is provided on the center of the common pad electrode 1102. Figure 66 and Figures 68 to 70 As shown, a wiring L1002 disposed on the center portion of the common pad electrode 1102 extends from the first substrate portion 1010 through the lower substrate 1210 of the second substrate portion 1020 and into the upper substrate 1220 of the second substrate portion 1020. The wiring L1002 is connected to the gate electrode AG of the amplification transistor AMP via wiring and the like disposed in the upper substrate 1220.

[0368] In addition, such as Figure 65 and Figure 70 As shown, the imaging device 1A shares a common pad electrode 1110 arranged across multiple sensor pixels 1012 and a wiring L1010 disposed on the common pad electrode 1110. For example, the imaging device 1A has a region in which, in a plan view, the well layers WE of each of the four sensor pixels 1012 are adjacent to each other across the element separation layer 1016. The common pad electrode 1110 is disposed in this region. The common pad electrode 1110 is disposed across the well layers WE of each of the four sensor pixels 1012 and is electrically connected to the well layers WE of each of the four sensor pixels 1012. As an example, a common pad electrode 1110 is disposed between one common pad electrode 1102 and another common pad electrode 1102 arranged in the Y-axis direction. In the Y-axis direction, the common pad electrodes 1102 and 1110 are arranged alternately. For example, the common pad electrode 1110 is formed of a polycrystalline silicon film doped with n-type or p-type impurities.

[0369] A wiring L1010 (i.e., a trap wiring) is provided at the center of the common pad electrode 1110. For example... Figure 65 and Figures 67 to 70 As shown, a wiring L1010 disposed on the center portion of the common pad electrode 1110 extends from the first substrate portion 1010 through the lower substrate 1210 of the second substrate portion 1020 and into the upper substrate 1220 of the second substrate portion 1020. The wiring L1010 is connected to a reference potential line via wiring or the like disposed within the upper substrate 1220. This reference potential line is used to supply a reference potential (e.g., ground potential: 0V).

[0370] A wiring L1010 disposed on the center portion of the common pad electrode 1110 is electrically connected to the upper surface of the common pad electrode 1110, the inner surface of the through hole disposed in the lower substrate 1210, and the inner surface of the through hole disposed in the upper substrate 1220. This connects the well layer WE of the semiconductor substrate 1011 of the first substrate portion 1010, the well layer of the lower substrate 1210 of the second substrate portion 1020, and the well layer of the upper substrate 1220 of the second substrate portion 1020 to a reference potential (e.g., ground potential: 0V).

[0371] The imaging device 1A according to Modification 9 of the present invention can achieve effects similar to those of the imaging device 1 according to the first embodiment. Furthermore, the imaging device 1A includes common pad electrodes 1102 and 1110, which are disposed on the front side 11a of the semiconductor substrate 1011 included in the first substrate portion 1010 and arranged across a plurality (e.g., four) of adjacent sensor pixels 1012. The common pad electrode 1102 is electrically connected to the floating diffusion portion FD of the four sensor pixels 1012. The common pad electrode 1110 is electrically connected to the well layer WE of the four sensor pixels 1012. Thus, the wiring L1002 connected to the floating diffusion portion FD can be shared in every four sensor pixels 1012. The wiring L1010 connected to the well layer WE can be shared in every four sensor pixels 1012. As a result, the number of wirings L1002 and L1010 can be reduced. Therefore, the area of ​​the sensor pixel 1012 can be reduced, and the camera device 1A can be miniaturized.

[0372] <13. Application Examples>

[0373] Figure 71 An example of a schematic construction of a camera system 7 including a camera device 1 according to any of the foregoing embodiments and their variations is shown.

[0374] For example, the camera system 7 is an electronic device including: a camera device such as a digital camera or video camera; or a portable terminal device such as a smartphone or tablet terminal. For example, the camera system 7 includes a camera device 1 according to any of the foregoing embodiments and their modifications, a DSP (digital signal processor) circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the camera system 7, the camera device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, operation unit 247, and power supply unit 248 according to the foregoing embodiments and their modifications are interconnected via a bus 249.

[0375] The imaging device 1 according to any of the foregoing embodiments and their variations outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit for processing the signals (image data) output from the imaging device 1 according to any of the foregoing embodiments and their variations. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in units of frames. For example, the display unit 245 includes a panel-type display such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays moving or still images captured by the imaging device 1 according to any of the foregoing embodiments and their variations. The storage unit 246 stores the image data of the moving or still images captured by the imaging device 1 according to any of the foregoing embodiments and their variations in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands regarding the various functions of the imaging system 7 according to the user's operation. The power supply unit 248 appropriately supplies various power sources, which serve as operating power sources for the camera device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to any of the foregoing embodiments and their variations, to these supply objects.

[0376] Next, the recording process in camera system 7 will be explained.

[0377] Figure 72 An example flowchart of the camera operation in the camera system 7 is shown. The user issues an instruction to start recording by operating the operation unit 247 (step S101). Then, the operation unit 247 sends a recording command to the camera device 1 (step S102). Upon receiving the recording command, the camera device 1 (specifically, the system control circuit 36) performs recording in a predetermined recording mode (step S103).

[0378] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 243. Here, the image data is the data of all pixels based on the pixel signal generated by the charge temporarily held in the floating diffuser FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the image data after predetermined signal processing to be stored in the frame memory 244, and the frame memory 244 causes the image data to be recorded in the storage unit 246 (step S105). In this way, imaging in the imaging system 7 is performed.

[0379] In this applicable example, the camera device 1 according to any of the foregoing embodiments and their variations is adapted into the camera system 7. This allows for the miniaturization or high-definition scaling of the camera device 1, thus providing a miniaturized or high-definition camera system 7.

[0380] <14. Application Examples>

[0381] [Application Example 1]

[0382] The technology according to the present invention (the technology) can be applied to a variety of products. For example, the technology according to the present invention can be implemented as a device installed on any mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal passenger vehicles, aircraft, drones, ships, robots, etc.

[0383] Figure 73 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention can be applied.

[0384] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 73 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0385] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 can function as a control device for various devices such as a drive force generating device for generating the vehicle's driving force, such as an internal combustion engine or drive motor; a drive force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0386] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 can function as a control device for various devices such as keyless entry systems, smart key systems, power windows, and various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches transmitted from a portable device used in place of a key can be input to the body system control unit 12020. The body system control unit 12020 receives these radio wave or signal inputs and controls the vehicle's door locks, power windows, lights, etc.

[0387] The exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to a camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing based on the received images, such as detecting people, cars, obstacles, signs, or text on the road.

[0388] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0389] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0390] For example, the microcomputer 12051 can calculate the control target values ​​for the drive force generating device, steering mechanism, or braking device based on the vehicle's external and internal information obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including: collision avoidance or impact mitigation, distance-based following, constant speed driving, collision warning, lane departure warning, etc.

[0391] In addition, the microcomputer 12051 can control the drive force generating device, steering mechanism, braking device, etc. based on the vehicle surrounding information obtained by the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, thereby performing coordinated control aimed at realizing autonomous driving and the like, which enables the vehicle to drive autonomously without relying on the driver's operation.

[0392] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external vehicle information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030, thereby performing coordinated control aimed at preventing glare, such as switching from high beams to low beams.

[0393] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying vehicle occupants or external to the vehicle. Figure 73 In the example, as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an onboard display and a head-up display.

[0394] Figure 74 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0395] exist Figure 74 In the vehicle 12100, camera units 12101, 12102, 12103, 12104 and 12105 are camera units 12031.

[0396] Cameras 12101, 12102, 12103, 12104, and 12105 are positioned, for example, on the front bumper, side mirrors, rear bumper, tailgate, and the upper part of the windshield inside the vehicle 12100. Camera 12101, located on the front bumper, and camera 12105, located on the upper part of the windshield inside the vehicle, primarily acquire images of the front of the vehicle 12100. Cameras 12102 and 12103, located on the side mirrors, primarily acquire images of the sides of the vehicle 12100. Camera 12104, located on the rear bumper or tailgate, primarily acquires images of the rear of the vehicle 12100. The images of the front acquired using cameras 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes ahead.

[0397] Incidentally, Figure 74Examples of the camera ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front bumper. Camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the side mirrors, respectively. Camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or trunk lid. For example, by superimposing the image data captured by camera units 12101 to 12104, a top-view image of vehicle 12100 can be obtained.

[0398] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0399] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of that distance over time (relative speed to vehicle 12100), thereby identifying three-dimensional objects as vehicles ahead: objects that are closest to the vehicle 12100, especially on the vehicle 12100's travel path, and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a pre-determined distance from the vehicle ahead and perform automatic braking control (including follow-up stopping control), automatic acceleration control (including follow-up starting control), etc. Therefore, coordinated control aimed at achieving autonomous driving, such as automatic driving, is possible.

[0400] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can classify three-dimensional object data into three-dimensional object data such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. Then, microcomputer 12051 determines the collision risk, which indicates the degree of danger of colliding with each obstacle. If the collision risk is equal to or higher than a set value and there is a possibility of collision, microcomputer 12051 can output an alarm to the driver via audio speaker 12061 or display unit 12062, or can perform forced deceleration or evasive steering via drive system control unit 12010. Thus, microcomputer 12051 can provide driving assistance for collision avoidance.

[0401] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, pedestrian identification is performed by the following steps: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to display a rectangular outline for emphasis overlaid on the identified pedestrian. Furthermore, the audio / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0402] The above description uses a mobile body control system capable of applying the technology of the present invention as an example. The technology of the present invention can be applied to the camera unit 12031 in the structure described above. Specifically, the camera device 1 according to any of the foregoing embodiments and their modifications can be applied to the camera unit 12031. By applying the technology of the present invention to the camera unit 12031, high-definition camera images with very little noise can be obtained; therefore, high-precision control can be performed using these camera images in the mobile body control system.

[0403] [Application Example 2]

[0404] Figure 75This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the present technology) is applicable.

[0405] exist Figure 75 The image shows a surgeon (physician) 11131 using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112; a support arm device 11120 for supporting the endoscope 11100; and a trolley 11200 equipped with various devices for endoscopic surgery.

[0406] Endoscope 11100 includes: a tube 11101, a region of which, measured from its distal end, having a predetermined length, is inserted into a body cavity of a patient 11132; and a camera head 11102 connected to the base of the tube 11101. In the illustrated example, an endoscope 11100 is shown as a so-called rigid endoscope configured with a rigid tube 11101. However, endoscope 11100 can also be configured as a flexible endoscope with a flexible tube.

[0407] The endoscope tube 11101 has an opening at its distal end, into which the objective lens is fitted. A light source device 11203 is connected to the endoscope 11100, such that light generated by the light source device 11203 is guided through a light guide extending inside the endoscope tube 11101 to the distal end of the endoscope tube 11101, and then through the objective lens to illuminate the object being observed within the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a direct-viewing endoscope, or it can be an oblique-viewing endoscope or a lateral-viewing endoscope.

[0408] An optical system and an imaging element are disposed inside the camera head 11102. Reflected light from the object being observed (observation light) is focused onto the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is transmitted as RAW (raw) data to the camera control unit (CCU) 11201.

[0409] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations on the image signals, such as image processing (de-mosaicing), for displaying images based on the image signals.

[0410] Under the control of CCU 11201, display device 11202 displays an image based on an image signal that has undergone image processing by CCU 11201.

[0411] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 11100 when imaging the surgical area, etc.

[0412] Input device 11204 is an input interface for endoscopic surgery system 11000. Users can input various information and commands into endoscopic surgery system 11000 through input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0413] The procedure control device 11205 controls the drive of the energy device 11112 used for tissue cauterization or incision, or sealing of blood vessels. The pneumoperitoneum device 11206 delivers gas into the patient's body cavity 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of vision of the endoscope 11100 and ensuring the operating space for the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, and graphs.

[0414] It should be noted that the light source device 11203 for supplying illumination light to the endoscope 11100 for imaging the surgical area may include, for example, an LED, a laser light source, or a white light source composed of a combination thereof. When the white light source is composed of a combination of red, green, and blue (RGB) laser light sources, the white balance adjustment of the captured image can be performed in the light source device 11203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. Furthermore, in this case, if the lasers from each of the RGB laser light sources are time-division multiplexed onto the object of observation, and the driving of the imaging element of the camera head 11102 is controlled synchronously with the illumination timing, then images corresponding to the R, G, and B colors respectively can be captured time-division multiplexed. According to this method, color images can be obtained even when no color filter is provided in the imaging element.

[0415] Furthermore, the drive of the light source device 11203 can be controlled to change the intensity of the light to be output at each predetermined time. By controlling the drive of the imaging element of the camera head 11102 in sync with the timing of the change in light intensity to acquire images in a time-division manner and synthesizing the images, a high dynamic range image that does not produce underexposed shadows or overexposed highlights can be generated.

[0416] Furthermore, the light source device 11203 can be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, a so-called narrow-band light observation (narrow-band imaging) can be performed, for example, by utilizing the wavelength dependence of light absorption in body tissues, irradiating light with a narrower band than the irradiation light used in ordinary observation (i.e., white light), thereby imaging a predetermined tissue, such as blood vessels in the mucosal surface, with high contrast. Alternatively, in special light observation, fluorescence observation can be performed using images obtained by irradiating fluorescence generated by excitation light. In fluorescence observation, body tissue can be irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into the body tissue, and the body tissue can be irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to the above-described special light observation.

[0417] Figure 76 It shows Figure 75 A block diagram illustrating an example of the functional configuration of the camera head 11102 and CCU 11201.

[0418] Camera head 11102 includes lens unit 11401, imaging unit 11402, drive unit 11403, communication unit 11404, and camera head control unit 11405. CCU 11201 includes communication unit 11411, image processing unit 11412, and control unit 11413. Camera head 11102 and CCU 11201 are connected to each other via transmission cable 11400 in a manner that enables communication between them.

[0419] Lens unit 11401 is an optical system disposed at the connection point with lens barrel 11101. Observation light entering from the distal end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 is composed of a combination of multiple lenses, including zoom lenses and focusing lenses.

[0420] The camera unit 11402 includes camera elements. The number of camera elements constituting the camera unit 11402 can be one (so-called single-plate type) or multiple (so-called multi-plate type). When the camera unit 11402 is configured as a multi-plate type, for example, a color image can be obtained by generating image signals corresponding to each of the RGB values ​​from each camera element and synthesizing the image signals. The camera unit 11402 can also be configured to have a pair of camera elements that respectively acquire image signals for the right eye and left eye for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of living tissue in the surgical area. It should be noted that when the camera unit 11402 is configured as a multi-plate type, multiple lens units 11401 can be provided corresponding to each camera element.

[0421] Alternatively, the camera unit 11402 may not be mounted on the camera head 11102. For example, the camera unit 11402 may be mounted inside the lens barrel 11101 and directly behind the objective lens.

[0422] The drive unit 11403 includes an actuator, and under the control of the camera head control unit 11405, moves the zoom lens and focusing lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0423] The communication unit 11404 includes communication devices for receiving various information from and sending various information to the CCU 11201. The communication unit 11404 transmits the image signal acquired from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0424] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera head 11102 and supplies the control signals to the camera head control unit 11405. For example, the control signals include information related to shooting conditions, such as: information for specifying the frame rate of the captured image, information for specifying the exposure value during shooting, and / or information for specifying the magnification and focus of the captured image, etc.

[0425] It should be noted that the aforementioned imaging conditions, such as frame rate, exposure value, magnification, and focus, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0426] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0427] The communication unit 11411 includes a communication device for receiving and sending various information to the camera head 11102. The communication unit 11411 receives image signals transmitted via the transmission cable 11400 from the camera head 11102.

[0428] In addition, the communication unit 11411 transmits control signals for controlling the camera head 11102 to the camera head 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0429] The image processing unit 11412 performs various image processing operations on the image signal in RAW data format transmitted from the camera head 11102.

[0430] The control unit 11413 performs various controls related to imaging the surgical area, etc., through the endoscope 11100 and displaying the images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0431] Furthermore, based on the image signal that has already been processed by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image reflecting the surgical area, etc. At this time, the control unit 11413 can use various image recognition techniques to identify various objects in the captured image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living areas, bleeding, and fog when using the energy treatment tool 11112 by detecting the edge shape, color, etc. of objects contained in the captured image. When the display device 11202 is controlled to display the captured image, the control unit 11413 can use the recognition results to overlay various surgical support information onto the image of the surgical area. By overlaying and presenting surgical support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0432] The transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable corresponding to both electrical and optical communication.

[0433] In the example shown here, wired communication is achieved using transmission cable 11400, but wireless communication is also possible between camera head 11102 and CCU 11201.

[0434] Examples of endoscopic surgical systems to which the technology according to the present invention can be applied have been described above. This technology can be suitably applied to the imaging unit 11402 of the camera head 11102 disposed in the endoscope 11100 in the configuration described above. By applying the technology according to the present invention to the imaging unit 11402, the imaging unit 11402 can be miniaturized or made high-definition, thereby providing a miniaturized or high-definition endoscope 11100.

[0435] Although the present invention has been described above with reference to the first to third embodiments, variations 1 to 8 thereof, applicable examples and application examples, the present invention is not limited to the foregoing embodiments. Various modifications are possible.

[0436] It should be noted that the effects described herein are merely illustrative. The effects of the invention are not limited to those described herein. The invention may have effects other than those described herein.

[0437] It should be noted that the present invention may also have the configuration described later. In the present invention according to the first embodiment having the configuration described later, an adjustment portion for adjusting the threshold voltage of the second transistor is provided on the side of the opening of the second semiconductor substrate near the gate of the second transistor and / or on the region of the second semiconductor substrate opposite to the first transistor. In a second imaging device according to an embodiment of the present invention, the end of the gate of the second transistor disposed in the second semiconductor substrate adjacent to the through wiring for electrically connecting the first substrate and the second substrate is embedded in an insulating film filled in the opening. The opening penetrates the second semiconductor substrate. The through wiring penetrates the opening. In a third imaging device according to an embodiment of the present invention, the through wiring that penetrates the opening of the second semiconductor substrate in the stacking direction and electrically connects the first substrate and the second substrate to each other is provided at a position offset from the center line of the gate of the second transistor disposed in the second semiconductor substrate, which is equally divided along the extension direction. This reduces the influence of the electric field of the through wiring on the second transistor and the influence of the electric field of the first transistor on the second transistor, and can reduce the characteristic variation of the second transistor. Thereby, image quality can be improved.

[0438] (1) A camera device, comprising:

[0439] A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel;

[0440] A second substrate, stacked on the first substrate, includes a second transistor and an opening disposed in a second semiconductor substrate having a surface opposite to the first substrate. The second transistor forms the sensor pixel. The opening penetrates the second semiconductor substrate in the stacking direction. The second substrate has an adjustment portion for adjusting the threshold voltage of the second transistor. The adjustment portion is formed on a side of the opening near the gate of the second transistor and / or on the region of the one surface of the second semiconductor substrate opposite to the first transistor.

[0441] A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate.

[0442] (2) The camera device according to (1), wherein,

[0443] The adjustment portion is formed on the entire surface of the side of the opening in the second semiconductor substrate.

[0444] (3) The camera device according to (1) or (2), wherein,

[0445] The adjustment portion is formed on the entire surface of one of the surfaces of the second semiconductor substrate.

[0446] (4) The camera device according to any one of (1) to (3), wherein,

[0447] The adjustment section includes an impurity region doped with p-type impurities.

[0448] (5) The camera device according to (4), wherein,

[0449] Boron (B) is doped in the impurity region.

[0450] (6) The camera device according to any one of (1) to (3), wherein,

[0451] The adjustment section is formed using a metal oxide film.

[0452] (7) The camera device according to (6), wherein,

[0453] The metal oxide film is an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, or a lanthanum oxide film.

[0454] (8) A camera device, comprising:

[0455] A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel;

[0456] A second substrate is stacked on the first substrate. The second substrate has an opening disposed in the second semiconductor substrate, the opening penetrating the second semiconductor substrate in the stacking direction, and the opening is filled with an insulating film.

[0457] Through wiring, the through wiring penetrating the insulating film, is used to electrically connect the first substrate and the second substrate; and

[0458] A second transistor, which is used in the second semiconductor substrate to form the sensor pixel, the second transistor includes a gate, at least one end of the gate adjacent to the through wiring being embedded in the insulating film.

[0459] (9) According to the camera device of (8), wherein,

[0460] The end of the gate embedded in the insulating film extends to a surface of the second semiconductor substrate opposite to the first substrate.

[0461] (10) A camera device, comprising:

[0462] A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel;

[0463] A second substrate, stacked on the first substrate, includes a second transistor disposed in a second semiconductor substrate and an opening, the second transistor constituting the sensor pixel, the opening penetrating the second semiconductor substrate in the stacking direction; and

[0464] A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate. The through-wire has a second center line at a position different from the first center line in the plan view. The first center line equally divides the gate of the second transistor along its extension direction, and the second center line equally divides the through-wire along the same direction as the first center line.

[0465] (11) The camera device according to (10), wherein,

[0466] The through wiring is configured such that its electric field over the channel region of the second transistor is less than the electric field over the channel region of the second transistor when the first center line and the second center line coincide.

[0467] (12) The camera device according to (10) or (11), wherein,

[0468] The second center line is offset relative to the first center line to the drain side of the second transistor.

[0469] (13) The camera device according to (10) or (11), wherein,

[0470] The through wiring is arranged on the extension lines of the source and drain of the second transistor.

[0471] (14) The camera device according to any one of (10) to (13), wherein,

[0472] The second semiconductor substrate also includes an impurity region doped with p-type impurities on the side near the through wiring.

[0473] (15) The camera device according to (14), wherein,

[0474] The impurity region includes a concentration of 10 15 cm -3 Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through wiring is 100 nm or more and 250 nm or less, the shortest distance between the second center line and the first center line is 100 nm or more.

[0475] (16) The camera device according to (14), wherein,

[0476] The impurity region includes a concentration of 10 15 cm -3 Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through-wire is 100 nm or more and 250 nm or less, the through-wire is arranged on the extension line of the source and drain of the second transistor.

[0477] (17) The camera device according to (14), wherein,

[0478] The impurity region includes a concentration of 10 15 cm -3Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through-line is 100 nm or more and 250 nm or less, the shortest distance between the gate terminal of the second transistor and the through-line is 250 nm or more.

[0479] This application claims priority to Japanese Patent Application No. 2019-119045, filed with the Japan Patent Office on June 26, 2019, the entire contents of which are incorporated herein by reference.

[0480] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations can be conceived based on design requirements and other factors, all of which fall within the scope of the appended claims and their equivalents.

Claims

1. A camera device, comprising: A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel; A second substrate is stacked on the first substrate. The second substrate includes a second transistor and an opening disposed in a second semiconductor substrate having a surface opposite to the first substrate. The second transistor is used to form the sensor pixel. The opening extends through the second semiconductor substrate in the stacking direction. The second substrate has an adjustment portion for adjusting the threshold voltage of the second transistor. The adjustment portion is formed on a side of the opening near the gate of the second transistor in a second direction different from the first direction in which the gate, source, and drain of the second transistor are arranged, and is formed on the region of the one surface of the second semiconductor substrate opposite to the first transistor. as well as A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate.

2. The camera device according to claim 1, wherein, The adjustment portion is formed on the entire surface of the side of the opening in the second semiconductor substrate.

3. The camera device according to claim 1, wherein, The adjustment portion is formed on the entire surface of one of the surfaces of the second semiconductor substrate.

4. The camera device according to any one of claims 1 to 3, wherein, The adjustment section includes an impurity region doped with p-type impurities.

5. The camera device according to claim 4, wherein, Boron (B) is doped in the impurity region.

6. The camera device according to any one of claims 1 to 3, wherein, The adjustment section is formed of a metal oxide film.

7. The camera device according to claim 6, wherein, The metal oxide film is an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, or a lanthanum oxide film.

8. A camera device, comprising: A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel; A second substrate is stacked on the first substrate. The second substrate has an opening disposed in a second semiconductor substrate, the opening penetrating the second semiconductor substrate in the stacking direction, and the opening is filled with a first insulating film. A through-wire, which passes through the first insulating film, is used to electrically connect the first substrate and the second substrate; A second transistor, which is used in the second semiconductor substrate to form the sensor pixel, the second transistor includes a gate; as well as Each of the component separation regions is located within the second semiconductor substrate at a portion overlapping with each end of the gate, and each of the component separation regions is formed of a second insulating film. Wherein, at least one end of the gate adjacent to the through wiring is embedded in the second insulating film.

9. The camera device according to claim 8, wherein, The end of the gate embedded in the second insulating film extends to a surface of the second semiconductor substrate opposite to the first substrate.

10. A camera device, comprising: A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel; A second substrate is stacked on the first substrate. The second substrate includes a second transistor disposed in a second semiconductor substrate and an opening. The second transistor is used to form the sensor pixel. The opening penetrates the second semiconductor substrate in the stacking direction. as well as A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate. The through-wire has a second center line located at a position different from the first center line in the plan view. The first center line equally divides the gate of the second transistor along its extending direction, and the second center line equally divides the through-wire along the same direction as the first center line. The second semiconductor substrate further includes an impurity region doped with p-type impurities on its side surface near the through wiring, and The impurity region includes a concentration of 10 15 cm -3 Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through wiring is 100 nm or more and 250 nm or less, the shortest distance between the second center line and the first center line is 100 nm or more.

11. The camera device according to claim 10, wherein, The through wiring is configured such that its electric field over the channel region of the second transistor is less than the electric field over the channel region of the second transistor when the first center line and the second center line coincide.

12. The camera device according to claim 10, wherein, The second center line is offset relative to the first center line to the drain side of the second transistor.

13. The camera device according to claim 10, wherein, The through wiring is arranged on the extension lines of the source and drain of the second transistor.

14. A camera device, comprising: A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel; A second substrate is stacked on the first substrate. The second substrate includes a second transistor disposed in a second semiconductor substrate and an opening. The second transistor is used to form the sensor pixel. The opening penetrates the second semiconductor substrate in the stacking direction. as well as A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate. The through-wire has a second center line located at a position different from the first center line in the plan view. The first center line equally divides the gate of the second transistor along its extending direction, and the second center line equally divides the through-wire along the same direction as the first center line. The second semiconductor substrate further includes an impurity region doped with p-type impurities on its side surface near the through wiring, and The impurity region includes a concentration of 10 15 cm -3 Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through-wire is 100 nm or more and 250 nm or less, the through-wire is arranged on the extension line of the source and drain of the second transistor.

15. A camera device, comprising: A first substrate, the first substrate including a photoelectric conversion unit and a first transistor disposed in a first semiconductor substrate, the photoelectric conversion unit and the first transistor being used to form a sensor pixel; A second substrate is stacked on the first substrate. The second substrate includes a second transistor disposed in a second semiconductor substrate and an opening. The second transistor is used to form the sensor pixel. The opening penetrates the second semiconductor substrate in the stacking direction. as well as A through-wire is disposed within the opening for electrically connecting the first substrate and the second substrate. The through-wire has a second center line located at a position different from the first center line in the plan view. The first center line equally divides the gate of the second transistor along its extending direction, and the second center line equally divides the through-wire along the same direction as the first center line. The second semiconductor substrate further includes an impurity region doped with p-type impurities on its side surface near the through wiring, and The impurity region includes a concentration of 10 15 cm -3 Above and 10 17 cm -3 In the case of the p-type impurities described below, and the direct distance between the gate of the second transistor and the through-line is 100 nm or more and 250 nm or less, the shortest distance between the gate terminal of the second transistor and the through-line is 250 nm or more.

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