Integrated circuit for physically unclonable functions and method of operation thereof

Abstract

The present disclosure provides an integrated circuit for a physically unclonable function (PUF) and an operating method thereof, the integrated circuit including: a controller configured to generate a control signal with reference to an address table; an address table representing a first mapping relationship between a first PUF cell group having a first predetermined mismatch distance with respect to PUF cell characteristics and a second PUF cell group, and representing a second mapping relationship between a third PUF cell group having a second predetermined mismatch distance with respect to PUF cell characteristics and a fourth PUF cell group; and a PUF block configured to provide a PUF cell data group to the controller according to the first mapping relationship and the second mapping relationship in response to the control signal. The controller can be configured to generate an authentication key by comparing the PUF cell data group with a reference data group, respectively.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0076760, entitled "Integrated Circuit for Physically Unclonable Functions and Method of Operating Thereof," filed on June 23, 2020, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to security technologies, and more specifically, to a physically unclonable function (PUF) circuit. Background Technology

[0004] Recently, with the rapid development of wired and wireless communication technologies and technologies related to smart devices, the demand for secure systems that can safely use these technologies has been increasing. Summary of the Invention

[0005] The embodiment relates to an integrated circuit for Physically Unclonable Functions (PUFs), the integrated circuit comprising: a controller configured to generate control signals with reference to an address table representing a first mapping between a first PUF unit group and a second PUF unit group, and representing a second mapping between a third PUF unit group and a fourth PUF unit group, wherein the first PUF unit group and the second PUF unit group have a first predetermined mismatch distance with respect to PUF unit characteristics, and the third PUF unit group and the fourth PUF unit group have a second predetermined mismatch distance with respect to PUF unit characteristics; and a PUF block configured to provide PUF unit data groups to the controller in response to the control signals according to the first and second mapping relationships. The controller may be configured to generate an authentication key by comparing the PUF unit data groups with reference data groups, respectively.

[0006] The embodiments also relate to an integrated circuit for Physically Unclonable Functions (PUFs), the integrated circuit comprising: a PUF block configured to include PUF cells; and a controller configured to receive PUF cell data pairs according to a first mapping relationship between a first PUF cell group and a second PUF cell group and a second mapping relationship between a third PUF cell group and a fourth PUF cell group, wherein the first PUF cell group and the second PUF cell group have a first predetermined mismatch distance with respect to PUF cell characteristics, and the third PUF cell group and the fourth PUF cell group have a second predetermined mismatch distance with respect to PUF cell characteristics. The controller may be configured to generate element keys forming authentication keys by comparing the PUF cell data pairs with reference data pairs respectively.

[0007] The embodiments also relate to a method of operating an integrated circuit, the integrated circuit including a controller and a physically unclonable function (PUF) block, the method comprising: receiving an authentication key request at the controller; in response to the authentication key request received through the controller, providing a control signal from the controller to the PUF block, the control signal being used to read PUF cell data pairs corresponding to a first PUF cell and a second PUF cell, the second PUF cell being paired with the first PUF cell; in response to the control signal, providing the PUF cell data pairs from the PUF block to the controller; comparing the PUF cell data pairs with reference data pairs respectively, wherein the comparison is performed by the controller; and generating an authentication key from the controller based on the comparison results, the authentication key including element keys corresponding to the PUF cell data pairs. Attached Figure Description

[0008] These features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating an integrated circuit according to an example embodiment;

[0010] Figures 2 to 4 It is shown Figure 1 A diagram illustrating an example of controller operation;

[0011] Figure 5 This shows the operation. Figure 1 A flowchart of a method for integrating integrated circuits;

[0012] Figure 6 It is shown Figure 5 A flowchart detailing an example embodiment of operations S120 and S140;

[0013] Figure 7 This shows the generation Figure 1 A flowchart detailing the method for using element keys in integrated circuits;

[0014] Figure 8A and Figure 8B This is a graph showing the incorrect PUF cell data items output by all physically unclonable function (PUF) cells in the mapped PUF cell group;

[0015] Figures 9 to 11 It is shown in Figure 8A and Figure 8B In the case of generating Figure 1 A flowchart of the method for obtaining authentication keys for integrated circuits;

[0016] Figure 12 This is a diagram illustrating an address table for managing the number of retries according to an example embodiment;

[0017] Figure 13 This indicates the settings (or updates). Figure 1 A flowchart of the operation of an integrated circuit;

[0018] Figure 14A and Figure 14B This indicates the settings (or updates). Figure 1 A diagram illustrating the operation of an integrated circuit; and

[0019] Figure 15 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0020] Figure 1 This is a block diagram illustrating an integrated circuit 10 according to an example embodiment. Figures 2 to 4 It is shown Figure 1 A diagram illustrating an example of the operation of controller 100.

[0021] Integrated circuit 10 may be referred to as an integrated circuit or device that supports physically unclonable functions (PUF).

[0022] In some example embodiments, the integrated circuit 10 can be fabricated using a semiconductor processor, and the components of the integrated circuit 10 can be packaged in a single package, or they can be packaged separately in two or more packages. Additionally, the integrated circuit 10 can be installed in each of various types of electronic devices that perform encryption or security authentication of data thereon.

[0023] Integrated circuit 10 can generate an authentication key KEY in response to an authentication key request signal REQ from an external device (such as an external host or external processor), and can provide the authentication key KEY to the external device. In some example embodiments, the external device may be a security device such as an encryption module or an authentication module.

[0024] Reference Figure 1 The integrated circuit 10 may include a controller 100, a PUF block 200, and a non-volatile memory 300. The controller 100 may generate an authentication key KEY by using the PUF block 200 in response to an authentication key request signal REQ received from an external host.

[0025] Controller 100 may include control logic 110, mapping register 120, and key generator 130. PUF block 200 may include PUF unit array 210 containing multiple PUF units. The multiple PUF units of PUF unit array 210 can generate unique signals with unique values ​​according to the PUF. PUF can refer to controlling unique values ​​corresponding to the hardware based on the inherent characteristics of the hardware.

[0026] In some example embodiments, although multiple hardware components, such as semiconductor chips, are manufactured using the same process, they are not physically identical, resulting in small deviations among them. Unique values ​​for these hardware components can be extracted based on these deviations, and these extracted values ​​can be used in applications requiring security, such as secure communication, secure data processing, user identification, and firmware updates.

[0027] In some example embodiments, each of the plurality of PUF cells in the PUF cell array 210 may have any structure that generates k-bit data (k being an integer not less than 2) with unique values. In some example embodiments, each of the plurality of PUF cells may have an SRAM-type PUF structure based on values ​​stored in static random access memory (SRAM) cells, a ring oscillator structure based on frequency fluctuations, a leakage-based PUF structure based on leakage current, or an arbiter PUF structure, in which the signal path is arbitrarily determined. Furthermore, each of the plurality of PUF cells may have a PUF structure including resistive elements.

[0028] In the following description, each of the plurality of PUF cells is depicted as a metal-oxide-semiconductor (MOS) transistor structure having characteristics associated with a unique threshold voltage, as an example only. Various structures capable of having unique characteristics to support PUFs can be applied to each of the plurality of PUF cells.

[0029] In the following description, the operation of the control logic 110 and key generator 130 included in controller 100 may be mixed with the operation of controller 100. Controller 100 may be implemented in hardware, or it may be implemented as any processing unit that includes executing a series of commands (or software). In some example embodiments, controller 100 may be implemented using a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0030] Control logic 110 may provide a control signal CS (for reading multiple PUF cell data pairs PUF_DP for generating the authentication key KEY) to PUF block 200 in response to the authentication key request signal REQ referencing address table TB_1. Hereinafter, the multiple PUF cell data pairs PUF_DP may be referred to as PUF cell data groups. The control signal CS may include a signal for outputting multiple PUF cell data pairs PUF_DP from the desired PUF cell among the multiple PUF cells of PUF cell array 210. The multiple PUF cells of PUF cell array 210 may form a threshold voltage distribution and may be pre-grouped according to the amplitude of the threshold voltage.

[0031] Reference Figure 2 Multiple PUF units can be divided into a first PUF unit group (Group_1) having a threshold voltage between a first reference point p1 and a second reference point p2, a second PUF unit group (Group_2) having a threshold voltage between a second reference point p2 and a third reference point p3, a third PUF unit group (Group_3) having a threshold voltage between a third reference point p3 and a fourth reference point p4, and a fourth PUF unit group (Group_4) having a threshold voltage between a fourth reference point p4 and a fifth reference point p5. This grouping can be pre-executed by the controller 100 during the operation of setting up the integrated circuit 10 before the integrated circuit 10 generates the authentication key KEY. The controller 100 can determine the first reference point p1 to the fifth reference point p5 during the operation of setting up the integrated circuit 10. The first reference point p1 to the fifth reference point p5 can be determined such that the number of PUF units included in the first PUF unit group (Group_1) to the fourth PUF unit group (Group_4) are equal or similar to each other.

[0032] In some example embodiments, the PUF block 200 can be configured such that a unique signal having a unique value generated by a plurality of PUF units can be provided to the controller 100 as PUF unit data with 2 bits. In some example embodiments, the PUF block 200 can output PUF unit data with 2 bits by comparing the unique signal generated by the plurality of PUF units with a third reference point p3 and then with a second reference point p2 or a fourth reference point p4. Hereinafter, for convenience, the plurality of PUF units can be referred to as outputting PUF unit data.

[0033] In some example embodiments, PUF units included in the first PUF unit group Group_1 can output PUF unit data "00", PUF units included in the second PUF unit group Group_2 can output PUF unit data "01", PUF units included in the third PUF unit group Group_3 can output PUF unit data "10", and PUF units included in the fourth PUF unit group Group_4 can output PUF unit data "11".

[0034] Reference Figure 3According to an example embodiment, the PUF cell array 210 may include 256 PUF cells C1 to C256. The PUF cells C1 to C256 may be divided into a first PUF cell group Group_1 to a fourth PUF cell group Group_4 based on the unique value of a cell characteristic (which may be, for example, a threshold voltage). The number of PUF cells included in each of the first PUF cell groups Group_1 to the fourth PUF cell group Group_4 may be 64 and may be equal to each other. In some example embodiments, the first PUF cell group Group_1 may be mapped to a third PUF cell group Group_3 to form a pair, and the second PUF cell group Group_2 may be mapped to the fourth PUF cell group Group_4 to form a pair.

[0035] In some example embodiments, the first PUF unit group Group_1 can be separated from the third PUF unit group Group_3 by a predetermined mismatch distance, and the second PUF unit group Group_2 can be separated from the fourth PUF unit group Group_4 by a predetermined mismatch distance. Because the PUF units are not physically identical to each other, mismatch distances can be generated. Mismatch distances can be used to characterize PUF unit groups that are not adjacent to each other and are set as pairs.

[0036] In some example embodiments, the first PUF unit group Group_1 and the fourth PUF unit group Group_4 may include strong PUF units, and the second PUF unit group Group_2 and the third PUF unit group Group_3 may include weak PUF units. Strong PUF units can output PUF unit data that corresponds to a PUF unit group adjacent to a PUF unit group that includes strong PUF units with a low probability, and weak PUF units can output PUF unit data that corresponds to a PUF unit group adjacent to a PUF unit group that includes strong PUF units with a high probability.

[0037] Therefore, based on the PUF cell data output from the PUF cells of the first PUF cell group Group_1 and the fourth PUF cell group Group_4, it can be determined whether the PUF cell data output from the PUF cells of the second PUF cell group Group_2 and the third PUF cell group Group_3 has correct values. The PUF cell data output from the PUF cells of the first PUF cell group Group_1 and the fourth PUF cell group Group_4 may have incorrect (or erroneous) values. In this case, refer to... Figures 8A to 10 Describe the method for generating authentication keys (KEYs).

[0038] Reference Figure 4Address table TB_1 may include information on the mapping of the addresses of PUF units in the first PUF unit group Group_1 to the addresses of PUF units in the third PUF unit group Group_3, and information on the mapping of the addresses of PUF units in the second PUF unit group Group_2 to the addresses of PUF units in the fourth PUF unit group Group_4, to suit the mapping relationship between the first PUF unit group Group_1 to the fourth PUF unit group Group_4.

[0039] Reference Figure 4 In the example embodiment shown, when the first PUF unit C1 is paired with the 79th PUF unit C79 (as an example), the address C1_ADD of the first PUF unit C1 can be mapped to the address C79_ADD of the 79th PUF unit C79 in the address table TB_1. Additionally, when the 256th PUF unit C256 is paired with the 67th PUF unit C67 (as another example), the address C256_ADD of the 256th PUF unit C256 can be mapped to the address C67_ADD of the 67th PUF unit C67 in the address table TB_1.

[0040] In some example embodiments, the controller 100 may pre-generate an address table TB_1 and store the address table TB_1 in non-volatile memory 300 during the operation of setting up the integrated circuit 10. In some example embodiments, the address table TB_1 may be copied from non-volatile memory 300 to mapping register 120 during the operation of generating authentication key KEY.

[0041] Refer again Figure 1 Referring to the PUF unit corresponding to at least one address included in the authentication key request signal REQ and the address table TB_1, control logic 110 can provide a control signal CS to PUF block 200 for reading PUF unit data pair PUF_DP output from the PUF unit paired with the corresponding PUF unit. In some example embodiments, when the authentication key request signal REQ including the address C1_ADD of the first PUF unit C1 is received, control logic 110 can refer to address table TB_1 to determine the address C79_ADD of the 79th PUF unit C79 paired with the first PUF unit C1, and then can provide the control signal CS to PUF block 200 for reading PUF unit data pair PUF_DP corresponding to the first PUF unit C1 and the 79th unit C79.

[0042] In some example embodiments, the key generator 130 can compare multiple PUF unit data pairs (PUF_DP) received from PUF block 200 with reference data pairs respectively, and can generate an authentication key KEY. The reference data pairs can also be referred to as reference data groups.

[0043] The authentication key KEY may include multiple element keys, each of which is generated from a PUF unit data pair. In some example embodiments, the key generator 130 may generate an nth element key (n is an integer greater than or equal to 1) having a value suitable for matching a reference data pair among the nth PUF unit data pairs PUF_DP. Hereinafter, matching may mean that the data pairs are identical to each other. On the other hand, when the nth PUF unit data pair does not match any of the reference data pairs, the key generator 130 may provide a matching result signal RS to the control logic 110, and the control logic 110 may retry in response to the matching result signal RS to generate the nth element key corresponding to the nth PUF unit data pair. That is, when an nth PUF unit data pair with an incorrect value is output from PUF block 200, the control logic 110 may again provide a control signal CS to PUF block 200 so that an nth PUF unit data pair with a correct value can be output from PUF block 200. The key generator 130 can generate the nth element key by comparing the read nth cell data pair with the reference data pair.

[0044] In some example embodiments, the number of retries for generating the nth element key can be predetermined, and when the number of retries exceeds the predetermined number, the control logic 110 can update the address table TB_1 so that the PUF unit corresponding to the corresponding PUF unit data pair (hereinafter referred to as the unavailable PUF unit) can be excluded from generating the authentication key KEY. Furthermore, the control logic 110 can generate a notification signal notifying the unavailable PUF unit and can provide the notification signal to an external host.

[0045] In some example embodiments, the controller 100 may determine the number of retries during the operation of the setting integrated circuit 10, and the number of retries may be equal or different among the PUF units or groups of PUF units. See below for further details. Figure 14A and Figure 14B Describe the method for determining the number of retries, executed by controller 100.

[0046] Integrated circuit 10 can provide the authentication key KEY generated by the above method to an external host.

[0047] According to the example embodiment, the integrated circuit 10 can refer to the address table TB_1 representing the mapping relationship in the PUF unit group to read multiple PUF unit data pairs PUF_DP, and can generate an authentication key KEY with reduced bit error rate and enhanced reliability by using multiple read PUF unit data pairs.

[0048] In addition, because integrated circuit 10 does not use an additional analog-to-digital converter (ADC) to generate the authentication key KEY, integrated circuit 10 can be designed to be smaller and its manufacturing cost can be reduced.

[0049] Figure 5 This shows the operation. Figure 1 The flowchart of the method for the integrated circuit 10.

[0050] Reference Figure 1 and Figure 5 In operation S100, the controller 100 can receive multiple PUF unit data pairs PUF_DP from the PUF block 200. Multiple PUF unit data pairs PUF_DP can be output from PUF units included in PUF unit groups, the PUF unit groups being mapped to each other with a predetermined mismatch distance regarding PUF unit characteristics.

[0051] In operation S120, the controller 100 can compare multiple PUF unit data pairs PUF_DP with reference data pairs respectively. The reference data pairs may have values ​​capable of determining whether the multiple PUF unit data pairs PUF_DP have correct values, and may be represented by values ​​respectively. Figure 2 The values ​​of the first PUF unit group Group_1 to the fourth PUF unit group Group_4 are used to determine the reference data pair.

[0052] In operation S140, controller 100 can generate authentication key KEY based on the comparison result of operation S120. Authentication key KEY includes element keys corresponding to multiple PUF unit data pairs PUF_DP.

[0053] Figure 6 It is shown Figure 5 A flowchart detailing an example embodiment of operations S120 and S140.

[0054] Reference Figure 1 and Figure 6 In operating S100 ( Figure 5 After that, in operation S122a, the controller 100 can compare the nth PUF unit data pair with the reference data pair.

[0055] In operation S141a, the controller 100 can determine whether the nth PUF cell data pair matches one of the reference data pairs. When it is determined in operation S141a that the nth PUF cell data pair matches one of the reference data pairs, then in operation S142a, the controller 100 can generate an element key for the nth PUF cell data pair, which has a value corresponding to the reference data pair that matches the nth PUF cell data pair.

[0056] In operation S143a, the controller 100 can determine whether 'n' has reached the number of 'm' PUF cell data pairs read. If it is determined in operation S143a that 'n' has not yet reached 'm' (the number of PUF cell data pairs read), then in operation S144a, 'n' is counted, and operation S122a can then be performed.

[0057] If, in operation S141a, it is determined that the nth PUF unit data pair does not match one of the reference data pairs, then in operation S145a, the controller 100 can again receive the nth PUF unit data pair from the PUF block 200. Subsequently, operation S122a can be performed.

[0058] Figure 7 This shows the generation Figure 1 A flowchart detailing the method for using element keys in integrated circuit 10 is provided below. For ease of understanding, please refer to... Figure 2 The given description is a premise.

[0059] Reference Figure 1 and Figure 7 In operation S300a, controller 100 may provide a control signal for reading the nth PUF unit data pair to PUF block 200. In operation S310a, controller 100 may receive the nth PUF unit data pair from PUF block 200. In operation S320a, the nth PUF unit data pair may be compared with each of '00 / 10' (or '10 / 00') and '01 / 11' (or '11 / 01'). The reference data pair '00 / 10' (or '10 / 00') may be used to determine whether the nth PUF unit data pair corresponds to the mapped first PUF unit group Group_1 and third PUF unit group Group_3, and the reference data pair '01 / 11' (or '11 / 01') may be used to determine whether the nth PUF unit data pair corresponds to the mapped second PUF unit group Group_1 and fourth PUF unit group Group_4.

[0060] When it is determined in operation S330a that the nth PUF unit data pair matches '00 / 10' (or '10 / 00'), the controller 100 may generate the nth element key with a value of '0'. When it is determined in operation S340a that the nth PUF unit data pair matches '01 / 11' (or '11 / 01'), the controller 100 may generate the nth element key with a value of '1'. On the other hand, when the nth PUF unit data pair does not match either '00 / 10' (or '10 / 00') or '01 / 11' (or '11 / 01'), the controller 100 may not generate the nth element key. In operation S350a, the controller 100 determines whether the nth element key has been generated. When it is determined in operation S350a that the nth element key has been generated, operation S360a is subsequently executed, such that the authentication key KEY including the nth element key can be provided to the external host. When it is determined in operation S350a that the key for the nth element has not been generated, operation S300a is then performed so that the nth PUF cell data pair can be reread from PUF block 200.

[0061] Figure 8A and Figure 8B This is a graph showing incorrect PUF cell data output by all PUF cells in the mapped PUF cell group. Figures 9 to 11 It is shown in Figure 8A and Figure 8B In the case of generating Figure 1 A flowchart of the method for obtaining the authentication key of integrated circuit 10.

[0062] Reference Figure 8A The xth PUF cell data pair xth PUF_DP is output from the PUF cells included in the first PUF cell group Group_1 and the third PUF cell group Group_3, which are mapped to each other, and will have a unique value '00 / 10' (or '10 / 00'). However, due to various factors, all the characteristics of the corresponding PUF cells will change, so that the xth PUF cell data pair xth PUF_DP can have a value '01 / 01'.

[0063] Reference Figure 8B Furthermore, the y-th PUF cell data pair yth PUF_DP is output from the PUF cells included in the second PUF cell group Group_2 and the fourth PUF cell group Group_4, which are mapped to each other, and will have a unique value '01 / 11' (or '11 / 01'). However, due to various factors, all the characteristics of the corresponding PUF cells will change, so that the y-th PUF cell data pair yth PUF_DP can have a value '10 / 10'.

[0064] like Figure 7As shown, when the xth PUF cell data pair xth PUF_DP and the yth PUF cell data pair yth PUF_DP have values ​​'01 / 01' and '10 / 10' respectively and do not match the reference data pair, the controller 100 may have to retry to generate element keys corresponding to the xth PUF cell data pair xth PUF_DP and the yth PUF cell data pair yth PUF_DP.

[0065] According to the example embodiment, the integrated circuit 10 can be used... Figure 8A and Figure 8B The element key is generated by mapping the first PUF unit group Group_1 to the fourth PUF unit group Group_4.

[0066] Figure 9 It is shown Figure 5 A flowchart detailing an example embodiment of operations S120 and S140.

[0067] exist Figure 9 In, because of previous reference Figure 6 Operations S100, S122b, and S141b to S144b are described, therefore their detailed descriptions are omitted.

[0068] Reference Figure 1 and Figure 9 When it is determined in operation S141b that the nth PUF cell data pair does not match one of the reference data pairs, operation S145b is subsequently executed, allowing the controller 100 to determine whether the values ​​of a specific bit in the nth PUF cell data pair are equal to each other. In some example embodiments, the specific bit may indicate whether each of the corresponding PUF cells in the nth PUF cell data pair has an upper 50% threshold voltage or a lower 50% threshold voltage. At this time, the reference... Figure 2 The specific bit can correspond to the high-order bit. In some example embodiments, the specific bit can correspond to the low-order bit. On the other hand, since the specific bit (or high-order bit) of the xth PUF cell data pair xth PUF_DP and the yth PUF cell data pair yth PUF_DP are equal to each other as '0' and '1', respectively, operation S146b can then be performed. When it is determined in operation S145b that the values ​​of the specific bits of the nth PUF cell data pair are equal to each other, in the subsequent operation S146b, the controller 100 can generate the element key of the nth PUF cell data pair, which has a value suitable for the specific bit.

[0069] In some example embodiments, controller 100 can generate an element key for the xth PUF cell data pair xth PUF_DP, which has a value of '0' considering the value of a specific bit (or high-order bit) of the xth PUF cell data pair xth PUF_DP. Additionally, controller 100 can generate an element key for the yth PUF cell data pair yth PUF_DP, which has a value of '1' considering the value of a specific bit (or high-order bit) of the yth PUF cell data pair yth PUF_DP. As a result, compared to... Figure 7 The operation S330a is compared, and an element key with a value of '0' corresponding to the xth PUF cell data pair xth PUF_DP can be appropriately generated, and compared with... Figure 7 The operation S340a is compared, and an element key with a value of '1' corresponding to the yth PUF cell data pair yth PUF_DP can be appropriately generated.

[0070] When it is determined in operation S145b that the values ​​of specific bits of the nth PUF unit data pair are not equal, in subsequent operation S147b, the controller 100 can again receive the nth PUF unit data pair from the PUF block 200. Then operation S122b can be executed.

[0071] Figure 10 This shows the generation Figure 1 A flowchart detailing the method for using element keys in integrated circuit 10 is provided below. For ease of understanding, please refer to... Figure 8A and Figure 8B The given description is a premise. Additionally, because of previous references... Figure 7 Operations S300b to S340b and operations S370b to S380b are described, therefore their detailed descriptions are omitted.

[0072] Reference Figure 10 In operation S350b following operation S340b, when the high-order bits of the nth PUF cell data pair are all equal to '0', the controller 100 can generate the nth element key with a value of '0'. In operation S360b, when the high-order bits of the nth PUF cell data pair are all equal to '1', the controller 100 can generate the nth element key with a value of '1'. As described above, although the nth PUF cell data pair does not match the reference data pair, the controller 100 can generate the nth element key based on the relationships within the mapped PUF cell groups.

[0073] Figure 11 This is a flowchart illustrating a method for generating an authentication key using a limited number of retries of an element key according to an example embodiment.

[0074] Reference Figure 1 and Figure 11 When operating S141a ( Figure 6 When it is determined in operation S410 that the nth PUF unit data pair does not match one of the reference data pairs, the controller 100 can determine in subsequent operation S410 whether the number of failed attempts to match the nth PUF unit data pair has reached the retry limit. If it is determined in operation S410 that the number of failed attempts to match the nth PUF unit data pair has not reached the retry limit, subsequent operation S145a can be executed. Figure 6 In some example embodiments, the controller 100 may predetermine the number of retries during the operation of the setting integrated circuit 10. The number of retries in the PUF cells of the PUF block 200 may be equal to each other, or in some example embodiments, the number of retries may differ between PUF cell groups or PUF cell subgroups. Multiple PUF cell subgroups may form a PUF cell group. (See also...) Figure 14A and Figure 14B The determination of the number of retries according to an example embodiment is described. When it is determined in operation S410 that the number of failures to match the nth PUF unit data pair has reached the number of retries, the controller 100 may determine that the generation of the nth element key by the nth PUF unit data pair has failed. In some example embodiments, because the controller 100 determines that the nth PUF unit data pair may not be used to generate the authentication key KEY in order to avoid unnecessary access to the PUF unit corresponding to the nth PUF unit data pair, an update operation to delete the address information on the corresponding PUF unit from the address table TB_1 may be performed. In operation S430, the controller 100 may provide a notification signal to the external host, notifying that the generation of the nth element key by the nth PUF unit data pair may not be necessary. When the notification signal is determined and the authentication key KEY is requested, the external host may consider the above situation.

[0075] As mentioned above, integrated circuits that support PUF can improve reliability and authentication key generation speed by limiting the number of retries, and thus exclude PUF units that prevent the generation of authentication keys.

[0076] Figure 12 This is a diagram illustrating the address table TB_2 for managing the number of retries according to an example embodiment.

[0077] Reference Figure 12 ,and Figure 4The address table TB_2 is compared with the address table TB_1, and the address table TB_2 may also include information about the number of retries. In some example embodiments, the number of retries to generate element keys for PUF cell data pairs corresponding to the addresses C1_ADD of the first PUF cell and C79_ADD of the 79th PUF cell that are mapped to each other may correspond to a first number RC1. The number of retries to generate element keys for PUF cell data pairs corresponding to the addresses C256_ADD of the 256th PUF cell and C67_ADD of the 67th PUF cell that are mapped to each other may correspond to a second number RC2. When a predetermined PUF cell data pair does not match a reference data pair, the controller 100 may determine the number of retries corresponding to the corresponding PUF cell data pair from the address table TB_2, read the corresponding PUF cell data pair by the number of retries, and may perform the operation of matching the corresponding PUF cell data pair with the reference data pair again. Although the number of retries has been described by using the address table TB_2, various methods can be used to manage the number of retries.

[0078] Figure 13 This indicates the settings (or updates). Figure 1 The flowchart of the operation of integrated circuit 10 is shown below. For ease of understanding, please refer to... Figure 2 The given description is a premise.

[0079] Reference Figure 1 and Figure 13 In operation S500, the controller 100 may receive unique signals of multiple PUF units from the PUF block 200 at least once during the setting (or updating) operation of the integrated circuit 10. The controller 100 may generate or update an address table for generating an authentication key KEY before the authentication operation by using the received unique signals of the PUF units. In operation S510, the controller 100 may group the multiple PUF units of the PUF block 200. In some example embodiments, the controller 100 may generate an address table by analyzing the values ​​of the unique signals of the multiple PUF units. Figure 2 The threshold voltage distribution. Controller 100 can divide the multiple PUF units into a first PUF unit group Group_1 to a fourth PUF unit group Group_4 by considering the values ​​of unique signals from the multiple PUF units. Additionally, controller 100 can determine a second reference point p2 to a fourth reference point p4 for representing the unique signals from the multiple PUF units as 2-bit data. In operation S520, controller 100 can map PUF unit groups with predetermined mismatch distances and can generate an address table representing the mapping relationships within the PUF unit groups. Because of the reference... Figure 4 and Figure 12The address table is described in detail, therefore its description is omitted. The controller 100 can store the generated address table in non-volatile memory 300. Additionally, for security, the controller 100 can remove unique signals from multiple PUF cells stored in predetermined registers to generate the address table.

[0080] Considering that the unique characteristics of the multiple PUF units in PUF block 200 may be irreversibly changed due to various factors, controller 100 can update the address table periodically or irregularly. In this case, controller 100 can update the address table by regrouping the multiple PUF units in PUF block 200 and remapping the PUF unit groups.

[0081] Figure 14A and Figure 14B This indicates the settings (or updates). Figure 1 A diagram illustrating the operation of integrated circuit 10.

[0082] Reference Figure 1 and Figure 14A In operation S600, the controller 100 may receive PUF cell data multiple times from multiple PUF cells of the PUF block 200 during the setting (or updating) operation of the integrated circuit 10. In operation S610, the controller 100 may determine the trend of multiple PUF cells by using the PUF cell data. Therefore, in some example embodiments, the controller 100 may determine the extent to which the PUF cell data value of a PUF cell has changed. In some example embodiments, when the number of times the PUF cell data value of a PUF cell changes is greater than a threshold, the controller 100 may determine that the probability of the PUF cell data value changing is high, and this trend may be taken into account when setting the number of retries corresponding to the corresponding PUF cell. In operation S620, the controller 100 may set the number of retries based on the determination result of operation S610, the number of retries may be arranged in an address table, and the address table may be stored in the non-volatile memory 300.

[0083] Reference Figure 14BPUF units exhibiting a high probability of data value change are included in the first PUF unit subgroups Sub_G21 and Sub_G22 of the second PUF unit group Group_2. Similarly, PUF units exhibiting a high probability of data value change are included in the third PUF unit subgroups Sub_G31 and Sub_G32 of the third PUF unit group Group_3. As an example embodiment only, the controller 100 may set the retry count for PUF units included in the first to fourth PUF unit subgroups Sub_G21, Sub_G22, Sub_G31, and Sub_G32 to be greater than the retry count for other PUF units. The retry count for PUF units included in the first to fourth PUF unit subgroups Sub_G21, Sub_G22, Sub_G31, and Sub_G32 may be set to be less than or equal to the retry count for other PUF units.

[0084] Figure 15 This is a block diagram illustrating an electronic device 1000 according to an example embodiment.

[0085] Electronic device 1000 can be one of various electronic devices that perform data encryption or security authentication, such as application processors, smart card integrated chips (ICs), mobile devices, data storage media such as solid-state drives (SSDs), memory sticks, universal flash memory (UFS) devices, memory cards, secure digital cards (SD cards), multimedia cards (MMCs) or eMMCs, and security devices.

[0086] Reference Figure 15 The electronic device 1000 may include at least one processor 1100, a PUF system 1200, an encryption module 1300, a non-volatile memory controller 1400, non-volatile memory 1410, random access memory (RAM) 1500, and an interface 1600. The electronic device 1000 may also include other components such as a communication module and input and output devices.

[0087] The processor 1100 can control all operations of the electronic device 1000. The processor 1100 can be implemented by a central processing unit (CPU) or a microprocessor, and can include single-core or multi-core processors.

[0088] RAM 1500 can operate as the working memory of the internal system of electronic device 1000. RAM 1500 may include at least one of volatile memory and non-volatile memory. Code and / or applications for managing electronic device 1000 can be loaded onto RAM 1500, and processor 1100 can execute the code and / or applications loaded onto RAM 1500. The code and / or applications can be stored in non-volatile memory 1410 or additional storage units.

[0089] Interface 1600 can be connected to input and output devices (not shown) via, for example, the following interfaces: RGB interface, CPU interface, serial interface, Mobile Display Digital Interface (MDDI), Interconnect Integrated Circuit (I2C) interface, Serial Peripheral Interface (SPI), Microcontroller Unit (MCU) interface, Mobile Industrial Processor Interface (MIPI), Embedded DisplayPort (eDP) interface, D-sub interface, optical interface, High Definition Multimedia Interface (HDMI), Mobile High Definition Link (MHL) interface, SD card / MMC interface, or Infrared Data Association (IrDA) standard interface.

[0090] The non-volatile memory controller 1400 can provide an interface between the non-volatile memory 1410 and other components of the electronic device 1000 (e.g., processor 1100, PUF system 1200, and encryption module 1300). Data to be stored in or read from the non-volatile memory 1410 can be received by or read from the non-volatile memory 1410 under the control of the memory controller 1400.

[0091] The non-volatile memory 1410 may include one of the following: one-time programmable (OTP) memory, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0092] The non-volatile memory 1410 can store code and / or applications for managing electronic device 1000 and user data. Additionally, to generate an authentication key KEY according to the example embodiment, an address table, reference points, and reference data pairs generated by the PUF system 1200 can be stored in the non-volatile memory 1410.

[0093] The encryption module 1300 can perform encryption and decryption on input and output data using the authentication key KEY provided by the PUF system 1200.

[0094] The PUF system 1200 can generate an authentication key KEY for security purposes. The PUF system 1200 can generate the authentication key KEY in response to an authentication key request signal provided by the processor 1100 or the encryption module 1300, and can provide the authentication key KEY to the encryption module 1300.

[0095] Reference Figures 1 to 14B The configuration and operation method of the described integrated circuit 10 can be applied to the PUF system 1200. The PUF system 1200 can be implemented through hardware, a combination of hardware and software, or a combination of hardware and firmware.

[0096] According to the example embodiment, the PUF system 1200 can generate an authentication key KEY that includes multiple element keys by receiving PUF unit data pairs with reference to an address table during the authentication operation and comparing the PUF unit data pairs with reference data pairs.

[0097] The address table according to the example embodiment can be formed to represent the relationship of PUF cell groups mapped to have a predetermined mismatch distance, and the PUF system 1200 can pre-generate the address table during the operation of setting the integrated circuit 10.

[0098] By summarizing and reviewing, security technologies with physically unclonable functions (PUFs) may be expected. PUF cells can be implemented in semiconductor chips using process variations generated in semiconductor manufacturing processes, and PUF cells can generate unpredictable random values. When keys are generated using PUF cells, it is possible to prevent the duplication of important keys, such as authentication keys stored in secure devices.

[0099] Multiple PUF units can include weak PUF units (where the key value may change with a high probability) and strong PUF units (where the key value may change with a low probability) due to variations in their characteristics. To ensure the reliability of the authentication key generated using multiple PUF units, weak PUF units can be selected and excluded from the generated authentication key. To select weak PUF units, the values ​​caused by their characteristics can be sorted for further subdivision, and thus complex logic such as an analog-to-digital converter (ADC) can be used. However, ADCs increase cost and the area of ​​the integrated circuit supporting the PUF.

[0100] As described above, the embodiments relate to an integrated circuit and a method of operation thereof for supporting physically unclonable functions (PUFs) with reduced bit error rate and enhanced reliability without complex logic.

[0101] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art up to the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An integrated circuit for physically unclonable functions, said integrated circuit comprising: A controller is configured to generate control signals with reference to an address table representing a first mapping relationship between a first group of physically unclonable function (PUF) cells and a second group of physically unclonable function (PUF) cells, and a second mapping relationship between a third group of physically unclonable function (PUF) cells and a fourth group of physically unclonable function (PUF) cells. The first group of PUF cells and the second group of PUF cells have a first predetermined mismatch distance with respect to the characteristics of the PUF cells, and the third group of PUF cells and the fourth group of PUF cells have a second predetermined mismatch distance with respect to the characteristics of the PUF cells. The mismatch distance is used to characterize PUF cell groups that are not adjacent to each other in the distribution of the characteristics of the PUF cells and are set as pairs. as well as A physically non-clonable function block, configured to provide a group of physically non-clonable function unit data to the controller in response to the control signal, according to the first mapping relationship and the second mapping relationship. The controller is configured to generate an authentication key by comparing the physical non-clonable function cell data set with a reference data set, respectively. The first and fourth physically unclonable function unit groups include multiple strong physically unclonable function units, and the second and third physically unclonable function unit groups include multiple weak physically unclonable function units. The probability of key value change in the multiple strong physically unclonable function units is lower than the probability of key value change in the multiple weak physically unclonable function units.

2. The integrated circuit according to claim 1, wherein, The physically unclonable function block is configured to include physically unclonable function units, which form a threshold voltage distribution and are divided into a first group of physically unclonable function units to a fourth group of physically unclonable function units based on the magnitude of the threshold voltage.

3. The integrated circuit according to claim 2, wherein, The first physical non-cloning function unit group corresponds to the lowest first region in the threshold voltage distribution, the second physical non-cloning function unit group corresponds to the second highest second region in the threshold voltage distribution, the third physical non-cloning function unit group corresponds to the second lowest third region in the threshold voltage distribution, and the fourth physical non-cloning function unit group corresponds to the highest fourth region in the threshold voltage distribution.

4. The integrated circuit according to claim 2, wherein, The address table includes: Information that the addresses of physically non-cloning function cells included in the first group of physically non-cloning function cells are mapped to the addresses of physically non-cloning function cells included in the second group of physically non-cloning function cells; and The address of the physically non-cloning function unit included in the third group of physically non-cloning function units is mapped to the address of the physically non-cloning function unit included in the fourth group of physically non-cloning function units.

5. The integrated circuit according to claim 1, wherein, The controller is configured to generate an nth element key for the nth physical non-cloning function cell data set in the physical non-cloning function cell data set, the nth element key having a value suitable for a reference data set in the reference data set that matches the nth physical non-cloning function cell data set, where n is an integer greater than or equal to 1.

6. The integrated circuit according to claim 1, wherein, When the nth physical non-cloning function cell data set in the physical non-cloning function cell data set does not match the reference data set, the controller is configured to retry to generate the nth element key corresponding to the nth physical non-cloning function cell data set, where n is an integer greater than or equal to 1.

7. The integrated circuit according to claim 6, wherein, When the number of retries used to generate the nth element key is greater than a predetermined number of retries, the controller is configured to update the address table such that the nth physical non-clonable function unit data set is not used to generate the authentication key.

8. The integrated circuit according to claim 7, wherein, The controller is configured to generate a notification signal indicating that the key of the nth element of the nth physical non-clonable function cell data group has not been generated, and The generated notification signal is provided to an external host.

9. The integrated circuit according to claim 1, wherein, When the nth physical non-cloning function cell data set in the physical non-cloning function cell data set does not match the reference data set, the controller is configured to determine whether the values ​​of specific bits of the nth physical non-cloning function cell data set are equal to each other, and generate the nth element key corresponding to the nth physical non-cloning function cell data set based on the determination result, where n is an integer greater than or equal to 1.

10. The integrated circuit according to claim 9, wherein, The specific location indicates that each of the corresponding physically unclonable function cells in the nth physically unclonable function cell data set has an upper 50% threshold voltage or a lower 50% threshold voltage, and When the specific locations of the nth physical non-clonable function unit data group are equal to each other, the controller is configured to generate the nth element key with a value suitable for the specific location.

11. The integrated circuit according to claim 1, wherein, In setting up the integrated circuit, the controller is configured to generate the address table through the following steps: Based on the unique signal received from the physically unclonable function unit, the physically unclonable function units of the physically unclonable function block are divided into the first group of physically unclonable function units to the fourth group of physically unclonable function units, and The addresses of the physically unclonable function units are mapped to fit the first mapping relationship and the second mapping relationship.

12. An integrated circuit for physically unclonable functions, said integrated circuit comprising: A block of physically non-clonable functions, which is configured to include physically non-clonable function units; as well as A controller is configured to receive pairs of Physically Unclonable Function (PUF) data based on a first mapping relationship between a first PUF group and a second PUF group, and a second mapping relationship between a third PUF group and a fourth PUF group. The first and second PUF groups have a first predetermined mismatch distance with respect to PUF characteristics, and the third and fourth PUF groups have a second predetermined mismatch distance with respect to the PUF characteristics. The mismatch distance characterizes PUF groups that are not adjacent to each other in the distribution of the PUF characteristics and are set as pairs. The controller is configured as follows: The element key forming the authentication key is generated by comparing the physical non-clonable function cell data pairs with reference data pairs, and An element key corresponding to the at least one physically non-clonable function cell data pair is generated by determining whether specific bits of at least one physically non-clonable function cell data pair that does not match the reference data pair are equal to each other.

13. The integrated circuit according to claim 12, wherein, The controller is configured to: Based on the matching result between the physically non-clonable function cell data pair and the reference data pair, the element key corresponding to the physically non-clonable function cell data pair is generated, and The element key is output to an external host.

14. The integrated circuit according to claim 12, wherein, The controller is configured to: Reread at least one physically non-clonable function cell data pair that does not match the reference data pair, and Generate element keys corresponding to the at least one physically unclonable function unit data pair.

15. The integrated circuit according to claim 12, wherein: The specific location indicates that each of the corresponding physically non-clonable function cells in the at least one physically non-clonable function cell data pair has an upper 50% threshold voltage or a lower 50% threshold voltage, and When the specific locations of the at least one physically non-clonable function cell data pair are equal to each other, the controller is configured to generate an element key having a value suitable for the specific location and corresponding to the at least one physically non-clonable function cell data pair.

16. The integrated circuit according to claim 12, wherein, In response to an authentication key request signal received from an external host, the controller is configured to: Based on the address table representing the first mapping relationship and the second mapping relationship, control signals for requesting the physical non-clonable function unit data pairs are provided to the physical non-clonable function block.

17. The integrated circuit according to claim 16, wherein, In setting up the integrated circuit, the controller is configured to generate the address table through the following steps: Based on the unique signal received from the physically unclonable function unit, the physically unclonable function units of the physically unclonable function block are divided into the first group of physically unclonable function units to the fourth group of physically unclonable function units, and The addresses of the physically unclonable function units are mapped to fit the first mapping relationship and the second mapping relationship.

18. The integrated circuit according to claim 17, wherein: The physically non-clonable function units form a threshold voltage distribution, and The first physical non-cloning function unit group corresponds to the lowest first region in the threshold voltage distribution, the second physical non-cloning function unit group corresponds to the second highest second region in the threshold voltage distribution, the third physical non-cloning function unit group corresponds to the second lowest third region in the threshold voltage distribution, and the fourth physical non-cloning function unit group corresponds to the highest fourth region in the threshold voltage distribution.

19. A method of operating an integrated circuit, the integrated circuit including a controller and a physically unclonable function block, the method comprising: Receive authentication key request at the controller; In response to the authentication key request received through the controller, a control signal is provided from the controller to the physically unclonable function block, the control signal being used to read a pair of physically unclonable function units corresponding to a first physically unclonable function unit and a second physically unclonable function unit, the second physically unclonable function unit being paired with the first physically unclonable function unit; In response to the control signal, the physically unclonable function cell data pair is provided from the physically unclonable function block to the controller; The physically non-clonable function cell data pairs are compared with reference data pairs, wherein the comparisons are performed by the controller; and An authentication key is generated from the controller based on the comparison result. The authentication key includes an element key corresponding to the physical non-clonable function cell data pair. Wherein, the first physically unclonable function unit is a strongly physically unclonable function unit, the second physically unclonable function unit is a weakly physically unclonable function unit, and the key value change probability of the strongly physically unclonable function unit is less than the key value change probability of the weakly physically unclonable function unit.

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