Cache Metadata Management

Abstract

This application relates to cache metadata management. A memory subsystem may include an interface controller coupled to non-volatile memory and volatile memory. The interface controller may operate the volatile memory as a cache using metadata such as validity information and dirty information. The interface controller may store the dirty information in the volatile memory and may store the validity information in an array in the interface controller.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 042,951, entitled "CACHE METADATA MANAGEMENT," filed on Jun. 23, 2020, by Song et al., which is assigned to the assignee of the present application and is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This technical field relates to cache metadata management. BACKGROUND

[0004] The following generally relates to one or more memory systems and, more particularly, to cache metadata management in a memory subsystem.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states and can store any one of them. To access the stored information, a component can read or sense at least one of the stored states of the memory device. To store information, a component can write or program a state into the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can retain its stored logical state for long periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. SUMMARY

[0007] A device is described. The device may include: a non-volatile memory; a volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable to cause the device to: store validity information in an array in the interface controller, the validity information indicating whether data stored in a set of volatile memory cells in the volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller; and store dirty information in the volatile memory, the dirty information indicating whether the data stored in the set of volatile memory cells in the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory.

[0008] A device is described. The device may include an interface controller coupled to a non-volatile memory and a volatile memory. The interface controller may be operable to cause the device to: receive an access command associated with a portion of the non-volatile memory from a host device coupled to the device; transfer validity information from an array in the interface controller to a register in the interface controller at least in part based on the access command, the validity information indicating whether data stored in a portion of the volatile memory was previously written to the portion of the volatile memory in response to a previous access command from the host device; and transfer dirty information from the volatile memory to the register at least in part based on the access command, the dirty information indicating whether the data stored in the portion of the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory.

[0009] A method is described. The method may include storing validity information in an array in an interface controller, the validity information indicating whether data stored in a set of volatile memory cells in a volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller; and storing dirty information in the volatile memory, the dirty information indicating whether the data stored in the set of volatile memory cells in the volatile memory does not exist in a non-volatile memory coupled to the interface controller or is inconsistent with corresponding data in the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting cache metadata management in accordance with an example disclosed herein is illustrated.

[0011] Figure 2 An example of a memory subsystem supporting cache metadata management in accordance with an example disclosed herein is illustrated.

[0012] Figure 3Illustrates an example of an apparatus supporting cache metadata management according to an example disclosed herein.

[0013] Figures 4 to 6 Illustrates an example of a method flow supporting cache metadata management according to an example disclosed herein.

[0014] Figure 7 Shows a row of volatile memory supporting cache metadata management according to aspects of the present disclosure.

[0015] Figure 8 Shows a block diagram of a memory subsystem supporting cache metadata management according to aspects of the present disclosure.

[0016] Figure 9 and 10 Shows a flowchart illustrating one or more methods for supporting cache management in a memory subsystem according to an example disclosed herein. Detailed Description

[0017] Devices such as electronic devices may include a main memory (e.g., a main memory for storing information among other operations) and a secondary memory that may operate as a cache. To operate the secondary memory as a cache, the device may use metadata indicating the data state in one or more portions of the secondary memory. For example, the device may use validity information that indicates whether the data stored in a portion of the memory is actual data (e.g., data previously written to that portion) or garbage data (e.g., data such as random data stored in that portion during initialization, startup, reset, or some other procedure). The device may also use dirty information that indicates whether the data stored in a portion of the memory has been modified since it was stored in the main memory or has been completely lost from the main memory.

[0018] In some instances, a device that uses metadata to manage a cache may store the metadata in a separate location, such as a separate array. However, storing the metadata in a separate array may be impractical if the size of the cache results in a high percentage of the array being consumed or a metadata volume that exceeds the storage capacity of the array. In an alternative, the device may store the cache's metadata within the cache itself. However, storing metadata in the cache may have negative impacts on latency and increase issues such as the cache's bandwidth consumption. For example, the latency to retrieve data from the cache may increase (e.g., double) relative to other metadata storage techniques because two read operations are performed on the cache when there is a cache hit. One read operation may be performed to determine that the requested data is in the cache, and another read operation may be performed again to retrieve the data. Similarly, the cache's bandwidth consumption is increased because both metadata and data are transferred from the cache in the case of a cache hit.

[0019] According to the techniques described herein, a device may store a certain amount of metadata, such as a relatively large amount of metadata (e.g., relative to the size of the array), by partitioning the storage of the metadata between the cache and the array and reserve the latency and bandwidth parameters for the cache. In some instances, the storage of the metadata may be partitioned based on the type of the metadata. For example, the device may store dirty information in the cache and store validity information in the array. Storing the dirty information in the cache may free up memory cells in the array for other information related to cache management. And storing the validity information in the array may reduce cache latency and bandwidth consumption by reducing the number of times the cache is read during a retrieval operation. In some instances, the metadata stored in the array or the cache may be updated by a masked write operation, which may reduce latency and power consumption relative to other update schemes (e.g., read-modify-write scheme).

[0020] Initially described in the context of a memory system and subsystem as described in reference Figure 1 and 2 The features of the present disclosure are described. The features of the present disclosure are described in the context of a device as described in reference Figure 3 as described in reference Figures 4 to 6 a method flow as described in reference Figure 7 and a volatile memory row as described in reference Figures 8 to 10 These and other features of the present disclosure are further illustrated and described by device diagrams and flowcharts related to cache metadata management as described in reference

[0021] Figure 1FIG. illustrates an example of a memory system 100 that supports cache management in a memory subsystem according to the examples disclosed herein. The memory system 100 may be included in an electronic device such as a computer or a telephone. The memory system 100 may include a host device 105 and a memory subsystem 110. The host device 105 may be a processor or a system-on-chip (SoC) that interfaces with an interface controller 115 and other components of the electronic device that includes the memory system 100. The memory subsystem 110 may store and provide access to electronic information (e.g., digital information, data) for the host device 105. The memory subsystem 110 may include an interface controller 115, volatile memory 120, and non-volatile memory 125. In some examples, the interface controller 115, volatile memory 120, and non-volatile memory 125 may be included in the same physical package such as package 130. However, the interface controller 115, volatile memory 120, and non-volatile memory 125 may be arranged on different respective dies (e.g., silicon dies).

[0022] Devices in the memory system 100 may be coupled by various conductive lines (e.g., traces, printed circuit board (PCB) routings, redistribution layer (RDL) routings) that may enable communication of information (e.g., commands, addresses, data) between the devices. The conductive lines may form channels, data buses, command buses, address buses, etc.

[0023] The memory subsystem 110 may be configured to provide the benefits of the non-volatile memory 125 while maintaining compatibility with the host device 105 that supports protocols for different types of memory (e.g., volatile memory 120, etc.). For example, the non-volatile memory 125 may provide benefits such as non-volatility, higher capacity, or lower power consumption (e.g., relative to the volatile memory 120). However, the host device 105 may be incompatible or inefficiently configured with respect to various aspects of the non-volatile memory 125. For example, the host device 105 may support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory 125. To compensate for the incompatibility between the host device 105 and the non-volatile memory 125, the memory subsystem 110 may be configured with volatile memory 120 that is compatible with the host device 105 and serves as a cache for the non-volatile memory 125. Thus, the host device 105 may use the protocols supported by the volatile memory 120 while benefiting from the advantages of the non-volatile memory 125.

[0024] In some instances, the memory system 100 may be included in or coupled to a computing device, an electronic device, a mobile computing device, or a wireless device. The device may be a portable electronic device. For example, the device may be a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. In some instances, the device may be configured for two-way wireless communication via a base station or an access point. In some instances, the device associated with the system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with the system 100 may be referred to as a user equipment (UE), a station (STA), a mobile terminal, etc.

[0025] The host device 105 may be configured to interface with the memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by the interface controller 115. Thus, in some instances, the host device 105 may interface directly with the interface controller 115 and indirectly with the non-volatile memory 125 and the volatile memory 120. In alternative instances, the host device 105 may interface directly with the non-volatile memory 125 and the volatile memory 120. The host device 105 may also interface with other components of the electronic device that includes the memory system 100 as well. The host device 105 may be or include a System-on-Chip (SoC), a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In some instances, the host device 105 may be referred to as a host.

[0026] The interface controller 115 may be configured to interface with the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105 (e.g., based on one or more commands or requests issued by the host device 105). For example, the interface controller 115 may facilitate the retrieval and storage of data in the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105. Thus, the interface controller 115 may facilitate data transfer between various sub-components, such as between at least some of the host device 105, the volatile memory 120, or the non-volatile memory 125. The interface controller 115 may interface with the host device 105 and the volatile memory 120 using the first protocol and may interface with the non-volatile memory 125 using a second protocol supported by the non-volatile memory 125.

[0027] The non-volatile memory 125 can be configured to store digital information (e.g., data) of the electronic device including the memory system 100. Thus, the non-volatile memory 125 can include an array of memory cells and a local memory controller configured to operate one or more arrays of memory cells. In some instances, the memory cells can be or include FeRAM cells (e.g., the non-volatile memory 125 can be FeRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a second protocol different from the first protocol used between the interface controller 115 and the host device 105. In some instances, the non-volatile memory 125 can have a longer access operation latency than the volatile memory 120. For example, retrieving data from the non-volatile memory 125 may take longer than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 may take longer than writing data to the volatile memory 120. In some instances, the non-volatile memory 125 can have a smaller page size than the volatile memory 120, as described herein.

[0028] The volatile memory 120 can be configured to operate as a cache for one or more components such as the non-volatile memory 125. For example, the volatile memory 120 can store information (e.g., data) of the electronic device including the memory system 100. Thus, the volatile memory 120 can include one or more arrays of memory cells and a local memory controller configured to operate one or more arrays of memory cells. In some instances, the memory cells can be or include DRAM cells (e.g., the volatile memory can be DRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using the first protocol used between the interface controller 115 and the host device 105.

[0029] In some instances, the volatile memory 120 can have a shorter access operation latency than the non-volatile memory 125. For example, retrieving data from the volatile memory 120 takes less time than retrieving data from the non-volatile memory 125. Similarly, writing data to the volatile memory 120 takes less time than writing data to the non-volatile memory 125. In some instances, the volatile memory 120 can have a larger page size than the non-volatile memory 125. For example, the page size of the volatile memory 120 can be 2 kilobytes (2 kB), while the page size of the non-volatile memory 125 can be 64 bytes (64B) or 128 bytes (128B).

[0030] Although the non-volatile memory 125 can be a higher density memory than the volatile memory 120, accessing the non-volatile memory 125 may take longer than accessing the volatile memory 120 (e.g., due to different architectures and protocols, etc.). Thus, operating the volatile memory 120 as a cache can reduce latency in the memory system 100. For example, by retrieving data from the volatile memory 120 rather than from the non-volatile memory 125, an access request for data from the host device 105 can be satisfied relatively quickly. To facilitate the operation of the volatile memory 120 as a cache, the interface controller 115 can include a plurality of buffers 135. The buffers 135 can be disposed on the same die as the interface controller 115 and can be configured to temporarily store data to be transferred between the volatile memory 120, the non-volatile memory 125, or the host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0031] An access operation may also be referred to as an access process or access procedure and may involve one or more sub-operations performed by one or more of the components of the memory subsystem 110. Examples of access operations may include a store operation in which data provided by the host device 105 is stored (e.g., written) in the volatile memory 120 or the non-volatile memory 125 (or both), and a retrieve operation in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and returned to the host device 105.

[0032] To store data in the memory subsystem 110, the host device 105 can initiate a store operation (or “store process”) by transmitting a store command (also referred to as a store request, write command, or write request) to the interface controller 115. The store command can be targeted at a set of non-volatile memory cells in the non-volatile memory 125. In some instances, a set of memory cells can also be referred to as a portion of the memory. The host device 105 can also provide the data to be written to the set of non-volatile memory cells to the interface controller 115. The interface controller 115 can temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, the interface controller 115 can transfer the data from buffer 135-a to the volatile memory 120 or the non-volatile memory 125 or both. In a write-through mode, the interface controller 115 can transfer the data to both the volatile memory 120 and the non-volatile memory 125. In a write-back mode, the interface controller 115 can transfer the data only to the volatile memory 120.

[0033] In any mode, interface controller 115 may identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a storage command. To this end, interface controller 115 may implement set-associative mapping, where each group (e.g., block) of one or more non-volatile memory cells in non-volatile memory 125 may be mapped to multiple sets of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement n-way set-associative mapping, which allows data from a group of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Thus, interface controller 115 may manage volatile memory 120 as a cache of non-volatile memory 125 by referring to the n sets of volatile memory cells associated with the target group of non-volatile memory cells. As used herein, unless otherwise described or indicated, a "set" of objects may refer to one or more objects. Although described with reference to set-associative mapping, interface controller 115 may manage volatile memory 120 as a cache by implementing one or more other types of mapping (e.g., direct mapping or associative mapping, etc.).

[0034] After determining which n sets of volatile memory cells are associated with the target group of non-volatile memory cells, interface controller 115 may store data in one or more of the n sets of volatile memory cells. In this way, subsequent retrieval commands for data from host device 105 can be effectively satisfied by retrieving data from the lower-latency volatile memory 120 rather than from the higher-latency non-volatile memory 125. Interface controller 115 may determine which of the n sets of volatile memory 120 stores the data based on one or more parameters associated with the data stored in the n sets of volatile memory 120, such as the validity, age, or modification status of the data. Thus, by storing data in volatile memory 120, the storage commands of host device 105 may be fully (e.g., in write-back mode) or partially (e.g., in write-through mode) satisfied. To track the data stored in volatile memory 120, interface controller 115 may store a tag address for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells), which indicates the non-volatile memory cell having data stored in a given set of volatile memory cells.

[0035] To retrieve data from the memory subsystem 110, the host device 105 may initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also known as a retrieval request, read command, or read request) to the interface controller 115. The retrieval command may target a set of one or more non-volatile memory cells in the non-volatile memory 125. Upon receiving the retrieval command, the interface controller 115 may check for the requested data in the volatile memory 120. For example, the interface controller 115 may check for the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If one of the n sets of volatile memory cells stores the requested data (e.g., stores the data of the target set of non-volatile memory cells), then the interface controller 115 may transfer the data from the volatile memory 120 to the buffer 135-a (e.g., in response to determining that one of the n sets of volatile memory cells stores the requested data), such that it may be transmitted to the host device 105. The term "hit" may be used to refer to the situation where the volatile memory 120 stores the data requested by the host device 105. If none of the n sets of one or more volatile memory cells store the requested data (e.g., the n sets of volatile memory cells store the data of a set of non-volatile memory cells other than the target set of non-volatile memory cells), then the interface controller 115 may transfer the requested data from the non-volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n sets of volatile memory cells do not store the requested data), such that it may be transmitted to the host device 105. The term "miss" may be used to refer to the situation where the volatile memory 120 does not store the data requested by the host device 105.

[0036] In a miss scenario, after the requested data is transferred to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120 such that the subsequent read request for the data can be satisfied by volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store the data in one of n groups of volatile memory cells associated with the target group of non-volatile memory cells. However, the n groups of volatile memory cells may already store data of other groups of non-volatile memory cells. Thus, to save the other data, interface controller 115 may transfer the other data to buffer 135-b such that it is transferred to non-volatile memory 125 for storage. This process may be referred to as "eviction", and the data transferred from volatile memory 120 to buffer 135-b may be referred to as "sacrifice" data. In some instances, interface controller 115 may transfer a subset of the sacrifice data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 may transfer one or more subsets of the sacrifice data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory but not the other) may be referred to as "modified" or "dirty" data in some instances. In some instances (e.g., when the interface controller operates in a mode such as write-back mode), dirty data may be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0037] In some instances, the interface controller 115 may operate the volatile memory 120 as a cache based on metadata that provides information about data stored in the volatile memory 120. For example, the interface controller 115 may use metadata such as validity information or dirty information to manage the volatile memory 120 as a cache. Validity information may include information indicating whether the data stored in the volatile memory 120 is actual data (e.g., data stored in the volatile memory 120 based on a command from the host device 105) or garbage data (e.g., data inadvertently stored or stored as a placeholder in the volatile memory 120 after initialization, startup, or some other procedure). Thus, the interface controller 115 may determine a cache hit or miss by referring to the validity information of the volatile memory 120. Dirty information may include information indicating whether the data stored in the volatile memory 120 is inconsistent with the data stored in the non-volatile memory 125. For example, the dirty information may indicate whether the data stored in the volatile memory 120 has been modified 1) because it has been stored in the non-volatile memory 125 (which may occur in write-through mode) or 2) does not exist in the non-volatile memory 125 (which may occur in write-back mode).

[0038] In some instances, the memory subsystem 110 may store the validity information and the dirty information in an array included in the interface controller 115. However, this storage technique may be impractical if problems such as the size of the volatile memory 120 (e.g., storage capacity, number of addressable memory cells) result in an amount of validity information and dirty information that exceeds (or disproportionately consumes) the storage capacity of the array. Alternatively, the memory subsystem 110 may store the validity information and the dirty information in the volatile memory 120. However, this storage technique may have a negative impact on the latency or bandwidth of the memory subsystem 110, among other issues. For example, in the case of a cache hit, the volatile memory may be accessed twice (e.g., once to read the validity information and again to read the requested data), which may increase the latency of retrieving the data. In addition, the validity information may be transferred from the volatile memory 120 in addition to the requested data, which may consume additional bandwidth (e.g., pins on the bus).

[0039] In accordance with the techniques described herein, the memory subsystem 110 can save array resources and improve the efficiency of cache retrieval operations, among other advantages, by storing validity information in the array and dirty information in the volatile memory 120. Storing the dirty information in the volatile memory 120 can save array resources by freeing up memory cells for other information. And storing the validity information in the array can improve the efficiency of cache retrieval operations by eliminating the need to access the volatile memory 120 twice in the case of a cache hit.

[0040] In some instances, the validity information may be referred to herein as a validity flag, a validity bit, or other suitable terms. Similarly, the dirty information may be referred to herein as a dirty flag, a dirty bit, or other suitable terms.

[0041] Figure 2 An example of a memory subsystem 200 that supports cache management in a memory subsystem in accordance with an example disclosed herein is illustrated. The memory subsystem 200 may be an example of the memory subsystem 110 described with reference to Figure 1 Thus, the memory subsystem 200 may interact with a host device as described with reference to Figure 1 The memory subsystem 200 may include an interface controller 202, a volatile memory 204, and a non-volatile memory 206, which may be examples of the interface controller 115, the volatile memory 120, and the non-volatile memory 125 described with reference to Figure 1 Thus, as described with reference to Figure 1 The interface controller 202 may interface with the volatile memory 204 and the non-volatile memory 206 on behalf of the host device. For example, the interface controller 202 may operate the volatile memory 204 as a cache for the non-volatile memory 206. Operating the volatile memory 204 as a cache may allow the subsystem to provide the benefits of the non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from the non-volatile memory 206.

[0042] In Figure 2 the dashed lines between components represent data flows or communication paths for data, while the solid lines between components represent command flows or communication paths for commands. In some instances, the memory subsystem 200 is one of a plurality of similar or identical subsystems that may be included in an electronic device. In some instances, each subsystem may be referred to as a die and may be associated with a respective channel of the host device.

[0043] The non-volatile memory 206 can be configured to operate as a main memory of a host device (e.g., a memory for long-term data storage). In some instances, the non-volatile memory 206 can include one or more FeRAM cell arrays. Each FeRAM cell can include a select component and a ferroelectric capacitor, and can be accessed by applying appropriate voltages to one or more access lines such as word lines, plate lines, and digit lines. In some instances, a subset of FeRAM cells coupled to an activated word line can be sensed (e.g., concurrently or simultaneously) without having to sense all FeRAM cells coupled to the activated word line. Thus, the page size of the FeRAM array can be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page can refer to memory cells in a row (e.g., a group of memory cells having a common row address), and the page size can refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size can refer to the size of data processed by various interfaces. In some instances, different memory device types can have different page sizes. For example, the DRAM page size (e.g., 2 kB) can be a superset of the non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0044] The smaller page size of the FeRAM array can provide various efficiency benefits because a single FeRAM cell can require more power to read or write than a single DRAM cell. For example, the smaller page size of the FeRAM array can facilitate efficient energy use because fewer FeRAM cells can be activated when the associated change in information is small. In some instances, the page size of the FeRAM cell array can vary dynamically (e.g., during operation of the FeRAM cell array) depending on, for example, the nature of the data and commands utilized with FeRAM operation.

[0045] Although a single FeRAM cell may require more power to read or write than a single DRAM cell, the FeRAM cell can maintain its stored logic state for a long time without an external power source because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization without an electric field. Thus, including a FeRAM array in the non-volatile memory 206 can provide an efficiency benefit relative to volatile memory cells (e.g., DRAM cells in the volatile memory 204) because it can reduce or eliminate the requirement to perform refresh operations.

[0046] The volatile memory 204 can be configured to operate as a cache for the non-volatile memory 206. In some instances, the volatile memory 204 can include one or more arrays of DRAM cells. Each DRAM cell can include a capacitor that includes a dielectric material to store a charge representing a programmable state. The memory cells of the volatile memory 204 can be logically grouped or arranged into one or more memory banks (referred to herein as "banks"). For example, the volatile memory 204 can include sixteen memory banks. The memory cells of a memory bank can be arranged in a grid or an array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digit lines (e.g., column lines) and word lines (e.g., row lines) of the memory cell. The rows of a memory bank can be referred to as pages, and the page size can refer to the number of columns or memory cells in a row. As described above, the page size of the volatile memory 204 can be different from (e.g., greater than) the page size of the non-volatile memory 206.

[0047] The interface controller 202 can include various circuits for interfacing (e.g., communicating) with other devices such as a host device, the volatile memory 204, and the non-volatile memory 206. For example, the interface controller 202 can include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces can support information communication using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 can support information communicated using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 can support information communicated using a second protocol. Thus, the various bus interfaces coupled to the interface controller 202 can support different data amounts or data rates.

[0048] The data bus interface 208 can be coupled to a data bus 260, a transaction bus 222, and a buffer circuit 224. The data bus interface 208 can be configured to transmit and receive data via the data bus 260 and to transmit and receive control information (e.g., acknowledgments / negative acknowledgments) or metadata via the transaction bus 222. The data bus interface 208 can also be configured to transfer data between the data bus 260 and the buffer circuit 224. The data bus 260 and the transaction bus 222 can be coupled to the interface controller 202 and the host device such that an electrical conduction path is established between the interface controller 202 and the host device. In some examples, the pins of the transaction bus 222 can be referred to as data mask inversion (DMI) pins. Although one data bus 260 and one transaction bus 222 are shown, any number of data buses 260 and any number of transaction buses 222 can be coupled to one or more data bus interfaces 208.

[0049] The C / A bus interface 210 can be coupled to a C / A bus 226 and a decoder 228. The C / A bus interface 210 can be configured to transmit and receive commands and addresses via the C / A bus 226. The commands and addresses received via the C / A bus 226 can be associated with the data received or transmitted via the data bus 260. The C / A bus interface 210 can also be configured to transmit commands and addresses to the decoder 228 such that the decoder 228 can decode the commands and relay the decoded commands and associated addresses to the command circuit 230.

[0050] The data bus interface 212 can be coupled to a data bus 232 and a memory interface circuit 234. The data bus interface 212 can be configured to transmit and receive data via the data bus 232, which can be coupled to the non-volatile memory 206. The data bus interface 212 can also be configured to transfer data between the data bus 232 and the memory interface circuit 234. The C / A bus interface 214 can be coupled to a C / A bus 236 and the memory interface circuit 234. The C / A bus interface 214 can be configured to receive commands and addresses from the memory interface circuit 234 and relay the commands and addresses to the non-volatile memory 206 (e.g., to the local controller of the non-volatile memory 206) via the C / A bus 236. The commands and addresses transmitted via the C / A bus 236 can be associated with the data received or transmitted via the data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206 such that an electrical conduction path is established between the interface controller 202 and the non-volatile memory 206.

[0051] The data bus interface 216 can be coupled to the data bus 238 and the memory interface circuit 240. The data bus interface 216 can be configured to transmit and receive data via the data bus 238 that can be coupled to the volatile memory 204. The data bus interface 216 can also be configured to transfer data between the data bus 238 and the memory interface circuit 240. The C / A bus interface 264 can be coupled to the C / A bus 242 and the memory interface circuit 240. The C / A bus interface 264 can be configured to receive commands and addresses from the memory interface circuit 240 and relay the commands and addresses to the volatile memory 204 (e.g., to the local controller of the volatile memory 204) via the C / A bus 242. The commands and addresses transmitted via the C / A bus 242 can be associated with the data received or transmitted via the data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204 such that an electrical conduction path is established between the interface controller 202 and the volatile memory 204.

[0052] In addition to the buses and bus interfaces for communicating with the coupled devices, the interface controller 202 can include circuitry for operating the non-volatile memory 206 as a main memory and the volatile memory 204 as a cache. For example, the interface controller 202 can include a command circuit 230, a buffer circuit 224, a cache management circuit 244, one or more engines 246, and one or more schedulers 248.

[0053] The command circuit 230 can be coupled to the buffer circuit 224, the decoder 228, the cache management circuit 244, the scheduler 248, and other components. The command circuit 230 can be configured to receive command and address information from the decoder 228 and store the command and address information in the queue 250. The command circuit 230 can include logic 262 that processes command information (e.g., from a host device) and stored information from other components (e.g., the cache management circuit 244, the buffer circuit 224), and uses this information to generate one or more commands for the scheduler 248. The command circuit 230 can also be configured to transfer address information (e.g., address bits) to the cache management circuit 244. In some instances, the logic 262 can be circuitry configured to operate as a finite state machine (FSM).

[0054] The buffer circuit 224 can be coupled to the data bus interface 208, the command circuit 230, the memory interface circuit 234, and the memory interface circuit 234. The buffer circuit 224 can include a set of one or more buffer circuits for at least some (if not each) of the memory banks of the volatile memory 204. The buffer circuit 224 can also include components for accessing the buffer circuit (e.g., a memory controller). In one example, the volatile memory 204 can include sixteen memory banks, and the buffer circuit 224 can include sixteen sets of buffer circuits. Each set of buffer circuits can be configured to store data from or for (or both) the corresponding memory bank of the volatile memory 204. For example, the set of buffer circuits for memory bank 0 (BK0) can be configured to store data from or for (or both) the first memory bank of the volatile memory 204, and the buffer circuit for memory bank 15 (BK15) can be configured to store data from or for (or both) the sixteenth memory bank of the volatile memory 204.

[0055] Each set of buffer circuits in the buffer circuit 224 can include a pair of buffers. The pair of buffers can include one buffer (e.g., an open page data (OPD) buffer) and another buffer (e.g., a sacrificed page data (VPD) buffer), the one buffer being configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device, and the other buffer being configured to store data of an eviction process generated by the access command. For example, the set of buffer circuits for BK0 can include buffer 218 and buffer 220, which can be instances of buffer 135-a and buffer 135-b, respectively. Buffer 218 can be configured to store BK0 data targeted by an access command from a host device. And buffer 220 can be configured to store data transferred from BK0 as part of an eviction process triggered by the access command. Each buffer in the set of buffer circuits can be configured to have a size (e.g., storage capacity) corresponding to the page size of the volatile memory 204. For example, if the page size of the volatile memory 204 is 2 kB, the size of each buffer can be 2 kB. Thus, in some examples, the size of the buffer can be equal to the page size of the volatile memory 204.

[0056] The cache management circuit 244 can be coupled to the command circuit 230, the engine 246, the scheduler 248, and other components. The cache management circuit 244 may include a set of cache management circuits for one or more memory banks (e.g., each memory bank) that are volatile memories. For example, the cache management circuit 244 may include sixteen sets of cache management circuits for BK0 to BK15. Each set of cache management circuits may include two memory arrays that may be configured to store storage information for the volatile memory 204. For example, the set of cache management circuits for BK0 may include the memory array 252 (e.g., CDRAM tag array (CDT-TA)) and the memory array 254 (e.g., CDRAM valid (CDT-V) array), which may be configured to store the storage information for BK0. In some instances, the memory arrays may also be referred to as arrays or buffers. In some instances, the memory arrays may be or include volatile memory cells, such as SRAM cells.

[0057] The storage information may include content information, validity information, or dirty information (or any combination thereof) associated with the volatile memory 204. The content information (which may also be referred to as tag information or address information) may indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) of a set of one or more volatile memory cells may indicate which set of one or more non-volatile memory cells currently has the data stored in that set of one or more volatile memory cells. As described above, the validity information may indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data having an expected order or form) or placeholder data (e.g., random or pseudo data that does not have an expected or significant order). The dirty information may indicate whether the data stored in a set of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data stored in a set of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirty information may indicate whether the data stored in a set of volatile memory cells has been updated relative to the data stored in the non-volatile memory 206.

[0058] The memory array 252 may include memory cells that store stored information (e.g., content and validity information) of an associated memory bank (e.g., BK0) of the volatile memory 204. The stored information may be stored on a per-page basis (e.g., there may be corresponding stored information for each page of the associated non-volatile memory bank). The interface controller 202 may check the requested data in the volatile memory 204 by referring to the stored information in the memory array 252. For example, the interface controller 202 may receive from a host device a retrieval command for data in a set of non-volatile memory cells in the non-volatile memory 206. The interface controller 202 may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to refer to the stored information in the memory array 252. For example, using set-associative mapping, the interface controller 202 may refer to the content information in the memory array 252 to determine which set of volatile memory cells (if any) stores the requested data.

[0059] In addition to storing the content information of the volatile memory cells, the memory array 252 may also store validity information indicating whether the data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, the volatile memory cells in the volatile memory 204 may initially store random data and continue to do so until the volatile memory cells are written with data from a host device or the non-volatile memory 206. To keep track of which data is valid, the memory array 252 may be configured to set a bit for each set of volatile memory cells when actual data is stored in the set. This bit may be referred to as a validity bit or a validity flag. Like the content information, the validity information stored in the memory array 252 may be stored on a per-page basis. Thus, in some instances, each validity bit may indicate the validity of the data stored in the associated page.

[0060] The memory array 254 may be similar to the memory array 252 and may also include memory cells that store validity information of a memory bank (e.g., BK0) storing volatile memory 204 associated with the memory array 252. However, the validity information stored in the memory array 254 may be based on sub-block storage rather than per-page storage of the memory array 252. For example, the validity information stored in the memory cells of the memory array 254 may indicate the validity of data of a subgroup of volatile memory cells in a group (e.g., a page) of volatile memory cells. For example, the validity information in the memory array 254 may indicate the validity of each subset (e.g., 32B or 64B) of data in a data page stored in BK0 of the volatile memory 204. Storing content information and validity information on a per-page basis in the memory array 252 may allow the interface controller 202 to quickly and efficiently determine whether there is a data hit or miss in the volatile memory 204. Storing validity information on a sub-block basis may allow the interface controller 202 to determine which data subsets are saved in the non-volatile memory 206 during an eviction process.

[0061] In addition to the validity information, the interface controller 202 may use dirty information to manage the volatile memory 204 as a cache. Similar to the validity information, the dirty information may be stored on a sub-block basis (e.g., each dirty bit may indicate the dirty state of a data subset in a data page). However, according to the techniques described herein, the dirty information may be stored in the volatile memory 204 and in some instances in the memory array 254. As described in more detail elsewhere herein, splitting the storage of the validity information and the dirty information between the memory array 254 and the volatile memory 204 may provide significant advantages compared to other storage techniques.

[0062] Each cache management circuit group may also include a corresponding pair of registers coupled to components such as command circuit 230, engine 246, memory interface circuit 234, memory interface circuit 240, and the memory array for that cache management circuit group. For example, the cache management circuit group may include a first register (e.g., register 256, which may be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information) from memory array 252 or scheduler 248-b or both. The cache management circuit group may also include a second register (e.g., register 258, which may be a victim page tag (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a or both. The information in register 256 and register 258 may be transmitted to command circuit 230 and engine 246 to enable these components to make decisions. For example, command circuit 230 may issue a command to read non-volatile memory 206 or volatile memory 204 based on the content information from register 256.

[0063] Engine 246-a may be coupled to register 256, register 258, and scheduler 248. Engine 246-a may be configured to receive storage information from various components and issue commands to scheduler 248 based on the storage information. For example, when interface controller 202 is in a first mode such as write-through mode, engine 246-a may issue a command to scheduler 248-b and, in response to scheduler 248-b, initiate or facilitate data transfer from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode such as write-back mode, engine 246-a may issue a command to scheduler 248-b, and in response, scheduler 248-b may initiate or facilitate data transfer from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 may ultimately be transferred to non-volatile memory 206 during a subsequent eviction process.

[0064] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive storage information from register 258 and issue commands to scheduler 248-a based on the storage information. For example, engine 246-b may issue a command to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of an eviction process). If buffer 220 holds a set of data transferred from volatile memory 204 (e.g., victim data), engine 246-b may indicate which subset or subsets (e.g., which 64B) of the set of data in buffer 220 should be transferred to non-volatile memory 206.

[0065] The scheduler 248-a can be coupled to various components of the interface controller 202 and can facilitate access to the non-volatile memory 206 by issuing commands to the memory interface circuit 234. The commands issued by the scheduler 248-a can be based on commands from the command circuit 230, the engine 246-a, the engine 246-b, or a combination of these components. Similarly, the scheduler 248-b can be coupled to various components of the interface controller 202 and can facilitate access to the volatile memory 204 by issuing commands to the memory interface circuit 240. The commands issued by the scheduler 248-b can be based on commands from the command circuit 230 or the engine 246-a or both.

[0066] The memory interface circuit 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuit 234 can prompt the C / A bus interface 214 to relay commands issued by the memory interface circuit 234 via the C / A bus 236 to the local controller in the non-volatile memory 206. And the memory interface circuit 234 can transfer data to or receive data from the non-volatile memory 206 via the data bus 232. In some instances, the commands issued by the memory interface circuit 234 can be supported by the non-volatile memory 206 but not by the volatile memory 204 (e.g., the commands issued by the memory interface circuit 234 can be different from the commands issued by the memory interface circuit 240).

[0067] The memory interface circuit 240 can communicate with the volatile memory 204 via one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuit 240 can prompt the C / A bus interface 264 to relay commands issued by the memory interface circuit 240 via the C / A bus 242 to the local controller of the volatile memory 204. And the memory interface circuit 240 can transfer data to or receive data from the volatile memory 204 via one or more data buses 238. In some instances, the commands issued by the memory interface circuit 240 can be supported by the volatile memory 204 but not by the non-volatile memory 206 (e.g., the commands issued by the memory interface circuit 240 can be different from the commands issued by the memory interface circuit 234).

[0068] The components of the interface controller 202 can operate together as the non-volatile memory 206 as the main memory and the volatile memory 204 as the cache. This operation can be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from the host device.

[0069] In some instances, the interface controller 202 may receive storage commands from a host device. The storage commands may be received via the C / A bus 226 and transmitted to the command circuit 230 via one or more of the C / A bus interface 210 and the decoder 228. The storage commands may include or be accompanied by address bits targeted at a memory address of the non-volatile memory 206. Data to be stored may be received via the data bus 260 and transmitted to the buffer 218 via the data bus interface 208. In the write-through mode, the interface controller 202 may transmit data to both the non-volatile memory 206 and the volatile memory 204. In the write-back mode, the interface controller 202 may transmit data only to the volatile memory 204. In either mode, the interface controller 202 may first check to see if the volatile memory 204 has memory cells available for storing data. To this end, the command circuit 230 may refer to the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets (e.g., pages) of volatile memory cells associated with the memory address are available (e.g., storing random or invalid data). For example, the command circuit 230 may determine whether one or more of the n sets of volatile memory cells are available based on tag information and validity information stored in the memory array 252. In some instances, a set of volatile memory cells in the volatile memory 204 may be referred to as a row or cache line.

[0070] If one of the n sets of associated volatile memory cells is available for storing information, the interface controller 202 may transmit data from the buffer 218 to the volatile memory 204 for storage in that set of volatile memory cells. However, if none of the associated sets of volatile memory cells are empty, the interface controller 202 may initiate an eviction process to make room for data in the volatile memory 204. The eviction process may involve transmitting old data (e.g., existing data) in one of the n sets of associated volatile memory cells to the buffer 220. The dirty information of the old data may also be transmitted to the memory array 254 or the register 258 to identify the dirty subset of the old data. After storing the old data in the buffer 220, new data may be transmitted from the buffer 218 to the volatile memory 204, and the old data may be transmitted from the buffer 220 to the non-volatile memory 206. In some instances, the dirty subset of the old data is transmitted to the non-volatile memory 206, and the clean subset (e.g., the unmodified subset) is discarded. The dirty subset may be identified by the engine 246-b based on the dirty information transmitted (e.g., from the volatile memory 204) to the memory array 254 or the register 258 during the eviction process.

[0071] In another example, interface controller 202 may receive a retrieval command from a host device. The retrieval command may be received via C / A bus 226 and transmitted to command circuit 230 through one or more of C / A bus interface 210 and decoder 228. The retrieval command may include address bits targeted at a memory address of non-volatile memory 206. Before attempting to access the targeted memory address of non-volatile memory 206, interface controller 202 may check to see if volatile memory 204 stores data. To this end, command circuit 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of n sets of volatile memory cells associated with the memory address store the requested data. For example, command circuit 230 may determine whether one or more of n sets of volatile memory cells store the requested data based on tag information and validity information stored in memory array 252. If the requested data is stored in volatile memory 204, interface controller 202 may transmit the requested data to buffer 218 for transmission to the host device via data bus 260.

[0072] If the requested data is not stored in volatile memory 204, interface controller 202 may retrieve the data from non-volatile memory 206 and transmit the data to buffer 218 for transmission to the host device via data bus 260. Additionally, interface controller 202 may transmit the requested data from buffer 218 to volatile memory 204 such that the data can be accessed with lower latency during subsequent retrieval operations. However, before transmitting the requested data, interface controller 202 may first determine whether one or more of n sets of associated volatile memory cells are available for storing the requested data. Interface controller 202 may determine the availability of n sets of associated volatile memory cells by communicating with associated cache management circuitry. If an associated set of volatile memory cells is available, interface controller 202 may transmit the data in buffer 218 to volatile memory 204 without performing an eviction process. Otherwise, interface controller 202 may transmit the data from buffer 218 to volatile memory 204 after performing an eviction process.

[0073] The memory subsystem 200 can be implemented in one or more configurations, including a single-chip version and a multi-chip version. The multi-chip version can include one or more components of the memory subsystem 200 on a chip separate from the chip including one or more other components of the memory subsystem 200, including the interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations of components). For example, in one multi-chip version, each individual chip can include each of the interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version can include the interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0074] As described above, the memory subsystem 200 can store different types of metadata in different memories of the memory subsystem 200. For example, the memory subsystem 200 can store dirty information in the volatile memory 204 and store validity information in the memory array 254. Storing the validity information in the memory array 254 and the dirty data in the volatile memory 204 can allow for the use of a large volatile memory 204 (e.g., a volatile memory 204 with more metadata than the memory array 254 can store or more metadata than is actually stored in the memory array 254) compared to storing both the validity information and the dirty information in the memory array 254. Storing the validity information in the memory array 254 and the dirty data in the volatile memory 204 can allow the interface controller 202 to perform a single read operation on the volatile memory 204 in the case of a cache hit, as opposed to two read operations, since the validity determination is performed by reading the memory array 254.

[0075] For example, the interface controller 202 can determine the validity of the stored data by reading the memory array 254 instead of the volatile memory 204, which means that a cache hit only involves one read operation on the volatile memory 204 (to retrieve the data). Similarly, in the case of a cache miss, no read operation is performed on the volatile memory array 204. Although determining the validity involves performing a read operation on the memory array 254, reading the memory array 254 instead of the volatile memory 204 has advantages such as being faster and consuming less power.

[0076] Therefore, splitting the storage of the validity information and the dirty information between the memory array 254 and the volatile memory 204 can provide significant benefits compared to other storage techniques.

[0077] Figure 3Illustrated is an example of apparatus 300 that supports cache metadata management according to an example disclosed herein. Apparatus 300 may be an example of the memory subsystem 110 described in reference Figure 1 or an example of the memory subsystem 200 described in reference Figure 2 Apparatus 300 may include an interface controller 305 and a volatile memory 310, which may be coupled to each other via one or more transmission lines and / or buses. Interface controller 305 may be an example of interface controller 115 described in reference Figure 1 or an example of interface controller 202 described in reference Figure 2 Volatile memory 310 may be an example of volatile memory 120 described in reference Figure 1 or an example of volatile memory 204 described in reference Figure 2 As described herein, apparatus 300 may store validity information in array 315 in interface controller 305 and store dirty information in volatile memory 310.

[0078] Interface controller 305 may include array 315, which may also be referred to as a memory array or a tag array. Array 315 may include sub-arrays 325 and 330, which may be examples of memory array 252 and memory array 254, respectively, as described in reference Figure 2 Accordingly, array 315 may include a plurality of memory volatile memory cells, such as SRAM cells. Array 315 may store the tag information of volatile memory array 320 in sub-array 325 and store the validity information of volatile memory array 320 in sub-array 330. The tag information in sub-array 325 may indicate the tag addresses of one or more rows in the associated memory bank of volatile memory array 320 (e.g., BK0). For example, sub-array 325 may store the tag information of rows 0 to N in volatile memory array 320. In some examples, sub-array 325 may also include validity information indicating row-based validity (e.g., one bit may indicate whether the associated row has valid or invalid data).

[0079] The validity information in sub-array 330 may indicate the validity of portions of rows in the associated memory bank of volatile memory array 320 (e.g., BK0). For example, sub-array 330 may store the validity information of thirty-two portions of row 0 in BK0. The validity information of a portion may also be referred to as a validity bit or a validity flag. In Figure 3In an example, the sub-array 330 stores thirty-two validity bits, with each part of a row storing one validity bit. In some examples, a part of a memory row may be or include thirty-two memory cells or sixty-four memory cells, and thus may store 32B or 64B of data respectively. A part of a memory or a memory row may also be referred to as a group of memory cells, a subset of memory cells, a section of memory, a subset of memory cells, or other suitable terms in a given context. Similarly, the data stored in a part of a memory or a memory row may be referred to as a data set, a data subset, a data sub-page, or other suitable terms.

[0080] The volatile memory 310 may include a local controller and circuitry for accessing a memory bank (e.g., BK0) of a volatile memory array 320 that may be or include volatile memory cells associated with the array 315. The volatile memory array 320 may include multiple columns and rows of volatile memory cells (e.g., DRAM cells). For example, the volatile memory array 320 may include rows 0 to row N. The volatile memory array 320 may include one or more sections of memory reserved for (e.g., dedicated to) storing data and other sections of memory reserved for storing dirty information. For example, one or more rows may include a section of memory reserved for storing data (“data section”) and a section of memory reserved for storing dirty information (“dirty information section”). A memory section may include a portion of memory associated with corresponding validity information stored in the sub-array 330 (e.g., a set of thirty-two memory cells or a set of sixty-four memory cells). In some examples, a row may include 2KB of data (e.g., 1KB of data in the first data section and 1KB of data in the second data section).

[0081] In some examples, each data section may be associated with a corresponding dirty information section that stores the dirty information of that data section. For example, in row N, the dirty information section 340-a may store the dirty information of the associated data section 335-a, and the dirty information section 340-b may store the dirty information of the associated data section 335-a. At a lower granularity level, each part in a data section may be associated with a corresponding dirty bit in the corresponding dirty information section. For example, if the data section 335-a includes sixteen parts, the dirty information section 340-a may include sixteen bits, each bit associated with a corresponding data part from the data section 335-a. Similarly, if the data section 335-b includes sixteen parts, the dirty information section 340-b may include sixteen bits, each bit associated with a corresponding data part from the data section 335-b. Thus, a group of memory cells (e.g., a portion of memory) in the volatile memory array 320 may be associated with dirty bits in the volatile memory array 320 and validity bits in the sub-array 330.

[0082] To quickly access the validity information stored in the sub-array 330 and the dirty information stored in the volatile memory array 320, the interface controller 305 can issue a command to the local controller such that the metadata is transferred to the registers in the interface controller 305. For example, the validity information and the dirty information can be transferred to the register 345, and the dirty information can be transferred to the register 350. The register 345 can be an instance of the register 256 (e.g., the OPT register) described in the reference Figure 2 and the register 350 can be an instance of the register 258 (e.g., the VPT register) described in the reference Figure 2 After the validity information and the dirty information have been transferred to the registers, the interface controller 305 can access the registers to effectively reference the validity information and the dirty information for cache management purposes. Although the storage of the validity information and the dirty information is shown, the register 345 can also store other information, such as the tag information transferred from the sub-array 325. Similarly, although the storage of the dirty information is shown, the register 350 can also store other information, such as the tag information transferred from the sub-array 325.

[0083] In some instances, the interface controller 305 can transfer the validity information from the sub-array 330 and the dirty information from the volatile memory array 320 to the register 345. As part of the access operation, the interface controller 305 can reference the validity information in the register 345 to determine which set of memory cells (portion of the memory) stores valid data. If the access operation results in writing data to the volatile memory array 320, the interface controller can update the dirty information in the register 345 to reflect any changes in the dirty state of the portion of the volatile memory array 320. If the access operation is triggered during an eviction process, the interface controller 305 can transfer the dirty information from the volatile memory array 320 to the register 350. The interface controller 305 can then reference the dirty information in the register 350 to determine which set of memory cells stores the dirty data that should be written back to the non-volatile memory.

[0084] To maintain the accuracy of validity information and dirty information after performing access operations on the volatile memory array 320, the device may update the validity information and dirty information in the register 345 when applicable. For example, after writing to a portion of the volatile memory array 320, the device may update the corresponding validity bit in the register 345. Once a command to close a row is received, the device may write the validity information in the register 345 back to the subarray 330 such that the subarray 330 has accurate (e.g., updated) validity information for the row. As another example, after writing to a portion of the volatile memory array 320, the device may update the corresponding dirty bit in the register 345. Once a command to close a row is received, the device may write the dirty information in the register 345 back to the volatile memory array 320 such that the volatile memory array 320 has accurate (e.g., updated) dirty information for the row.

[0085] Thus, the device 300 that stores validity information in the subarray 330 and dirty information in the volatile memory array 320 may use registers to reference and update the validity information and dirty information, and thus operate more efficiently and effectively.

[0086] Figure 4 An example of a method flow 400 that supports cache metadata management in accordance with examples disclosed herein is illustrated. The method flow 400 may be an example of a method flow implemented by a device that stores validity information in an array and stores dirty information in a volatile memory that serves as a non-volatile memory cache. Thus, in other examples, the method flow 400 may be implemented by the memory subsystem 110 described with reference to Figure 1 the memory subsystem 200 described with reference to Figure 2 or the device 300 described with reference to Figure 3 In some instances, aspects of the method flow 400 may be implemented by an interface controller and other components. Additionally or alternatively, aspects of the method flow 400 may be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, the instructions, when executed by a controller (e.g., the interface controller 115), may cause the controller to perform the operations of the method flow 400.

[0087] Alternative instances of the method flow 400 may be implemented, where some operations are performed in a different order than described or not performed at all. In some instances, the method flow 400 may include operations not mentioned herein (e.g., additional operations may be added). Additionally, some operations may be performed in parallel (e.g., concurrently, or during overlapping time periods).

[0088]

[0089] ​At 405, the device may receive an activate (ACT) command from the host device that is associated with a row (e.g., row N) of a volatile memory such as volatile memory array 320. In response to the activate command, at 410, the device may transfer metadata for the row to a register in the device, such as register 345. For example, the device may transfer tag information for row N from sub-array 325 and validity information for row N from sub-array 330 (e.g., thirty-two validity bits) to register 345. In some instances, the device may transfer dirty information for row N from volatile memory array 320 to register 345. The device may also open the associated volatile memory row (e.g., the device may open row N in volatile memory array 320). Opening a row may also be referred to as activating the row and may involve applying an activation voltage to a word line associated with the row.

[0090] At 415, the device may determine whether a subsequent command received from the host device is a read command. If the device determines that the subsequent command is a read command, then at 420, the device may determine whether data stored in row N of volatile memory array 320 is valid. The device may determine the validity of the data stored in row N by referring to the validity information in register 345. If it is determined that the data stored in row N is valid, then at 425, the device may return the data stored in row N to the host device. The device may then return to step 415. The device may not update the validity information in register 345 because the validity information already indicates that the data stored in row N is valid (i.e., the validity information is already accurate).

[0091] If it is determined at 420 that the data stored in row N is invalid, then at 430, the device may return the requested data from non-volatile memory to the host device. At 435, the device may store the requested data in volatile memory array 320 (e.g., for faster retrieval in the future). For example, the device may store the requested data in row N. Thus, at 440, the device may update the validity information for row N in register 345. For example, the device may modify the state of the validity bits in register 345 that are associated with the portion of row N in which the requested data has been written. The device may also update the dirty information for row N in register 345 when applicable. After updating the relevant metadata in register 345, the device may return to step 415.

[0092] At 415, if the device determines that the subsequent command is not a read command, then at 445, the device can determine whether the subsequent command is a write command. If the device determines that the subsequent command is a write command, then at 450, the device can write the data provided by the host device to the volatile memory array 320. For example, the device can store the requested data in row N. Thus, at 455, the device can update the validity information of row N in the register 345. For example, the device can modify the state of the validity bit in the register 345, where the validity bit is the associated part of row N in which the provided data has been written. The device can also update the dirty information of row N and / or the tag information of row N in the register 345 when applicable. After updating the validity information in the relevant metadata in the register 345, the device can return to step 415.

[0093] At 445, if the device determines that the subsequent command is not a write command, then at 460, the device can determine whether the subsequent command is a precharge command. Although shown separately, in some instances, the determinations at 415, 445, and 460 can be collapsed into a single operation. If the device determines that the subsequent command is a precharge command, then at 465, the device can update the validity information stored in the subarray 330 by writing the validity information in the register 345 back to the subarray 330. In some instances, the validity information is updated in the subarray 330 using a masked write operation as described in reference Figure 7 as described.

[0094] At 470, the device can determine whether any dirty information in the register 345 has been updated. For example, the dirty information can be updated in the register 345 in response to the device writing data to the volatile memory array 320 rather than to the non-volatile array (which can occur, for example, in a write-back mode). If the device determines that the dirty information has been updated, then at 475, the device can issue a special write command (e.g., a write dirty flag (WRCD) command) to the volatile memory 310 such that the updated dirty information in the register 345 is written to the volatile memory array 320. In some instances, the dirty information is updated in the volatile memory array 320 using a masked write operation as described in reference Figure 7 as described. After updating the dirty information in the volatile memory array 320, the device can issue a precharge command to the volatile memory 310 at 480 to close the row.

[0095] Thus, a device that stores metadata in two different memories can update the metadata of the open rows in the register and can save the updated metadata in the memories by writing the updated metadata back to the memories when the rows are closed.

[0096] Figure 5An example of a method flow 500 that supports cache metadata management according to an example disclosed herein is illustrated. The method flow 500 can be an example of a method flow implemented by a device that stores validity information in an array and stores dirty information in a volatile memory that serves as a non-volatile memory cache. Thus, the method flow 500 can be implemented by the memory subsystem 110 described with reference to Figure 1 the memory subsystem 200 described with reference to Figure 2 or the device 300 described with reference to Figure 3 . The method flow 500 can include aspects of the method flow 400 and vice versa. For example, when a write command is received (e.g., as part of a storage operation), the method flow 500 can be implemented by a device.

[0097] In some examples, aspects of the method flow 500 can be implemented by an interface controller and other components. Additionally or alternatively, aspects of the method flow 500 can be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, when executed by a controller (e.g., the interface controller 115), the instructions can cause the controller to perform the operations of the method flow 500.

[0098] Alternative examples of the method flow 500 can be implemented, where some operations are performed in a different order than described or not performed at all. In some examples, the method flow 500 can include operations not mentioned below (e.g., additional operations can be added). Additionally, some operations can be performed in parallel (e.g., concurrently, or during overlapping time periods).

[0099] At 505, the device may receive (e.g., from a host device via a command bus) an activation command for a non-volatile memory bank. The activation command may be associated with a row address indicating a row of the non-volatile memory. At 515, the device may receive (e.g., from a host device via a command bus) a write command for the row. The write command may be associated with data provided by the host device. The write command may also be referred to as a store command. At 515, the device may transfer metadata (e.g., tag information, validity information, and dirty information) of a volatile memory row to a first register (e.g., register 256 or register 345) in response to the write command. The validity information may include validity information of the row (e.g., bits indicating the validity state of the row) and / or validity information of portions of the row (e.g., thirty-two bits each indicating the validity state of a corresponding portion of the row). The validity information of portions of the row may be transferred from an array (such as sub-array 330) to the first register. The dirty information may include dirty information of portions of the row (e.g., thirty-two bits each indicating the dirty state of a corresponding portion of the row). The dirty information of portions of the row may be transferred from the volatile memory (such as volatile memory array 320) to the first register.

[0100] At 520, the device may determine whether a volatile memory row associated with the non-volatile memory row is available for storing the provided data. For example, the device may refer to the tag information and validity information in the first register to see if valid data has already been stored in the row of the volatile memory. If the row of the volatile memory is available, at 525, the device may store the data in the row of the volatile memory. For example, the device may activate the row of the volatile memory and write the provided data to some or all portions of the row of the volatile memory. The provided data may be transferred from a first buffer (e.g., buffer 135-a or buffer 218) to the volatile memory. At 530, the device may update the validity information in the first register based on storing the data in the row of the volatile memory. For example, the device may modify the validity bits associated with the portions of the row where the data is written. The device may also update the tag information of the row to reflect what data is stored therein.

[0101] At 540, the device may update the dirty information in the first register based on storing the data in the row of the volatile memory. For example, the device may modify the dirty bits associated with the portions of the row where the data is written. If the device operates in a write-through mode (where the data is also stored in the non-volatile memory), the device may update the appropriate dirty bits to reflect that the corresponding portions store clean data. If the device operates in a write-back mode, the device may update the appropriate dirty bits to reflect that the corresponding portions store dirty data.

[0102] After 540, the device can continue to access rows of the volatile memory (e.g., by reading from or writing to a row) until the device receives a precharge command at 545. In response to the precharge command, at 550, the device can update the dirty information in the volatile memory by writing the dirty information in the first register back to the volatile memory. Also in some instances in response to the precharge command, at 555, the device can update the validity information in the array by writing the validity information in the first register back to the array. In some instances, the device can use one or more masked write operations to update the validity information and / or the dirty information, as described with reference to Figure 7 which is described. Additionally, the device can close the row of the volatile memory such that another row in the memory bank can be opened.

[0103] At 520, if the device determines that a row of the volatile memory is unavailable, then at 560, the device can store the provided data in the non-volatile memory. The provided data can be transferred from the first buffer to the non-volatile memory. At 570, the device can evict data (e.g., a page) from the row of the volatile memory by transferring the data to a second buffer in the device (e.g., buffer 135-b or buffer 220). The operation at 570 can be part of an eviction process 565, which can free up space in the volatile memory for new data and save the old data in the non-volatile memory.

[0104] At 575, the device can transfer the dirty information associated with the row of the volatile memory to a second register. By transferring the dirty information to the second register, the device can effectively reference the dirty information to determine which set of data should be stored in the non-volatile memory. At 580, the device can transfer the dirty set of the sacrificed data from the buffer to the non-volatile memory for storage. The device can also discard clean sets of the sacrificed data that do not need to be stored in the non-volatile memory (e.g., because they are already stored there). After 580, the device can perform the operation at 525. For example, the device can store the provided data in an open row of the volatile memory by transferring the provided data to the volatile memory (e.g., from the first buffer) and writing the provided data to one or more portions of the open row. Then, the device can continue to perform the operations at 530 to 555.

[0105] Thus, the device can service requests to store data from a host device by using metadata stored in two different memories of the device.

[0106] Figure 6Illustrated is an example of a method flow 600 that supports cache metadata management according to an example disclosed herein. The method flow 600 can be an example of a method flow implemented by a device that stores validity information in an array and stores dirty information in a volatile memory that serves as a non-volatile memory cache. Thus, the method flow 600 can be implemented by the memory subsystem 110 described with reference to Figure 1 the memory subsystem 200 described with reference to Figure 2 or the device 300 described with reference to Figure 3 The method flow 600 can include aspects of the method flow 400 and the method flow 500, or aspects of the method flow 600 can be included in the method flow 400 and the method flow 500. For example, when a read command is received (e.g., as part of a retrieval operation), the method flow 600 can be implemented by a device.

[0107] In some examples, aspects of the method flow 600 can be implemented by an interface controller and other components. Additionally or alternatively, aspects of the method flow 600 can be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, when executed by a controller (e.g., the interface controller 115), the instructions can cause the controller to perform the operations of the method flow 600.

[0108] Alternative examples of the method flow 600 can be implemented, where some operations are performed in a different order than described or not performed at all. In some examples, the method flow 600 can include operations not mentioned below (e.g., additional operations can be added). Additionally, some operations can be performed in parallel (e.g., concurrently, or during overlapping time periods).

[0109] At 605, the device can receive (e.g., from a host device via a command bus) an activation command for a non-volatile memory bank. The activation command can be associated with a row address indicating a row of the non-volatile memory. At 610, the device can receive (e.g., from a host device via a command bus) a read command for the row. The read command can be associated with data requested by the host device. The read command can also be referred to as a retrieval command.

[0110] At 615, the device may transfer tag information, validity information, and dirty information to a first register (e.g., register 256 or register 345) in response to a read command. The validity information may include validity information of a row of volatile memory associated with a row address of non-volatile memory. The validity information may include bits representing the validity state of a row of volatile memory and / or validity bits of portions of the row (e.g., thirty-two bits each representing the validity state of a corresponding portion of the row). The validity information of portions of the row may be transferred from an array such as sub-array 330 to the first register. The dirty information may include dirty information of portions of the row (e.g., thirty-two bits each representing the dirty state of a corresponding portion of the row). The dirty information of portions of the row may be transferred from volatile memory (such as volatile memory array 320) to the first register.

[0111] At 620, the device may determine whether a row of volatile memory stores the requested data. For example, the device may 1) refer to the tag information in the first register to determine whether the data stored in the row is associated with a non-volatile row address, and 2) refer to the validity information in the first register to determine whether the data stored in the row is valid data. If a row of volatile memory stores unrequested data or invalid data, at 625, the device may return the requested data from the row of non-volatile memory to the host device. For example, the device may transfer the requested data to a first buffer, such as buffer 135-a or buffer 218, for transmission to the host device.

[0112] At 630, the device evicts data (e.g., a page) from a row of volatile memory by transferring the data to a second buffer (e.g., buffer 135-b or buffer 220) in the device. The operation at 630 may be part of an eviction process 635, which may free up space in volatile memory for the requested data and save the old data in non-volatile memory. At 640, the device may transfer the dirty information associated with the row of volatile memory to a second register (e.g., register 258 or register 350). By transferring the dirty information to the second register, the device may effectively refer to the dirty information to determine which set of data should be stored in non-volatile memory. At 645, the device may transfer the dirty set of sacrificed data from the buffer to non-volatile memory for storage. The device may also discard clean sets of sacrificed data that do not need to be stored in non-volatile memory (e.g., because they are already stored there).

[0113] At 650, the device may store the requested data in a row of the volatile memory. For example, the device may activate a row of the volatile memory and write the requested data to some or all parts of the row of the volatile memory. The requested data may be transferred from a first buffer (e.g., buffer 135-a or buffer 218) to the volatile memory. At 655, the device may update the validity information in the first register based on storing the data in the row of the volatile memory. For example, the device may modify the validity bit associated with the part of the row where the requested data is written.

[0114] At 660, the device may update the dirty information in the first register. For example, the device may modify the dirty bit associated with the part of the row where the requested data is written. Since the row of the volatile memory stores the same data as the non-volatile memory, the device may update the appropriate dirty bit to reflect that the corresponding part stores clean data.

[0115] After 660, the device may continue to access the row of the volatile memory (e.g., by reading from or writing to the row) until the device receives a precharge command at 665. In response to the precharge command, at 670, the device may update the dirty information in the volatile memory by writing the dirty information in the first register back to the volatile memory. Also in response to the precharge command, at 675, the device may update the validity information in the array by writing the validity information in the first register back to the array. In some instances, the device may use one or more masked write operations to update the validity information and / or the dirty information, as described with reference to Figure 7 described. Additionally, the device may close the row of the volatile memory so that another row in the memory bank can be opened.

[0116] At 620, if the device determines that the row of the volatile memory stores valid requested data, then at 680, the device may return the data from the row of the volatile memory to the host device. For example, the device may activate the row of the volatile memory and transfer the requested data to the host device (e.g., via the first buffer). After 680, the device may continue to access the row of the volatile memory (e.g., by reading from or writing to the row) until the device receives a precharge command at 685. In response to the precharge command, at 690, the device may update the validity information in the array by writing the validity information in the first register back to the array. Additionally, the device may close the row of the volatile memory so that another row in the memory bank can be opened.

[0117] Thus, the device may serve a request for data from a host device by using metadata stored in two different memories of the device.

[0118] Figure 7Illustrated is an example of a row 700 of volatile memory at different times during an update process that supports cache metadata management. The update process may include one or more masked write (MWR) operations and may be an example of an update process implemented by a device that stores validity information in an array and dirty information in volatile memory. For example, the update process may be implemented by the memory subsystem 110 described with reference to Figure 1 the memory subsystem 200 described with reference to Figure 2 or the device 300 described with reference to Figure 3 .

[0119] Aspects of the update process may be included in method flow 400, method flow 500, or method flow 600. For example, the update process may be implemented by a device to update dirty information in volatile memory. Although described with respect to dirty information, the update process may be used to update validity information in the device array.

[0120] Row 700 may be a row of a memory bank in a volatile memory as described herein. For example, row 700 may be row n in volatile memory 204 or volatile memory array 320. Row 700 may include a plurality of memory cells, each memory cell storing a dirty bit corresponding to a portion of the row in the volatile memory. Thus, row 700 may store validity information for the corresponding row of the volatile memory. Each memory cell in row 700 may be associated with a respective column address such that the memory cell has a unique address relative to other memory cells in row 700.

[0121] Initially (e.g., at startup, reset, or some other program), the dirty information in row 700 may be set to a default configuration, such as all logical zeros, to indicate that invalid data is stored in portions of the corresponding row. For example, the dirty information in row 700 may indicate that each 64B of a 2kB row is invalid.

[0122] At some point, the device may write data to one or more portions of the volatile memory. For example, the device may write data to a portion of the row associated with row 700. If the data is inconsistent with the corresponding data in the associated row of the non-volatile memory or if the data does not exist in the associated row of the non-volatile memory, the device may determine to update the dirty information in row 700 to reflect as much dirty information as possible. In some examples, the device may use a register such as register 258 or register 350 to keep track of which dirty bits need to be updated.

[0123] In this example, the device may determine that the dirty bits stored in memory cell 0, memory cell 9, and memory cell 21 need to be updated (e.g., the dirty bits stored in memory cell 0, memory cell 9, and memory cell 21 have been modified in a register). Thus, the device may issue a masked write command to the volatile memory to perform a masked write operation on row 700. The masked write operation may update a subset of the dirty bits in a row while maintaining the state of other dirty bits in that row. For example, performing a masked write operation on row 700 may change the dirty bits in memory cell 0, memory cell 9, and memory cell 21 from zero to one without affecting the dirty bits in other memory cells of row 700.

[0124] The masked write operation may provide latency and bandwidth benefits over alternative update processes such as a read-modify-write (RMW) process. The RMW process may involve the device reading the row storing the data to be modified, determining which bits to modify, and writing the entire row (e.g., writing a new value to the bits to be modified and writing the same value to the bits to be retained). Thus, compared to the masked write operation, performing an RMW process to update the dirty bits may involve additional read operations, increasing latency, power consumption, and bandwidth consumption.

[0125] After performing the masked write operation to update the dirty bits in memory cell 0, memory cell 9, and memory cell 21, the device may write data to additional portions of the row associated with row 700. For example, the device may write data to portions associated with memory cell 12 and memory cell 31. If the data written to memory cell 12 and memory cell 31 is inconsistent with the corresponding data in the associated row of the non-volatile memory or if the data does not exist in the associated row of the non-volatile memory, the device may determine to update the dirty information in row 700 to reflect as much dirty information as possible. As described above, the device may use a register such as register 258 or register 350 to keep track of which dirty bits need to be updated. When determining to update the dirty bits in memory cell 12 and memory cell 31, the device initiates a masked write operation for those memory cells to effect the update. The masked write operation may change the dirty bits in memory cell 12 and memory cell 31 from zero to one without affecting the dirty bits in other memory cells of row 700.

[0126] Thus, the device may implement a masked write operation to update the dirty bits stored in the volatile memory. Although described with respect to dirty information, the update process may be used to update validity information in the device array.

[0127] Figure 8 FIG. 800 is a block diagram illustrating a memory subsystem 805 that supports cache metadata management in accordance with examples disclosed herein. The memory subsystem 805 may be respectively referenced Figure 1and 2 Examples of aspects of the memory subsystem 110 or memory subsystem 200 described above. Thus, the memory subsystem 805 can be coupled to a host device, volatile memory, and non-volatile memory. The memory subsystem 805 can include a validity information manager 810, a dirty information manager 815, a data manager 820, a validity information update manager 825, a dirty information update manager 830, and an association manager 835. Each of these modules can include circuitry configured to perform the functions described herein. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses or other conductive connections).

[0128] The memory subsystem 805 can be configured to manage cache metadata described herein. In a first example, the validity information manager 810 can be configured to store validity information in an array (e.g., array 254, sub-array 330) in an interface controller, the validity information indicating whether data in a set of volatile memory cells stored in volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller. The set of memory cells can be a row of volatile memory or one or more portions of a row of volatile memory. The dirty information manager 815 can be configured to store dirty information in volatile memory, the dirty information indicating whether data in the set of volatile memory cells stored in volatile memory does not exist in non-volatile memory or is inconsistent with corresponding data in non-volatile memory.

[0129] The validity information manager 810 can be configured to transfer the validity information from the array to a first register (e.g., register 256, register 345) at least partially based on an access command from the host device. The dirty information manager 815 can be configured to transfer the dirty information from volatile memory to a second register (e.g., register 258, register 350) at least partially based on transferring data to be stored in the set of volatile memory cells to a buffer (e.g., buffer 135-b, buffer 220).

[0130] The data manager 820 can be configured to replace data stored in the set of volatile memory cells with second data. The validity information update manager 825 can be configured to update the validity information of the set of volatile memory cells at least partially based on replacing the data with the second data. In some examples, the validity information is or includes a single validity bit among a plurality of validity bits. In such cases, the validity information update manager 825 can be configured to update the validity information by performing a masked write operation in which a subset of the plurality of validity bits in the array is modified and the remaining validity bits are maintained.

[0131] The data manager 820 can be configured to replace the data stored in the set of volatile memory cells with second data. The dirty information update manager 830 can be configured to update the dirty information of the set of volatile memory cells at least in part based on replacing the data with second data. In some instances, the data manager 820 can be configured to transfer the data stored in the set of volatile memory cells to a buffer (e.g., buffer 135-b, buffer 220) in the interface controller before replacing the data with second data. In such instances, the data manager 820 can be configured to transfer the dirty information from the volatile memory to a register (e.g., register 258, register 350) in the interface controller at least in part based on transferring the data, where the dirty information is transferred before updating the dirty information.

[0132] In some instances, the dirty information is or includes a single dirty bit among a plurality of dirty bits. In such instances, the dirty information update manager 830 can be configured to update the dirty information by performing a masked write operation in which a subset of the plurality of dirty bits in the volatile memory is modified and the remaining dirty bits are preserved.

[0133] In some instances, the validity information is or includes validity bits that are included in a set of validity bits in a set of memory cells stored in the array. In such instances, the association manager 835 can be configured to determine the association between each memory cell in the set of memory cells and a corresponding set of volatile memory cells for storing data in the volatile memory. In some instances, the dirty information is or includes dirty bits that are included in a set of dirty bits in a second set of volatile memory cells reserved in the volatile memory for storing dirty information. In such instances, the association manager can be configured to determine the association between each memory cell in the second set of volatile memory cells and a corresponding set of volatile memory cells reserved for storing data in the volatile memory.

[0134] In some instances, the data manager 820 can be configured to receive a command (e.g., a write command) to store second data in a set of non-volatile memory cells in the non-volatile memory. The data manager 820 can also be configured to determine at least in part based on the validity information in the array that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells. The data manager 820 can also be configured to replace the data in the set of volatile memory cells with second data at least in part based on determining that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells.

[0135] In some instances, the data manager 820 is configured to receive a command (e.g., a read command) to retrieve data from a set of non-volatile memory cells in non-volatile memory. The data manager 820 may also be configured to determine that data stored in the set of volatile memory cells was previously written to the set of volatile memory cells based at least in part on validity information. The data manager 820 may also be configured to retrieve data from the set of volatile memory cells based at least in part on determining that data stored in the set of volatile memory cells was previously written to the set of volatile memory cells.

[0136] In some instances, the data manager 820 is configured to determine that data stored in the set of volatile memory cells does not exist in non-volatile memory or is inconsistent with corresponding data in non-volatile memory based at least in part on dirty information. The data manager 820 may also be configured to transfer data from the set of volatile memory cells to non-volatile memory based at least in part on determining that data stored in the set of volatile memory cells does not exist in non-volatile memory or is inconsistent with corresponding data in non-volatile memory.

[0137] As described above, the memory subsystem 805 may be configured to manage cache metadata described herein. In a second instance, the data manager 820 may be configured to receive an access command (e.g., a read command, a write command) associated with a portion of non-volatile memory from a host device coupled to the memory subsystem 805. The validity information manager 810 may be configured to transfer validity information from an array (e.g., array 254, sub-array 330) in the interface controller to a first register (e.g., register 256, register 345) in the interface controller based at least in part on the access command, the validity information indicating whether data stored in a portion of volatile memory was previously written to the portion of volatile memory in response to a previous access command from the host device. The dirty information manager 815 may be configured to transfer dirty information from volatile memory to the first register based at least in part on the access command, the dirty information indicating whether data stored in the portion of volatile memory does not exist in non-volatile memory or is inconsistent with corresponding data in non-volatile memory.

[0138] The data manager 820 may be configured to store second data in the portion of volatile memory based at least in part on the access command. The validity information update manager 825 may be configured to perform a masked write operation based at least in part on accessing the portion of volatile memory to replace the validity information with second validity information.

[0139] The data manager 820 may be configured to transfer data stored in this portion of the volatile memory to a buffer (e.g., buffer 135-b, buffer 220) in the interface controller at least in part based on an access command. The dirty information update manager 830 may be configured to perform a masked write operation at least in part based on the transferred data to replace the dirty information with second dirty information.

[0140] The association manager 835 may be configured to determine the association between this portion of the volatile memory and a first memory cell in the array that stores validity information. The association manager 835 may be configured to determine the association between this portion of the volatile memory and a second memory cell in the volatile memory that stores dirty information.

[0141] The data manager 820 may be configured to transfer data stored in this portion of the volatile memory to a buffer (e.g., buffer 135-b, buffer 220) at least in part based on the validity information. The dirty information manager 815 may be configured to transfer the dirty information to a second register at least in part based on transferring the data to the buffer. The data manager 820 may be configured to transfer a subset of the data from the buffer to the non-volatile memory at least in part based on transferring the dirty information to the second register.

[0142] When the access command is a store command (e.g., a write command), the data manager 820 may be configured to determine that the data stored in this portion of the volatile memory has been previously written to this portion of the volatile memory at least in part based on the validity information, and transfer the data to the buffer at least in part based on this determination. The data manager 820 may also be configured to store second data in this portion of the volatile memory after transferring the data from the volatile memory to the buffer.

[0143] When the access command is a retrieval command (e.g., a read command), the data manager 820 may be configured to determine that the volatile memory does not store data associated with the retrieval command. The data manager 820 may also be configured to store the data associated with the retrieval command in this portion of the volatile memory at least in part based on this determination after transferring the data from the volatile memory to the buffer.

[0144] Figure 9 A flowchart illustrating one or more methods 900 for supporting cache metadata management in accordance with aspects of the present disclosure is shown. The operations of method 900 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of method 900 may be performed by a component such as that referenced in Figures 1 to 3The described memory subsystem performs. In some instances, the memory subsystem may execute a set of instructions to control functional elements of the memory subsystem to perform the described functions. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform aspects of the described functions.

[0145] In some instances, the operations of method 900 may be implemented by a device that includes non-volatile memory, volatile memory, and an interface controller coupled to the non-volatile memory and the volatile memory.

[0146] At 905, the method may include storing validity information in an array in the interface controller, the validity information indicating whether data in a set of volatile memory cells stored in the volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller. The operation of 905 may be performed according to the methods described herein. In some instances, aspects of the operation of 905 may be performed by a validity information manager as described in reference to Figure 8 the described validity information manager.

[0147] At 910, the method may include storing dirty information in the volatile memory, the dirty information indicating whether data in the set of volatile memory cells stored in the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory. The operation of 910 may be performed according to the methods described herein. In some instances, aspects of the operation of 910 may be performed by a dirty information manager as described in reference to Figure 8 the described dirty information manager.

[0148] In some instances, the devices described herein may execute one or more methods, such as method 900. The device may include features, methods, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for storing validity information in an array in the interface controller and dirty information in the volatile memory, the validity information indicating whether data in a set of volatile memory cells stored in the volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller; the dirty information indicating whether data in the set of volatile memory cells stored in the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory.

[0149] Some examples of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for transferring validity information from an array to a first register based at least in part on an access command from a host device; and transferring dirty information from volatile memory to a second register based at least in part on transferring data stored in the set of volatile memory cells to a buffer.

[0150] Some examples of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for replacing data stored in the set of volatile memory cells with second data; and updating validity information of the set of volatile memory cells based at least in part on replacing data with second data.

[0151] In some examples, the validity information includes a single validity bit among a plurality of validity bits. In such examples, the method 900 and apparatus described herein may further include operations, features, methods, or instructions for performing a masked write operation in which a subset of the plurality of validity bits in the array is modified and the remaining validity bits are maintained, wherein the validity information is updated based at least in part on the masked write operation.

[0152] Some examples of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for replacing data stored in the set of volatile memory cells with second data; and updating dirty information of the set of volatile memory cells based at least in part on replacing data with second data. Some examples of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for transferring data stored in the set of volatile memory cells to a buffer in an interface controller before replacing the data with second data; and transferring dirty information from volatile memory to a register in the interface controller based at least in part on transferring the data, wherein the dirty information is transferred before updating the dirty information.

[0153] In some examples, the dirty information includes a single dirty bit among a plurality of dirty bits. In such examples, the method 900 and apparatus described herein may further include operations, features, methods, or instructions for performing a masked write operation in which a subset of the plurality of dirty bits in the volatile memory is modified and the remaining dirty bits are maintained, wherein the dirty information is updated based at least in part on the masked write operation.

[0154] In some instances, the validity information includes validity bits, which are included in a set of validity bits in a set of memory cells stored in an array. In such instances, the method 900 and apparatus described herein may further include operations, features, methods, or instructions for determining the association between each memory cell in the set of memory cells and a corresponding set of volatile memory cells for storing data in volatile memory.

[0155] In some instances, the dirty information includes dirty bits, which are included in a set of dirty bits in a second set of volatile memory cells reserved in volatile memory for storing dirty information. In such instances, the method 900 and apparatus described herein may further include operations, features, methods, or instructions for determining the association between each memory cell in the second set of volatile memory cells and a corresponding set of volatile memory cells reserved for storing data in volatile memory.

[0156] Some instances of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for receiving a command to store second data in a set of non-volatile memory cells in non-volatile memory; determining, at least in part based on the validity information in the array, that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells; and replacing the data in the set of volatile memory cells with the second data, at least in part based on the determination that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells.

[0157] Some instances of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for receiving a command to retrieve data from a set of non-volatile memory cells in non-volatile memory; determining, at least in part based on the validity information, that the data stored in the set of volatile memory cells has been previously written to the set of volatile memory cells; and retrieving the data from the set of volatile memory cells, at least in part based on the determination that the data stored in the set of volatile memory cells has been previously written to the set of volatile memory cells.

[0158] Some instances of the method 900 and apparatus described herein may further include operations, features, methods, or instructions for determining, at least in part based on the dirty information, that the data stored in the set of volatile memory cells does not exist in non-volatile memory or is inconsistent with the corresponding data in non-volatile memory; and transferring the data from the set of volatile memory cells to non-volatile memory, at least in part based on the determination that the data stored in the set of volatile memory cells does not exist in non-volatile memory or is inconsistent with the corresponding data in non-volatile memory.

[0159] Figure 10FIG. shows a flowchart of one or more methods 1000 for supporting cache metadata management in accordance with aspects of the present disclosure. Operations of method 1000 may be implemented by a memory subsystem or components thereof as described herein. For example, operations of method 1000 may be performed by a memory subsystem as described with reference to Figures 1 to 3 as described. In some instances, the memory subsystem may execute a set of instructions to control functional elements of the memory subsystem to perform the described functions. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform aspects of the described functions.

[0160] In some instances, operations of method 1000 may be implemented by a device including an interface controller coupled to non-volatile memory and volatile memory.

[0161] At 1005, the method may include receiving, from a host device coupled to the device, an access command associated with a portion of non-volatile memory. The operation of 1005 may be performed in accordance with the methods described herein. In some instances, aspects of the operation of 1005 may be performed by a data manager as described with reference to Figure 8 as described.

[0162] At 1010, the method may include transferring, at least in part based on the access command, validity information from an array in the interface controller to a first register in the interface controller, the validity information indicating whether data stored in a portion of the volatile memory was previously written to the portion of the volatile memory in response to a previous access command from the host device. The operation of 1010 may be performed in accordance with the methods described herein. In some instances, aspects of the operation of 1010 may be performed by a validity information manager as described with reference to Figure 8 as described.

[0163] At 1015, the method may include transferring, at least in part based on the access command, dirty information from the volatile memory to a register, the dirty information indicating whether data stored in the portion of the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory. The operation of 1015 may be performed in accordance with the methods described herein. In some instances, aspects of the operation of 1015 may be performed by a dirty information manager as described with reference to Figure 8 as described.

[0164] In some instances, the devices described herein may perform one or more methods, such as method 1000. The device may include features, methods, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving an access command associated with a portion of non-volatile memory from a host device coupled to the device; transferring validity information from an array in an interface controller to a first register in the interface controller at least in part based on the access command; and transferring dirty information from volatile memory to a register at least in part based on the access command, the validity information indicating whether data stored in a portion of the volatile memory was previously written to that portion of the volatile memory in response to a previous access command from the host device; and transferring dirty information from the volatile memory to the register at least in part based on the access command, the dirty information indicating whether data stored in that portion of the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory.

[0165] Some instances of method 1000 and the device described herein may further include operations, features, methods, or instructions for storing second data in that portion of the volatile memory at least in part based on the access command; and performing a masked write operation at least in part based on accessing that portion of the volatile memory to replace the validity information with second validity information.

[0166] Some instances of method 1000 and the device described herein may further include operations, features, methods, or instructions for transferring data stored in that portion of the volatile memory to a buffer in the interface controller at least in part based on the access command; and performing a masked write operation at least in part based on transferring the data to replace the dirty information with second dirty information.

[0167] Some instances of method 1000 and the device described herein may further include operations, features, methods, or instructions for determining an association between that portion of the volatile memory and a first memory cell in the array storing the validity information; and determining an association between that portion of the volatile memory and a second memory cell in the volatile memory storing the dirty information.

[0168] Some instances of method 1000 and the device described herein may further include operations, features, methods, or instructions for transferring data stored in that portion of the volatile memory to a buffer at least in part based on the validity information, wherein the dirty information is transferred to a second register at least in part based on transferring the data to the buffer. Some instances of method 1000 and the device described herein may further include operations, features, methods, or instructions for transferring a subset of the data from the buffer to the non-volatile memory at least in part based on transferring the dirty information to the second register.

[0169] In some instances, the access command is a store command for the second data. In such instances, the method 1000 and apparatus described herein may further include operations, features, methods, or instructions for determining, at least in part based on validity information, that data stored in that portion of the volatile memory has been previously written to that portion of the volatile memory and, after transferring the data from the volatile memory to the buffer, storing the second data in that portion of the volatile memory; wherein the data is transferred to the buffer at least in part based on that determination.

[0170] In some instances, the access command is a retrieve command. In such instances, the method 1000 and apparatus described herein may further include operations, features, methods, or instructions for determining that the volatile memory does not store data associated with the retrieve command; and, at least in part based on that determination, after transferring the data from the volatile memory to the buffer, storing the data associated with the retrieve command in that portion of the volatile memory.

[0171] It should be noted that the above methods describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0172] The information and signals described herein may be represented using any of a variety of different technologies and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0173] A protocol may define one or more communication processes and one or more communication parameters that a device or component supports for use. For example, a protocol may define various operations, the timing and frequency of these operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication for which pins are reserved, the size of data processed at various components such as an interface, the data rate supported by various components such as an interface, or the bandwidth supported by various components such as an interface, and other parameters and metrics, or any combination thereof. The use of a shared protocol enables interaction between devices because each device can operate in a manner that is expected, recognized, and understood by another device. For example, two devices that support the same protocol may interact according to the policies, processes, and parameters defined by the protocol, while two devices that support different protocols may be incompatible.

[0174] For illustration, two devices that support different protocols may be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices that support different protocols may be incompatible because the protocols define different transfer procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to a command may be different). Merely converting a command to an action should not be construed as using two different protocols. Instead, two protocols may be considered different if the corresponding procedures or parameters defined by the protocols vary. For example, if a device supports different addressing schemes or different transfer procedures for responding to commands, it can be said that the device supports two different protocols.

[0175] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating (or electrically contacting or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between components that are electronically communicating (or electrically contacting or connected or coupled) with each other can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components can be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0176] The term "couple" refers to a state of moving from an open-circuit relationship between components to a closed-circuit relationship between components, where in the open-circuit relationship, signals cannot currently be transferred between the components via the conductive path, and in the closed-circuit relationship, signals can be transferred between the components via the conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components on a conductive path where signals were not previously allowed to flow.

[0177] The term "isolate" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, when a switch is open, two components separated by the switch located between the components are isolated from each other. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously allowed signals to flow.

[0178] The devices (including memory arrays) discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-region can be controlled by doping with various chemicals including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0179] The switching components or transistors discussed herein may represent field effect transistors (FETs), and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive materials (e.g., metals). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate, the transistor can be "on" or "activated". When a voltage less than the transistor threshold voltage is applied to the transistor gate, the transistor can be "off" or "deactivated".

[0180] The description presented herein in conjunction with the figures describes example configurations and does not represent all examples that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details that provide an understanding of the technology. However, the technology can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0181] In the figures, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by following the reference numeral with a dash and a second label that differentiates the similar components. If only the first reference numeral is used in the specification, the description can apply to any one of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0182] The information and signals described in this document can be represented using any of a variety of different technologies and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0183] The various illustrative block diagrams and modules described in connection with the disclosure herein can be implemented or executed with a general purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0184] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored or transmitted as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the above functions can be implemented using software, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions can also be physically located in various positions, including being distributed such that portions of the functions are implemented at different physical locations. Further, as used herein, including in the claims, the "or" used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0185] A computer-readable medium includes a non-transitory computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer, or a general purpose or special purpose processor. Additionally, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. Disk and optical disks as used herein include CD, laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0186] The description provided herein enables a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: a non-volatile memory; a volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to: write dirty information and validity information for a set of memory cells in the volatile memory to a register of the interface controller, at least in part based on an access command, the validity information received from an array in the interface controller and the dirty information received from the volatile memory; update both the validity information and the dirty information in the register of the interface controller, at least in part based on accessing the volatile memory; transfer the validity information from the register to the array and transfer the dirty information from the register to the volatile memory, at least in part based on updating the validity information and the dirty information; store the validity information in the array in the interface controller, the validity information indicating whether data in a set of volatile memory cells stored in the volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller; and store the dirty information in the volatile memory, the dirty information indicating whether data in the set of volatile memory cells stored in the volatile memory does not exist in the non-volatile memory or is inconsistent with corresponding data in the non-volatile memory.

2. The apparatus according to claim 1, wherein the interface controller is operable to cause the apparatus to: transfer the dirty information from the volatile memory to a second register, at least in part based on transferring the data stored in the set of volatile memory cells to a buffer.

3. The apparatus according to claim 1, wherein the interface controller is operable to cause the apparatus to: replace the data stored in the set of volatile memory cells with second data, wherein the validity information is updated at least in part based on replacing the data with the second data.

4. The apparatus according to claim 3, wherein the validity information comprises a single validity bit of a plurality of validity bits, and wherein the interface controller is operable to cause the apparatus to: perform a masked write operation, wherein a subset of the plurality of validity bits in the array is modified and the remaining validity bits are maintained, and wherein the validity information is updated again at least in part based on the masked write operation.

5. The apparatus according to claim 1, wherein the interface controller is operable to cause the apparatus to: replace the data stored in the set of volatile memory cells with second data, wherein the dirty information for the set of volatile memory cells is updated at least in part based on replacing the data with the second data.

6. The apparatus according to claim 5, wherein the interface controller is operable to cause the apparatus to: ​ Before replacing the data with the second data, transfer the data stored in the group of volatile memory cells to a buffer in the interface controller; and Transfer the dirty information from the volatile memory to the register in the interface controller at least in part based on transferring the data, wherein the dirty information is transferred before updating the dirty information.

7. The apparatus of claim 5, wherein the dirty information includes a single dirty bit of a plurality of dirty bits, and wherein the interface controller is operable to cause the apparatus to: Perform a masked write operation, wherein a subset of the plurality of dirty bits in the volatile memory is modified and the remaining dirty bits are maintained, wherein the dirty information is updated again at least in part based on the masked write operation.

8. The apparatus of claim 1, wherein the validity information includes validity bits, the validity bits being included in a set of validity bits in a set of memory cells stored in the array, and wherein the interface controller is operable to cause the apparatus to: Determine the association between each memory cell in the set of memory cells and a corresponding set of volatile memory cells for storing data in the volatile memory.

9. The apparatus of claim 1, wherein the dirty information includes dirty bits, the dirty bits being included in a set of dirty bits in a second set of volatile memory cells reserved in the volatile memory for storing dirty information, and wherein the interface controller is operable to cause the apparatus to: Determine the association between each memory cell in the second set of volatile memory cells and a corresponding set of volatile memory cells reserved in the volatile memory for storing data.

10. The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: Receive a command to store second data in a set of non-volatile memory cells in the non-volatile memory; Determine at least in part based on the validity information in the array that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells; And Replace the data in the set of volatile memory cells with the second data at least in part based on determining that the data stored in the set of volatile memory cells has not been previously written to the set of volatile memory cells.

11. The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: Receive a command to retrieve data from a set of non-volatile memory cells in the non-volatile memory; Determine at least in part based on the validity information that the data stored in the set of volatile memory cells has been previously written to the set of volatile memory cells; And Retrieve the data from the set of volatile memory cells at least in part based on determining that the data stored in the set of volatile memory cells has been previously written to the set of volatile memory cells.

12. The apparatus of claim 11, wherein the interface controller is operable to cause the apparatus to: Determine that the data stored in the group of volatile memory cells does not exist in the non-volatile memory or is inconsistent with the corresponding data in the non-volatile memory, at least in part based on the dirty information; and Transfer the data from the group of volatile memory cells to the non-volatile memory, at least in part based on determining that the data stored in the group of volatile memory cells does not exist in the non-volatile memory or is inconsistent with the corresponding data in the non-volatile memory.

13. An apparatus, which comprises: An interface controller coupled to a non-volatile memory and a volatile memory, the interface controller being operable to cause the apparatus to: Receive an access command associated with a portion of the non-volatile memory from a host device coupled to the apparatus; Transfer validity information from an array in the interface controller to a register in the interface controller, at least in part based on the access command, the validity information indicating whether data stored in a portion of the volatile memory was previously written to the portion of the volatile memory in response to a previous access command from the host device; Transfer dirty information from the volatile memory to the register, at least in part based on the access command, the dirty information indicating whether the data stored in the portion of the volatile memory does not exist in the non-volatile memory or is inconsistent with the corresponding data in the non-volatile memory; Update both the validity information and the dirty information in the register of the interface controller, at least in part based on accessing the volatile memory; and Transfer the validity information from the register to the array and transfer the dirty information from the register to the volatile memory, at least in part based on updating the validity information and the dirty information.

14. The apparatus according to claim 13, wherein the interface controller is operable to cause the apparatus to: Store second data in the portion of the volatile memory, at least in part based on the access command; and Perform a masked write operation, at least in part based on accessing the portion of the volatile memory, to replace the validity information with second validity information.

15. The apparatus according to claim 13, wherein the interface controller is operable to cause the apparatus to: Transfer the data stored in the portion of the volatile memory to a buffer in the interface controller, at least in part based on the access command; and Perform a masked write operation, at least in part based on transferring the data, to replace the dirty information with second dirty information.

16. The apparatus according to claim 13, wherein the interface controller is operable to cause the apparatus to: Determine an association between the portion of the volatile memory and a first memory cell in the array that stores the validity information; and Determine an association between the portion of the volatile memory and a second memory cell in the volatile memory that stores the dirty information.

17. The device according to claim 13, and wherein the interface controller is operable to cause the device to: transfer the data stored in the portion of the volatile memory to a buffer at least in part based on the validity information; and transfer the dirty information to a second register at least in part based on transferring the data to the buffer.

18. The device according to claim 17, wherein the interface controller is operable to cause the device to: transfer a subset of the data from the buffer to the non-volatile memory at least in part based on transferring the dirty information to the second register.

19. The device according to claim 17, wherein the access command includes a store command for second data, and wherein the interface controller is operable to cause the device to: determine that the data stored in the portion of the volatile memory was previously written to the portion of the volatile memory at least in part based on the validity information, and transfer the data to the buffer at least in part based on the determination; and store the second data in the portion of the volatile memory after transferring the data from the volatile memory to the buffer.

20. The device according to claim 17, wherein the access command includes a retrieve command, and wherein the interface controller is operable to cause the device to: determine that the volatile memory does not store data associated with the retrieve command; and store the data associated with the retrieve command in the portion of the volatile memory at least in part based on the determination, after transferring the data from the volatile memory to the buffer.

21. A method, which comprises: writing dirty information and validity information for a set of memory cells in a volatile memory to a register of an interface controller at least in part based on an access command, the validity information being received from an array in the interface controller and the dirty information being received from the volatile memory; updating both the validity information and the dirty information in the register of the interface controller at least in part based on accessing the volatile memory; transferring the validity information from the register to the array and transferring the dirty information from the register to the volatile memory at least in part based on updating the validity information and the dirty information; storing the validity information in the array in the interface controller, the validity information indicating whether data stored in a set of volatile memory cells in the volatile memory was previously written to the set of volatile memory cells in response to an access command from a host device coupled to the interface controller; and storing the dirty information in the volatile memory, the dirty information indicating whether the data stored in the set of volatile memory cells in the volatile memory does not exist in a non-volatile memory coupled to the interface controller or is inconsistent with corresponding data in the non-volatile memory.

22. The method according to claim 21, further comprising: transferring the dirty information from the volatile memory to the register, at least in part, based on transferring the data stored in the set of volatile memory cells to a buffer.

23. The method according to claim 21, further comprising: replacing the data stored in the set of volatile memory cells with second data, wherein the validity information of the set of volatile memory cells is updated at least in part based on replacing the data with the second data.

24. The method according to claim 23, wherein the validity information comprises a single validity bit among a plurality of validity bits, and wherein the method further comprising: performing a masked write operation, wherein a subset of the plurality of validity bits in the array is modified and the remaining validity bits are maintained, and wherein the validity information is updated again at least in part based on the masked write operation.

25. The method according to claim 21, further comprising: replacing the data stored in the set of volatile memory cells with second data, wherein the dirty information of the set of volatile memory cells is updated at least in part based on replacing the data with the second data.

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