Packaging substrate and manufacturing method thereof

Abstract

The present invention provides a packaging carrier and a method for manufacturing the same. The packaging carrier includes a substrate, at least one intermediate board, a conductive structure layer, a first build-up layer structure, and a second build-up layer structure. The intermediate board is disposed in at least one opening of the substrate, and the intermediate board includes a glass substrate, at least one conductive through hole, at least one first pad, and at least one second pad. The conductive through hole penetrates the glass substrate, and the first pad and the second pad are respectively disposed on the upper surface and the lower surface of the glass substrate opposite to each other and connected to the opposite ends of the conductive through hole. The conductive structure layer is disposed on the substrate and structurally and electrically connects the first pad and the second pad. The first build-up layer structure and the second build-up layer structure are respectively disposed on the first surface and the second surface of the substrate and are electrically connected to the conductive structure layer. The packaging carrier provided by the present invention has better coplanarity.

Description

Technical Field

[0001] The present invention relates to a substrate structure and a manufacturing method thereof, and in particular to a packaging carrier and a manufacturing method thereof. Background Art

[0002] The current embedded passive component substrate (EPS) structure can only be connected on one side, and the back side of the passive component cannot be laid out with wires, so it cannot be effectively utilized. Generally speaking, the connection between the passive component and the substrate is through a conductive blind hole; or, the wire pattern on the substrate is directly connected to the contact point of the passive component for single-sided wire layout. Since the conductive blind hole has more connection interfaces, that is, there are two connection interfaces, upper and lower, it is easy to cause poor conductivity. Furthermore, the conductive blind hole also has the characteristic of a small contact area at the bottom of the hole. Since the desmear process must be performed, if the residue at the bottom of the hole cannot be effectively removed, the electrical reliability will be poor. In addition, most of the current substrates are copper foil substrates. Due to their own material properties, they are more likely to produce irregular warping, which makes the coplanarity of the chip packaging area poor, and the chip cannot be effectively configured in the chip packaging area on the copper foil substrate, which leads to low packaging yield. In addition, the size of the passive component is small, and it is also impossible to provide a rigid support structure as a packaging area. Summary of the invention

[0003] The present invention is directed to a packaging carrier having better coplanarity.

[0004] The present invention is directed to a method for manufacturing a packaging carrier, which is used to manufacture the above-mentioned packaging carrier, can improve chip packaging yield and structural rigidity, and has better conductive performance and structural reliability.

[0005] According to an embodiment of the present invention, a package carrier includes a substrate, at least one intermediate board, a conductive structure layer, a first build-up layer structure, and a second build-up layer structure. The substrate has a first surface and a second surface opposite to each other and at least one opening connecting the first surface and the second surface. The intermediate board is arranged in the opening of the substrate, and the intermediate board includes a glass substrate, at least one conductive through hole, at least one first pad, and at least one second pad. The conductive through hole penetrates the glass substrate, and the first pad and the second pad are respectively arranged on the upper surface and the lower surface of the glass substrate opposite to each other and connected to the opposite ends of the conductive through hole. The conductive structure layer is arranged on the substrate and structurally and electrically connects the first pad and the second pad. The first build-up layer structure is arranged on the first surface of the substrate and is electrically connected to the conductive structure layer. The second build-up layer structure is arranged on the second surface of the substrate and is electrically connected to the conductive structure layer.

[0006] In the packaging carrier according to the embodiment of the present invention, the packaging carrier further comprises an insulating layer, which fills the opening of the substrate, covers the upper surface and the lower surface of the glass substrate, and exposes the first pad and the second pad. The insulating layer is cut flush with the first surface and the second surface of the substrate.

[0007] In the package carrier according to an embodiment of the present invention, the substrate further has at least one through hole. The conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conductive layer. The conductive layer covers the inner wall of the through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface. The first patterned circuit layer is structurally and electrically connected to the first pad. The second patterned circuit layer is structurally and electrically connected to the second pad.

[0008] In a packaging carrier according to an embodiment of the present invention, the packaging carrier further comprises a first solder mask, a second solder mask, a first surface treatment layer and a second surface treatment layer. The first solder mask is disposed on the first build-up layer structure. The first solder mask has a plurality of first openings, and the first openings expose a portion of the first build-up layer structure. The second solder mask is disposed on the second build-up layer structure. The second solder mask has a plurality of second openings, and the second openings expose a portion of the second build-up layer structure. The first surface treatment layer is disposed on the first build-up layer structure exposed by the first opening. The second surface treatment layer is disposed on the second build-up layer structure exposed by the second opening.

[0009] In the packaging carrier according to an embodiment of the present invention, the packaging carrier further comprises a plurality of first solder balls and a plurality of second solder balls. The first solder balls are respectively arranged in the first openings of the first solder mask. The first surface treatment layer is located between the first solder balls and the first build-up layer structure. The second solder balls are respectively arranged in the second openings of the second solder mask. The second surface treatment layer is located between the second solder balls and the second build-up layer structure.

[0010] According to an embodiment of the present invention, a method for manufacturing a packaging carrier includes the following steps. A substrate having at least one opening is provided. At least one intermediate board is placed in the opening of the substrate. Each intermediate board includes a glass substrate, at least one conductive through hole, at least one first pad, and at least one second pad. The conductive through hole penetrates the glass substrate, and the first pad and the second pad are respectively arranged on the upper surface and the lower surface of the glass substrate opposite to each other and connected to the opposite ends of the conductive through hole. A conductive structure layer is formed on the substrate, wherein the conductive structure layer structurally and electrically connects the first pad and the second pad. A first build-up layer structure and a second build-up layer structure are respectively formed on the first surface and the second surface of the substrate. The first build-up layer structure and the second build-up layer structure are respectively electrically connected to the conductive structure layer.

[0011] In the method for manufacturing a package carrier according to an embodiment of the present invention, the method for manufacturing a package carrier further includes: before forming the conductive structure layer on the substrate, forming an insulating material layer in the opening of the substrate. The insulating material layer fills the opening, covers the upper surface and the lower surface of the glass substrate, and extends to cover the first surface of the substrate and the first pad. A portion of the insulating material layer is removed to form an insulating layer. The insulating layer exposes the first pad and the second pad, and is cut flush with the first surface and the second surface of the substrate.

[0012] In the method for manufacturing a packaging carrier according to an embodiment of the present invention, the step of forming a conductive structure layer on the substrate includes: forming at least one through hole on the substrate. Forming a conductive material layer on the substrate. The conductive material layer covers the inner wall of the through hole and extends to cover the insulating layer, the first pad and the second pad, and the first surface and the second surface of the substrate. Patterning the conductive material layer to form a conductive structure layer. The conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conductive layer. The conductive layer covers the inner wall of the through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface. The first patterned circuit layer is structurally and electrically connected to the first pad. The second patterned circuit layer is structurally and electrically connected to the second pad.

[0013] In the method for manufacturing a package carrier according to an embodiment of the present invention, the method for manufacturing a package carrier further includes: forming a first solder mask layer on the first build-up layer structure. The first solder mask layer has a plurality of first openings, and the first openings expose a portion of the first build-up layer structure. Forming a second solder mask layer on the second build-up layer structure. The second solder mask layer has a plurality of second openings, and the second openings expose a portion of the second build-up layer structure. Forming a first surface treatment layer on the first build-up layer structure exposed by the first opening. Forming a second surface treatment layer on the second build-up layer structure exposed by the second opening.

[0014] In the method for manufacturing a package carrier according to an embodiment of the present invention, the method for manufacturing a package carrier further comprises: forming a plurality of first solder balls in a first opening of a first solder mask layer, respectively. The first surface treatment layer is located between the first solder balls and the first build-up layer structure, respectively. Forming a plurality of second solder balls in a second opening of a second solder mask layer, respectively. The second surface treatment layer is located between the second solder balls and the second build-up layer structure.

[0015] Based on the above, in the design of the packaging carrier of the present invention, an intermediate board is placed in the opening of the substrate to be used as a passive component, wherein the conductive structure layer structurally and electrically connects the first pad and the second pad of the intermediate board. That is, there is only one contact surface between the conductive structure layer and the first pad and between the conductive structure layer and the second pad, respectively, presenting a blind hole-free connection and high coplanarity. Furthermore, the intermediate board can be electrically connected to the conductive structure layer on both sides. In addition to having better circuit flexibility and utilization, the intermediate board can also serve as a rigid support structure to improve the rigidity of the subsequent packaging structure. In addition, since the packaging carrier of the present invention is a component embedded packaging carrier, in addition to having better coplanarity, thereby improving the subsequent chip packaging yield, it can also have better conductivity, structural reliability and thinner packaging thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1H is a cross-sectional schematic diagram of a method for manufacturing a packaging carrier according to an embodiment of the present invention;

[0017] Figure 2 is a cross-sectional schematic diagram of a packaging carrier according to an embodiment of the present invention;

[0018] Figure 3 Multiple chips are packaged into Figure 2 A cross-sectional schematic diagram of a packaging substrate.

[0019] Description of Reference Numerals

[0020] 10: adhesive layer;

[0021] 20: chip;

[0022] 100a, 100b: packaging substrate;

[0023] 110a, 110b: substrate;

[0024] 111: first surface;

[0025] 112: core layer;

[0026] 113: second surface;

[0027] 114: first copper foil layer;

[0028] 115a, 115b: opening;

[0029] 116: second copper foil layer;

[0030] 117: through hole;

[0031] 120: intermediate board;

[0032] 121: upper surface;

[0033] 122: glass substrate;

[0034] 123: lower surface;

[0035] 124: conductive through hole;

[0036] 126: first pad;

[0037] 128: second pad;

[0038] 130a: insulating material layer;

[0039] 130: insulating layer;

[0040] 140a: conductive material layer;

[0041] 140: conductive structure layer;

[0042] 142: a first patterned circuit layer;

[0043] 144: a second patterned circuit layer;

[0044] 146: conductive layer;

[0045] 150: first build-up layer structure;

[0046] 152: dielectric layer;

[0047] 154: circuit layer;

[0048] 156: conductive blind via;

[0049] 160: second build-up structure;

[0050] 162: dielectric layer;

[0051] 164: circuit layer;

[0052] 166: conductive blind via;

[0053] 170: first solder mask;

[0054] 172: First opening;

[0055] 175: second solder mask;

[0056] 177: Second opening;

[0057] 180: first surface treatment layer;

[0058] 185: second surface treatment layer;

[0059] 190: first solder ball;

[0060] 195: second solder ball;

[0061] G: Gap. DETAILED DESCRIPTION

[0062] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0063] Figures 1A to 1H is a cross-sectional schematic diagram of a method for manufacturing a package carrier according to an embodiment of the present invention. Regarding the method for manufacturing a package carrier of this embodiment, first, please refer to Figure 1A , providing a substrate 110a. In detail, the substrate 110a of the present embodiment includes a core layer 112, a first copper foil layer 114 and a second copper foil layer 116, wherein the first copper foil layer 114 and the second copper foil layer 116 are respectively located on two opposite surfaces of the core layer 112. Here, the substrate 110a is, for example, a copper foil substrate, and the material of the core layer 112 is, for example, glass fiber, but the present invention is not limited to this substrate 110a. In other embodiments not shown, the substrate may also be a BT resin substrate, a plastic substrate, a ceramic substrate or other appropriate substrates.

[0064] Next, please refer to Figure 1B At least one opening 115a (one opening 115a is schematically shown) is formed on the substrate 110a, wherein the opening 115a penetrates the first copper foil layer 114, the core layer 112 and the second copper foil layer 116. Thus, the substrate 110a having the opening 115a is provided.

[0065] Next, please refer to Figure 1B , the adhesive layer 10 is attached to the substrate 110 a , wherein the substrate 110 a has a first surface 111 and a second surface 113 opposite to each other, and the second surface 113 of the substrate 110 a is bonded to the adhesive layer 10 .

[0066] Next, please refer to Figure 1B, at least one interposer 120 (schematically showing one interposer 120) is placed in the opening 115a of the substrate 110a, and is positioned in the opening 115a by the adhesive layer 10. In detail, the interposer 120 of this embodiment includes a glass substrate 122, at least one conductive via 124 (schematically showing three conductive vias 124), at least one first pad 126 (schematically showing three first pads 126), and at least one second pad 128 (schematically showing three second pads 128). The conductive via 124 penetrates the glass substrate 122, and the first pad 126 and the second pad 128 are respectively disposed on the upper surface 121 and the lower surface 123 of the glass substrate 122 that are opposite to each other and connected to the opposite ends of the conductive via 122. In other words, the first pad 126 and the second pad 128 are disposed corresponding to each other and are located at the opposite ends of the conductive via 122. Preferably, the conductive via 122, the first pad 126 and the second pad 128 are made of the same material and are seamlessly connected. At this time, the second pad 128 of the intermediate board 120 is bonded to the adhesive layer 10, and the intermediate board 120 is positioned in the opening 115a. Figure 1B As shown, the interposer 120 is not in direct contact with the opening 115a, but has a gap G with the inner wall of the opening 115a. The first pad 126 may be coplanar with the first surface 111 of the substrate 110a, and the second pad 128 may be coplanar with the second surface 113 of the substrate 110a, but the present invention is not limited thereto.

[0067] Next, please also refer to Figure 1B as well as Figure 1C The insulating material layer 130a is formed in the opening 115a of the substrate 110a by lamination, glue filling, plugging, etc. to seal the substrate 110a. At this time, the insulating material layer 130a fills the opening 115a, covers the upper surface 121 and the lower surface 123 of the glass substrate 122, and extends to cover the first surface 111 and the first pad 126 of the substrate 110a.

[0068] Next, please refer to Figure 1C , the adhesive layer 10 is removed to expose the second surface 113 of the substrate 110 a , a portion of the insulating material layer 130 a and the second pad 128 .

[0069] Next, please also refer to Figure 1C and Figure 1D, by chemical-mechanical polishing (CMP) or plasma thinning, a portion of the insulating material layer 130a is removed to form an insulating layer 130. At this time, the insulating layer 130 exposes the first pad 126 and the second pad 128 of the interposer 120 and is aligned with the first surface 111 and the second surface 113 of the substrate 110a.

[0070] Next, please refer to Figure 1E , forming at least one through hole 117 (two through holes 117 are schematically shown) on the substrate 110a. Next, a conductive material layer 140a is formed on the substrate 110a by electroplating or sputtering, wherein the conductive material layer 140a covers the inner wall of the through hole 117 and extends to cover the insulating layer 130, the first pad 126 and the second pad 128, and the first surface 111 and the second surface 113 of the substrate 110a. That is, the entire board surface is metallized.

[0071] Next, please also refer to Figure 1E and Figure 1F , the conductive material layer 140a is patterned by a subtractive method to form a conductive structure layer 140. The conductive structure layer 140 includes a first patterned circuit layer 142, a second patterned circuit layer 144 and at least one conductive layer 146 (two conductive layers 146 are schematically shown). The conductive layer 146 covers the inner wall of the through hole and connects the first patterned circuit layer 142 located on the first surface 111 of the substrate 110a and the second patterned circuit layer 144 located on the second surface 113 of the substrate 110a. That is, the conductive layer 146 is used to conduct the first patterned circuit layer 142 and the second patterned circuit layer 144. Here, the conductive structure layer 140 exposes a portion of the surface of the core layer 112 of the substrate 110a, and the first patterned circuit layer 142 includes the remaining first copper foil layer 114, and the second patterned circuit layer 144 includes the remaining second copper foil layer 116. In particular, the first patterned circuit layer 142 is structurally and electrically connected to the first pad 126, and the second patterned circuit layer 144 is structurally and electrically connected to the second pad 128. At this time, there is only one contact plane between the first patterned circuit layer 142 and the first pad 126, and there is only one contact plane between the second patterned circuit layer 144 and the second pad 128, which can have a larger contact area, and can provide better conductivity and better connection reliability, and present no blind hole connection and high coplanarity. At this point, the conductive structure layer 140 has been formed on the substrate 110a, wherein the conductive structure layer 140 is structurally and electrically connected to the first pad 126 and the second pad 128 of the interposer 120.

[0072] Next, please refer to Figure 1G, respectively forming a first build-up layer structure 150 and a second build-up layer structure 160 on the first surface 111 and the second surface 113 of the substrate 110a. The first build-up layer structure 150 and the second build-up layer structure 160 are respectively electrically connected to the conductive structure layer 140. In detail, the first build-up layer structure 150 includes at least one dielectric layer 152 (schematically showing one dielectric layer 152), at least one circuit layer 154 (schematically showing one circuit layer 154) and at least one conductive blind via 156 (schematically showing multiple conductive blind vias 156). The dielectric layer 152 at least covers the first patterned circuit layer 142 and fills into the through hole 117. The circuit layer 154 is disposed on the dielectric layer 152 and is electrically connected to the first patterned circuit layer 142 through the conductive blind via 156. The second build-up structure 160 includes at least one dielectric layer 162 (schematically showing one dielectric layer 162), at least one circuit layer 164 (schematically showing one circuit layer 164), and at least one conductive blind via 166 (schematically showing a plurality of conductive blind vias 166). The dielectric layer 162 at least covers the second patterned circuit layer 144 and fills the through hole 117. The circuit layer 164 is disposed on the dielectric layer 162 and is electrically connected to the second patterned circuit layer 144 through the conductive blind via 166.

[0073] Next, please refer to Figure 1G , forming a first solder mask 170 on the first build-up structure 150, and forming a second solder mask 175 on the second build-up structure 160. The first solder mask 170 has a plurality of first openings 172, and the first openings 172 expose a portion of the circuit layer 154 of the first build-up structure 150. The second solder mask 175 has a plurality of second openings 177, and the second openings 177 expose a portion of the circuit layer 164 of the second build-up structure 160. Next, forming a first surface treatment layer 180 on the portion of the circuit layer 154 of the first build-up structure 150 exposed by the first openings 172, and forming a second surface treatment layer 185 on the portion of the circuit layer 164 of the second build-up structure 160 exposed by the second openings 177, to protect the circuit layer 154 and the circuit layer 164 respectively.

[0074] Finally, please refer to Figure 1H, a plurality of first solder balls 190 are formed in the first openings 172 of the first solder mask 170, wherein the first surface treatment layer 180 is located between the first solder balls 190 and the first build-up structure 150. A plurality of second solder balls 195 are formed in the second openings 177 of the second solder mask 175, wherein the second surface treatment layer 185 is located between the second solder balls 195 and the second build-up structure 160. Here, the size of the first solder balls 190 is actually smaller than the size of the second solder balls 195, wherein the first solder balls 190 are suitable for being electrically connected to passive components, active components or other chips of smaller size, and the second solder balls 195 are suitable for being electrically connected to packages or other electronic devices of larger size. At this point, the production of the package carrier 100a has been completed.

[0075] In terms of structure, please refer to Figure 1H , the package carrier 100a includes a substrate 110a, an interposer 120, a conductive structure layer 140, a first build-up structure 150, and a second build-up structure 160. The substrate 110a has a first surface 111 and a second surface 113 opposite to each other, and an opening 115a connecting the first surface 111 and the second surface 113. The interposer 120 is disposed in the opening 115a of the substrate 110a, and the interposer 120 includes a glass substrate 122, a conductive via 124, a first pad 126, and a second pad 128. The conductive via 124 penetrates the glass substrate 122, and the first pad 126 and the second pad 128 are respectively disposed on the upper surface 121 and the lower surface 123 of the glass substrate 122 opposite to each other and connected to opposite ends of the conductive via 124. The conductive structure layer 140 is disposed on the substrate 110a and structurally and electrically connects the first pad 126 and the second pad 128. The first build-up structure 150 is disposed on the first surface 111 of the substrate 110a and is electrically connected to the conductive structure layer 140. The second build-up structure 160 is disposed on the second surface 113 of the substrate 110a and is electrically connected to the conductive structure layer 140.

[0076] Furthermore, the package carrier 100a of the present embodiment further includes an insulating layer 130, wherein the insulating layer 130 fills the opening 115a of the substrate 110a, covers the upper surface 121 and the lower surface 123 of the glass substrate 120, and exposes the first pad 126 and the second pad 128. Preferably, the insulating layer 130 is flush with the first surface 111 and the second surface 113 of the substrate 110a. The substrate 110a of the present embodiment further has a through hole 117, and the conductive structure layer 140 includes a first patterned circuit layer 142, a second patterned circuit layer 144, and a conductive layer 146. The conductive layer 146 covers the inner wall of the through hole 117, and connects the first patterned circuit layer 142 on the first surface 111 and the second patterned circuit layer 144 on the second surface 113. The first patterned circuit layer 142 is structurally and electrically connected to the first pad 126. The second patterned circuit layer 144 is structurally and electrically connected to the second pad 128 .

[0077] In addition, the package carrier 100a of the present embodiment further includes a first solder mask layer 170, a second solder mask layer 175, a first surface treatment layer 180, and a second surface treatment layer 185. The first solder mask layer 170 is disposed on the first build-up layer structure 150, wherein the first solder mask layer 170 has a first opening 172, and the first opening 172 exposes a portion of the first build-up layer structure 150. The second solder mask layer 175 is disposed on the second build-up layer structure 160, wherein the second solder mask layer 175 has a second opening 177, and the second opening 177 exposes a portion of the second build-up layer structure 160. The first surface treatment layer 180 is disposed on the first build-up layer structure 150 exposed by the first opening 172. The second surface treatment layer 185 is disposed on the second build-up layer structure 160 exposed by the second opening 177.

[0078] In addition, in order to electrically connect with an external circuit, the package carrier 100a of the present embodiment further includes a plurality of first solder balls 190 and a plurality of second solder balls 195. The first solder balls 190 are respectively disposed in the first openings 172 of the first solder mask 170, wherein the first surface treatment layer 180 is located between the first solder balls 190 and the first build-up structure 150. The second solder balls 195 are respectively disposed in the second openings 177 of the second solder mask 175, wherein the second surface treatment layer 185 is located between the second solder balls 195 and the second build-up structure 160.

[0079] Since the interposer 120 of the present embodiment is based on the glass substrate 122 with high rigidity, high flatness and high dimensional stability, and the conductive structure layer 140 is directly connected to the first pad 126 and the second pad 128. That is, there is only one contact surface between the conductive structure layer 140 and the first pad 126 and between the conductive structure layer 140 and the second pad 128, respectively, which can have a larger contact area, and can provide better conductivity and better connection reliability, and present no blind hole connection and high coplanarity. In short, the interposer 120 of the present embodiment can be electrically connected to the conductive structure layer 140 on both sides. In addition to having better circuit flexibility and utilization, the interposer 120 can also be used as a rigid support structure to improve the rigidity of the subsequent packaging structure.

[0080] Furthermore, since the interposer 120 of the present embodiment provides a contact connection structure with high rigidity, high coplanarity and high flatness, the first solder balls 190 and the second solder balls 195 formed on the interposer 120 and electrically connected to the external circuit can form chip connection points with high coplanarity. In addition, since the interposer 120 of the present embodiment is placed in the opening 115 of the substrate 110a, it can be regarded as a passive component, so the package carrier 100a of the present embodiment can be regarded as a component embedded package carrier, which can not only have better coplanarity, thereby improving the subsequent chip packaging yield, but also have better conductive performance, structural reliability and thinner packaging thickness.

[0081] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0082] Figure 2 It is a cross-sectional schematic diagram of a packaging carrier according to an embodiment of the present invention. Figure 3 Multiple chips are packaged into Figure 2 Please refer to the cross-sectional diagram of the package carrier board. Figure 2 The package carrier 100b of this embodiment and Figure 1H The difference between the two is that the substrate 110b of this embodiment has a plurality of openings 115b (two openings 115b are schematically shown), and a plurality of intermediary boards 120 (two intermediary boards 120 are schematically shown) are respectively placed in the openings 115b. For application, please refer to Figure 3, at least one chip 20 (two chips 20 are schematically shown) can be bonded to the package carrier 100b through the first solder balls 190. That is, the package carrier 100b of this embodiment can realize multi-chip packaging through multiple interposers 120, which can not only improve the chip packaging yield, but also meet the modularization requirements.

[0083] In summary, in the design of the packaging carrier of the present invention, an intermediate board is placed in the opening of the substrate to be used as a passive component, wherein the conductive structure layer structurally and electrically connects the first pad and the second pad of the intermediate board. That is, there is only one contact surface between the conductive structure layer and the first pad and between the conductive structure layer and the second pad, respectively, presenting a blind hole-free connection and high coplanarity. Furthermore, the intermediate board can be electrically connected to the conductive structure layer on both sides. In addition to having better circuit flexibility and utilization, the intermediate board can also serve as a rigid support structure to improve the rigidity of the subsequent packaging structure. In addition, since the packaging carrier of the present invention is a component embedded packaging carrier, in addition to having better coplanarity, thereby improving the subsequent chip packaging yield, it can also have better conductivity, structural reliability and thinner packaging thickness.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging carrier, characterized in that: include: A substrate having a first surface and a second surface opposite to each other and at least one opening connecting the first surface and the second surface; At least one intermediate board is disposed in the at least one opening of the substrate, each of the intermediate boards comprises a glass substrate, at least one conductive through hole, at least one first pad and at least one second pad, the at least one conductive through hole penetrates the glass substrate, and the at least one first pad and the at least one second pad are respectively disposed on the upper surface and the lower surface of the glass substrate opposite to each other and connected to opposite ends of the conductive through hole; A conductive structure layer, disposed on the substrate, and structurally and electrically connecting the at least one first pad and the at least one second pad; A first build-up layer structure, disposed on the first surface of the substrate and electrically connected to the conductive structure layer; as well as The second build-up layer structure is disposed on the second surface of the substrate and is electrically connected to the conductive structure layer. The at least one conductive through hole, the at least one first pad and the at least one second pad have the same material and are seamlessly connected.

2. The packaging carrier according to claim 1, characterized in that: Also includes: The insulating layer fills the at least one opening of the substrate, covers the upper surface and the lower surface of the glass substrate, and exposes the at least one first pad and the at least one second pad, wherein the insulating layer is aligned with the first surface and the second surface of the substrate.

3. The packaging carrier according to claim 1, characterized in that: The substrate also has at least one through hole, and the conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conductive layer. The at least one conductive layer covers the inner wall of the at least one through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface. The first patterned circuit layer is structurally and electrically connected to the at least one first pad, and the second patterned circuit layer is structurally and electrically connected to the at least one second pad.

4. The packaging carrier according to claim 1, characterized in that: Also includes: A first solder mask layer is disposed on the first build-up layer structure, wherein the first solder mask layer has a plurality of first openings, and the plurality of first openings expose a portion of the first build-up layer structure; A second solder mask layer is disposed on the second build-up layer structure, wherein the second solder mask layer has a plurality of second openings, and the plurality of second openings expose a portion of the second build-up layer structure; A first surface treatment layer is disposed on the first build-up layer structure exposed by the plurality of first openings; as well as The second surface treatment layer is disposed on the second build-up layer structures exposed by the plurality of second openings.

5. The packaging carrier according to claim 4, characterized in that: Also includes: A plurality of first solder balls are respectively disposed in the plurality of first openings of the first solder resist layer, and the first surface treatment layer is located between the plurality of first solder balls and the first build-up layer structure; as well as A plurality of second solder balls are respectively disposed in the plurality of second openings of the second solder resist layer, and the second surface treatment layer is located between the plurality of second solder balls and the second build-up layer structure.

6. A method for manufacturing a packaging carrier, characterized in that: include: Providing a substrate having at least one opening; Placing at least one intermediate board in the at least one opening of the substrate, each of the intermediate boards comprising a glass substrate, at least one conductive through hole, at least one first pad and at least one second pad, the at least one conductive through hole penetrating the glass substrate, and the at least one first pad and the at least one second pad respectively disposed on the upper surface and the lower surface of the glass substrate opposite to each other and connected to opposite ends of the conductive through hole; forming a conductive structure layer on the substrate, wherein the conductive structure layer structurally and electrically connects the at least one first pad and the at least one second pad; as well as A first build-up layer structure and a second build-up layer structure are respectively formed on the first surface and the second surface of the substrate, the first build-up layer structure and the second build-up layer structure are respectively electrically connected to the conductive structure layer, and the at least one conductive through hole, the at least one first pad and the at least one second pad have the same material and are seamlessly connected.

7. The method for manufacturing a packaging carrier according to claim 6, characterized in that: Also includes: Before forming the conductive structure layer on the substrate, forming an insulating material layer in the at least one opening of the substrate, the insulating material layer filling the at least one opening, covering the upper surface and the lower surface of the glass substrate, and extending to cover the first surface of the substrate and the at least one first pad; as well as A portion of the insulating material layer is removed to form an insulating layer, wherein the insulating layer exposes the at least one first pad and the at least one second pad and is aligned with the first surface and the second surface of the substrate.

8. The method for manufacturing a packaging carrier according to claim 7, characterized in that: The step of forming the conductive structure layer on the substrate comprises: forming at least one through hole on the substrate; forming a conductive material layer on the substrate, the conductive material layer covering the inner wall of the at least one through hole and extending to cover the insulating layer, the at least one first pad and the at least one second pad, and the first surface and the second surface of the substrate; and The conductive material layer is patterned to form the conductive structure layer, wherein the conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conductive layer, the at least one conductive layer covers the inner wall of the at least one through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface, the first patterned circuit layer is structurally and electrically connected to the at least one first pad, and the second patterned circuit layer is structurally and electrically connected to the at least one second pad.

9. The method for manufacturing a packaging carrier according to claim 6, characterized in that: Also includes: forming a first solder mask layer on the first build-up layer structure, wherein the first solder mask layer has a plurality of first openings, and the plurality of first openings expose a portion of the first build-up layer structure; forming a second solder mask layer on the second build-up layer structure, wherein the second solder mask layer has a plurality of second openings, and the plurality of second openings expose a portion of the second build-up layer structure; forming a first surface treatment layer on the first build-up layer structures exposed by the plurality of first openings; as well as A second surface treatment layer is formed on the second build-up layer structures exposed by the plurality of second openings.

10. The method for manufacturing a packaging carrier according to claim 9, characterized in that: Also includes: forming a plurality of first solder balls in the plurality of first openings of the first solder resist layer respectively, wherein the first surface treatment layer is located between the plurality of first solder balls and the first build-up layer structure; as well as A plurality of second solder balls are respectively formed in the plurality of second openings of the second solder resist layer, wherein the second surface treatment layer is located between the plurality of second solder balls and the second build-up layer structure.

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