Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a preparation method thereof, relating to the field of semiconductor technology, the semiconductor device comprises a substrate and a semiconductor layer, the semiconductor layer is divided into two spaced active areas, and an inactive area located outside the active area, a first source, a drain and a gate are arranged in the active area, a source pad, a drain pad and a gate pad are arranged in the inactive area, the drain pad is connected to the drain, and the gate pad is connected to the gate; a second source is connected to the two active areas, the second source comprises a first metal part, a second metal part and a third metal part, the first metal part and the third metal part are respectively connected to the two active areas, and the second metal part is located in the inactive area between the two active areas; the source pad is respectively connected to the first source and the second source, and the source pad and the second source share the second metal part, so as to obtain a prefabricated device structure. The semiconductor device can improve the problem of complex probe distribution caused by the source test pad being arranged at the edge of the chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the miniaturization and high integration of semiconductor devices, the size of semiconductor devices is getting smaller and smaller, and the problem of their electrical performance is becoming more and more prominent. Therefore, in order to ensure the quality of semiconductor devices, it is particularly important to conduct electrical testing on the semiconductor device structure.

[0003] Traditional semiconductor devices are usually equipped with test pads that are electrically connected to the active area of ​​the device for electrical testing, including source test pads, drain test pads, and gate test pads. After all process steps are completed, the test pads are electrically tested using test probes, and by analyzing the test data, problems in the semiconductor manufacturing process can be effectively monitored, which helps adjust and optimize the manufacturing process, as well as control product yield.

[0004] In order to avoid the problem of potential reduction and potential unevenness caused by device size and effectively reduce the abnormal rate during testing, such as Figure 1 As shown, the existing source test pads usually include two, and the two source test pads are respectively arranged on opposite sides of the chip edge, which occupies too many probe resources and easily leads to complex spatial distribution of the probes, which is not conducive to simultaneous testing of multiple chips, thereby affecting the test efficiency of the chip. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for preparing the same, which can improve the problem of complex probe distribution caused by setting a source test pad at the edge of a chip, and help to test multiple chips at the same time, thereby improving the test efficiency of the chip.

[0006] The embodiment of the present invention is achieved as follows:

[0007] In one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a substrate and a semiconductor layer arranged on the substrate, the semiconductor layer is divided into two spaced active areas, and an inactive area located outside the active area, the active area is provided with a first source, a drain and a gate, the inactive area is provided with a source pad, a drain pad and a gate pad, the drain pad is connected to the drain, and the gate pad is connected to the gate; a second source is connected and arranged on the two spaced active areas, the second source includes a first metal part, a second metal part and a third metal part connected in sequence, the first metal part and the third metal part are respectively connected to the two active areas, and the second metal part is located in the inactive area between the two active areas; the source pad is respectively connected to the first source and the second source, and the source pad and the second source share the second metal part, so as to obtain a prefabricated device structure. The semiconductor device can improve the problem of complex probe distribution caused by the source test pad being arranged at the edge of the chip, which is helpful for simultaneous testing of multiple chips, thereby improving the test efficiency of the chip.

[0008] Optionally, the second source includes an ohmic metal layer and an interconnection metal layer disposed on the ohmic metal layer, and the second metal portion is formed on the ohmic metal layer and the interconnection metal layer.

[0009] Optionally, the active area includes at least one sub-active area, and the sub-active area includes N+1 first sources, N drains and N gates, where N is a positive integer greater than or equal to 1; wherein the first sources and the drains are alternately arranged along a first direction of the active area, and the gate is inserted between adjacent first sources and drains, and the first direction is perpendicular to the connection direction of the gate pad and the drain pad.

[0010] Optionally, along the first direction, the width of the second source is greater than the width of the first source.

[0011] Optionally, along the first direction, a minimum distance between a center of the source pad and the gate is smaller than a minimum distance between the gate and a center of a cutting path.

[0012] Optionally, it also includes a dielectric layer arranged on the prefabricated device structure, the dielectric layer covers the active area and the passive area, and the dielectric layer is provided with a source pad window for exposing the source pad, a drain pad window for exposing the drain pad, and a gate pad window for exposing the gate pad.

[0013] Optionally, it also includes a protective layer arranged on the dielectric layer, the protective layer covers the active area and the passive area, and the protective layer is provided with a first opening for exposing the source pad window, a second opening for exposing the drain pad window, and a third opening for exposing the gate pad window.

[0014] Optionally, when the source electrode has a grounding through hole, the orthographic projections of the source electrode pad and the grounding through hole on the substrate have no overlapping area.

[0015] Another aspect of an embodiment of the present invention provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, and the method comprises:

[0016] Forming a semiconductor layer on a substrate, wherein the semiconductor layer is divided into two active regions spaced apart from each other and an inactive region located outside the active region;

[0017] A first source, a drain and a gate are respectively manufactured on the active area, a source pad, a drain pad and a gate pad are respectively manufactured on the passive area, a second source is manufactured on the two active areas spaced apart, the second source comprises a first metal part, a second metal part and a third metal part connected in sequence, the first metal part and the third metal part are respectively connected to the two active areas, the second metal part is located in the passive area between the two active areas, and the source pad and the second source share the second metal part;

[0018] The drain pad is connected to the drain, the gate pad is connected to the gate, and the source pad is connected to the first source and the second source respectively to obtain a prefabricated device structure.

[0019] The beneficial effects of the embodiments of the present invention include:

[0020] The semiconductor device comprises: a substrate and a semiconductor layer arranged on the substrate, wherein the semiconductor layer is divided into two spaced active areas and an inactive area located outside the active area, wherein a first source, a drain and a gate are arranged in the active area, and a source pad, a drain pad and a gate pad are arranged in the inactive area, wherein the drain pad is connected to the drain, and the gate pad is connected to the gate; a second source is connected to the two spaced active areas, wherein the second source comprises a first metal part, a second metal part and a third metal part connected in sequence, wherein the first metal part and the third metal part are respectively connected to the two active areas, and the second metal part is located in the inactive area between the two active areas; the source pad is respectively connected to the first source and the second source, and the source pad and the second source share the second metal part, thereby obtaining a prefabricated device structure. When using a probe to test the semiconductor device, the probe can be directly connected to the source pad located between the two active areas (i.e., the middle of the chip). Compared with the semiconductor device in the prior art, the probe needs to be connected to the source test pads located on the opposite sides of the chip edge (i.e., the upper and lower ends of the chip) respectively. This semiconductor device can make the distribution of the probe simpler, which is conducive to simultaneous testing of multiple chips, thereby improving the testing efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a structural schematic diagram of a semiconductor device in the prior art;

[0023] Figure 2 One of the structural schematic diagrams of a semiconductor device provided by an embodiment of the present invention;

[0024] Figure 3 A second structural schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0025] Figure 4 for Figure 3 Sectional view at AA;

[0026] Figure 5 A third structural schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0027] Figure 6 A fourth structural schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0028] Figure 7 for Figure 6Cross-sectional view at BB.

[0029] Icon: 100-substrate; 200-semiconductor layer; 201-active area; 202-passive area; 210-first source; 220-drain; 230-gate; 240-second source; 241-first metal part; 242-second metal part; 243-third metal part; 244-ohmic metal layer; 245-interconnection metal layer; 246-first interconnection metal layer; 247-second interconnection metal layer; 250-source pad; 260-drain pad; 270-gate pad; 300-dielectric layer; 110-chip edge. DETAILED DESCRIPTION

[0030] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the applications of these concepts not specifically proposed herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0031] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intervening element. Similarly, it should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "extending directly onto another element", there is no intervening element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intervening element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intervening element.

[0033] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures.

[0034] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It should also be understood that when used herein, the term "comprising" indicates the presence of the features, integers, steps, operations, elements, and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups of the above.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in this document.

[0036] Please refer to Figures 2 to 7 In one aspect of this embodiment, a semiconductor device is provided, including: a substrate 100, which may be a base material for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, etc. Figure 2 and Figure 5 As shown, the edge of the substrate 100 may be an edge 110 of a single chip divided by dicing streets on a wafer.

[0037] Then, a semiconductor layer 200 is deposited on the substrate 100. The deposition method can be through chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes. Those skilled in the art should be able to make reasonable selections and designs based on actual conditions, and no specific restrictions are made here.

[0038] The semiconductor layer 200 is divided into two active areas 201 spaced apart from each other, and a passive area 202 located outside the active area 201. It is worth noting that since the two active areas 201 are spaced apart from each other, there is also a passive area 202 arranged around the active area 201 between the two active areas 201. The active area 201 and the passive area 202 on the semiconductor layer 200 can be defined by a mesa isolation process or an ion implantation process, which will not be explained here. Among them, the semiconductor layer 200 can be one layer, two layers or multiple layers, and when setting, it should be reasonably selected in combination with the device type, such as an insulated gate field effect transistor (MISFET), a high electron mobility transistor (HEMT), etc. Those skilled in the art should be able to make reasonable selections and designs according to actual conditions, and no specific restrictions are made here.

[0039] An active device is arranged in the active region 201 of the semiconductor layer 200. For example, a first source 210, a drain 220 and a gate 230 are arranged in the active region 201. It should be understood by those skilled in the art that the gate 230 is located between the first source 210 and the drain 220, so that the gate 230 can form an active structure with a gate control function above the channel between the first source 210 and the drain 220. The active device can be one or more. When there are more than one active devices, there can be more than one first source 210, drain 220 and gate 230. The first source 210 and drain 220 can be shared between the multiple active devices, so that more active devices can be integrated within the limited area of ​​the chip. A source pad 250 , a drain pad 260 and a gate pad 270 are provided in the inactive region 202 of the semiconductor layer 200 . The drain pad 260 is connected to the drain 220 , and the gate pad 270 is connected to the gate 230 . The connection may be through metal connection.

[0040] A second source 240 is connected to two active regions 201 spaced apart from each other, and the second source 240 includes a first metal portion 241, a second metal portion 242, and a third metal portion 243 connected in sequence, wherein the first metal portion 241 and the third metal portion 243 are connected to the two active regions 201, respectively, and the second metal portion 242 is located in the inactive region 202 between the two active regions 201. The first metal portion 241, the second metal portion 242, and the third metal portion 243 here are for more clearly describing the regional division of the second source 240. In the actual device structure manufacturing process, the first metal portion 241, the second metal portion 242, and the third metal portion 243 can be manufactured simultaneously in the same process step. Those skilled in the art should be able to make reasonable selections and designs according to actual conditions, and no specific restrictions are made here.

[0041] The source pad 250 is connected to the first source 210 and the second source 240 respectively, and the source pad 250 and the second source 240 share the second metal part 242, so as to obtain a prefabricated device structure. When the semiconductor device is tested by a probe, the probe can be directly connected to the source pad 250 located between the two active areas 201 (i.e., the middle of the chip). Compared with the semiconductor device in the prior art, the probe needs to be connected to the source test pads located on the opposite sides of the chip edge 110 (i.e., the upper end and the lower end of the chip), respectively. The semiconductor device can make the distribution of the probe simpler, which is helpful for testing multiple chips at the same time, thereby improving the test efficiency of the chip.

[0042] As described above, the semiconductor device includes: a substrate 100 and a semiconductor layer 200 disposed on the substrate 100, the semiconductor layer 200 is divided into two spaced active regions 201, and a passive region 202 located outside the active region 201, the active region 201 is provided with a first source 210, a drain 220 and a gate 230, the passive region 202 is provided with a source pad 250, a drain pad 260 and a gate pad 270, the drain pad 260 is connected to the drain 220, and the gate pad 270 is connected to the gate 230; A second source 240 is connected to each active area 201, and the second source 240 includes a first metal part 241, a second metal part 242 and a third metal part 243 which are connected in sequence. The first metal part 241 and the third metal part 243 are respectively connected to the two active areas 201, and the second metal part 242 is located in the inactive area 202 between the two active areas 201; the source pad 250 is respectively connected to the first source 210 and the second source 240, and the source pad 250 and the second source 240 share the second metal part 242 to obtain a prefabricated device structure. When using a probe to test the semiconductor device, the probe can be directly connected to the source pad 250 located between the two active areas 201 (i.e., the middle of the chip). Compared with the semiconductor device in the prior art, the probe needs to be connected to the source test pads located on the opposite sides of the chip edge 110 (i.e., the upper and lower ends of the chip) respectively. This semiconductor device can make the distribution of the probe simpler, which is conducive to simultaneous testing of multiple chips, thereby improving the testing efficiency of the chip.

[0043] In addition, in order to avoid the problem of potential reduction and uneven potential, the semiconductor device in the prior art will set source test pads at both ends of the chip respectively. Therefore, there is also the problem that the source test pad occupies a large area on the chip. Since the semiconductor device sets the source pad 250 in the middle of the chip, the semiconductor device can also reduce the area occupied by the source pad 250 on the chip, improve the utilization rate of the wafer area, and increase the number of chips produced by a single chip. In addition, the semiconductor device in the prior art also has the problem that the part located in the middle of the chip has poor heat dissipation and the part located at both ends of the chip has good heat dissipation. Since the semiconductor device sets the source pad 250 in the middle of the chip, the source pad 250 can also effectively improve the heat dissipation effect in the middle of the chip. At the same time, since the semiconductor device sets the source pad 250 in the middle of the chip, the semiconductor device can also reduce the voltage drop problem from the test point of the probe on the source pad 250 to the far end of the test, effectively reducing the abnormality rate during the test.

[0044] The above-mentioned source pad 250 can be used as a source wire bonding pad or as a source test pad. Similarly, the drain pad 260 can be used as a drain 220 wire bonding pad or as a drain 220 test pad. The gate pad 270 can be used as a gate 230 wire bonding pad or as a gate 230 test pad. Technical personnel in this field should be able to make reasonable selections and designs based on actual conditions, and no specific restrictions are made here.

[0045] For example, Figure 4 and Figure 7 As shown, the second source 240 includes an ohmic metal layer 244 and an interconnection metal layer 245 disposed on the ohmic metal layer 244. For example, the interconnection metal layer 245 may be one or more. When the interconnection metal layer 245 is multiple, for example, the first interconnection metal layer 246 and the second interconnection metal layer 247. When the orthographic projection of the ohmic metal layer 244 on the substrate 100 and the orthographic projection of the source pad 250 on the substrate 100 have an overlapping area, the second metal portion 242 is formed on the ohmic metal layer 244 and the interconnection metal layer 245.

[0046] For example, Figures 2 to 4 As shown, in some embodiments, the orthographic projection of the second metal portion 242 on the substrate 100 falls within the orthographic projection of the ohmic metal layer 244 on the substrate 100 and the orthographic projection of the interconnection metal layer 245 on the substrate 100, respectively; for example, as Figures 5 to 7 As shown, in some other embodiments, the orthographic projection of the second metal portion 242 on the substrate 100 overlaps with the orthographic projection of the ohmic metal layer 244 of the second source 240 on the substrate 100 and the orthographic projection of the interconnection metal layer 245 on the substrate 100 .

[0047] Optionally, the active area 201 includes at least one sub-active area, and the sub-active area includes N+1 first sources 210, N drains 220 and N gates 230, where N is a positive integer greater than or equal to 1; wherein the first sources 210 and the drains 220 are alternately arranged along a first direction of the active area 201, and the gates 230 are inserted between adjacent first sources 210 and drains 220, and the first direction is perpendicular to the connection direction of the gate pad 270 and the drain pad 260. For example, the first source 210 and the second source 240 are located on opposite sides of the active area 201 along the first direction, so as to facilitate the connection and setting of the second source 240 between the two active areas 201, thereby facilitating the setting of the source pad 250 in the middle of the chip. For example, Figure 2 and Figure 3 As shown, in some embodiments, the active region 201 includes a sub-active region, and the sub-active region includes three first sources 210 , two drains 220 and two gates 230 .

[0048] Since the second source 240 needs to be connected to the two active areas 201 respectively through the first metal part 241 and the second metal part 242, and also needs to share the second metal part 242 with the second source 240, therefore, optionally, along the first direction, the width L2 of the second source 240 is greater than the width L1 of the first source 210. Optionally, along the first direction, the minimum spacing L3 between the center of the source pad 250 and the gate 230 is less than the minimum spacing L4 between the gate 230 and the center of the cutting path.

[0049] Optionally, in order to improve the stability and reliability of the semiconductor device, as Figure 3 and Figure 6 As shown, the semiconductor device also includes a dielectric layer 300 disposed on the prefabricated device structure, and the dielectric layer 300 covers the active area 201 and the passive area 202. The dielectric layer 300 can prevent water vapor from entering the semiconductor device to effectively protect the semiconductor device. Since the basic functions of the dielectric layer 300 are well known to those skilled in the art, no further explanation is given here. By etching, a window can be opened on the dielectric layer 300. For example, a source pad 250 window for exposing the source pad 250, a drain pad 260 window for exposing the drain pad 260, and a gate pad 270 window for exposing the gate pad 270 are provided on the dielectric layer 300. Those skilled in the art should understand that the orthographic projection of the source pad 250 window on the source pad 250 is located within the source pad 250 . Similarly, the orthographic projection of the drain pad 260 window on the drain pad 260 is located within the drain pad 260 , and the orthographic projection of the gate pad 270 window on the gate pad 270 is located within the gate pad 270 .

[0050] For example, after the first source 210, the drain 220 and the gate 230 are formed on the semiconductor layer 200, metal is also formed simultaneously. A whole dielectric layer 300 is epitaxially grown on the basis of this structure, and then windows are etched and opened at corresponding positions so that the metal below can be exposed from the windows. In this way, the part of the metal connected to the drain 220 exposed in the window of the drain pad 260 can be used as the drain pad 260, the part of the metal connected to the gate 230 exposed in the window of the gate pad 270 can be used as the gate pad 270, and the part of the metal connected to the first source 210 and the second source 240 respectively exposed in the window of the source pad 250 can be used as the source pad 250.

[0051] Optionally, in order to further improve the stability and reliability of the semiconductor device, the semiconductor device further includes a protective layer disposed on the dielectric layer 300, the protective layer covers the active area 201 and the passive area 202, and the protective layer is provided with a first opening for exposing the window of the source pad 250, a second opening for exposing the window of the drain pad 260, and a third opening for exposing the window of the gate pad 270. For example, the opening area of ​​the first opening is smaller than the opening area of ​​the window of the source pad 250, the opening area of ​​the second opening is smaller than the opening area of ​​the window of the drain pad 260, and the opening area of ​​the third opening is smaller than the opening area of ​​the window of the gate pad 270, so that the semiconductor device can further improve the ability of the semiconductor device to prevent water vapor intrusion through the protective layer.

[0052] Optionally, when the source has a grounding through hole, the orthographic projections of the source pad 250 and the grounding through hole on the substrate 100 have no overlapping area, so as to avoid the probe penetrating the source pad 250 and extending into the grounding through hole during electrical testing. For example, the grounding through hole is located at one end of the first source 210 close to the drain pad 260, or the grounding through hole is located at one end of the first source 210 close to the gate pad 270, and it is only necessary to make the orthographic projections of the source pad 250 and the grounding through hole on the substrate 100 have no overlapping area. Those skilled in the art should be able to make reasonable selections and designs according to actual conditions, and no specific restrictions are made here.

[0053] Another aspect of the present embodiment provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, and the method includes:

[0054] S100, forming a semiconductor layer 200 on a substrate 100, wherein the semiconductor layer 200 is divided into two active regions 201 spaced apart from each other and an inactive region 202 located outside the active region 201;

[0055] S200, respectively fabricating a first source 210, a drain 220 and a gate 230 on the active region 201, respectively fabricating a source pad 250, a drain pad 260 and a gate pad 270 on the passive region 202, and fabricating a second source 240 on two spaced active regions 201, wherein the second source 240 comprises a first metal portion 241, a second metal portion 242 and a third metal portion 243 connected in sequence, wherein the first metal portion 241 and the third metal portion 243 are respectively connected to the two active regions 201, the second metal portion 242 is located in the passive region 202 between the two active regions 201, and the source pad 250 and the second source 240 share the second metal portion 242;

[0056] S300 , connecting the drain pad 260 to the drain 220 , connecting the gate pad 270 to the gate 230 , and connecting the source pad 250 to the first source 210 and the second source 240 , respectively, to obtain a prefabricated device structure.

[0057] Since a second source 240 is connected and arranged on two spaced active areas 201, the second source 240 includes a first metal part 241, a second metal part 242 and a third metal part 243 which are connected in sequence, wherein the first metal part 241 and the third metal part 243 are respectively connected to the two active areas 201, the second metal part 242 is located in the inactive area 202 between the two active areas 201, and the source pad 250 and the second source 240 share the second metal part 242. Therefore, when the semiconductor device is tested by a probe, the probe can be directly connected to the source pad 250 located between the two active areas 201 (i.e., the middle of the chip). Compared with the semiconductor device in the prior art, the probe needs to be connected to the source test pads located on the opposite sides of the chip edge 110 (i.e., the upper end and the lower end of the chip) respectively. The semiconductor device can make the distribution of the probe simpler, which is helpful for simultaneous testing of multiple chips, thereby improving the testing efficiency of the chip.

[0058] In addition, since the semiconductor device has a source pad 250 disposed in the middle of the chip, the semiconductor device can also reduce the area occupied by the source pad 250 on the chip, improve the utilization rate of the wafer area, and increase the number of chips produced by a single chip. In addition, since the semiconductor device has a source pad 250 disposed in the middle of the chip, the source pad 250 can also effectively improve the heat dissipation effect in the middle of the chip. At the same time, since the semiconductor device has a source pad 250 disposed in the middle of the chip, the semiconductor device can also reduce the voltage drop problem from the test point of the probe on the source pad 250 to the far end of the test, effectively reducing the abnormality rate during the test.

[0059] It should be noted that where the preparation method of the semiconductor device provided in this embodiment has the same structure as the semiconductor device in the previous text, those skilled in the art can infer its preparation method based on the structural description in the previous text, and this application will not repeat the description.

[0060] The above description is only an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0061] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

Claims

1. A semiconductor device, It is characterized in that The invention comprises: a substrate and a semiconductor layer arranged on the substrate, wherein the semiconductor layer is divided into two spaced active areas and a passive area located outside the active area, wherein a first source, a drain and a gate are arranged in the active area, and a source pad, a drain pad and a gate pad are arranged in the passive area, wherein the drain pad is connected to the drain, and the gate pad is connected to the gate; a second source is connected to the two spaced active areas, wherein the second source comprises a first metal part, a second metal part and a third metal part connected in sequence, wherein the first metal part and the third metal part are respectively connected to the two active areas, and the second metal part is located in the passive area between the two active areas; the source pad is respectively connected to the first source and the second source, and the source pad and the second source share the second metal part, thereby obtaining a prefabricated device structure.

2. The semiconductor device according to claim 1, It is characterized in that The second source includes an ohmic metal layer and an interconnection metal layer disposed on the ohmic metal layer, and the second metal portion is formed on the ohmic metal layer and the interconnection metal layer.

3. The semiconductor device according to claim 1, It is characterized in that The active area includes at least one sub-active area, and the sub-active area includes N+1 first sources, N drains and N gates, where N is a positive integer greater than or equal to 1; wherein the first sources and the drains are alternately arranged along a first direction of the active area, and the gates are inserted between adjacent first sources and drains, and the first direction is perpendicular to the connection direction of the gate pad and the drain pad.

4. The semiconductor device according to claim 3, It is characterized in that Along the first direction, the width of the second source is greater than the width of the first source.

5. The semiconductor device according to claim 3, It is characterized in that Along the first direction, a minimum distance between a center of the source pad and the gate is smaller than a minimum distance between the gate and a center of a scribe line.

6. The semiconductor device according to claim 1, It is characterized in that It also includes a dielectric layer arranged on the prefabricated device structure, the dielectric layer covers the active area and the passive area, and the dielectric layer is provided with a source pad window for exposing the source pad, a drain pad window for exposing the drain pad, and a gate pad window for exposing the gate pad.

7. The semiconductor device according to claim 6, It is characterized in that It also includes a protective layer arranged on the dielectric layer, the protective layer covers the active area and the passive area, and the protective layer is provided with a first opening for exposing the source pad window, a second opening for exposing the drain pad window, and a third opening for exposing the gate pad window.

8. The semiconductor device according to claim 1, It is characterized in that When the source electrode has a grounding through hole, the orthographic projections of the source electrode pad and the grounding through hole on the substrate have no overlapping area.

9. A method for preparing a semiconductor device, It is characterized in that For preparing a semiconductor device according to any one of claims 1 to 8, the method comprising: Forming a semiconductor layer on a substrate, wherein the semiconductor layer is divided into two active regions spaced apart from each other and an inactive region located outside the active region; A first source, a drain and a gate are respectively manufactured on the active area, a source pad, a drain pad and a gate pad are respectively manufactured on the passive area, a second source is manufactured on the two active areas spaced apart, the second source comprises a first metal part, a second metal part and a third metal part connected in sequence, the first metal part and the third metal part are respectively connected to the two active areas, the second metal part is located in the passive area between the two active areas, and the source pad and the second source share the second metal part; The drain pad is connected to the drain, the gate pad is connected to the gate, and the source pad is connected to the first source and the second source respectively to obtain a prefabricated device structure.

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