Photoelectric conversion device and system, movable body control system, and semiconductor device

Abstract

Provided are a photoelectric conversion device and system, a movable body control system, and a semiconductor device. The photoelectric conversion device includes a first chip including a first semiconductor element layer and a second chip including a second semiconductor element layer, the first chip and the second chip being joined by a plurality of metal junctions between the first semiconductor element layer and the second semiconductor element layer, a plurality of pixel circuits including a first pixel block and a second pixel block, the first pixel block including n pixel circuits, n being an integer greater than or equal to 3, the plurality of metal junctions including a first metal junction connecting the first semiconductor element layer and the second semiconductor element layer, and the number of the first metal junctions arranged at positions overlapping the first pixel block in a plan view being smaller than the number of the first metal junctions arranged at positions overlapping the second pixel block in a plan view.

Description

TECHNICAL FIELD

[0001] The present application relates to a photoelectric conversion device. BACKGROUND

[0002] It is known to electrically connect a plurality of chips stacked in a photoelectric conversion device via metal junctions formed by a wiring pattern that joins the respective chips.

[0003] Japanese Patent Application Publication No. 2018-056580 discusses a photoelectric conversion device that includes a first chip having a first semiconductor element layer including a pixel region in which a plurality of pixels are arranged two-dimensionally, and a second chip having a second semiconductor element layer. The first chip is stacked with the second chip and joined by metal junctions.

[0004] The technology discussed in Japanese Patent Application Publication No. 2018-056580 does not discuss a desired arrangement position of the metal junctions that connect the first chip and the second chip, and a desired number of the metal junctions to be arranged. The technology discussed in Japanese Patent Application Publication No. 2018-056580 can improve the characteristics of the photoelectric conversion device by investigating a desired arrangement position of the metal junctions that connect the first chip and the second chip, and a desired number of the metal junctions to be arranged. SUMMARY

[0005] The present disclosure aims to provide a photoelectric conversion device having improved characteristics.

[0006] According to an aspect of the present disclosure, there is provided a photoelectric conversion device including: a first chip including a first semiconductor element layer, the first semiconductor element layer including a plurality of pixel circuits; and a second chip including a second semiconductor element layer, wherein the first chip and the second chip are joined by a plurality of metal junctions between the first semiconductor element layer and the second semiconductor element layer, wherein the plurality of pixel circuits includes a first pixel block including n pixel circuits and a second pixel block including the same number of pixel circuits as the first pixel block, n being an integer greater than or equal to 3, wherein the plurality of metal junctions includes first metal junctions that connect the first semiconductor element layer and the second semiconductor element layer, and wherein an arrangement pattern of the first metal junctions in the first pixel block, which are arranged at positions overlapping the first pixel block in a plan view, is different from an arrangement pattern of the first metal junctions in the second pixel block, which are arranged at positions overlapping the second pixel block in a plan view.

[0007] According to another aspect of the present disclosure, there is provided a semiconductor device including: a first chip including a first semiconductor element layer; and a second chip including a second semiconductor element layer, wherein the first chip and the second chip are joined by a plurality of metal junctions between the first semiconductor element layer and the second semiconductor element layer, wherein the plurality of metal junctions include a first metal junction connecting the first semiconductor element layer and the second semiconductor element layer, wherein a first block overlaps o metal junctions of the plurality of metal junctions in a plan view, o being an integer greater than or equal to 3, and a second block has the same area as the first block in the plan view and overlaps the same number of metal junctions as the metal junctions arranged in the first block, and wherein an arrangement pattern of the first metal junction arranged at a position overlapping the first block in the plan view is different from an arrangement pattern of the first metal junction arranged at a position overlapping the second block in the plan view.

[0008] Other features of the present application will become apparent from the following description of example embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-sectional schematic view of a photoelectric conversion device according to a first example embodiment.

[0010] Figure 2A , Figure 2B and Figure 2C are plan schematic views of a photoelectric conversion device according to the first example embodiment.

[0011] Figure 3 is an equivalent circuit diagram of a pixel of a photoelectric conversion device according to the first example embodiment.

[0012] Figure 4A and Figure 4B are arrangement diagrams of metal junctions of a pixel portion of a photoelectric conversion device according to a comparative example.

[0013] Figure 5A , Figure 5B and Figure 5C are schematic diagrams showing connection relationships between members of a photoelectric conversion device according to the first example embodiment.

[0014] Figure 6A and Figure 6B are arrangement diagrams of metal junctions of a pixel portion of a photoelectric conversion device according to a second example embodiment.

[0015] Figure 7is a layout of metal junctions of a pixel section of a photoelectric conversion device according to a third example embodiment.

[0016] Figure 8A and Figure 8B is a schematic view of heat distribution of a photoelectric conversion device according to a fourth example embodiment.

[0017] Figure 9 is a layout of metal junctions of a pixel section of a photoelectric conversion device according to a fourth example embodiment.

[0018] Figure 10 is a layout of metal junctions of a photoelectric conversion device according to a fourth example embodiment.

[0019] Figure 11 is a layout of pads and metal junctions of a photoelectric conversion device according to a fifth example embodiment.

[0020] Figure 12A , Figure 12B and Figure 12C each show a configuration example of a connection region of a photoelectric conversion device according to a fifth example embodiment.

[0021] Figure 13A and Figure 13B are schematic views showing a connection relationship between members of a photoelectric conversion device according to a fifth example embodiment.

[0022] Figure 14 is a layout of metal junctions of a photoelectric conversion device according to a sixth example embodiment.

[0023] Figure 15 is a block diagram of a photoelectric conversion system according to a seventh example embodiment.

[0024] Figure 16A and Figure 16B are conceptual views of a photoelectric conversion system and a movable body according to an eighth example embodiment. DETAILED DESCRIPTION

[0025] The following example embodiments serve to realize the technical idea of the present disclosure and are not intended to limit the present disclosure. In order to make the description clear, the size and positional relationship of the members shown in the drawings are sometimes exaggerated. In the following description, the same parts are assigned the same reference numerals, and redundant description will sometimes be omitted.

[0026] In the description of each of the example embodiments, the main surface of each semiconductor element layer refers to the surface (front surface) on which a transistor is formed. In addition, the back surface refers to the surface opposite the main surface. The upward direction corresponds to the direction from the front surface of the semiconductor element layer 101 toward the back surface, and the downward direction and the depth direction correspond to the direction from the back surface of the semiconductor element layer 101 toward the front surface.

[0027] A description will be given below of the case where the signal carrier is an electron, but the signal carrier can be a hole. In this case, all of the polarities and the conductivity types are reversed.

[0028] Reference will be made to Figures 1 to 5C A photoelectric conversion device according to a first example embodiment of the present disclosure will be described. Figure 1 is a cross-sectional schematic view of a photoelectric conversion device according to each of the example embodiments. The photoelectric conversion device is, for example, a semiconductor device that can be used as an image sensor, an exposure sensor, or a distance measuring sensor. A description will be given below of the case where an image sensor is used as the photoelectric conversion device.

[0029] As Figure 1 indicated, the photoelectric conversion device is a stack of a chip 308 and a chip 309. The chip 308 includes a semiconductor element layer 101 and a wiring structure 190. In the present specification, the "semiconductor element layer" includes not only a semiconductor layer but also a gate of a transistor formed between semiconductor layers. The wiring layers and the contact plugs of the wiring structure are not included in the "semiconductor element layer". The chip 309 includes a semiconductor element layer 130 and a wiring structure 191. The chip 308 and the chip 309 are stacked in such a manner that the wiring structure 190 of the chip 308 and the wiring structure 191 of the chip 309 are located between the semiconductor element layer 101 and the semiconductor element layer 130. In the present specification, a chip naturally includes a chip in a state separated from a wafer as Figure 1 indicated, and also includes a chip in a state of a wafer and to be separated in the future.

[0030] Figure 1 The photoelectric conversion device indicated is a so-called back-illuminated photoelectric conversion device in which light is incident from the back surface 103 side of the semiconductor element layer 101, and a photoelectric conversion element receives light.

[0031] The chip 308 and the chip 309 are joined by a metal junction MB formed by joining a wiring of a wiring layer located at the lowermost layer of the wiring structure 190 and a wiring of a wiring layer located at the uppermost layer of the wiring structure 191. The metal junction MB has a structure in which a metal forming a wiring layer and a metal forming a wiring layer are directly joined. It can also be said that the bottom surface of the wiring structure 190 and the top surface of the wiring structure 191 are joined at a junction surface X. In other words, the chip 308 and the chip 309 are joined at the junction surface X. The junction surface X is constituted by the bottom surface of the wiring structure 190 and the top surface of the wiring structure 191. A connection member such as a micro-junction can be used between the wiring of the wiring layer 114 and the wiring of the wiring layer 113.

[0032] In Figure 1 , the metal junction MB is formed by joining the wiring of the wiring layer 114 of the wiring structure 190 and the wiring of the wiring layer 143 of the wiring structure 191. Hereinafter, a portion of the metal junction MB included in the chip 308 (i.e., a portion constituting a portion of the wiring layer 114) will be sometimes referred to as a portion MBxA. In a similar manner, a portion of the metal junction MB included in the chip 309 (i.e., a portion constituting a portion of the wiring layer 143) will be sometimes referred to as a portion MBxB. A main component of the metal junction is, for example, desired to be copper. The main component being copper means that the ratio of copper to all components is greater than 90%.

[0033] As Figure 1 indicated, the photoelectric conversion device according to the present exemplary embodiment includes a plurality of types of metal junctions MB. For example, the photoelectric conversion device includes a metal junction MB1 connecting the semiconductor element layer 101 and the semiconductor element layer 130, and a metal junction MB not connected to at least one of the semiconductor element layer 101 and the semiconductor element layer 130. Examples of the latter metal junction MB include a metal junction MB2, a metal junction MB3, a metal junction MB4, and a metal junction MB5, which will be described below.

[0034] The metal junction MB2 is a metal junction that is connected to a wiring located at an upper layer of the metal junction MB2 and a wiring located at a lower layer of the metal junction MB2, and is not connected to at least one semiconductor element layer. On one hand, the metal junction MB2 is a metal junction that includes a via plug connected to a top surface and a bottom surface, and is not connected to at least one semiconductor element layer. On the other hand, the metal junction MB2 is a metal junction that includes a protrusion provided at a top surface and a bottom surface, and is not connected to at least one semiconductor element layer. In the present specification, the "via plug" can be a member formed separately from a wiring layer, or can be a member integrally formed using a dual damascene method.

[0035] The metal bonding part MB3 is a metal bonding part connected to a wiring located in the layer below the metal bonding part MB3 and having a top surface that contacts the interlayer insulating material. On one hand, the metal bonding part MB3 is a metal bonding part including a via plug connected to the bottom surface and having a top surface that contacts the interlayer insulating material. On the other hand, the metal bonding part MB3 is a metal bonding part having a bottom surface formed with a protrusion and having a top surface that is not formed with a protrusion.

[0036] The metal bonding part MB4 is a metal bonding part connected to a wiring located in the layer above the metal bonding part MB4 and having a bottom surface that contacts the interlayer insulating material. On one hand, the metal bonding part MB4 is a metal bonding part including a via plug connected to the top surface and having a bottom surface that contacts the interlayer insulating material. On the other hand, the metal bonding part MB4 is a metal bonding part having a top surface formed with a protrusion and having a bottom surface that is not formed with a protrusion.

[0037] The metal bonding part MB5 is a metal bonding part not connected to a wiring located in the layer above the metal bonding part MB5 and a wiring located in the layer below the metal bonding part MB5. On one hand, the metal bonding part MB5 is a metal bonding part having a top surface and a bottom surface that are not connected to a via plug. On the other hand, the metal bonding part MB5 is a metal bonding part having a top surface and a bottom surface that contact the interlayer insulating material.

[0038] In the Figure 1 , all types of metal bonding parts corresponding to the metal bonding parts MB2 to MB5 are included, but it is enough to include at least any one of the types of the metal bonding parts MB2 to MB5 and the metal bonding part MB1. In addition, in the Figure 1 , the metal bonding part MB2, the metal bonding part MB3, and the metal bonding part MB4 are not connected to both the semiconductor element layer 101 and the semiconductor element layer 130, but can also have a configuration connected to either one of the semiconductor element layer 101 and the semiconductor element layer 130 without being connected to the other.

[0039] Details of the configuration of the chip 308 and the configuration of the chip 309 will be described with reference to Figures 1 to 3 . Figure 2A is a plan view of the chip 308. Figure 2B is a plan view of the chip 309. Figure 2C is a plan view of each of the metal bonding parts MB on the bonding surface X. For the sake of convenience in explanation, Figure 2A and Figure 2B A part of the wiring layer, the contact plug, and the via plug is not shown. In addition, in Figure 2A and Figure 2BIn the plan view, the metal junction MB1 is shown in an arrangement relationship that does not physically overlap with each component such as the pixel region 400 and the timing control circuit 500. In fact, as shown in the arrangement of the pixel region 400 and the timing control circuit 500 in Figure 1 the metal junction MB1 can be arranged directly above or directly below the components via a plurality of wiring layers. Further, as shown in Figure 1 and Figures 2A to 2C the metal junction of the signal between the members is arranged at a common position between the members. In Figure 2A and Figure 2B the components arranged in the peripheral region portion are arranged vertically symmetrically. For the sake of simplifying the drawing, the reference numerals of the components and the metal junction MB arranged vertically symmetrically are partially omitted. In this specification, the "planar" refers to a plane parallel to the junction surface X between the chip 308 and the chip 309. In addition, the "plan view" refers to a view observed from a direction perpendicular to the junction surface X.

[0040] First, the chip 308 will be described.

[0041] The semiconductor layer of the semiconductor element layer 101 is, for example, a silicon semiconductor substrate. The semiconductor element layer 101 includes the pixel region 400 in which pixel circuits of a plurality of pixels 600 are arranged in a two-dimensional array in a plan view. The pixel 600 converts a light signal into an electric signal and outputs the converted signal. The pixel 600 can be indicated as a minimum unit of a circuit arranged in a cycle to form an image. In addition, the pixel circuit included in the pixel 600 and arranged in the semiconductor element layer 101 only needs to include at least a photoelectric conversion element 603. The photoelectric conversion element 603 is an element that generates electrons and holes by photoelectric conversion. For example, a photodiode can be used as the photoelectric conversion element 603. The pixel circuit can include components other than the photoelectric conversion element. For example, the pixel circuit can also include at least any one of a transfer transistor, a floating diffusion (FD), a reset transistor, an amplification transistor, a capacity increasing transistor, and a selection transistor. Typically, the pixel 600 includes a selection transistor and a set of elements connected to a signal line via the selection transistor. In other words, the selection transistor can be an outer edge of the pixel circuit. Alternatively, the amplification transistor can be an outer edge of the pixel circuit. Alternatively, the pixel 600 can include a set of the photoelectric conversion element and the transfer transistor. Alternatively, the pixel 600 can include one or a plurality of photoelectric conversion elements, and a set of one amplification circuit or one AD conversion circuit. The following will describe the case where: Figure 3The illustrated amplification transistor 608 functions as an outer fringe disposed in the pixel circuit in the semiconductor element layer 101. Part of the components of the pixel 600 can be disposed in the semiconductor element layer 101, and the other part of the components can be disposed in the semiconductor element layer 130. In this case, the components of the pixel circuit of the pixel 600 disposed in the semiconductor element layer 101 can include the photoelectric conversion element 603.

[0042] Figure 3 The illustrated pixel circuit includes a power supply line 601, a ground line 602, a photoelectric conversion element 603, a reset transistor 604, a transfer transistor 606, an amplification transistor 608, and an output line 609. The reset transistor 604 and the transfer transistor 606 are controlled by a reset control line 605 and a transfer control line 607, respectively. The output line 609 is an output line shared by a plurality of pixels 600, and is connected to the wiring 403. The wirings 402 and 407 for controlling reset and transfer, and the wiring 406 for supplying a power supply voltage are connected to the pixel region 400. The pixel circuit of the pixel 600 is disposed in the semiconductor element layer 101 as Figure 1 illustrated. Figure 1 The photoelectric conversion element 603, the transfer transistor 606, and the amplification transistor 608 are illustrated, and the reset transistor 604 is not illustrated.

[0043] As Figure 1 illustrated, the semiconductor element layer 101 includes an n-type semiconductor region 115 forming the photoelectric conversion element 603, an n-type semiconductor region 116 functioning as a drain of the transfer transistor 606, and an element isolation structure 120. The transfer transistor 606 includes the n-type semiconductor region 115, the n-type semiconductor region 116, and the gate electrode 108. The charge accumulated in the n-type semiconductor region 115 is transferred to the n-type semiconductor region 116 through the gate electrode 108. The potential based on the charge transferred to the n-type semiconductor region 116 is connected to the gate electrode 118 of the amplification transistor 608 via the contact plug 109, the wiring of the wiring layer 110, the via plug 111, and the wiring of the wiring layer 112. The n-type semiconductor region 117 forming the source / drain region of the amplification transistor 608 is disposed in the well 119. The source of the amplification transistor 608 is connected to Figure 3 the illustrated power supply line 601, and the drain is connected to Figure 3 the illustrated output line 609. The drain of the amplification transistor 608 is connected to the signal processing circuit 410 via the contact plug, the wiring of the wiring layer 110, the via plug, and the wiring of the wiring layer 112.

[0044] Figure 1An N-type transistor 200, which is a part of the signal processing circuit 410, is shown. The N-type transistor 200 includes a well 121, an n-type semiconductor region 123 that forms a source / drain region of the N-type transistor, and a gate electrode 122. In the present exemplary embodiment, a reference potential is connected to the gate electrode 122 of the N-type transistor 200, and a source electrode is connected to a ground line 602. A drain electrode is connected to a drain electrode of an amplification transistor 608 via a contact plug 109, a wiring pattern of a wiring layer 110, a via plug, and a wiring pattern of a wiring layer 112. In this example, a source follower circuit is constituted by the amplification transistor 608 and the N-type transistor 200 of the signal processing circuit 410.

[0045] The photoelectric conversion element can be a pinned photodiode that further includes a p-type semiconductor region, or can be a photogate, and can be appropriately changed.

[0046] The signal processing circuit 410 further includes an inverting circuit that includes an N-type transistor 205 and a P-type transistor 206. The inverting circuit outputs a pixel signal converted into a digital signal to a signal processing control circuit 503 of the chip 309 via a metal bond MB1-3. The metal bond MB1-3 is connected to gate electrodes 151 and 154 of the inverting circuit including the N-type transistor 203 and the P-type transistor 204 via a via plug, a wiring of a wiring layer 141, a via plug, and a wiring of a wiring layer. The N-type transistor 205 includes a well 156, an n-type semiconductor region 158 that forms a source / drain region of the N-type transistor, and a gate electrode 157. The P-type transistor 206 includes a well 159, a p-type semiconductor region 161 that forms a source / drain region of the P-type transistor, and a gate electrode 160. A source of the N-type transistor 205 is connected to a ground potential, and a drain is connected to a contact plug, a wiring of a wiring layer 110, a via plug, and a wiring of a wiring layer 112. On the other hand, a source of the P-type transistor 206 is connected to a power supply potential, and a drain is connected to a contact plug, a wiring of a wiring layer 110, a via plug, and a wiring of a wiring layer 112. In the present exemplary embodiment, the drains of the N-type transistor 205 and the P-type transistor 206 are connected by a wiring pattern of the wiring layer 112, and form the inverting circuit. The wiring of the wiring layer 112 to which the drains of the N-type transistor 205 and the P-type transistor 206 are connected is further connected to a wiring of a wiring layer 143 via a via plug and a wiring of a wiring layer 114. As described above, the metal bond MB is formed by bonding each wiring of the wiring layers 114 and 143.

[0047] The wiring of the wiring layer 114 is connected to the gate electrode 108 of the transfer transistor 606 via a via plug, the wiring of the wiring layer 112, a via plug, the wiring of the wiring layer 110, and a contact plug. In the pixel 600 of the chip 308, the charge transport operation is controlled by the timing control circuit 500 of the chip 309. The connection relationship of these components corresponds to Figure 2A the wiring 407 and the metal bonding parts MB1A-8 in Figure 2B the metal bonding parts MB1B-8 and the wiring 509 in

[0048] In the pad portion 312, a pad wiring 313 for connection with an external terminal and an opening 100 for exposing a part of the pad wiring 313 are arranged. In Figure 1 the pad wiring 313 is connected to the wiring 700 of the wiring layer 112 via a metal bonding part MB2 and a via plug connected to the top surface and the bottom surface of the metal bonding part MB2. The wiring 700 is, for example, a power supply line, and supplies power to components arranged on the chip 308. In Figure 1 the pad wiring 313 and the wiring 700 are connected by a plurality of metal bonding parts MB2. This can reduce the parasitic resistance of the metal bonding part MB2. In Figure 1 the pad wiring 313 is arranged in the wiring layer 141 of the chip 309, but the arrangement position is not limited thereto. For example, the pad wiring 313 can be arranged in any wiring layer of the wiring structure 190, or the pad wiring 313 can be arranged in an upper layer of the semiconductor element layer 101.

[0049] The wiring structure 190 includes M (M is an integer greater than or equal to 1) wiring layers, interlayer insulating materials, and contact plugs connecting the wiring layers and the semiconductor element layer 101. The wiring layer of a certain layer and the wiring layer of a different height can be connected via a via plug. The number of interlayer insulating layers included in the wiring structure 190, the number of wiring layers, the number of via plugs, and the number of contact plugs can be arbitrarily set. In Figure 1 the wiring structure 190 includes three wiring layers 110, 112, and 114, and interlayer insulating materials 104 to 107 arranged between the wiring layers and between the wiring patterns included in the wiring layers. The wiring structure 190 further includes via plugs 111 and 113 connecting the wiring layers, and a contact plug 109 connecting the wiring layer 110 and the semiconductor element layer 101.

[0050] On the back surface 103 side of the semiconductor element layer 101, in a region overlapping with the pixel region 400 in a plan view, a planarization layer 124, a color filter layer 125 including a plurality of color filters, a planarization layer 126, and a microlens layer 127 including a plurality of microlenses are arranged in this order. Figure 1A single pixel 600 is shown. In reality, multiple pixels 600 are arranged. Furthermore, each of the multiple color filters and each of the multiple microlenses can be arranged to correspond to a photoelectric conversion element. A microlens and a color filter can be configured for multiple photoelectric conversion elements.

[0051] Next, chip 309 will be described. The following will mainly provide... Figure 1 The description of the construction of the chip 309 shown below, and will refer to the following Figure 2B describe Figure 1 Components not shown in the diagram.

[0052] The semiconductor layer 130 is, for example, a silicon semiconductor substrate. The semiconductor element layer 130 includes circuitry. For example, the circuitry is configured as follows: Figure 2B The transistors in the vertical scanning circuit 501, horizontal scanning circuit 502, signal processing control circuit 503, clock generation circuit 504, and timing control circuit 500 shown are all considered. The timing control circuit 500 is a circuit that controls the driving of at least any one of the transistors in the pixel circuit.

[0053] exist Figure 1 In the example shown, a portion of the timing control circuit 500 and a portion of the signal processing control circuit 503 are arranged on the chip 309.

[0054] The timing control circuit 500 is the circuit that controls the entire photoelectric conversion device. Figure 1 An inverting circuit including an N-type transistor 201 and a P-type transistor 202 is shown as part of a timing control circuit 500. An n-type semiconductor region 145, forming the source / drain region of the N-type transistor 201, is formed in a well 144. The N-type transistor 201 includes a gate electrode 137 and the n-type semiconductor region 145 forming the source / drain region. A p-type semiconductor region 148, forming the source / drain region of the P-type transistor 202, is formed in a well 146. The P-type transistor 202 includes a gate electrode 147 and the p-type semiconductor region 148 forming the source / drain region. The source of the N-type transistor 201 is connected to ground potential, and its drain is connected to the contact plug, the wiring of wiring layer 139, the via plug, and the wiring of wiring layer 141. Conversely, the source of the P-type transistor 202 is connected to a power supply potential, and its drain is connected to the contact plug, the wiring of wiring layer 139, the via plug, and the wiring of wiring layer 141. The drain electrodes of N-type transistor 201 and P-type transistor 202 are connected to the wiring of wiring layer 141, which is also connected to the wiring of wiring layer 114 of chip 308 via vias of wiring layer 142 and wiring of wiring layer 143.

[0055] In this example, the N-type transistor 203 and the P-type transistor 204 are arranged as part circuits of the signal processing control circuit 503. The n-type semiconductor region 152 forming the source / drain region of the N-type transistor 203 is formed in the well 150. The N-type transistor 203 includes the gate electrode 151 and the n-type semiconductor region 152 forming the source / drain region. The p-type semiconductor region 155 forming the source / drain region of the P-type transistor 204 is formed in the well 153. The P-type transistor 204 includes the gate electrode 154 and the p-type semiconductor region 155 forming the source / drain region. The source electrode of the N-type transistor 203 is connected to the ground potential, and the drain electrode is connected to a wiring of the wiring layer 139 via a contact of the contact layer 138. The source electrode of the P-type transistor 204 is connected to the power supply potential, and the drain electrode is connected to a wiring of the wiring layer 139 via a contact of the contact layer 138. In this example embodiment, the drain electrodes of the N-type transistor 203 and the P-type transistor 204 are connected by a wiring of the wiring layer 139.

[0056] The wiring structure 191 includes N (N is an integer greater than or equal to 1) wiring layers, interlayer insulating materials, and contact plugs connecting the semiconductor element layer 130 and the wiring layers. Two wiring layers can be connected via a via plug. The number of interlayer insulating films included in the wiring structure 191, the number of wiring layers, the number of contacts, and the number of via plugs can be arbitrarily set. In Figure 1 In this example, the wiring structure 191 includes three wiring layers 140, 142, and 143, and the interlayer insulating materials 133 to 136 arranged between the wiring layers and between the wiring patterns included in the wiring layers. The wiring structure 191 further includes a via plug connecting the wiring layers 141 and 142 of different heights, and a contact plug connecting a wiring pattern of the wiring layer 140 and the semiconductor element layer 130.

[0057] In Figure 2A In this example, for example, a circuit that transmits a signal for driving a photoelectric conversion element arranged in the pixel region 400 is arranged in the peripheral region. More specifically, the pixel control circuit 401, the signal processing circuit 410, the signal generation circuits 412 and 423, and the output unit 420 are arranged in the peripheral region. For example, the circuit is any one of the transistors constituting the pixel control circuit 401, the signal processing circuit 410, the signal generation circuits 412 and 423, and the output unit 420.

[0058] The wirings 406 and 407 are connected to the chip 309 via the metal bonds MB1A-7 and MB1A-8, and are supplied with power and a driving signal. In Figure 2A and Figure 2BIn the present example, the wirings 406 and 407 and the metal bonds MB1A-7 and MB1A-8 are each shown as a single component. In reality, a plurality of wirings and a plurality of metal bonds MB1 are arranged as a plurality of power supply lines, a plurality of ground lines, and a plurality of control lines. In addition, even if the same power supply and the same signal are provided, in order to reduce the resistance of the wirings and the metal bonds MB1, a plurality of wirings and a plurality of metal bonds MB1 are sometimes arranged. In the following description, even if a plurality of wirings and a plurality of metal bonds MB1 are expected to be arranged, in order to simplify the drawing and the description, the input-output signals transmitted via the wirings and the metal bonds MB1 will be omitted.

[0059] The pixel control circuit 401 controls the photoelectric conversion, transfer, and reset of the photoelectric conversion elements included in the pixel region 400 and the selection of the row from which the pixel signal is to be output via the wiring 402. For example, the pixel control circuit 401 receives power and a ground potential from the chip 309 via the metal bond MB1A-9 and the wiring 404. Since the power and the ground potential have different potentials, the power and the ground potential are actually provided from two different metal bonds and wirings (not shown in the above drawing). In addition, a control signal is provided from the chip 309 via the metal bond MB1A-10 and the wiring 405.

[0060] The signal output from the pixel region 400 is input to the signal processing circuit 410 via the wiring 403. The signal processing circuit 410 includes a constant current circuit, for example, forms a source follower circuit by connecting to the amplification transistor 608 of the pixel 600 via the output line 609, and amplifies the pixel signal. In addition, the signal processing circuit 410 can be configured to convert the pixel signal, which is an analog signal, to a digital signal by performing analog / digital conversion (A / D conversion) on the output from the source follower circuit. As other functions, the signal processing circuit 410 can have a function of further amplifying the output of the source follower circuit, a correlated double sampling (CDS) function, and a function of sampling and holding (S / H) the pixel signal. In addition, the signal processing circuit 410 can include a digital memory that stores the A / D conversion result, and a scanning unit for reading out the digital data stored in the digital memory. As an example, the signal processing circuit 410 according to the present example embodiment is configured to convert the pixel signal to a digital signal, store the digital data of one pixel as a multi-bit digital signal to the digital memory, and simultaneously output the digital data of one pixel. The signal processing circuit 410 receives power and a ground potential from the chip 309 via the metal bond MB1A-2 and the wiring 411. In addition, a control signal is provided from the chip 309 via the metal bond MB1A-1 and the wiring 406. The pixel signal processed by the signal processing circuit 410 is output to the chip 309 via the wiring 417 and the metal bond MB1A-3.

[0061] The signal generation circuit 412 is a circuit that generates various signals to be supplied to the signal processing circuit 410. For example, the signal generation circuit 412 generates a drive clock and a reference voltage to be used in an A / D conversion operation of the signal processing circuit 410, and supplies the generated drive clock and reference voltage to the signal processing circuit 410 via the wiring 413. A power supply voltage and a ground voltage are supplied from the chip 309 to the signal generation circuit 412 via the metal bump MB1A-2 and the wiring 411. In Figure 2A , the same power supply voltage and ground voltage as the signal processing circuit 410 are supplied. Actually, different power supply voltages and different ground voltages can be supplied. Further, a control signal is supplied from the chip 309 to the signal generation circuit 412 via the metal bump MB1A-1, the wiring 415, the metal bump MB1A-11, and the wiring 414.

[0062] The output unit 420 has a function of outputting a pixel signal processed by the chip 309 to the outside of the photoelectric conversion device. For example, the output unit 420 has an output function of a method of outputting a voltage from a single terminal such as a buffer circuit, or an output function of a low voltage differential signal (LVDS) method having two terminals of a difference. Further, if the pixel signal is a digital signal as in the present exemplary embodiment, the output unit 420 can have, for example, a parallel-to-serial conversion (P / S conversion) function. A power supply voltage and a ground voltage are supplied from the chip 309 to the output unit 420 via the metal bump MB1A-5 and the wiring 422.

[0063] The signal generation circuit 423 is a circuit that generates various signals to be supplied to the output unit 420. For example, the signal generation circuit 423 generates a reference voltage and a clock for driving P / S conversion or LVDS, and supplies the generated reference voltage and clock to the output unit 420 via the wiring 424. Like the output unit 420, a power supply voltage and a ground voltage are supplied to the signal generation circuit 423 via the metal bump MB1A-5 and the wiring 422.

[0064] Next, the configuration of the chip 309 will be described with reference to Figure 2B , as well as the description of Figure 2B . Like the description of Figure 2AThe power supply voltage, the ground voltage, and the control signal are actually supplied from a plurality of wiring and metal junctions, which are omitted in the drawings and the description. A circuit that generates a control signal for driving the components of the chip 308 and a circuit that processes a signal from the photoelectric conversion element of the chip 308 are arranged on the chip 309. Further, a plurality of pad wiring 313 that supplies a potential from the outside of the photoelectric conversion device is arranged on the chip 309. Examples of the method of supplying a potential from the outside of the photoelectric conversion device include a method of supplying a potential to the pad wiring 313 via wire bonding, and a method of forming an embedded metal and supplying a potential using a bump. A description will be given below of a case using wire bonding as an example.

[0065] For wire bonding, the chip 308 needs to be perforated at a position corresponding to the arrangement position of the pad wiring 313 of the chip 309. Figure 2A A plurality of openings 100 are shown for clarifying the positional relationship of the pad wiring 313 arranged on the chip 309. More specifically, Figure 2A The shown openings 100A-1 to 100A-13 are opening portions of the pad wiring 313B-1 to 313B-13 of the chip 309. Specifically, the opening 100A-1 corresponds to the pad wiring 313B-1, the opening 100A-2 corresponds to the pad wiring 313B-2, and the remaining openings similarly correspond to the remaining pad wirings.

[0066] The power supply voltage, the ground voltage, and the control signal from the outside of the photoelectric conversion device are supplied from the pad wiring 313B-9 to the timing control circuit 500 via the wiring 508. The control signal from the outside of the photoelectric conversion device is, for example, a control signal for serial communication from an external controller (not shown). A protection circuit is connected in parallel or in series to at least a part or desirably all of the pad wiring 313B. This can reduce electrical damage to the pad wiring 313B during wire bonding or a manufacturing process.

[0067] Further, the control signal is supplied to the chip 308 via the wiring 509 and the metal junction MB1B-8. Further, in the present exemplary embodiment, the drive of a part of the pixel region 400 is controlled via the metal junction MB1A-8 of the chip 308 and the wiring 407.

[0068] The power supply voltage, the ground voltage, and the control signal are supplied from the pad wiring 313B-12 and the wiring 510 to the vertical scanning circuit 501, which drives the pixel control circuit 401 of the chip 308 via the wiring 511 and the metal junction MB1B-10. The control of the pixel region 400, such as photoelectric conversion, transfer, reset, and selection of a row from which a pixel signal is to be output, is performed by the vertical scanning circuit 501.

[0069] A power supply voltage, a ground voltage, and a control signal are supplied from the pad wiring 313B-1 and the wiring 512 to the horizontal scanning circuit 502 and the clock generation circuit 504. The horizontal scanning circuit 502 drives the signal processing circuit 410 and the signal generation circuit 412 of the chip 308 via the wiring 513 and the metal bonding portion MB1B-1. The clock generation circuit 504 is, for example, a phase-locked loop (PLL) circuit, and is controlled in linkage with the horizontal scanning circuit 502 via the wiring 517. A control signal and a clock generated by the clock generation circuit 504 are supplied to the signal generation circuit 412 via the wiring 518 and the metal bonding portion MB1B-11.

[0070] A power supply voltage, a ground voltage, and a control signal are supplied from the pad wiring 313B-4, the wiring 514, the pad wiring 313B-5, and the wiring 515 to the signal processing control circuit 503. In the present exemplary embodiment, different power supply voltages are supplied to the signal processing control circuit 503, and the pad wiring 313 is explicitly separated. A multi-bit pixel signal converted from an analog signal to a digital signal by the signal processing circuit 410 of the chip 308 is input to the signal processing control circuit 503 via the wiring 417, the metal bonding portion MB1A-3, the metal bonding portion MB1B-3, and the wiring 516. The input pixel signal is subjected to various types of digital signal processing, such as addition or subtraction of digital gain or offset, compression processing, and data scrambling processing. The pixel signal subjected to the digital signal processing is input to the output unit 420 of the chip 308 via the wiring 517, the metal bonding portion MB1B-4, the metal bonding portion MB1A-4, and the wiring 421. Further, the signal processing control circuit 503 also supplies a signal in synchronization with the digital signal processing of the pixel signal to the signal generation circuit 423 of the chip 308 via the wiring 517, the metal bonding portion MB1B-4, the metal bonding portion MB1A-4, and the wiring 421. In the present exemplary embodiment, the signal processing control circuit 503 is driven by different power supplies depending on the signal processing circuit 410 and the output unit 420 having different power supplies. The output of the output unit 420 is output to the outside of the photoelectric conversion device from the pad wiring 313B-7 via the wiring 425, the metal bonding portion MB1A-6, the metal bonding portion MB1B-6, and the wiring 531.

[0071] Figure 2C A plan view of the bonding surface X is shown. In addition, the position of the pixel region 400 is indicated by a broken line. In Figure 2C In the present exemplary embodiment, in order to maintain in-plane uniformity of the bonding surface, the pattern of the metal bonding portion is arranged substantially uniformly over the entire surface. As described with reference to Figure 1The metal bonding portion connected to the semiconductor element layer 101 and the semiconductor element layer 130 is indicated as a metal bonding portion MB1. In addition, the metal bonding portion not connected to the wiring located in the upper layer of the metal bonding portion MB5 and the wiring located in the lower layer of the metal bonding portion MB5 is indicated as a metal bonding portion MB5. In Figure 2C , at least any one of the metal bonding portions MB2 to MB4 can be used instead of the metal bonding portion MB5. It is not necessary to arrange the metal bonding portions MB2 to MB5, and only the metal bonding portion MB1 can be arranged.

[0072] In Figure 2A , the pixel region 400 has a configuration driven from the left and right via the wirings 402 and 407. The configuration is not limited to this. By connecting a control signal, it is possible to control Figure 2C The metal bonding portion MB5 located directly below the pixel region 400 shown in the drawing can be replaced with the metal bonding portion MB1, and it is possible to control the pixel region 400. The pixel region 400 has a configuration in which pixel blocks each including n (n is an integer greater than or equal to 3) pixels 600 are two-dimensionally arranged. It is desirable that each pixel block include m columns x l rows (m is an integer greater than or equal to 2, and l is an integer greater than or equal to 2) of pixels. The pixel block includes n adjacent pixels 600. The first pixel block and the second pixel block include different pixels. For example, the pixel blocks are divided by control of the drive timing. For example, it is possible to control the accumulation period of the signal charge of the first pixel block to be a first period, and it is possible to control the accumulation period of the signal charge of the second pixel block to be a second period different from the first period. With this configuration, it is possible to control the accumulation time most suitable for each of the pixel blocks in each of the two-dimensionally arranged pixel block regions according to the brightness of the subject, and it is possible to expand the dynamic range of the captured image. Hereinafter, an example of controlling the pixel blocks by the drive timing will be described in detail, but the control configuration is not limited to this configuration. Even if the drive timing is the same, it is possible to select pixels in an arbitrary range, and it is possible to divide a plurality of selected pixels into one block. For example, the first pixel block can include n pixel circuits, and the second pixel block can include the same number of pixel circuits as the first pixel block. Even in this case, there is room for improvement in the characteristics of the photoelectric conversion device.

[0073] Next, the connection relationship between the pixels 600 arranged in the pixel region 400 of the chip 308 and the components arranged on the chip 309 will be described.

[0074] First, the connection relationship between the pixels 600 in the pixel region 400 of the chip 308 and a part of the timing control circuit 500 of the chip 309 according to the comparative example will be described with reference to Figure 4A and Figure 4B After that, the connection relationship between the pixels 600 in the pixel region 400 of the chip 308 and the timing control circuit 500 of the chip 309 according to the embodiment will be described with reference to Figure 5A and Figure 5BThe connection relationship between the chip 308 and the chip 309 according to the present exemplary embodiment will be described.

[0075] Figure 4A The chip 308 shown in FIG. 4A includes a pixel block 430 including pixels 600 binned by three rows and three columns among the pixel region 400. Figure 4A The connection relationship between the pixel block 430 and a circuit that controls the pixel transfer operation of the timing control circuit 500 is shown. The circuit that controls the pixel transfer operation is an inverter circuit including a power supply line 620, a ground line 621, a P-type transistor 622, and an N-type transistor 623. In the pixel block 430, the pixel 600 is connected to the power supply line 620 and the ground line 621. Figure 4A In the example shown, the pixel block 430 is driven via a common transfer control line 607. The pixel 600 arranged in the semiconductor element layer 101 of the chip 308 and the timing control circuit 500 arranged in the semiconductor element layer 130 of the chip 309 are connected by the metal bonding portion MB1-20. More specifically, the pixel block 430 is controlled by the timing control circuit 500 via the wiring 624, the metal bonding portion MB1-20, and the transfer control line 607. As described with reference to Figure 2C In the example shown, the pixel block 430 is driven via a common transfer control line 607. The pixel 600 arranged in the semiconductor element layer 101 of the chip 308 and the timing control circuit 500 arranged in the semiconductor element layer 130 of the chip 309 are connected by the metal bonding portion MB1-20. More specifically, the pixel block 430 is controlled by the timing control circuit 500 via the wiring 624, the metal bonding portion MB1-20, and the transfer control line 607. As described with reference to Figure 4A In the example shown in FIG. 4B, in order to maintain uniformity of the arrangement of the metal bonding portions, a plurality of metal bonding portions MB5 are arranged. At least any one of the metal bonding portions MB2 to MB4 can be used instead of the metal bonding portion MB5.

[0076] Figure 4B The arrangement relationship between the pixel block 430, the metal bonding portion MB1-20, and the metal bonding portion MB5 is shown. In the pixel region 400, the pixel blocks 430 each including a plurality of pixels 600 are arranged in five rows and six columns, but the configuration is not limited thereto. In each of the pixel blocks 430, a total of nine metal bonding portions MB1 and MB5 are arranged. Among the metal bonding portions, the signal line for controlling the pixel transfer is connected to the metal bonding portion MB1-20. Among the pixels 600 included in the pixel block 430 and arranged in three rows and three columns, the metal bonding portion MB1-20 is arranged at a position overlapping the pixel 600 arranged in the second row and the second column, and the metal bonding portion MB5 is arranged at a position overlapping the other pixel 600. In other words, among the nine metal bonding portions MB arranged at a position overlapping the pixel block 430, the signal line is connected at a rate of 1 / 9.

[0077] Next, the connection relationship between the pixels 600 of the pixel blocks 430 and 432 and the pad wiring 313B-8 arranged on the chip 309 according to the present exemplary embodiment will be described with reference to Figure 5A and Figure 5B Next, the connection relationship between the pixels 600 of the pixel blocks 430 and 432 and the pad wiring 313B-8 arranged on the chip 309 according to the present exemplary embodiment will be described with reference to

[0078] Figure 5Ais a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431.

[0079] Figure 5B is a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431. Figure 5A is a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431. Figure 5B is a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431. Figure 5A is a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431.

[0080] is a view showing the connection relationship between the ground lines 602 of the pixels 600 of the chip 308 and the pad wiring 313B-8 of the chip 309. The chip 308 includes the pixel blocks 430 and 431 that constitute a part of the pixel region 400. The pad wiring 313B-8 arranged on the chip 309 is connected to the ground lines 602 of the pixel blocks 430 and 431 via the wiring 532, the plurality of metal junctions MB1-7, and the plurality of wirings 406. The pixel block 430 is connected to the pad wiring 313B-8 through the metal junction MB1-7 connected by one of the plurality of metal junctions corresponding to the pixel block 430. The pixel block 431 is connected to the pad wiring 313B-8 through the metal junctions MB1-7 connected by five of the plurality of metal junctions corresponding to the pixel block 431. Figure 5BAs shown, the number of metal bonds MB1-7 arranged to correspond to the pixel block 430 is different from the number of metal bonds MB1-7 arranged to correspond to the pixel block 431. In other words, the number of metal bonds MB1 arranged at positions overlapping the pixel block 430 in a plan view is different from the number of metal bonds MB1 arranged at positions overlapping the pixel block 431 in a plan view. More specifically, the pixel blocks differ in that the number of metal bonds MB1 arranged at positions overlapping the pixel block 430 in a plan view is smaller than the number of metal bonds MB1 arranged at positions overlapping the pixel block 431. In addition, the number of metal bonds of the pixel block 431 not connected to at least one of the first semiconductor element layer and the second semiconductor element layer is smaller than the number of metal bonds of the pixel block 430 not connected to at least one of the first semiconductor element layer and the second semiconductor element layer. In this way, the number of metal bonds MB1 varies between the pixel blocks.

[0081] For example, if a plurality of pixel blocks are arranged in the column direction, the pad wiring 313B-8 can be arranged near the pixel blocks in the first row and the pixel blocks in the last row. The wiring 532 has a limited resistance value determined in accordance with the manufacturing process to be used. Therefore, the pixel blocks 430 in the first row and the last row are connected to the wiring 532 and the pad wiring 313B-8 with relatively lower resistance than the pixel blocks 431 located therebetween. In other words, the distance between the pixel blocks 431 and the pad wiring 313B-8 is longer than the distance between the pixel blocks 430 and the pad wiring 313B-8. The "distance" refers to the shortest distance. Furthermore, the metal bonds MB1 also have a limited resistance value. If the number of metal bonds MB1 is large, the resistance becomes low, and if the number of metal bonds MB1 is small, the resistance becomes high. Therefore, the resistance component of the metal bonds MB1-7 between the wiring 532 and 406 of the pixel block 430 is higher than the resistance component of the metal bonds MB1-7 between the wiring 532 and 406 of the pixel block 431.

[0082] If the voltage drop amount of the power supply line or the ground line due to the interconnection resistance varies within the plane of the pixel region 400, it sometimes causes a shadow in the captured image. In the present exemplary embodiment, the number of metal bonds MB is adjusted based on the interconnection resistance component generated in accordance with the arrangement position of the pad wiring 313B-8, and the resistance value from the pad wiring 313B-8 to the pixel block 430 or 431 is adjusted. Thereby, the difference in the resistance value is reduced. With this configuration, the shadow due to the difference in the voltage drop amount of the ground potential between the pixel blocks is prevented.

[0083] In Figure 5BIn the present example, the arrangement position of the metal bonding portion MB1 is the center of each pixel block, but the connection position is not limited thereto. In addition, among the plurality of pixel blocks, the arrangement position of the metal bonding portion MB1 can be different from one another. In addition, in the present example, the pixel blocks arranged in the first and last rows are the same, but as shown in FIG. 4B, different pixel blocks 432 to 434 can be arranged in each row. Furthermore, different pixel blocks can be arranged in each column, or different pixel blocks can be arranged in each row and each column. Figure 5B In the present example, the pixel blocks arranged in the first and last rows are the same, but as shown in FIG. 4B, different pixel blocks 432 to 434 can be arranged in each row. Furthermore, different pixel blocks can be arranged in each column, or different pixel blocks can be arranged in each row and each column. Figure 5C In the present example, the pixel blocks arranged in the first and last rows are the same, but as shown in FIG. 4B, different pixel blocks 432 to 434 can be arranged in each row. Furthermore, different pixel blocks can be arranged in each column, or different pixel blocks can be arranged in each row and each column.

[0084] The example of forming pixel blocks for each of the transfer operations of the pixel 600 has been described with reference to Figure 5A , Figure 5B and Figure 5C , but the configuration is not limited thereto. For example, the unit of the pixel block can be determined based on the unit of the number of pixels to be subjected to the reset operation, or the unit of the number of pixels to be read. Alternatively, the area or block unit can be determined based on the resistance value of the power supply line or the ground line of the pixel, and the number or density of the metal bonding portions can be adjusted to reduce the resistance difference between the blocks. Furthermore, when the signal line connected at the metal bonding portion is the control line as described with reference to Figure 4A , the number or density of the metal bonding portions within the pixel block can also be changed to adjust the interconnection resistance as a method of reducing the difference in the control waveform between the pixel blocks.

[0085] In addition, the configuration of the photoelectric conversion device such as the components to be arranged on the chip 308 and the chip 309 and the combination of the components is not limited to the configuration described in the present example embodiment. For example, only the pixel region 400 can be arranged on the chip 308, and the signal processing circuit and the control circuit can be arranged on the chip 309. Alternatively, each pixel included in the pixel region can have a configuration including a signal processing function such as an A / D converter.

[0086] In the present example embodiment, in the configuration including a plurality of unit blocks (such as the pixel blocks 430 to 434) in which a plurality of metal bonding portions can be arranged, the resistance value of the metal bonding portion can be adjusted in the pixel block by adjusting the number or density of the metal bonding portion for each pixel block. With such a configuration, the resistance component of the power supply line or the ground line connected to the pixel region 400 can be adjusted for each area of the pixel block, and image degradation such as shading due to the resistance difference between the pixel blocks can be suppressed.

[0087] will be described with reference to Figure 6A and Figure 6BA photoelectric conversion apparatus according to a second exemplary embodiment of the present disclosure is described. The photoelectric conversion apparatus according to the second exemplary embodiment differs from the photoelectric conversion apparatus according to the first exemplary embodiment in that the pixel region 400 includes pixel blocks 435 having effective pixels and pixel blocks 430 having light-shielding pixels, and the number of metal joints MB1-7 varies between pixel blocks 430 and pixel blocks 435. Figures 1 to 5C Similar components of the photoelectric conversion device shown according to the first exemplary embodiment are assigned the same reference numerals, and their descriptions will be omitted or simplified.

[0088] Figure 6A This is a planar schematic diagram showing the arrangement of pixel blocks 430 and 435 and the arrangement of metal joints MB1-7. As an example of the construction of a photoelectric conversion device, optical light-shielding portions are sometimes arranged in a portion of the pixel region 400. For example, this can be achieved by... Figure 1 A light-shielding film is disposed on at least one of the top and bottom surfaces of the planarization layer 124, and the light-shielding film covers a portion of the pixel area 400 to achieve light shielding. Figure 6A In this configuration, the light-shielding portion 800 is positioned at the overlap with the pixel block 430 arranged in the first row of the pixel area 400. The unit of the pixel block can be determined based on the number of rows and columns of the required light-shielding area.

[0089] In some cases, the potential of the light-shielding portion 800 is fixed, so that changes in the light-shielding portion 800 caused by interference noise will not affect the pixel region 400 via parasitic capacitance. For example, by connecting the light-shielding portion 800 to the power line or ground line of the pixel block via a through-hole plug, the potential of the light-shielding portion 800 can be set to the same potential as the power supply potential or ground potential of the pixel 600. With this configuration, the light-shielding portion 800 also serves as a power supply wiring or ground line for the pixel 600. Therefore, the interconnection resistance of the power line or ground line is reduced. In other words, in the area where the pixel block 430 is arranged, the interconnection resistance of the power line or ground line is relatively small compared to the area where the pixel block 435 is arranged. The resistance difference of the power line or ground line can cause output differences or shadow shape differences in the pixel 600. Therefore, by arranging the light-shielding portion 800, output characteristic differences due to the resistance difference of the power line or ground line may sometimes be generated between the light-shielding area and the opening area. When using the pixel output of the light-shielding part 800 for various types of signal processing (such as correction of pixel signals in the aperture), due to the inconsistency between the output characteristics of the aperture area and the light-shielding area where the light-shielding part 800 is arranged, it is sometimes impossible to obtain the signal processing accuracy or the desired signal processing result.

[0090] In the present exemplary embodiment, at least one of the number and density of the metal junctions MB1-7 to which the power supply line or the ground line is connected is changed between the pixel block 430 and the pixel block 435. With this configuration, it is possible to reduce the difference in the interconnection resistance value of the power supply line or the ground line between the light shielding portion 800 and the other opening regions, and to reduce the difference in the dark state output characteristic between the light shielding portion 800 and the opening regions.

[0091] Further, as Figure 2A the pixel control circuit 401 and the signal processing circuit 410 in the pixel region 400 and the components adjacent to the pixel region 400 share the power supply line and the ground line. In this case, similarly to the case where the light shielding portion 800 is arranged as described with reference to Figure 6A the pixel region 400 and the other components, the interconnection resistance of the boundary region between the pixel region 400 and the other components becomes relatively lower than the interconnection resistance of the central region of the pixel region 400. Therefore, sometimes an output difference is generated between the central region and the peripheral region of the pixel region 400. Figure 6B A configuration is shown in which the pixel blocks 435 are arranged in three rows and four columns in the center, and the pixel blocks 430 are arranged in the periphery of the pixel region 400. By employing Figure 6B the configuration shown in FIG. 8, even in the case where the power supply line and the ground line are shared by the pixel region 400 and the peripheral components, it is possible to reduce the difference in the interconnection resistance value of the power supply line and the ground line, and to reduce the output difference between the central region and the peripheral region of the pixel region 400.

[0092] Also in the present exemplary embodiment, similarly to the first exemplary embodiment, the unit of the pixel block is not limited to Figure 6A the configuration shown in FIG. 1. Figure 6B

[0093] Also in the present exemplary embodiment, in a configuration including a plurality of unit blocks (such as the pixel blocks) in which a plurality of metal junctions can be arranged, by adjusting the number or density of the metal junctions for each unit block, it is possible to adjust the resistance value of the metal junctions for each unit block. With this configuration, it is possible to adjust the resistance component of the power supply line or the ground line connected to the pixel region 400 for each region of the unit block, and to suppress image degradation such as shading due to the resistance difference between the regions.

[0094] In addition, in the present exemplary embodiment, the pixel region 400 and the peripheral components share the power supply line and the ground line. Figure 6B ​In the pixel region 400 as well as in other components (such as the signal processing circuit 410) that share the power line and the ground line with the pixel region 400, a resistance distribution of the power line and the ground line is generated in the vicinity of the pixel region 400 and in other regions. In the signal processing circuit 410 as well, the resistance distribution in the signal processing circuit 410 can be adjusted, for example, by adjusting the number or density of the metal junctions of the power line and the ground line for each unit block or region similarly to the pixel blocks. With this configuration, a one-dimensional shading generated in other components such as the signal processing circuit 410 can be suppressed.

[0095] A photoelectric conversion device according to a third exemplary embodiment of the present disclosure will be described with reference to Figure 7 A photoelectric conversion device according to a third exemplary embodiment of the present disclosure will be described with reference to Figures 1 to 6B Components similar to those of the photoelectric conversion devices according to the first and second exemplary embodiments shown in FIGS. 1A and 2A are assigned the same reference numerals, and the description will be omitted or simplified.

[0096] As described in the first and second exemplary embodiments, depending on the resistance distribution of the power line or the ground line in the pixel region 400, the output of the pixel 600 sometimes has an output characteristic based on the resistance distribution. For example, this is one of factors that deteriorate the image quality by horizontal or vertical continuous outputs having an output characteristic with a certain tendency, such as a shading. In particular, a continuously varying output characteristic is likely to be recognized as a shape in a captured image.

[0097] As Figure 7 As shown in FIG. 3A, since the multiple pixel blocks with different numbers and arrangement patterns of the metal junctions MB are randomly arranged, the interconnection resistance distribution of the power line or the ground line does not become a continuous distribution. More specifically, the arrangement pattern of the metal junctions MB1 arranged at a position overlapping the first pixel block in a plan view is different from the arrangement pattern of the metal junctions MB1 arranged at a position overlapping the second pixel block in the plan view. In other words, when the metal junctions MB1 arranged at the position overlapping the first pixel block in the plan view are overlaid with the metal junctions MB1 arranged at the position overlapping the second pixel block in the plan view, the metal junctions MB1 are arranged at different positions. The metal junctions MB1 arranged at the position overlapping the first pixel block in the plan view are overlaid with the metal junctions MB1 arranged at the position overlapping the second pixel block in the plan view means that the metal junctions MB1 are translated and overlaid. Not all of the metal junctions MB1 need to be arranged at different positions, and it is enough that at least one metal junction MB1 is arranged at a different position.

[0098] According to the present exemplary embodiment, an output characteristic due to a distribution of interconnection resistance is less likely to be recognized as a continuous output characteristic.

[0099] To further prevent image degradation, a configuration that defines a difference in density of the metal junctions MB between adjacent pixel blocks, or a configuration that determines the number or density of the metal junctions MB for each pixel block in accordance with a resistance distribution of the wiring, can be employed. There can be pixel blocks in which no metal junctions MB are arranged.

[0100] In the first and second exemplary embodiments, a configuration is described in which image degradation is suppressed by reducing a difference in interconnection resistance due to an arrangement position of the pad wiring 313, an arrangement of the light shielding portion 800, and an interconnection relationship of components arranged around the pixel region 400. In the present exemplary embodiment, in a configuration including a plurality of unit blocks (such as the pixel blocks 436) in which a plurality of metal junctions MB can be arranged, a specific pattern of output characteristics can be suppressed by changing the number or density of the metal junctions MB between the unit blocks.

[0101] A photoelectric conversion device according to a fourth exemplary embodiment of the present disclosure will be described with reference to Figure 8A , Figure 8B and Figure 9 The photoelectric conversion device according to the present exemplary embodiment differs from the photoelectric conversion device according to the first exemplary embodiment in that the number of metal junctions MB1 within a pixel block varies from one end to the other. Similar components to those of the photoelectric conversion devices according to the first, second, and third exemplary embodiments are assigned the same reference numerals, and the description will be omitted or simplified. Figures 1 to 7

[0102] With respect to the Figure 2A and Figure 2B described in the first exemplary embodiment, Figure 8A and Figure 8B are diagrams each showing an example of a heat distribution generated by the operation of each component. Figure 9 is a diagram showing a configuration of an arrangement of the pixel blocks 430, 435, 437, and 438 and an arrangement of the metal junctions MB1-7 in the photoelectric conversion device according to the present exemplary embodiment.

[0103] In Figure 2A and Figure 2B , the operation frequency and the power consumption vary among components. For example, because the output unit 420 in Figure 2A and the output unit 420 in Figure 2B ​The signal processing control circuit 503 in the signal processing control circuit 503 is a component that performs digital signal processing, and therefore the output unit 420 and the signal processing control circuit 503 operate at a higher frequency than other components. Among these components, the power supply fluctuation and the power consumption sometimes become relatively larger than those of other components. This also applies to the signal generation circuits 412 and 423. Because the signal generation circuits 412 and 423 are circuits that generate a clock for A / D conversion operation, a reference comparison voltage, and a clock for P / S conversion, the power supply fluctuation and the power consumption sometimes become relatively larger than those of other components. The influence of the power supply fluctuation propagates to other components via a wiring, or a parasitic capacitance between a wiring or an insulating layer. On the other hand, for example, a consumed current at the time of circuit operation functions as a heat generation factor together with a resistance component of a power supply line or a ground line, and a resistance component of an element included in each circuit, such as a transistor element or a resistance element. If the power consumption is larger than that of other components, a local heat source is generated in some cases, and a specific heat distribution is generated. Even within one component, a power consumption difference, that is, a heat distribution is sometimes generated due to a difference in element density, or a difference in drive frequency or activation rate of a transistor per unit time.

[0104] Figure 8A FIG. 9 is a diagram showing an example of a heat distribution of the chip 308. The heat distribution 900 is a heat distribution centered on the output unit 420, and the heat distribution 901 is a heat distribution centered on the signal generation circuit 423. Figure 8A The heat distribution of the signal generation circuit 412 is omitted in FIG. 9.

[0105] In the heat distribution of the chip 308, Figure 8A Among the heat distributions of the chip 308, the heat distribution 900 particularly affects the pixels 600 in the pixel region 400. The photoelectric conversion element 603 included in the pixel 600 generally generates noise called dark current. Since the dark current varies depending on temperature, in the case of the heat distribution shown in Figure 8A the heat distribution 900, the size of the dark current differs between the vicinity of the heat distribution 900 in the pixel region 400 and other regions, and image unevenness or a two-dimensional shadow is generated in a captured image, which degrades image quality. Figure 8B FIG. 10 is a diagram showing an example of a heat distribution of the chip 309. The heat distribution 902 is a heat distribution centered on the signal processing control circuit 503. Figure 8B The position of the pixel region 400 arranged on the chip 308 is shown. Figure 8B The heat distribution 902 is shown to affect the pixel region 400 in the bonded state. The heat distribution 902 due to the signal processing control circuit 503 also affects the dark current of the pixel region 400, and image unevenness or a two-dimensional shadow is generated in a captured image, which degrades image quality. In this way, depending on the position of a component to be arranged, or a difference in power consumption, a heat distribution is generated on the chip 308 or the chip 309, and image degradation is generated due to the influence of the heat distribution.

[0106] Therefore, in the present exemplary embodiment, the number of metal junctions MB1 of a pixel block located near the heat distribution 902, and the number of metal junctions MB1 of a pixel block located farther from the heat distribution 902 than the pixel block vary. Figure 9 A configuration is shown in which pixel blocks 430, 435, 437, and 438 having different arrangement numbers and densities of metal junctions MB1 are arranged. The pixel blocks 437 and 438 include pixel blocks having a vertically inverted arrangement pattern, and are assigned the same number.

[0107] In the present exemplary embodiment, particularly for the heat distribution 902 due to the signal processing control circuit 503, the arrangement number or density of metal junctions MB1 is reduced and the arrangement pattern is adjusted. This is to reduce heat transport from the chip 309 to the chip 308. Heat transport will be described with reference to Figure 1

[0108] As described with reference to Figure 1 In a state in which the chip 308 and the chip 309 are joined, the interlayer insulating films 107 and 136 and the wiring layers 114 and 143 contact each other. Heat generated by the signal processing control circuit 503 is transported based on the thermal conductivities of the interlayer insulating layers, the contact layers, and the wiring layers included in the wiring structure 191. The thermal conductivity of the metal forming the wiring layers and the contact layers is generally higher than the thermal conductivity of the insulating material forming the insulating films. In other words, heat is more easily transported to the metal junctions MB1 to which the wiring layers and the contact layers are connected to connect signal lines, power supply lines, and ground lines than to the metal junctions MB5. Therefore, as shown in Figure 9 by employing a configuration in which the numbers, densities, and / or arrangement patterns of the metal junctions MB1 and the metal junctions MB5 are adapted to the heat distribution 902, transport of heat generated in the signal processing control circuit 503 can be reduced. With this configuration, the influence of the heat distribution 902 due to the signal processing control circuit 503 on the pixel region 400 can be reduced, and image degradation due to dark current unevenness and two-dimensional shading can be suppressed.

[0109] In the present exemplary embodiment, a configuration in which heat transport from the signal processing control circuit 503 to the pixel region 400 is reduced has been described, but the influence of heat distribution can similarly occur in the signal processing circuit 410 and other components. Therefore, a configuration in which heat transport of the other components is adjusted can be employed. Figure 10 Arrangement positions of the pixel region 400, the signal processing circuit 410, the output unit 420, and the signal generation circuit 423 on the joining surface X are shown, and arrangement examples of the metal junctions MB1 to MB5 are shown.

[0110] A configuration is employed in which heat transport is reduced by adjusting the arrangement pattern of the metal junctions MB1 with respect to the heat distribution 902.​ Figure 8B The described heat distribution 902 reduces the number and / or density of arrangements of the metal junctions MB1 connected to control signals, power supply lines, or ground lines connected to the signal processing circuit 410 to reduce heat transfer from the signal processing control circuit 503. On the other hand, if the heat distribution does not affect other components (such as the signal generation circuit 423), a configuration is adopted in which the number or density of arrangements of the metal junctions MB1 connected to control signals, power supply lines, or ground lines connected to the signal processing circuit 423 is increased.

[0111] With this configuration, heat transfer to the chip 309 can be increased, heat generated in the signal generation circuit 423 can be diffused to the chip 309, and a heat dissipation effect can be obtained. With this configuration, circuit failure and characteristic changes that can occur in the signal generation circuit 423 at high temperatures can be prevented. The mutual influence of heat distribution of the output unit 420 arranged in the vicinity can also be reduced. Furthermore, for example, by increasing the connection ratio to wiring (such as the pad wiring 313B) connected to the outside of the photoelectric conversion device or wiring having a large volume, a higher effect can be obtained. For example, if the pad wiring 313B is connected, the heat transfer path such as via the lead mounting package or the substrate of the photoelectric conversion device is increased, and the amount of heat dissipation can be increased. If the volume of the wiring is large, the heat capacity is increased, and the amount of heat change can be reduced.

[0112] As described above, in the present exemplary embodiment, the number, density, and / or arrangement pattern of the metal junctions MB1 are adjusted with respect to heat distribution that can be generated due to differences in power consumption between components, and heat transfer is adjusted. With this configuration, the influence of image degradation of a captured image and changes in temperature characteristics of a circuit due to heat distribution can be suppressed. The heat distribution can be calculated by simulation dedicated to heat analysis, power consumption calculation, and according to the activation rate of each circuit.

[0113] If the power supply or ground potential is shared between components, the number, density, and arrangement position and pattern of the metal junctions MB1 can be adjusted with respect to power fluctuations that are not described in the present exemplary embodiment. With this configuration, in some cases, the influence of power fluctuations via metal between components can be reduced.

[0114] In the above description, the set of pixels 600 of the first accumulation time and the set of pixels 600 of the second accumulation time different from the first accumulation time are each referred to as a pixel block. In the present exemplary embodiment, the pixel block is not necessarily the set of pixels 600 of different accumulation times. For example, in the pixel region 400, m (m is an integer greater than or equal to 4) pixels 600 can be regarded as a block 1, m pixels 600 arranged at a position different from the block 1 can be regarded as a block 2, and the block 1 and the block 2 can be compared. In the pixel region, if the block 2 is arranged farther from the signal processing control circuit that causes the heat distribution 900 than the block 1, the number of the metal junctions MB1 arranged to correspond to the block 2 can be greater than the number of the metal junctions MB1 arranged to correspond to the block 1.

[0115] A photoelectric conversion device according to a fifth exemplary embodiment according to the present disclosure will be described with reference to Figures 11 to 13B The photoelectric conversion device according to the present exemplary embodiment differs from the photoelectric conversion device according to the first exemplary embodiment in that a pattern of metal junctions MBP is used instead of the metal junctions MB5. As with the photoelectric conversion devices according to the first to fourth exemplary embodiments, like components are assigned the same reference numerals, and the description thereof will be omitted or simplified. Figures 1 to 10

[0116] Figure 11 is a diagram showing the relationship between the arrangement positions of the respective components described with reference to Figure 2A and Figure 2B in the first exemplary embodiment, the arrangement of the pad wiring 313, and the arrangement of the metal junctions. Figure 12A Figure 12B and Figure 12C are diagrams showing the arrangement number and the density of the connection regions.

[0117] Figure 13A and Figure 13B are diagrams showing the connection relationship between the components arranged on the chip 308 and the pad wiring arranged on the chip 309.

[0118] Figure 11 shows the arrangement positions of the pixel region 400, the signal processing circuit 410, the output unit 420, and the pad wiring 313 on the bonding surface X, and the pattern of the metal junctions MBP shown in Figures 12A to 12C is used instead of the metal junctions MB5. In Figure 11 ​​In the periphery region, the peripheral region includes a first block and a second block which overlap with o (o is an integer of 3 or more) metal junctions MB in a plan view. The second block has the same area as the first block and overlaps with the same number of metal junctions as the number of metal junctions arranged in the first block. In addition, the number of metal junctions MB1 arranged at positions overlapping with the first block in the plan view is different from the number of metal junctions MB1 arranged at positions overlapping with the second block in the plan view.

[0119] As Figures 12A to 12C shown, in the pattern of metal junctions MBP, a plurality of metal junctions MB are arranged. Figures 12A to 12C Four metal junctions MB are shown, but the number of metal junctions MB is not limited to four. For convenience of explanation, Figure 11 a configuration of a connection relationship different from the connection relationship between the pad wiring 313 and the respective components described with reference to Figure 2A Fig. 6 is a schematic view showing a connection relationship between the signal processing circuit 410 and the pad wiring 313B-31 and 313B-36. In Figure 12A a configuration in which the metal junctions MB arranged at positions overlapping with the first block are shown, and Figure 12B a configuration in which the metal junctions MB arranged at positions overlapping with the second block are shown. At this time, the number of metal junctions MB arranged in the respective blocks is the same, but the number of metal junctions MB1 connecting the semiconductor element layer 101 and the semiconductor element layer 130 differs between the blocks. In this way, in the periphery region, the number of metal junctions MB1 can vary between the blocks.

[0120] Figure 13A Fig. 6 is a schematic view showing a connection relationship between the signal processing circuit 410 and the pad wiring 313B-31 and 313B-36. In Figure 11 the configuration, the pad wiring 313B-31 and 313B-36 are connected to the signal processing circuit 410 via the pattern of metal junctions MBP. In Figure 13A the configuration, the pattern of metal junctions MBP connected to the pad wiring 313B-31 includes three metal junctions MB1 and one metal junction as Figure 12A shown. On the other hand, the pattern of metal junctions MBP connected to the pad wiring 313B-36 includes four metal junctions MB1 as Figure 12B shown.

[0121] A component arranged in one direction or both directions as the signal processing circuit 410 corresponding to the pixel region 400 sometimes receives a power supply potential or a ground potential supplied from a plurality of pads to achieve low resistance of a power supply or ground wiring. For example, by receiving a power supply potential or a ground potential supplied from the left and right as in the present exemplary embodiment, the interconnection resistance can be reduced and the influence of voltage drop is also reduced. In this case, it is desirable to make the resistance value of the path from the pad wiring 313B-31 to the signal processing circuit 410 equal to the resistance value of the path from the pad wiring 313B-36 to the signal processing circuit 410. For example, if the resistance values are different between the left and right, a gradient of the voltage drop of the power supply or ground potential corresponding to the resistance values is generated. In this case, the potential gradient deteriorates the relationship with another reference potential (not shown) or a control signal (not shown) supplied from the left and right of the signal processing circuit 410, and in some cases, a failure or abnormal output characteristic of the signal processing is generated. For example, a shadow tilted to the left or right is sometimes generated in the A / D conversion output. In particular, in a photoelectric conversion device, the pixel region 400 is designed to have an optical symmetry characteristic. Therefore, the optical characteristic of the captured image can be affected by the shadow tilted to either of the left and right directions of the signal processing circuit 410.

[0122] In the present exemplary embodiment, since the arrangement positions of the pad wiring 313B-31 and the pad wiring 313B-36, the interconnection distance from the pad wiring and the signal processing circuit 410 is different between the left and right. Therefore, if the wiring having the same line width is arranged, the resistance of the path from the pad to the signal processing circuit 410 varies between the left and right. The interconnection resistance can be made equal by adjusting the line width and the wiring pattern, but sometimes the adjustment is not easy due to the limitation generated by the relationship with other components. As shown in FIG. 6, by adjusting the number of the metal junctions MB1 connected to the pad wiring 313B-31 and the pad wiring 313B-36, the resistance component different between the left and right can be easily adjusted. With this configuration, the power supply potential or the ground potential can be symmetrically supplied. Figure 13A

[0123] Figure 13B is a schematic diagram showing the connection relationship between the two terminals of the differential output of the output unit 420 and the pad wirings 313B-34 and 313B-35. The transmission path of the wiring of the two terminals of the differential output needs to be designed in such a way that the impedance of each transmission path is made equal in consideration of the impedance of the transmission path (not shown) outside the photoelectric conversion device. Therefore, the arrangement relationship of the output terminals of the output unit 420 and the pad wirings is such that the output wirings are symmetrically arranged, but in some cases, due to other components to be arranged and the positions of the pad wirings, such a symmetric arrangement cannot be easily achieved. In this case, as shown in FIG. 7, by adjusting the number of the metal junctions MB1 connected to the pad wiring 313B-34 and the pad wiring 313B-35, the resistance component different between the left and right can be easily adjusted. With this configuration, the two terminals of the differential output of the output unit 420 can be symmetrically arranged. Figure 12B ​As shown, for example, the arrangement for the pad wiring 313B-34 includes a pattern MBP of metal junctions as shown in Figure 12C On the other hand, for example, the arrangement for the pad wiring 313B-35 includes a pattern MBP of metal junctions as shown in Figure 12A In this way, by adjusting the number or density of the metal junctions MB1, the impedance of the transmission path of the differential output two-terminal can be easily adjusted.

[0124] The same applies to the pixel region 400. By adjusting the wiring and the configuration of the pattern MBP of the metal junctions connected to the four pads, the power supply potential or the ground potential can be provided symmetrically vertically and horizontally.

[0125] As described above, the number of the pattern MBP of the metal junctions and the number or distribution of the metal junctions MB1 and MB5 in the pattern MBP of the metal junctions are not limited to Figures 12A to 12C the configuration shown. Furthermore, at least any one of the metal junctions MB2 to MB5 can be used instead of the metal junction MB5. In the present exemplary embodiment, the configuration example focusing on the connection relationship between the pad wiring and the respective components has been described, but the configuration of the present exemplary embodiment can also be applied to a signal path including a metal junction.

[0126] As described above, by adjusting the number or density of the metal junctions MB for the wiring including the metal junctions MB, such as a power supply line, a ground line, or a signal line, the impedance including the interconnection resistance can be easily adjusted.

[0127] A photoelectric conversion device according to a sixth exemplary embodiment according to the present disclosure will be described with reference to Figure 14 the drawings. Similar components to the photoelectric conversion devices according to the first to fifth exemplary embodiments shown in Figures 1 to 13B are assigned the same reference numerals, and the description thereof will be omitted or simplified.

[0128] Figure 14 is a diagram showing the arrangement of the metal junctions for one output line of the differential output two-terminal with respect to the connection of the output unit 420 and the pad wiring 313B-34 and 313B-35 described with reference to Figure 13B the output unit 420 in the fifth exemplary embodiment.

[0129] In the region overlapping with the output unit 420 in the plan view, nine metal bonds MB1 are arranged in three rows and three columns, and connect one of the two terminals of the differential output of the output unit 420. In addition, metal bonds including any one of the metal bonds MB2 to MB5 are arranged in two rows and two columns to surround the nine metal bonds MB1 in the plan view. Furthermore, outside the metal bonds MB2 to MB5, the metal bonds MB1 are arranged, and connect signal lines, power supply lines, and ground lines different from the differential output lines of the output unit 420. Other output lines also have a similar arrangement and connection configuration to Figure 14 .

[0130] If the output unit 420 has a differential output format such as LVDS, a certain amount of current flows in the metal bond MB1 arranged in the center via an end element (not shown) outside the photoelectric conversion device. In this case, a magnetic field is generated around the metal bond MB1 in which the current flows. If the digital data changes, the current flow direction also changes, and the magnetic field also changes. For example, if the metal bonds MB2 to MB5 connected to the power supply or signal lines of other components are arranged adjacent to the central metal bond MB1, in some cases, they are affected by the changing magnetic field. For example, depending on the change of the photographic subject object, the digital data changes, and the power supply fluctuation of other components is caused in conjunction with the current change caused by the change of the digital data. Therefore, a malfunction or noise can be caused. This can cause image degradation of the captured image.

[0131] In the present exemplary embodiment, by reducing the number or density of the metal bonds MB1 in the periphery of the metal bonds MB1 connected to the differential output lines, it is possible to reduce the influence of the magnetic field change on the power supply lines or signal lines of other components. In components other than the differential output terminals, in some cases, the change of the power supply current via the metal bonds is large. Also in these cases, in a similar manner, by reducing the number or density of the peripheral metal bonds MB1 for the connection region of the power supply line or ground line in which the current change is large, it is possible to reduce the influence of the magnetic field change on the power supply lines or signal lines of other components.

[0132] Figure 15 is a block diagram showing the configuration of the photoelectric conversion system 50 according to the seventh exemplary embodiment. The photoelectric conversion system 50 according to the present exemplary embodiment includes a photoelectric conversion device 2000, and the configuration of any of the above-described photoelectric conversion devices is applicable to the photoelectric conversion device 2000. Figure 15An imaging system is shown as a photoelectric conversion system 50. Specific examples of the imaging system include a digital still camera, a digital video camera, and a monitoring camera. The photoelectric conversion system 50 includes a photoelectric conversion device 2000, a lens 5020, an aperture 507, and a barrier 506 for protecting the lens 5020. The photoelectric conversion system 50 includes a signal processing unit 5080 (an image signal generation unit) that processes an output signal output from the photoelectric conversion device 2000. The signal processing unit 5080 performs an operation of signal processing of an input signal after various types of correction and compression of the input signal are performed as necessary. The signal processing unit 5080 can have a function of performing AD conversion processing of an output signal output from the photoelectric conversion device 2000. The photoelectric conversion system 50 further includes a buffer memory unit 51 for temporarily storing image data and an external interface unit (external I / F unit) 52 for communicating with an external computer. The photoelectric conversion system 50 further includes a recording medium 53 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 54 for recording imaging data to or reading out imaging data from the recording medium 53.

[0133] The photoelectric conversion system 50 further includes a general control / computation unit 55 that performs various types of computation and controls the entire digital still camera, and a timing signal generation unit 56 that outputs various timing signals to the photoelectric conversion device 2000 and the signal processing unit 5080. The photoelectric conversion device 2000 outputs an image signal to the signal processing unit 5080. The signal processing unit 5080 performs predetermined signal processing on the image signal output from the photoelectric conversion device 2000, and outputs image data. In addition, the signal processing unit 5080 generates an image using the image signal.

[0134] By using the photoelectric conversion device according to each of the above-described example embodiments for the photoelectric conversion system, an imaging system capable of acquiring a higher quality image can be realized.

[0135] A photoelectric conversion system and a movable body according to an eighth example embodiment will be described with reference to Figure 16A and Figure 16B A photoelectric conversion system and a movable body according to an eighth example embodiment will be described with reference to Figure 16A and Figure 16BExamples of a vehicle system and an imaging system mounted on the vehicle system are shown. A photoelectric conversion system 701 includes a photoelectric conversion device 702, an image pre-processing unit 715, an integrated circuit 703, and an optical system 714. The optical system 714 forms an optical image of a subject on the photoelectric conversion device 702. The photoelectric conversion device 702 converts the optical image of the subject that has been formed by the optical system 714 into an electric signal. The photoelectric conversion device 702 is any photoelectric conversion device according to the above-described exemplary embodiments. The image pre-processing unit 715 performs predetermined signal processing on a signal output from the photoelectric conversion device 702. The photoelectric conversion system 701 includes at least two sets of the optical system 714, the photoelectric conversion device 702, and the image pre-processing unit 715, and outputs from the image pre-processing units 715 of the respective sets are input to the integrated circuit 703.

[0136] The integrated circuit 703 is an integrated circuit for the photoelectric conversion system, and includes an image processing unit 704 having a memory 705, an optical distance measurement unit 706, a parallax calculation unit 707, an object recognition unit 708, and a failure detection unit 709. The image processing unit 704 performs image processing such as development processing and defect correction on an output signal of the image pre-processing unit 715. The memory 705 temporarily stores a captured image, and stores a defect position of an imaging pixel. The optical distance measurement unit 706 performs focusing and distance measurement of a subject. The parallax calculation unit 707 calculates parallax (phase difference of a parallax image) from a plurality of image data acquired by a plurality of photoelectric conversion devices 702. The object recognition unit 708 detects a subject such as a vehicle, a road, a traffic sign, or a person. If the failure detection unit 709 detects a failure of the photoelectric conversion device 702, the failure detection unit 709 issues a failure alarm to a main control unit 713.

[0137] The integrated circuit 703 can be realized by a dedicated hardware, can be realized by a software module, or can be realized by a combination thereof. In addition, the integrated circuit 703 can be realized by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or can be realized by a combination thereof.

[0138] The main control unit 713 controls operations of the photoelectric conversion system 701, a vehicle sensor 710, and a control unit 720. A configuration in which the main control unit 713 is not included, and the photoelectric conversion system 701, the vehicle sensor 710, and the control unit 720 individually include a communication interface and transmit and receive a control signal via a communication network (for example, a controller area network (CAN) standard) can also be employed.

[0139] The integrated circuit 703 has a function of receiving a control signal from the main control unit 713 or transmitting a control signal and a setting value to the photoelectric conversion device 702 using its own control unit. For example, the integrated circuit 703 transmits a setting for driving the voltage switch 13 in the photoelectric conversion device 702 or a setting for switching the voltage switch 13 for each frame.

[0140] The photoelectric conversion system 701 is connected to the vehicle sensor 710 and can detect a vehicle running state such as a vehicle speed, a yaw rate, and a steering angle, a vehicle external environment, and a state of other vehicles and obstacles. The vehicle sensor 710 also functions as a distance information acquisition unit that acquires distance information on a distance to an object from a parallax image. Further, the photoelectric conversion system 701 is connected to a driving support control unit 711 that performs various types of driving support such as automatic steering, automatic driving, and a collision avoidance function. In particular, the collision avoidance function estimates or determines whether or not there is a collision with other vehicles or obstacles on the basis of detection results of the photoelectric conversion system 701 and the vehicle sensor 710. If a collision is estimated, the collision avoidance function thereby performs avoidance control or activates a safety device at the time of collision.

[0141] Further, the photoelectric conversion system 701 is also connected to an alarm device 712 that gives a warning to a driver on the basis of a determination result obtained by the collision determination unit. For example, if the determination result obtained by the collision determination unit indicates that a collision is highly likely to occur, the main control unit 713 performs vehicle control to avoid a collision or reduce damage by braking, releasing the accelerator, or suppressing engine output. The alarm device 712 gives an alarm to a user by giving an alarm such as a warning sound, displaying warning information on a display unit screen of a car navigation system or an instrument panel, or vibrating a seat belt or a steering wheel.

[0142] In the present exemplary embodiment, for example, the photoelectric conversion system 701 captures an image of a vehicle periphery such as a front side or a rear side of the vehicle. Figure 16B An arrangement example of the photoelectric conversion system 701 for capturing an image of a front side of a vehicle using the photoelectric conversion system 701 is shown.

[0143] In the present exemplary embodiment, an example in which control is performed so as not to collide with other vehicles has been described. The photoelectric conversion system can also be applied to control for automatic operation by following other vehicles or control for automatic operation so as not to deviate from a lane. Further, in addition to a vehicle such as a car, the photoelectric conversion system 701 can also be applied to a movable body (movable device) such as a ship, an airplane, or an industrial robot. Further, in addition to a movable body, the photoelectric conversion system 701 can also be applied to a device in which object recognition is widely used such as an intelligent transport system (ITS).

[0144] Other exemplary embodiments

[0145] Exemplary embodiments are described above, but the present disclosure is not limited to these exemplary embodiments, and various changes and modifications can be made. In addition, exemplary embodiments can be applied to each other.

[0146] According to exemplary embodiments of the present disclosure, an opto-electric conversion device having improved characteristics can be provided.

[0147] While the application has been described with reference to exemplary embodiments, it is to be understood that the application is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all the variations and equivalents.

Claims

1. A photoelectric conversion device, comprising: The first chip includes a first semiconductor element layer, the first semiconductor element layer including a plurality of pixel circuits arranged in rows and columns; as well as The second chip includes a second semiconductor element layer. The first chip and the second chip are joined together by multiple metal bonding portions between the first semiconductor element layer and the second semiconductor element layer. The plurality of pixel circuits includes a first pixel block, a second pixel block, and a third pixel block. The first pixel block includes n pixel circuits, where n is an integer greater than or equal to 3. The second pixel block includes the same number of pixel circuits as the first pixel block. The third pixel block includes the same number of pixel circuits as the first pixel block. The plurality of metal bonding portions include a first metal bonding portion connecting the first semiconductor element layer and the second semiconductor element layer. The arrangement pattern of the first metal joint in the first pixel block, located at the position overlapping with the first pixel block in the planar view, is different from the arrangement pattern of the first metal joint in the second pixel block, located at the position overlapping with the second pixel block in the planar view. At least three adjacent pixel blocks are different from each other in terms of the arrangement pattern of the metal joint, and each of the at least three adjacent pixel blocks has a pixel circuit included in a plurality of pixel circuits arranged in a row.

2. The photoelectric conversion device according to claim 1, wherein, The difference between the arrangement pattern in the first pixel block and the arrangement pattern in the second pixel block is that the number of the first metal joints arranged at the positions overlapping with the first pixel block in the plan view is less than the number of the first metal joints arranged at the positions overlapping with the second pixel block in the plan view.

3. The photoelectric conversion device according to claim 1, further comprising: Pad routing, with potential provided to the pad routing. Wherein, the distance from the pad wiring to the first pixel block is shorter than the distance from the pad wiring to the second pixel block.

4. The photoelectric conversion device according to claim 1, in, In the plan view, the distance from the first pixel block to the center of the pixel region including the plurality of pixel circuits is longer than the distance from the second pixel block to the center of the pixel region.

5. The photoelectric conversion device according to claim 1, in, Each of the plurality of pixel circuits includes a photoelectric conversion element. In this configuration, the photoelectric conversion elements of the n pixel circuits arranged in the first pixel block are covered by light-shielding portions, and In this configuration, photoelectric conversion elements are arranged so that light enters the same number of pixel circuits arranged in the second pixel block as in the first pixel block.

6. The photoelectric conversion device according to claim 1, further comprising a signal processing circuit. in, The distance between the first pixel block and the signal processing circuit is shorter than the distance between the second pixel block and the signal processing circuit.

7. The photoelectric conversion device according to claim 6, in, The signal processing circuit includes an output unit, and The distance between the first pixel block and the output unit is shorter than the distance between the second pixel block and the output unit.

8. The photoelectric conversion device according to claim 1, in, The number of the first metal joints in the second pixel block that are arranged at positions overlapping with the second pixel block in the planar view is two or more, and Wherein, at least one of the two or more first metal joints in the second pixel block is different from the arrangement pattern of the first metal joints in the first pixel block at the position that overlaps with the first pixel block in the plan view.

9. The photoelectric conversion device according to claim 1, wherein, The first pixel block and the second pixel block, which includes the same number of pixel circuits as the first pixel block, each have n pixel circuits arranged in m columns and l rows, where m is an integer greater than or equal to 2 and l is an integer greater than or equal to 2.

10. The photoelectric conversion device according to claim 1, wherein, In the first pixel block, the accumulation period of signal charge in the n pixel circuits is controlled during a first time period, and in the second pixel block, the accumulation period of signal charge in the same number of pixel circuits as the first pixel block is controlled during a second time period different from the first time period.

11. The photoelectric conversion device according to claim 10, in, In the third pixel block, a third time period, different from the first and second time periods, is used to control the accumulation of signal charge in the same number of pixel circuits as the first pixel block. In the plan view, the number of first metal joints arranged at the position overlapping with the first pixel block, the number of first metal joints arranged at the position overlapping with the second pixel block, and the number of first metal joints arranged at the position overlapping with the third pixel block are different from each other.

12. The photoelectric conversion device according to claim 10, further comprising an output unit, in, In the planar view, the distance between the first pixel block and the output unit is shorter than the distance between the second pixel block and the output unit.

13. The photoelectric conversion device according to claim 1, in, The plurality of metal bonding portions include a second metal bonding portion, which is not connected to the first semiconductor element layer or the second semiconductor element layer, or is not connected to both the first semiconductor element layer and the second semiconductor element layer. In the plan view, the number of second metal joints arranged at the position overlapping with the first pixel block is greater than the number of second metal joints arranged at the position overlapping with the second pixel block.

14. The photoelectric conversion device according to claim 1, wherein, The first pixel block and the second pixel block are arranged adjacent to each other.

15. The photoelectric conversion device according to claim 1, wherein, The output line is connected to the first metal joint.

16. The photoelectric conversion device according to claim 1, wherein, The main component of the plurality of metal joints is copper.

17. The photoelectric conversion device according to claim 1, in, Each of the plurality of pixel circuits includes a photoelectric conversion element, and The plurality of metal joints are arranged such that one metal joint corresponds to one photoelectric conversion element.

18. A photoelectric conversion system, comprising: The photoelectric conversion device according to any one of claims 1 to 17; as well as A signal processing unit is configured to process the signal obtained through the photoelectric conversion device.

19. A mobile body control system, comprising: The photoelectric conversion device according to any one of claims 1 to 17; The distance information acquisition unit is configured to acquire distance information about the distance to the target object based on the signal from the photoelectric conversion device; as well as The control unit is configured to control the movable body based on the distance information.

20. A semiconductor device comprising: A first chip includes a first semiconductor element layer, the first semiconductor element layer including a plurality of circuits arranged in rows and columns; as well as The second chip includes a second semiconductor element layer. The first chip and the second chip are joined together by multiple metal bonding portions between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal bonding portions include a first metal bonding portion connecting the first semiconductor element layer and the second semiconductor element layer. The first chip includes a first block and a second block. In a plan view, the first block overlaps with o metal joints of the plurality of metal joints, where o is an integer greater than or equal to 3. The second block has the same area as the first block in the plan view and overlaps with the same number of metal joints arranged in the first block. The first chip also includes a third block, which has the same area as the first block in the plan view and overlaps with the same number of metal joints arranged in the first block. The first, second, and third blocks differ from each other in the arrangement pattern of their metal joints.

21. The semiconductor device according to claim 20, wherein, The difference between the arrangement pattern in the first block and the arrangement pattern in the second block is that the number of the first metal joints arranged at the position where they overlap with the first block in the plan view is less than the number of the first metal joints arranged at the position where they overlap with the second block in the plan view.

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