Gallium nitride normally-off device with a hybrid gate electrode structure and its manufacturing method

Abstract

The present invention discloses a normally-off gallium nitride device with a hybrid gate electrode structure and a preparation method thereof. The device includes: a buffer layer, a GaN channel layer, an AlGaN layer, and a P-GaN cap layer sequentially disposed on a substrate layer; two ohmic electrodes disposed on the AlGaN layer; a gate dielectric layer disposed on the P-GaN cap layer and on both sides of the P-GaN cap layer; a passivation layer disposed on the AlGaN layer between the ohmic electrode and the gate dielectric layer on both sides of the P-GaN cap layer; a gate electrode disposed on the gate dielectric layer and filling a groove of the gate dielectric layer; wherein, the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrodes filling in a plurality of grooves form a hybrid gate structure of a MIS gate electrode structure and a Schottky gate electrode structure; the gate electrodes on the gate dielectric layers on both sides of the P-GaN cap layer and the gate dielectric layers on both sides of the P-GaN cap layer form a field plate structure. The present invention improves the threshold voltage of the gate electrode of the device, increases the switching frequency of the device, and simultaneously improves the long-term reliability of the gate electrode of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and particularly relates to a GaN normally-off device with a hybrid gate electrode structure and a preparation method thereof. Background Art

[0002] Wide-bandgap semiconductor materials represented by gallium nitride (GaN) have a relatively high critical breakdown electric field, and can achieve lower capacitance and on-resistance under the same breakdown voltage. They are recognized as the next-generation power device materials. Therefore, developing GaN power devices to replace traditional silicon (Si)-based devices is a key means to improve the efficiency of electric energy utilization and thus alleviate the energy crisis, and is expected to play a crucial role in emerging markets. As a representative device of GaN, the high electron mobility transistor (HEMT) based on the AlGaN / GaN epitaxial structure has received extensive attention due to its unique high-mobility two-dimensional electron gas (2DEG), and exhibits excellent performance in high power, high frequency, etc.

[0003] Conventional AlGaN / GaN high electron mobility transistors (HEMTs) are normally-on devices, and an additional gate voltage needs to be applied to cut off the channel during actual operation, resulting in a more complex circuit design and unnecessary power consumption. At the same time, there are also relatively large safety risks. In view of the deficiencies of normally-on devices in actual operation, normally-off AlGaN / GaN high electron mobility transistors (HEMTs) have become the development direction. Currently, among many methods, using a P-GaN cap layer to realize a normally-off device has become one of the most mature solutions and has been successfully commercialized. According to different contact types with P-GaN, the gate electrode structure of this type of normally-off device can be further divided into an ohmic gate electrode, a Schottky gate electrode, and a metal-insulator-semiconductor (MIS) gate electrode.

[0004] However, currently, the threshold voltage of the gate electrode of the P-GaN cap layer high electron mobility transistor (HEMT) remains at about 2V, which cannot meet the requirements for the threshold voltage of the gate electrode in actual operation. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a GaN normally-off device with a hybrid gate electrode structure and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] An embodiment of the present invention provides a normally-off gallium nitride device with a hybrid gate electrode structure, including: a substrate layer; a buffer layer, a GaN channel layer, an AlGaN layer, and a P-GaN cap layer sequentially disposed on the substrate layer;

[0007] Two ohmic electrodes disposed on the AlGaN layer; wherein, the two ohmic electrodes are respectively disposed at both ends of the upper surface of the AlGaN layer, and the P-GaN cap layer is disposed between the two ohmic electrodes;

[0008] A gate dielectric layer disposed on the P-GaN cap layer and on both sides of the P-GaN cap layer; wherein, a plurality of grooves are disposed on the gate dielectric layer on the P-GaN cap layer, and each groove penetrates through the gate dielectric layer to the upper surface of the P-GaN cap layer;

[0009] A passivation layer disposed on the AlGaN layer, and the passivation layer is located between the ohmic electrodes and the gate dielectric layers on both sides of the P-GaN cap layer;

[0010] A gate electrode disposed on the gate dielectric layer and filling the plurality of grooves; wherein, the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrode filling the plurality of grooves constitute a hybrid gate electrode structure of a MIS gate structure and a Schottky gate structure, and the gate electrode on the gate dielectric layer on both sides of the P-GaN cap layer and the gate dielectric layers on both sides of the P-GaN cap layer constitute a field plate structure.

[0011] In an embodiment of the present invention, the thickness of the P-GaN cap layer is 50 nm to 150 nm, and the doping concentration is 1.0×10 17 cm -3 ~1.0×10 21 cm -3 .

[0012] In an embodiment of the present invention, the thickness of the gate dielectric layer on the P-GaN cap layer is 5 nm to 100 nm.

[0013] In an embodiment of the present invention, the width of each groove is 1 μm to 10 μm, and the interval between adjacent grooves is 1 μm to 10 μm.

[0014] In an embodiment of the present invention, the thickness of the gate dielectric layers on both sides of the P-GaN cap layer in the vertical direction is 55 nm to 250 nm.

[0015] In an embodiment of the present invention, the thickness of the passivation layer is 5 nm to 1000 nm.

[0016] In an embodiment of the present invention, it further includes:

[0017] A Pad electrode disposed on the gate electrode and the ohmic electrode.

[0018] Another embodiment of the present invention provides a method for fabricating a normally-off gallium nitride device with a hybrid gate electrode structure, including:

[0019] Forming a buffer layer, a GaN channel layer, an AlGaN layer, and a P-GaN cap layer in sequence on a substrate layer;

[0020] Forming an isolation region in the overall structure including the substrate layer, the buffer layer, the GaN channel layer, the AlGaN layer, and the P-GaN cap layer, and etching the P-GaN cap layer, the AlGaN layer, and the GaN channel layer outside the isolation region until the buffer layer to form isolation between devices;

[0021] Forming a gate electrode region on the P-GaN cap layer, and etching the P-GaN cap layer outside the gate electrode region until the AlGaN layer to form the P-GaN cap layer of the gate electrode region;

[0022] Depositing a gate dielectric layer on the P-GaN cap layer in the gate electrode region and on both sides of the P-GaN cap layer in the gate electrode region;

[0023] Depositing a passivation layer on the AlGaN layer not covered by the gate dielectric layer;

[0024] Forming an ohmic region on the passivation layer, and etching the passivation layer in the ohmic region until the AlGaN layer;

[0025] Depositing a titanium / aluminum / titanium / gold multi-layer metal thin film in sequence on the ohmic region on the AlGaN layer to form an ohmic electrode;

[0026] Etching a plurality of grooves distributed at intervals on the gate dielectric layer on the P-GaN cap layer, and etching each groove until the P-GaN cap layer;

[0027] Depositing a titanium / gold multi-layer metal thin film in sequence on the gate dielectric layer and in each groove to form a gate electrode; wherein, the gate electrodes formed on the gate dielectric layer on the P-GaN cap layer and in each groove constitute a hybrid gate structure of a MIS gate structure and a Schottky gate structure, and the gate electrodes on the gate dielectric layers on both sides of the P-GaN cap layer and the gate dielectric layers on both sides of the P-GaN cap layer constitute a field plate structure.

[0028] In an embodiment of the present invention, it further includes:

[0029] Forming a Pad region on the gate electrode and the ohmic electrode, and forming a Pad electrode in the Pad region.

[0030] Advantages of the present invention:

[0031] The normally-off gallium nitride device with a hybrid gate electrode structure proposed by the present invention is based on the conventional P-GaN / AlGaN / GaN epitaxial structure. The gate electrode adopts a gate electrode structure that combines the MIS gate electrode structure and the Schottky gate electrode structure. By using the MIS gate electrode structure, the threshold voltage of the device gate electrode is increased. Combining the characteristics of high capacitance and high transconductance of the Schottky gate electrode structure, the threshold voltage of the device gate electrode in actual operation can reach 3V. At the same time, by utilizing the high carrier mobility of the two-dimensional electron gas channel, the switching frequency of the normally-off MIS gate electrode structure device is further increased while maintaining the high threshold voltage of the device gate electrode. At the same time, a field plate structure is formed between the two ends of the gate electrode and the gate dielectric layer, improving the long-term reliability of the device gate electrode.

[0032] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0033] Figure 1 is a schematic structural diagram of a normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of another normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention;

[0035] Figure 3 is a schematic preparation process diagram of a normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention;

[0036] Figures 4a to 4i is a schematic preparation structure diagram of a normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention;

[0037] Figure 5 is a schematic preparation process diagram of another normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention.

[0038] Description of the Reference Numerals:

[0039] 1 - Substrate layer; 2 - Buffer layer; 3 - GaN channel layer; 4 - AlGaN layer; 5 - P-GaN cap layer; 6 - Gate dielectric layer; 7 - Passivation layer; 8 - Ohmic electrode; 9 - Gate electrode. Detailed Embodiments

[0040] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0041] Embodiment 1

[0042] In order to increase the threshold voltage of the device, an embodiment of the present invention provides a normally-off gallium nitride device with a hybrid gate electrode structure. Please refer to Figure 1 , Figure 1 FIG. is a schematic structural diagram of a normally-off gallium nitride device with a hybrid gate electrode structure provided by an embodiment of the present invention. The device includes:

[0043] Substrate layer 1;

[0044] A buffer layer 2, a GaN channel layer 3, and an AlGaN layer 4 sequentially disposed on the substrate layer 1;

[0045] A P-GaN cap layer 5 and two ohmic electrodes 8 disposed on the AlGaN layer 4; wherein, the two ohmic electrodes 8 are respectively disposed at both ends of the upper surface of the AlGaN layer 4, and the P-GaN cap layer 5 is disposed between the two ohmic electrodes 8;

[0046] A gate dielectric layer 6 disposed on the P-GaN cap layer 5 and on both sides of the P-GaN cap layer 5; wherein, a plurality of grooves are disposed on the gate dielectric layer 6 on the P-GaN cap layer 5, and each groove penetrates through the gate dielectric layer 6 to the upper surface of the P-GaN cap layer 5;

[0047] A passivation layer 7 disposed on the AlGaN layer, and the passivation layer 7 is located between the ohmic electrode and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5;

[0048] A gate electrode disposed on the gate dielectric layer 6 and filling a plurality of grooves; wherein, the gate electrode on the gate dielectric layer 6 on the P-GaN cap layer 5 and the gate electrodes filling a plurality of grooves form a hybrid gate electrode structure of a MIS gate structure and a Schottky gate structure, and the gate electrodes on the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 form a field plate structure.

[0049] Specifically, in order to increase the threshold voltage of the device gate electrode, an embodiment of the present invention is based on a conventional normally-off MIS gate electrode structure. Aiming at the problems of low gate electrode capacitance, transconductance, and switching frequency in this structure, Schottky contacts are periodically introduced into the MIS gate electrode structure to increase the gate electrode capacitance, transconductance, and switching frequency in the normally-off transistor device, so as to increase the threshold voltage of the device gate electrode. At the same time, a field plate structure is formed by using a gate metal and a dielectric layer around the gate electrode to improve the long-term reliability of the device gate electrode. Specifically:

[0050] In an embodiment of the present invention, an epitaxial heterojunction structure of P-GaN / AlGaN / GaN is formed on a substrate layer 1, an ohmic electrode 8 is provided on the epitaxial heterojunction structure, an MIS gate electrode structure composed of a gate dielectric layer 6 on a P-GaN cap layer 5 and a gate electrode 9 on the gate dielectric layer 6, and a Schottky gate electrode structure composed of the gate dielectric layer 6 and the gate electrode 9 filled in a plurality of grooves and in contact with the P-GaN cap layer 5 are formed to form a hybrid gate electrode structure with a periodically distributed MIS gate electrode structure and Schottky gate electrode structure, and a field plate structure composed of the gate electrode 9 on the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5. The formed hybrid gate electrode structure integrates an MIS gate electrode and a Schottky gate electrode structure within the same gate electrode structure, and forms a hybrid gate electrode structure with a periodic arrangement of MIS gate electrodes and Schottky gate electrodes inside the gate electrode, which not only improves the threshold voltage and gate electrode leakage current of the gate electrode, but also improves the transconductance and conversion rate of the gate electrode. Moreover, due to the field plate structure formed by the gate metal on the gate dielectric layer 6 and the gate dielectric layer 6 at the edge of the hybrid gate electrode structure, the long-term reliability of the device gate electrode is further increased.

[0051] Preferably, the substrate 1 is a silicon substrate.

[0052] Preferably, the thickness of the buffer layer 2 is 0 μm to 5 μm; the thickness of the GaN channel layer 3 is 10 nm to 4000 nm, and the GaN channel layer 3 is intrinsically doped; the thickness of the AlGaN barrier layer is 10 nm to 25 nm, and the AlGaN barrier layer is intrinsically doped.

[0053] Preferably, the thickness of the P-GaN cap layer 5 is 50 nm to 150 nm, and the doping concentration is 1.0×10 17 cm -3 ~1.0×10 21 cm -3 。

[0054] Preferably, the ohmic electrode 8 is a titanium / aluminum / titanium / gold multi-layer thin film with a thickness of 200 nm to 500 nm.

[0055] Preferably, the gate dielectric layer 6 is silicon nitride (SiN), and the thickness of the gate dielectric layer 6 is 5 nm to 100 nm.

[0056] Preferably, the width of each groove is 1 μm to 10 μm, and the interval between adjacent grooves is 1 μm to 10 μm.

[0057] Preferably, the thickness of the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 in the vertical direction is 55 nm to 250 nm.

[0058] Preferably, the thickness of the passivation layer 7 is 5 nm to 1000 nm.

[0059] Preferably, the gate electrode 9 is a titanium / gold multi-layer thin film, and the thickness of the gate electrode 9 located on the gate dielectric layer 6 is 30 nm to 200 nm.

[0060] For another alternative of the embodiment of the present invention, please refer to Figure 2 , Figure 2 FIG. is a schematic structural diagram of another gallium nitride normally-off device with a hybrid gate electrode structure provided by the embodiment of the present invention. The device further includes:

[0061] Pad electrodes disposed on the gate electrode 9 and the ohmic electrode 8.

[0062] Preferably, the Pad electrode is made of gold, and the thickness of the Pad electrode is 0.1 μm to 5 μm.

[0063] In summary, for the gallium nitride normally-off device with a hybrid gate electrode structure proposed in the embodiment of the present invention, on the basis of the conventional P-GaN / AlGaN / GaN epitaxial structure, the gate electrode 9 on the P-GaN cap layer 5 adopts a gate electrode structure that mixes the MIS gate electrode structure and the Schottky gate electrode structure. The MIS gate electrode structure is used to increase the threshold voltage of the device gate electrode. Combining the characteristics of the high capacitance and high transconductance of the Schottky gate electrode structure, the threshold voltage of the device gate electrode can reach 3 V in actual operation; at the same time, using the high carrier mobility of the two-dimensional electron gas channel, while maintaining the high threshold voltage of the device gate electrode, the switching frequency of the normally-off MIS gate electrode structure device is further increased. At the same time, the gate electrode 9 on the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 form a field plate structure, improving the long-term reliability of the device gate electrode.

[0064] Based on the same inventive concept, the embodiment of the present invention also proposes a preparation method for a gallium nitride normally-off device with a hybrid gate electrode structure, including the following steps:

[0065] S301: A buffer layer 2, a GaN channel layer 3, an AlGaN layer 4, and a P-GaN cap layer 5 are sequentially formed on the substrate layer 1.

[0066] Specifically, please refer to Figure 4a , in the embodiment of the present invention, a buffer layer 2 with a thickness of 0 μm to 5 μm, an intrinsically doped GaN channel layer 3 with a thickness of 10 nm to 4000 nm, an intrinsically doped AlGaN barrier layer 4 with a thickness of 10 nm to 25 nm, and a P-GaN cap layer 5 with a thickness of 50 nm to 150 nm and a doping concentration of 1.0×10 17 cm -3 ~1.0×10 21 cm -3 are sequentially deposited and formed on the surface of the substrate 1 by metal organic chemical vapor deposition.

[0067] S302. Form an isolation region in the overall structure including the substrate layer 1, buffer layer 2, GaN channel layer 3, AlGaN layer 4, and P-GaN cap layer 5, and etch the P-GaN cap layer 5, AlGaN layer 4, and GaN channel layer 3 outside the isolation region until the buffer layer 2 to form isolation between devices.

[0068] Specifically, please refer to Figure 4b , in the embodiment of the present invention, a photolithography and development technique is adopted, and a photoresist is used as a mask layer to form an isolation region. An isolation region is formed in the overall structure including the substrate layer 1, buffer layer 2, GaN channel layer 3, AlGaN layer 4, and P-GaN cap layer 5. A dry etching technique is used to etch the P-GaN cap layer, AlGaN barrier layer, and GaN channel layer 3 outside the isolation region until the buffer layer 2 to form isolation between devices.

[0069] S303. Form a gate electrode region on the P-GaN cap layer 5, and etch the P-GaN cap layer 5 outside the gate electrode region until the AlGaN layer 4, the P-GaN cap layer 5 in the gate electrode region.

[0070] Specifically, please refer to Figure 4c , in the embodiment of the present invention, a photolithography and development technique is adopted, and a photoresist is used as a mask layer to form a gate electrode region. A gate electrode region is formed on the P-GaN cap layer 5. A dry etching technique is used to etch the P-GaN cap layer 5 outside the gate electrode region until the AlGaN layer 4 to form the P-GaN cap layer 5 in the gate electrode region, that is, Figure 1 the P-GaN cap layer 5 shown in Figure 1 the P-GaN cap layer 5 formed in the gate electrode region shown.

[0071] S304. Deposit a gate dielectric layer 6 on the P-GaN cap layer 5 in the gate electrode region and on both sides of the P-GaN cap layer 5 in the gate electrode region.

[0072] Specifically, please refer to Figure 4d , in the embodiment of the present invention, a vapor phase epitaxial deposition technique is used to deposit a gate dielectric layer 6 with a thickness of 5 nm to 100 nm on the P-GaN cap layer 5 in the gate electrode region, and deposit a gate dielectric layer 6 with a vertical thickness of 55 nm to 250 nm on both sides of the P-GaN cap layer 5. Among them, the gate dielectric layer 6 can be a layer of silicon nitride (SiN), but is not limited to silicon nitride.

[0073] S305. Deposit a passivation layer 7 on the AlGaN layer 4 not covered by the gate dielectric layer 6.

[0074] Specifically, please refer to Figure 4e, in the embodiment of the present invention, a passivation layer 7 with a thickness of 5 nm to 1000 nm is deposited on the AlGaN layer 4 not covered by the gate dielectric layer 6 by using chemical vapor deposition technology. Among them, the passivation layer 7 can be a layer of silicon nitride (SiO2), but is not limited to silicon dioxide.

[0075] It should be noted that the gate dielectric layer 6 and the passivation layer 7 deposited in step S304 of the embodiment of the present invention can be of different materials or the same material, and are specifically deposited according to actual needs. When the deposited gate dielectric layer 6 and the passivation layer 7 are of the same material, S304 and S305 can be implemented in one step and do not need to be implemented in two independent steps.

[0076] S306. Form an ohmic region on the passivation layer 7, and etch the passivation layer 7 in the ohmic region until the AlGaN layer 4.

[0077] Specifically, please refer to Figure 4f , in the embodiment of the present invention, a photolithography and development technology is adopted, and a photoresist is used as a mask layer to form an ohmic region on the passivation layer 7; a wet etching technology is adopted to etch the passivation layer 7 in the ohmic region until the AlGaN layer 4, and the wet etching solution is a 15% HF solution. In the embodiment of the present invention, the etching accuracy of the ohmic region is improved by wet etching.

[0078] S307. Deposit a titanium / aluminum / titanium / gold multi-layer thin film on the AlGaN layer 4 in sequence to form an ohmic electrode 8.

[0079] Specifically, please refer to Figure 4g , in the embodiment of the present invention, a magnetron sputtering method is adopted to deposit a titanium / aluminum / titanium / gold multi-layer thin film on both ends of the upper surface of the AlGaN layer 4 in sequence to form an ohmic electrode 8. Then, the titanium / aluminum / titanium / gold multi-layer thin film outside the AlGaN layer 4 is peeled off by using a lift-off method, and a thermal annealing treatment is carried out in a nitrogen atmosphere, and the annealing temperature is 500 °C to 900 °C to form an ohmic contact.

[0080] S308. Etch a plurality of grooves distributed at intervals on the gate dielectric layer 6 on the P-GaN cap layer 5, and each groove is etched until the P-GaN cap layer 5.

[0081] Specifically, please refer to Figure 4h , in an alternative solution of the embodiment of the present invention, a photolithography and development technology is adopted, and a photoresist is used as a mask layer to form a groove region on the gate dielectric layer 6 on the P-GaN cap layer 5; a dry etching technology is adopted to etch the gate dielectric layer 6 in the groove region to form a plurality of grooves distributed at intervals, and each groove is etched until the P-GaN cap layer 5 to form a Schottky gate electrode position. Preferably, the width of each groove is 1 μm to 10 μm, and the interval between adjacent grooves is 1 μm to 10 μm.

[0082] Another alternative solution in the embodiment of the present invention is that after etching 70% - 80% of the thickness of the gate dielectric layer 6 outside the etched groove region during the dry etching process, a wet etching technique is adopted to etch the position of the Schottky gate electrode on the gate dielectric layer 6. The specific wet etching solution is a 15% HF solution, and the remaining gate dielectric layer 6 in the etched groove region is etched until several grooves are formed at intervals in the P-GaN cap layer 5. Through wet etching, the etching accuracy of the grooves can be improved in the embodiment of the present invention.

[0083] After the dry or wet etching of the grooves is completed, a rapid annealing technique is adopted to anneal the device structure as Figure 4h shown, and the annealing temperature is 300°C - 600°C to improve the contact quality between the gate dielectric layer 6 and the P-GaN cap layer 5 ( Figure 1 the P-GaN cap layer in

[0084] S309. On the gate dielectric layer 6 and in each groove, a titanium / gold multi-layer metal thin film is deposited in sequence to form the gate electrode 9; among them, the gate electrode 9 formed on the gate dielectric layer 6 on the P-GaN cap layer 5 and in each groove constitutes a hybrid gate structure of an MIS gate structure and a Schottky gate structure, and the gate electrode 9 on the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 constitute a field plate structure.

[0085] Specifically, please refer to Figure 4i . In the embodiment of the present invention, a magnetron sputtering method is adopted to deposit a titanium / gold multi-layer thin film in sequence on the gate dielectric layer 6 and in each groove to form the gate electrode 9. Then, the metal outside the gate electrode region is peeled off by a lift-off method. The gate electrode 9 formed on the gate dielectric layer 6 on the P-GaN cap layer 5 and in each groove constitutes a hybrid gate structure of an MIS gate electrode structure and a Schottky gate electrode structure, and the gate electrode 9 on the gate dielectric layer on both sides of the P-GaN cap layer 5 and the gate dielectric layer 6 on both sides of the P-GaN cap layer 5 constitute a field plate structure. After the gate electrode 9 is formed, a rapid annealing technique is adopted to anneal the device structure as Figure 4i shown, and the annealing temperature is 300°C - 600°C to improve the contact quality between the gate electrode 9 and the P-GaN cap layer 5.

[0086] Another alternative solution proposed in the embodiment of the present invention, please refer to Figure 5 , Figure 5 is a schematic diagram of the preparation process of another gallium nitride normally-off device with a hybrid gate electrode structure provided by the embodiment of the present invention. On the basis of the above steps S301 - S309, it further includes:

[0087] S310. A Pad region is formed on the gate electrode 9 and the ohmic electrode 8, and gold is deposited in the Pad region to form the Pad electrode 10.

[0088] Specifically, please refer to againFigure 2 In the embodiment of the present invention, a photolithography and development technique is adopted. A photoresist is used as a mask layer to form a Pad region on the gate electrode 9 and two ohmic electrodes 8, and gold is deposited in the Pad region by magnetron sputtering or electroplating to form a Pad electrode 10 with a thickness of 0.1 μm to 5 μm.

[0089] The operation methods such as metal organic chemical vapor deposition method, magnetron sputtering method, and lift-off method mentioned in the embodiments of the present invention are all prior arts and will not be elaborated here.

[0090] For the embodiments of the preparation method, since it is basically similar to the device embodiments, the description is relatively simple. For the relevant parts, refer to the partial description of the device embodiments.

[0091] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0092] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0093] Although the present application is described herein in connection with various embodiments, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0094] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as falling within the protection scope of the present invention.

Claims

1. A normally-off gallium nitride device with a hybrid gate electrode structure, characterized in that, Comprising: A substrate layer; A buffer layer, a GaN channel layer, and an AlGaN layer sequentially disposed on the substrate layer; A P-GaN cap layer and two ohmic electrodes disposed on the AlGaN layer; wherein, the two ohmic electrodes are respectively disposed at both ends of the upper surface of the AlGaN layer, and the P-GaN cap layer is disposed between the two ohmic electrodes; A gate dielectric layer disposed on the P-GaN cap layer and on both sides of the P-GaN cap layer; wherein, a plurality of grooves are disposed on the gate dielectric layer on the P-GaN cap layer, and each groove penetrates through the gate dielectric layer to the upper surface of the P-GaN cap layer; A passivation layer disposed above the AlGaN layer, and the passivation layer is located between the ohmic electrodes and the gate dielectric layers on both sides of the P-GaN cap layer; A gate electrode disposed on the gate dielectric layer and filling a plurality of the grooves; wherein, the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrodes filling a plurality of the grooves constitute a hybrid gate electrode structure with a periodic arrangement of MIS gate structures and Schottky gate structures, and the gate electrodes on the gate dielectric layers on both sides of the P-GaN cap layer and the gate dielectric layers on both sides of the P-GaN cap layer constitute a field plate structure; A periodically distributed MIS gate structure and Schottky gate structure are integrated in the same gate electrode. By using the MIS gate structure, the threshold voltage of the device gate electrode is increased. Combining the characteristics of the high capacitance and high transconductance of the Schottky gate structure, the threshold voltage of the device gate electrode reaches 3V during actual operation.

2. The normally-off gallium nitride device having a hybrid gate electrode structure according to claim 1, characterized in that, The thickness of the P-GaN cap layer is 50 nm to 150 nm, and the doping concentration is 1.0×10 17 cm -3 ~1.0×10 21 cm -3 .

3. The normally-off gallium nitride device with a hybrid gate electrode structure according to claim 1, characterized in that The thickness of the gate dielectric layer on the P-GaN cap layer is 5nm to 100nm.

4. The normally-off gallium nitride device with a hybrid gate electrode structure according to claim 1, characterized in that, The width of each groove is 1μm to 10μm, and the interval between adjacent grooves is 1μm to 10μm.

5. The normally-off gallium nitride device with a hybrid gate electrode structure according to claim 1, characterized in that, The thickness of the gate dielectric layers on both sides of the P-GaN cap layer in the vertical direction is 55nm to 250nm.

6. The normally-off gallium nitride device with a hybrid gate electrode structure according to claim 1, characterized in that, The thickness of the passivation layer is 5nm to 1000nm.

7. The normally-off gallium nitride device with a hybrid gate electrode structure according to claim 1, characterized in that, Further comprising: Pad electrodes disposed on the gate electrodes and the ohmic electrodes.

8. A method for fabricating a normally-off gallium nitride device with a hybrid gate electrode structure, characterized in that, Comprising: Sequentially forming a buffer layer, a GaN channel layer, an AlGaN layer, and a P-GaN cap layer on the substrate layer; Forming an isolation region in the overall structure including the substrate layer, the buffer layer, the GaN channel layer, the AlGaN layer, and the P-GaN cap layer, and etching the P-GaN cap layer, the AlGaN layer, and the GaN channel layer outside the isolation region until the buffer layer to form isolation between devices; Forming a gate electrode region on the P-GaN cap layer, and etching the P-GaN cap layer outside the gate electrode region until the AlGaN layer to form the P-GaN cap layer of the gate electrode region; Depositing a gate dielectric layer on the P-GaN cap layer in the gate electrode region and on both sides of the P-GaN cap layer in the gate electrode region; Depositing a passivation layer on the AlGaN layer not covered by the gate dielectric layer; Forming an ohmic region on the passivation layer, and etching the passivation layer in the ohmic region until the AlGaN layer; An ohmic electrode is formed by sequentially depositing a titanium / aluminum / titanium / gold multi-layer metal thin film on the ohmic region on the AlGaN layer; A plurality of grooves spaced apart are etched in the gate dielectric layer on the P-GaN cap layer, and each of the grooves is etched until the P-GaN cap layer; A gate electrode is formed by sequentially depositing a titanium / gold multi-layer metal thin film on the gate dielectric layer and in each of the grooves; wherein, the gate electrodes formed on the gate dielectric layer on the P-GaN cap layer and in each of the grooves constitute a hybrid gate structure in which a MIS gate structure and a Schottky gate structure are arranged periodically, and the gate electrodes on the gate dielectric layers on both sides of the P-GaN cap layer and the gate dielectric layers on both sides of the P-GaN cap layer constitute a field plate structure; a periodically distributed MIS gate structure and a Schottky gate structure are integrated in the same gate electrode, the threshold voltage of the device gate electrode is increased by using the MIS gate structure, and combined with the characteristics of high capacitance and high transconductance of the Schottky gate structure, the threshold voltage of the device gate electrode in actual operation reaches 3V.

9. The method for manufacturing a gallium nitride normally-off device having a hybrid gate electrode structure according to claim 8 further includes: A Pad region is formed on the gate electrode and the ohmic electrode, and a Pad electrode is formed in the Pad region.

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