Storage device and method of forming the same

Abstract

Some embodiments relate to a memory device and a method for forming the same. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge can be selectively formed in the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity with oxygen than the active metal layer.

Description

Technical Field

[0001] The present invention relates to a storage device and a method for forming the same. Background Art

[0002] Many modern electronic devices include electronic memory. Electronic memory can be volatile memory or non-volatile memory. Non-volatile memory can retain its stored data without power, while volatile memory loses its stored data when power is off. Programmable metallization cell (PMC) random access memory (RAM) (which may also be called nanobridge or electrolytic memory) is expected to become a candidate for the next generation of non-volatile electronic memory because of its advantages over current electronic memory. Compared with current non-volatile memory (such as flash random access memory), PMC RAM generally has better performance and reliability. Compared with current volatile memory (such as dynamic random access memory (DRAM) and static random access memory (SRAM)), PMC RAM generally has better performance and density and has lower power consumption. Summary of the invention

[0003] An embodiment of the present invention provides a storage device, comprising: a substrate, a first electrode, a data storage layer, a second electrode, an active metal layer, and a buffer layer. The first electrode overlies the substrate. The data storage layer overlies the first electrode. The second electrode overlies the data storage layer, wherein a conductive bridge can be selectively formed in the data storage layer to couple the first electrode to the second electrode. The active metal layer is disposed between the data storage layer and the second electrode. The buffer layer is disposed between the active metal layer and the second electrode, wherein the buffer layer has a lower reactivity with oxygen than the active metal layer.

[0004] An embodiment of the present invention provides a storage device, comprising: a dielectric structure, a selector structure, and a first storage unit. The dielectric structure is overlaid on a substrate. The selector structure is arranged in the dielectric structure, wherein the selector structure includes a selector overlaid on a first electrode. The first storage unit is overlaid on the selector structure and arranged in the dielectric structure, wherein the first storage unit includes a second electrode, a data storage layer overlaid on the second electrode, a third electrode overlaid on the data storage layer, and a buffer layer arranged between the data storage layer and the third electrode, wherein the buffer layer includes a first conductive material and the third electrode includes a second conductive material different from the first conductive material.

[0005] An embodiment of the present invention provides a method for forming a storage device, which includes: forming a bottom electrode through hole on a substrate; forming a storage unit layer stack on the bottom electrode through hole, wherein the storage unit layer stack includes a lower electrode layer, a data storage structure, a buffer layer and an upper electrode layer, wherein the buffer layer is arranged between the data storage structure and the upper electrode layer; performing a first etching process on the upper electrode layer to form an upper electrode on the buffer layer, wherein the first etching process exposes the upper surface of the buffer layer; and performing a second etching process on the buffer layer, the data storage structure and the lower electrode layer to form a storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of memory devices including a buffer layer overlying a data storage layer are shown.

[0008] Figure 1B Cross-sectional views of some embodiments of a one-selector one-memory cell (1S1MC) stack having a memory cell overlying a selector structure are shown, wherein the memory cell includes a buffer layer overlying a data storage layer.

[0009] Figures 2A to 2D Show Figure 1A Cross-sectional views of various alternative embodiments of storage devices are shown.

[0010] FIG. 3A to FIG. 3B Cross-sectional views of various embodiments of a memory device including an embedded memory region including a plurality of memory cells and a logic region laterally adjacent to the embedded memory region are shown.

[0011] FIG. 4A to FIG. 4CVarious views of some embodiments of an integrated circuit (IC) including a plurality of 1S1MC stacks disposed between a plurality of bit lines and a plurality of word lines are shown.

[0012] Figures 5 to 11 Cross-sectional views of some embodiments of methods of forming a memory cell including a buffer layer overlying a data storage layer are shown.

[0013] Fig.12 Methods of some embodiments including methods of forming a memory cell including a buffer layer overlying a data storage layer are shown in a flow chart format. DETAILED DESCRIPTION

[0014] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] The programmable metallization cell generally includes a data storage layer arranged between a top electrode and a bottom electrode. An active metal layer may be disposed between the data storage layer and the top electrode. During a set operation, a set voltage is applied across the top electrode and the bottom electrode so that a conductive bridge is formed in the data storage layer (e.g., resulting in a low resistance state). When the set voltage is applied, ions may travel from the active metal layer to the data storage layer, thereby forming a conductive bridge in the data storage layer. During a reset operation, a reset voltage is applied across the top electrode and the bottom electrode so that the conductive bridge may be at least partially removed from the data storage layer (e.g., resulting in a high resistance state). When the reset voltage is applied, ions may travel from the data storage layer to the active metal layer, thereby at least partially dissolving the conductive bridge in the data storage layer.

[0017] During the production of a programmable metallization cell, a memory cell stack is formed on a substrate. The memory cell stack includes a top electrode layer, a bottom electrode layer, a data storage layer disposed between the top electrode layer and the bottom electrode layer, and an active metal layer disposed between the data storage layer and the top electrode layer. A hard mask layer is formed on the top electrode layer. A separate etching process is then performed to define the top electrode and the bottom electrode. For example, a first etching process (e.g., a first plasma etching process) is performed by patterning the top electrode layer to define the top electrode. The first etching process may expose the upper surface of the active metal layer and / or may over-etch into the active metal layer. In addition, the first etching process may include exposing the top electrode layer and the active metal layer to one or more fluorine-based etchants (e.g., carbon tetrafluoride (e.g., CF4), sulfur hexafluoride (e.g., SF6), etc.). The one or more fluorine-based etchants may react with the active metal layer, thereby causing byproducts (e.g., aluminum fluoride (e.g., AlF3)) to form on the upper surface of the active metal layer and / or on the sidewalls of the top electrode and the sidewalls of the hard mask layer. During the second etching process (e.g., a second plasma etching process) used to define the bottom electrode, byproducts from the first etching process may be etched and redeposited on the sidewalls of the data storage layer. Since the byproducts are conductive, the byproducts may electrically short the top electrode to the bottom electrode, thereby rendering the programmable metallization unit inoperable. In addition, if left in place, the byproducts may also cause long-term reliability issues, for example, due to the diffusion of the byproducts to adjacent structures during subsequent annealing processes. Therefore, a wet cleaning process (e.g., using a cleaning solution such as hydrofluoric acid and / or deionized water) may be used after the separate etching process to reduce and / or remove the redeposited byproducts. However, the wet cleaning process may damage the interface between the top electrode and / or the bottom electrode and the data storage layer, resulting in peeling between layers. This may, to a certain extent, impair the stability, durability and / or switching time of the programmable metallization unit.

[0018] In some embodiments of the present disclosure, in order to eliminate the formation and / or re-deposition of byproducts on the sidewalls of the memory cell stack, a buffer layer may be formed between the top electrode layer and the active metal layer before etching the memory cell stack. Therefore, after the buffer layer is formed, a masking layer is formed over the central portion of the top electrode layer. A first etching process (e.g., a first plasma etch comprising one or more fluorine-based etchants) is performed based on the masking layer to remove a portion of the top electrode layer, thereby defining the top electrode and exposing the upper surface of the buffer layer in a region laterally offset from the masking layer. Since the first etching process stops on the buffer layer, the first etching does not contact the active metal layer and will not cause the formation of byproducts (e.g., aluminum fluoride (e.g., AlF3)) between the one or more fluorine-based etchants and the active metal layer. A second etching process (e.g., a second plasma etch comprising chlorine (e.g., Cl2), boron trichloride (e.g., BCl3), sulfur dioxide (e.g., SO2), etc.) is performed on the buffer layer and the underlying layer to define the programmable metallization cell. The second etching process utilizes one or more fluorine-free etchants to prevent or reduce the formation of byproducts between the one or more fluorine-free etchants and the layers of the memory cell stack located below the buffer layer (e.g., active metal layer, data storage layer, etc.). In addition, since no byproducts are formed during the first etching process, the second etching process may not redeposit conductive materials (e.g., byproducts from the first etching process) onto the sidewalls of the programmable metallization cell. Therefore, the buffer layer reduces the redeposition of conductive materials on the sidewalls of the programmable metallization cell during fabrication, thereby preventing the top electrode from being shorted to the bottom electrode. This will improve the performance, durability, and / or reliability of the programmable metallization cell to a certain extent.

[0019] In addition, after the first etching process, a cleaning process (e.g., a wet cleaning process using hydrofluoric acid and / or deionized water) may be performed on the upper surface of the top electrode and the buffer layer. The cleaning process may remove any undesirable byproducts formed between the one or more fluorine-based etchants and the top electrode layer and / or the buffer layer. Since the buffer layer overlies the data storage layer and the active metal layer, the cleaning process may not damage the interface between the data storage layer and the active metal layer and / or the bottom electrode layer. This may reduce the peeling between the layers of the programmable metallization unit, thereby improving the stability and / or durability of the programmable metallization unit.

[0020] Figure 1AA cross-sectional view of some embodiments of a memory device 100a having a memory cell 126 is shown, the memory cell 126 including a buffer layer 134 overlying a data storage layer 130. The memory cell 126 may be configured, for example, as a programmable metallization cell, a cation-type resistive random-access memory (RRAM) cell, or some other suitable type of RRAM cell. It should be noted that the cation-type RRAM cell may be referred to, for example, as a programmable metallization cell (PMC) or a conductive-bridging random-access memory (CBRAM) cell.

[0021] The memory device 100a includes a substrate 102 and a memory cell 126 overlying the substrate 102. A lower interconnect dielectric structure 118 overlies the substrate 102. A lower via 114 is disposed in the lower interconnect dielectric structure 118 and overlies the substrate 102. In addition, a lower conductive wire 116 is disposed in the lower interconnect dielectric structure 118 and overlies the lower via 114. A semiconductor device 104 may be disposed on and / or above the substrate 102. In some embodiments, the semiconductor device 104 may be configured as a transistor, for example. In such an embodiment, the semiconductor device 104 includes a source / drain region 106, a gate dielectric layer 108, a gate electrode 110, and a sidewall spacer 112. In various embodiments, the lower via 114 overlies the source / drain region 106 of the semiconductor device 104.

[0022] A dielectric layer 120 is disposed over the lower interconnect dielectric structure 118. An upper interconnect dielectric structure 122 overlies the dielectric layer 120. A memory cell 126 is disposed within the upper interconnect dielectric structure 122 and overlies the bottom electrode via 124. In some embodiments, the memory cell 126 includes a first electrode 128, a data storage layer 130, an active metal layer 132, a buffer layer 134, and a second electrode 136. A top electrode via 138 overlies the second electrode 136. An upper via 140 overlies the top electrode via 138, and an upper conductive wire 142 overlies the upper via 140. In some embodiments, the active metal layer 132 may be configured as an ion reservoir layer, the first electrode 128 may be configured as a bottom electrode, and the second electrode 136 may be configured as a top electrode.

[0023] In various embodiments, the memory cell 126 is configured as a programmable metallization cell so that a conductive bridge (not shown) can be selectively formed in the region 131 of the data storage layer 130. In such an embodiment, during the operation of the memory cell 126, the conductive bridge can be repeatedly formed and dissolved in the region 131 of the data storage layer 130 so that the memory cell 126 changes between a low resistance state and a high resistance state. When forming the conductive bridge, a set voltage is applied between the first electrode 128 and the second electrode 136. The set voltage can cause oxidation of the active metal layer 132 and form metal cations. In addition, the electric field formed by the set voltage causes the metal cations to migrate to the data storage layer 130 and be reduced to the conductive bridge in the region 131. When dissolving or removing the conductive bridge, a reset voltage is applied between the first electrode 128 and the second electrode 136. The reset voltage can cause oxidation of the conductive bridge and form metal cations. In addition, the electric field formed by the reset voltage causes the metal cations to migrate to the active metal layer 132 and be reduced to the active metal layer 132.

[0024] The first electrode 128 and the second electrode 136 and the active metal layer 132 are electrically conductive. However, the active metal layer 132 is electrochemically active compared to the first electrode 128 and the second electrode 136. Therefore, the first electrode 128 and the second electrode 136 have lower reactivity with oxygen than the active metal layer 132 and rely on more energy to oxidize than the active metal layer 132. For example, the first electrode 128 and the second electrode 136 may rely on 5 electron volts (eV) or more to oxidize, while the active metal layer 132 may rely on 3 eV or less to oxidize. However, other eV values ​​are also suitable. The first electrode 128 and the second electrode 136 may be or may include, for example, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing materials.

[0025] The data storage layer 130 may be a solid electrolyte for metal cations generated by oxidation of the active metal layer 132. For example, in the case where the active metal layer 132 is or includes aluminum, the data storage layer 130 may be a solid electrolyte for aluminum cations. In some embodiments, the data storage layer 130 is or includes silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), silicon nitride (e.g., SiN x ), aluminum oxide (e.g., Al2O3), zirconium oxide (e.g., ZrO2), tantalum oxide (e.g., TaO x ), titanium oxide (e.g., TiO x), aluminum nitride, some other suitable dielectric, or any combination of the foregoing dielectrics. In addition, in some embodiments, the data storage layer 130 is or includes germanium sulfide (e.g., GeS), germanium selenide (e.g., GeSe), germanium tellurium (e.g., GeTe), metal oxide, amorphous silicon, some other suitable electrolyte, or any combination of the foregoing electrolytes. In some embodiments, the active metal layer 132 may be or may include, for example, aluminum, copper, zirconium, tellurium, some other suitable material, or any combination of the foregoing materials. In yet other embodiments, the active metal layer 132 may consist of or consist essentially of aluminum, copper, zirconium, or tellurium.

[0026] In various embodiments, the buffer layer 134 is disposed between the active metal layer 132 and the second electrode 136. In some embodiments, the buffer layer 134 may be or may include, for example, ruthenium, carbon, some other suitable material, or any combination of the foregoing materials. In other embodiments, the buffer layer 134 may be or may include a single material (e.g., ruthenium or carbon), such that the buffer layer 134 is a continuous layer formed of a single material. In yet other embodiments, the buffer layer 134 is conductive and electrochemically inert compared to the active metal layer 132. In such embodiments, the buffer layer 134 has a lower reactivity with oxygen than the active metal layer 132 and relies on more energy to oxidize than the active metal layer 132. In yet other embodiments, the buffer layer 134 may consist of or consist essentially of carbon or ruthenium.

[0027] In some embodiments, during the fabrication of the memory cell 126, a first etching process is performed to form the second electrode 136. In various embodiments, the first etching process includes performing a plasma etch comprising one or more fluorine-based etchants. By providing a buffer layer 134 on the data storage layer 130, the formation and / or redeposition of byproducts from the active metal layer 132 and / or the second electrode 136 and the one or more fluorine-based etchants on the outer sidewalls of the memory cell 126 are mitigated during fabrication. By mitigating the redeposition of byproducts from the buffer layer 134 and / or the second electrode 136, the outer sidewalls of the memory cell 126 are not electrically shorted together by the conductive material, and thus the memory cell 126 can be changed between a high resistance state and a low resistance state. This improves the performance, durability, and / or reliability of the memory cell 126 to a certain extent.

[0028] In other embodiments, the second electrode 136 may be or may include a diffusible substance (e.g., titanium, tantalum, metal nitrides of the foregoing substances, etc.). In yet other embodiments, if the diffusible substance travels to the data storage layer 130 and / or the active metal layer 132, the diffusible substance may mitigate the ability of the memory cell 126 to switch between a high resistance state and a low resistance state. This may occur because the electric field formed by the reset voltage may not be able to remove the diffusible substance from the data storage layer 130, thereby reducing the ability to dissolve and / or remove the conductive bridge. In some embodiments, the buffer layer 134 may be or may include a diffusion barrier material, such as (for example) ruthenium, iridium, some other diffusion barrier material, etc. Therefore, in various embodiments, the second electrode 136 includes a first conductive material, and the buffer layer 134 includes a second conductive material different from the first conductive material. In some embodiments, the buffer layer 134 is conductive and / or is configured to block or otherwise slow down the diffusion of the diffusible substance to the data storage layer 130 and / or the active metal layer 132. In some such embodiments, the buffer layer 134 includes a low diffusivity material (e.g., ruthenium, iridium, etc.) that blocks or otherwise slows down the diffusion of diffusive substances. For example, since the buffer layer 134 includes a single continuous layer formed of a low diffusivity material, the buffer layer 134 may have a grain size that is smaller than the grain size of the second electrode 136, so that the diffusive substances may not travel through the grain boundaries of the buffer layer 134 to the data storage layer 130. In other embodiments, the buffer layer 134 may not include grain boundaries (e.g., the buffer layer 134 may have an amorphous structure), thereby increasing the complexity of the diffusion path of the diffusive substances of the second electrode 136. Therefore, the buffer layer 134 may increase the complexity of the diffusion path of the diffusive substances, thereby blocking or slowing down the diffusion of the diffusive substances from the second electrode 136 to the data storage layer 130. This may improve the durability and / or stability of the memory cell 126 to a certain extent. Therefore, in some embodiments, the buffer layer 134 may be configured as and / or referred to as a diffusion barrier layer.

[0029] Figure 1B Show according to Figure 1A Cross-sectional views of some embodiments of memory device 100b are shown as some alternative embodiments of memory device 100a.

[0030] In some embodiments, the memory device 100b includes a memory cell 126 overlying a selector structure 144. The memory cell 126 includes a second electrode 136, a data storage layer 130, an active metal layer 132, a buffer layer 134, and a third electrode 148 overlying the buffer layer 134. The selector structure 144 includes a selector 146 overlying the first electrode 128. In various embodiments, the memory cell 126 and the selector 146 form a 1-selector 1-memory cell (1S1MC) stack 150. The 1S1MC stack 150 is disposed above the bottom electrode through hole 124. In some embodiments, the third electrode 148 may be or may include, for example, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing materials. Therefore, in various embodiments, the first electrode 128, the second electrode 136, and the third electrode 148 may respectively include the same material (e.g., tungsten, titanium, tantalum, titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing materials). In some embodiments, the first electrode 128 may be referred to as a lower electrode, the second electrode 136 may be referred to as a middle electrode, and the third electrode 148 may be referred to as an upper electrode.

[0031] In some embodiments, the selector 146 may include one or more materials configured to have an electrical response similar to that of a diode (e.g., a PN diode, a PiN diode, a Schottky diode, an oxide semiconductor-oxide diode, etc.). In such embodiments, the selector 146 has a threshold voltage that allows current to flow through the selector 146 if the threshold voltage is exceeded, and blocks current flow if the applied voltage is less than the threshold voltage. Since the selector 146 is configured to selectively block current from flowing through the memory cell 126, the selector 146 is configured to selectively provide access to the memory cell 126.

[0032] In some embodiments, the selector 146 may be or may include a threshold type selector, such as, for example, an ovonic threshold switch (OTS). In some such embodiments, the selector 146 may include a binary material (e.g., SiTe, GeTe, CTe, BTe, ZnTe, AlTe, etc.), a ternary material (e.g., GeSeAs, GeSeSb, GeSbTe, GeSiAs, etc.), a quaternary material (e.g., GeSeAsTe, GeSeTeSi, GeSeTeAs, etc.), some other suitable material, or any combination of the foregoing materials. In other embodiments, the selector 146 may be or may include a voltage conductive bridge (VCB) selector. In some such embodiments, the selector 146 may include a layer formed of Ag and hafnium oxide (e.g., HfO2), a layer formed of Cu and hafnium oxide (e.g., HfO2), a layer formed of Al and silicon dioxide (e.g., SiO2), a layer formed of Ag and tantalum oxide (e.g., TaO2), etc. In various embodiments, the selector 146 may be or may include, for example, boron, carbon, gallium, germanium, arsenic, selenium, nitrogen, some other suitable material, or any combination of the foregoing materials. In some embodiments, the selector 146 may be or may include a threshold type selector and an overlying exponential type selector stacked on each other. In still other embodiments, the selector 146 may be or may include a filament-based selector, a rectifier, a varistor-type selector, a doped-chalcogenide-based selector, a Mott effect based selector, a mixed-ionic-electronic-conductive (MIEC)-based selector, a field-assisted-superliner-threshold (FAST) selector, a voltage conductive bridge (VCB) selector, an exponential type selector, etc.

[0033] Figure 2A A cross-sectional view of some embodiments of a memory device 200 a is shown having a 1S1MC stack 150 overlying a substrate 102 .

[0034] In some embodiments, the 1S1MC stack 150 includes a memory cell 126 and a selector structure 144 overlying a substrate 102. In some embodiments, the substrate 102 may be or may include, for example, a semiconductor body, such as a single crystal silicon / complementary metal-oxide-semiconductor (CMOS) block, silicon-germanium (SiGe), silicon-on-insulator (SOI), or another suitable material. A dielectric layer 120 overlies the substrate 102, and an upper interconnect dielectric structure 122 overlies the dielectric layer 120. In addition, a bottom electrode via 124 is disposed in the dielectric layer 120 and is located below the memory cell 126. In some embodiments, the dielectric layer 120 may be or may include, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, some other suitable material, or any combination of the foregoing materials. In yet other embodiments, the upper interconnect dielectric structure 122 may be or may include, for example, silicon dioxide, a low-k dielectric, an ultra-low-k dielectric, some other suitable material, or any combination of the foregoing materials. As used herein, a low-k dielectric may be, for example, a dielectric having a dielectric constant less than about 3.9, 2, or 1.5. In various embodiments, the bottom electrode via 124 may be or may include, for example, copper, aluminum, tungsten, another suitable conductive material, or any combination of the foregoing materials.

[0035] In various embodiments, the selector structure 144 includes a first electrode 128 and a selector 146, wherein the first electrode 128 is disposed between the selector 146 and the bottom electrode through-hole 124. In some embodiments, the memory cell 126 includes a second electrode 136, a data storage layer 130, an active metal layer 132, a buffer layer 134, and a third electrode 148. In some embodiments, the opposite sidewalls of the memory cell 126 are substantially aligned with the opposite sidewalls of the selector structure 144 and are respectively tilted relative to a line (not shown) perpendicular to the top surface of the bottom electrode through-hole 124. In other embodiments, the opposite straight sidewalls of the first electrode 128 are substantially aligned with the opposite straight sidewalls of the selector 146 and are respectively tilted relative to a line perpendicular to the top surface of the bottom electrode through-hole 124. In some other embodiments, the relative straight sidewalls of the second electrode 136, the relative straight sidewalls of the data storage layer 130, the relative sidewalls of the active metal layer 132, the relative sidewalls of the buffer layer 134, and the relative sidewalls of the third electrode 148 are substantially aligned and are respectively inclined relative to a line perpendicular to the top surface of the bottom electrode through hole 124.

[0036] The top electrode via 138 is disposed in the upper interconnect dielectric structure 122 and overlies the memory cell 126. In some embodiments, the top electrode via 138 may be or may include, for example, copper, aluminum, tungsten, another suitable conductive material, or any combination of the foregoing materials. The upper via 140 and the upper conductive wire 142 are disposed in the upper interconnect dielectric structure 122. The upper via 140 is disposed between the upper conductive wire 142 and the top electrode via 138. In some embodiments, the upper via 140 and the upper conductive wire 142 may be or may include, for example, copper, aluminum, tungsten, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing materials.

[0037] Figure 2B Show according to Figure 2A Some alternative embodiments of the memory device 200a are shown in cross-sectional views of some embodiments of the memory device 200b, in which the active metal layer ( Figure 2A As shown in 132).

[0038] like Figure 2BAs shown in , in some embodiments, the lower surface of the buffer layer 134 may directly contact the upper surface of the data storage layer 130, and the upper surface of the buffer layer 134 may directly contact the lower surface of the third electrode 148. The memory cell 126 is configured to store data and may be a non-voltage memory cell. In some embodiments, the memory cell 126 may be a resistance switching memory cell configured to store data based on the resistance state of the data storage layer 130, such as (for example) an RRAM cell, a phase-change random-access memory (PCRAM) cell, etc. For example, the data storage layer 130 may have a high resistance state associated with a first data state (e.g., binary "0") or a low resistance state associated with a second data state (e.g., binary "1"). In some embodiments, the data storage layer 130 may be or may include, for example, a chalcogenide, an oxide (e.g., silicon dioxide), a nitride, a high dielectric constant dielectric, some other suitable dielectric, or any combination of the foregoing materials. In various embodiments, when the memory cell 126 is configured as a PCRAM cell, the data storage layer 130 may be or may include, for example, a chalcogenide, sulfur (S), selenium (Se), tellurium (Te), selenium sulfide (SeS), germanium antimony telluride (GeSbTe), silver indium antimony telluride (AgInSbTe), etc., wherein the chalcogenide is composed of at least one chalcogen ion (e.g., a chemical element in column VI of the periodic table). In other embodiments, the data storage layer 130 may include a chalcogenide doped with one or more dopants such as, for example, boron, carbon, some other suitable dopant, or any combination of the foregoing dopants. In other embodiments, when the memory cell 126 is configured as an RRAM cell, the data storage layer 130 may be or may include, for example, a high-k dielectric (e.g., aluminum oxide, hafnium oxide, tantalum oxide), another suitable high-k dielectric, or any combination of the foregoing high-k dielectrics. In other embodiments, the memory cell 126 may be a magnetoresistive random-access memory (MRAM) cell. In such embodiments, the data storage layer 130 may include a magnetic tunnel junction (MTJ) configured to store data based on the magnetic orientation of the MTJ.

[0039] In some embodiments, during the fabrication of the memory cell 126, a first etching process (e.g., a first plasma etching including one or more fluorine-based etchants) is performed to form the second electrode 136. By providing the buffer layer 134 on the data storage layer 130, the formation and / or redeposition of byproducts (e.g., aluminum fluoride (e.g., AlF3)) from the data storage layer 130 and the one or more fluorine-based etchants on the outer sidewalls of the memory cell 126 are reduced. By reducing the formation of byproducts on / in the data storage layer 130, the durability and / or stability of the memory cell 126 can be improved. In addition, by reducing the redeposition of byproducts from the data storage layer 130, the outer sidewalls of the memory cell 126 are not electrically shorted together. This ensures, to a certain extent, that the memory cell 126 can be changed between a high resistance state and a low resistance state, thereby improving the performance and durability of the memory cell 126.

[0040] Figure 2C Show according to Figure 2B Some embodiments of the memory device 200c of some alternative embodiments of the memory device 200b are cross-sectional views in which the selector structure ( Figure 2B 144 ). In this embodiment, the data storage layer 130 is disposed between the first electrode 128 and the second electrode 136 , and the buffer layer 134 is disposed between the data storage layer 130 and the second electrode 136 .

[0041] Figure 2D Show according to Figure 2A Some embodiments of memory devices 200 d that are alternative embodiments of the memory device 200 a are cross-sectional views, wherein the maximum width of the third electrode 148 is smaller than the width of the buffer layer 134 .

[0042] Figure 3A A cross-sectional view of some embodiments of a memory device 300a is shown, the memory device 300a includes an embedded memory region 302a including a plurality of memory cells 126a to 126d and a logic region 302b laterally adjacent to the embedded memory region 302a.

[0043] In some embodiments, the embedded memory region 302a includes a dielectric layer 120 disposed on the lower interconnect dielectric structure 118. In various embodiments, the dielectric layer 120 may be referred to as an etch stop layer. The plurality of memory cells 126a to 126d are laterally disposed within the embedded memory region 302a and overlying the lower interconnect dielectric structure 118. In various embodiments, each of the memory cells 126a to 126d includes a second electrode 136, a data storage layer 130, an active metal layer 132, a buffer layer 134, and a third electrode 148. In yet other embodiments, each of the memory cells 126a to 126d may be configured as Figures 1A to 2D 1 and / or described in . In other embodiments, each of the memory cells 126a to 126d directly overlies the corresponding selector structure 144, so that each of the memory cells 126a to 126d and the corresponding selector structure 144 are part of the 1S1MC stack. In some embodiments, the selector structure 144 includes a selector 146 overlying the first electrode 128. In still other embodiments, the active metal layer 132 (not shown) of each of the memory cells 126a to 126d can be omitted, so that the buffer layer 134 directly contacts the upper surface of the data storage layer 130 (for example, see Figure 2B ). In some such embodiments, each of the memory cells 126a-126d may be configured as an RRAM cell, a PCRAM cell, an MRAM cell, or the like.

[0044] The upper interconnect dielectric structure 122 may be or may include, for example, a dielectric material such as silicon dioxide, silicon oxycarbide containing hydrogen (SiCOH), a low dielectric constant dielectric, an extremely low dielectric constant dielectric, other suitable dielectric materials, or any combination of the foregoing dielectric materials. The effective dielectric constant of the upper interconnect dielectric structure 122 is a function of the dielectric material included in the structure and the physical structure of the structure. For example, the upper interconnect dielectric structure 122 may have porosity and / or a plurality of air-gaps 304 that reduce the effective dielectric constant of the upper interconnect dielectric structure 122. In some embodiments, porosity is the void space distributed throughout the dielectric material, and air-gaps are larger voids in the dielectric layer that would otherwise be filled with dielectric material. The air-gaps 304 may be referred to as voids, pores, openings, etc. In some embodiments, the upper interconnect dielectric structure 122 may have an effective dielectric constant in the range of about 2 to 3.6 or in another suitable range. In yet other embodiments, the porosity of the upper interconnect dielectric structure 122 may be, for example, in a range of about 0.1% to 40% or another suitable value. The air gaps 304 are disposed between adjacent memory cells within the plurality of memory cells 126a to 126d and may be configured to reduce the effective dielectric constant of the upper interconnect dielectric structure 122, thereby reducing the capacitance between adjacent conductive structures (e.g., layers of memory cells 126a to 126d) within the upper interconnect dielectric structure 122. This is in part due to the dielectric constant of each air gap 304 being approximately 1. Therefore, by introducing the air gaps 304 between the plurality of memory cells 126a to 126d, the resistance-capacitance (RC) delay between adjacent conductive structures within the upper interconnect dielectric structure 122 is reduced, thereby improving the performance and reliability of the memory device 300a.

[0045] To increase the number of devices disposed on the substrate 102, the feature size of the memory cells 126a to 126d may be reduced and / or the lateral distance Ld between adjacent memory cells in the plurality of memory cells 126a to 126d may be reduced. In yet other embodiments, during operation of the memory cells 126a to 126d, when a set operation and / or a reset operation is performed on each memory cell 126a to 126d, heat may accumulate within and / or around the data storage layer 130. However, in an embodiment where the air gap 304 (not shown) is omitted, as the lateral distance Ld is reduced, heat from, for example, the first memory cell 126a may traverse the lateral distance Ld to the second memory cell 126b that is laterally adjacent to the first memory cell 126a. In such an embodiment, the lateral distance Ld may be referred to as a heat conduction path. This may cause thermal cross-talk between the first memory cell 126a and the second memory cell 126b, where heat from the first memory cell 126a is radiated to the second memory cell 126b. The thermal cross-talk may cause high heat to accumulate around the data storage layer 130 of each memory cell 126a to 126d, thereby causing charge leakage (i.e., leakage current) across each memory cell 126a to 126d, inconsistent data states across the memory cells 126a to 126d, and / or delamination between layers within each of the memory cells 126a to 126d. This may, to some extent, reduce the energy efficiency of the memory cells 126a to 126d, reduce the number of set operations and / or reset operations that can be performed on each memory cell 126a to 126d, and / or limit the size of the memory cells 126a to 126d. In an embodiment according to the present disclosure, by providing an air gap 304 between adjacent storage cells in the plurality of storage cells 126a to 126d, the heat conduction path (i.e., the path along which heat travels) between the adjacent storage cells is increased. For example, by providing a first air gap 304a between a first storage cell 126a and a second storage cell 126b, heat from the first storage cell 126a can cross the first heat conduction path 305 to reach the second storage cell 126b. This is because the thermal conductivity of each air gap 304 is less than the thermal conductivity of the dielectric material of the upper interconnect dielectric structure 122. In various embodiments, the heat conduction path between adjacent storage cells in the plurality of storage cells 126a to 126d is greater than the lateral distance Ld. For example, the first heat conduction path 305 is greater than the lateral distance Ld between the first storage cell 126a and the second storage cell 126b.Therefore, by setting air gaps 304 between adjacent memory cells among the multiple memory cells 126a to 126d, thermal crosstalk between the multiple memory cells 126a to 126d is reduced, thereby improving the durability of the memory cells 126a to 126d and reducing inconsistent data states at both ends of the multiple memory cells 126a to 126d.

[0046] In various embodiments, each of the memory cells 126a to 126d is configured as a PCRAM cell, so that the data storage layer 130 of each memory cell 126a to 126d may be or may include a phase change element (PCE) configured to switch between a crystalline phase and an amorphous phase. In such an embodiment, the active metal layer 132 (not shown) may be omitted. In addition, the PCE may be or may include, for example, a chalcogenide. During operation of the memory cells 126a to 126d, the bottom electrode via 124, the first electrode 128, and / or the second electrode 136 may be configured as a heating structure configured to apply heat to the PCE to change the PCE between an amorphous phase and a crystalline phase. For example, changing the PCE to a crystalline phase (e.g., performing a set operation) may be performed at a low temperature (e.g., about 460 Kelvin (K) to 500 Kelvin), and changing the PCE to an amorphous phase (e.g., performing a reset operation) may be performed at a high temperature (e.g., about 900K). The crystalline phase may correspond to a low resistance state (e.g., binary "1") and the amorphous phase may correspond to a high resistance state (e.g., binary "0"). Since the air gap 304 is disposed between the plurality of memory cells 126a to 126d, thermal isolation between the memory cells 126a to 126d is increased, thereby reducing inaccurate data states of each memory cell 126a to 126d. For example, the first air gap 304a may reduce thermal crosstalk between the first memory cell 126a and the second memory cell 126b, thereby preventing heat from a reset operation performed on the first memory cell 126a from changing the data state of the second memory cell 126b. This may improve the durability and performance of the memory device 300a.

[0047] The logic region 302b includes a bottom interconnect hole 306 disposed in the lower interconnect dielectric structure 118. A second via 308 is disposed in the upper interconnect dielectric structure 122 and overlies the bottom interconnect hole 306. In some embodiments, the second via 308 may be or may include, for example, ruthenium, copper, aluminum, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing materials. A second conductive wire 310 is disposed in the upper interconnect dielectric structure 122 and overlies the second via 308. In other embodiments, the second conductive wire 310 may be or may include, for example, ruthenium, copper, aluminum, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing materials.

[0048] Figure 3B Shown with Figure 3A Some alternative embodiments of the memory device 300a are cross-sectional views of some embodiments of the memory device 300b, wherein the selector structure ( Figure 3A In some other embodiments, the active metal layer 132 (not shown) of each memory cell 126a to 126d may be omitted so that the buffer layer 134 directly contacts the data storage layer 130 (see, for example, Figure 2C ). In some such embodiments, each of the memory cells 126a to 126d may be configured as an RRAM cell, a PCRAM cell, an MRAM cell, or the like.

[0049] FIG. 4A to FIG. 4C Various views of some embodiments of an integrated circuit (IC) 400 are shown having a plurality of 1-selector 1-memory cell (1S1MC) stacks 150 disposed between a plurality of word lines 403 and a plurality of bit lines 404 . Figure 4C Schematic diagrams showing some embodiments of the plurality of 1S1MC stacks 150 . Figure 4A Shown along Figure 4C A cross-sectional view of some embodiments of the integrated circuit 400 is shown taken along line AA′. Figure 4B Shown along Figure 4C Cross-sectional views of some alternative embodiments of the integrated circuit 400 are shown taken along line BB′.

[0050] The integrated circuit 400 includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) 405a and a second MOSFET 405b disposed on / in a semiconductor substrate 406. The first MOSFET 405a and the second MOSFET 405b each include a pair of source / drain regions 424 disposed in the semiconductor substrate 406 and laterally spaced apart. A gate dielectric layer 420 is disposed between the source / drain regions 424 over the semiconductor substrate 406, and a gate electrode 421 is disposed over the gate dielectric layer 420.

[0051] An inter-level dielectric (ILD) layer 412 is disposed over the first MOSFET 405a and the second MOSFET 405b and the semiconductor substrate 406. The ILD layer 412 includes one or more ILD materials. In some embodiments, the ILD layer 412 may be or may include one or more of a low-k dielectric layer, an extremely low-k dielectric layer, an oxide layer (e.g., a silicon dioxide layer), or the like. In addition, a conductive contact 414 is disposed within the ILD layer 412. The conductive contact 414 extends through the ILD layer 412 to the gate electrode 421 and the pair of source / drain regions 424. In various embodiments, the conductive contact 414 may be or may include, for example, copper, tungsten, aluminum, titanium, tantalum, some other suitable material, or any combination of the foregoing materials.

[0052] An interconnect structure 407 is disposed on the semiconductor substrate 406. The interconnect structure 407 includes a plurality of inter-metal dielectric (IMD) layers 418, a plurality of conductive wires 415, and a plurality of vias 416. The plurality of conductive wires 415 and the plurality of vias 416 are disposed within the plurality of IMD layers 418. The conductive wires 415 and the vias 416 are configured to provide electrical connections between various devices disposed throughout the integrated circuit 400. In some embodiments, the IMD layers 418 may each include a low-k dielectric layer, an extremely low-k dielectric layer, an oxide layer (e.g., a silicon dioxide layer), etc. In various embodiments, the conductive wires 415 and the vias 416 may be or may include, for example, copper, aluminum, tungsten, ruthenium, titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing materials.

[0053] In various embodiments, the plurality of 1S1MC stacks 150 are disposed within the interconnect structure 407. In various embodiments, the plurality of 1S1MC stacks 150 are disposed within one of the IMD layers 418. In other embodiments, the plurality of 1S1MC stacks 150 may be disposed within the plurality of IMD layers 418. In addition, the plurality of bit lines 404 are disposed within the IMD layer 418 and overly the plurality of 1S1MC stacks 150. The bit lines 404 are arranged parallel to each other and each extends laterally in a first direction. The plurality of word lines 403 are disposed within the IMD layer 418 and below the plurality of 1S1MC stacks 150. In some embodiments, the word lines 403 are arranged parallel to each other and each extends laterally in a second direction orthogonal to the first direction. In some embodiments, the bit lines 404 and the word lines 403 may be or may include, for example, aluminum, copper, tungsten, titanium, tantalum, some other suitable material, or any combination of the foregoing materials.

[0054] The plurality of 1S1MC stacks 150 are disposed between the plurality of word lines 403 and the plurality of bit lines 404 in a vertical direction. In some embodiments, the 1S1MC stacks 150 are arranged in an array having a plurality of rows and a plurality of columns. Individual bit lines in the plurality of bit lines 404 and individual word lines in the plurality of word lines 403 are coupled to each individual 1S1MC stack 150. In yet other embodiments, each of the 1S1MC stacks 150 includes a memory cell 126 overlying a selector structure 144. In some embodiments, the selector structure 144 includes a selector 146 and a first electrode 128, wherein the first electrode 128 is disposed between the selector 146 and the corresponding word line 403. In various embodiments, the memory cell 126 includes a second electrode 136, a data storage layer 130, a buffer layer 134, and a third electrode 148, wherein the buffer layer 134 is disposed between the data storage layer 130 and the corresponding bit line 404. In some other embodiments, an active metal layer (not shown) is disposed along the upper surface of the data storage layer 130 and is disposed between the buffer layer 134 and the data storage layer 130 in a vertical direction. In some alternative embodiments, the first electrode 128 (not shown) is omitted so that the selector 146 directly contacts the corresponding word line 403. In other embodiments, the third electrode 148 (not shown) is omitted so that the buffer layer 134 directly contacts the corresponding bit line 404. In some other embodiments, a plurality of air gaps (not shown) may be disposed between adjacent memory cells in the plurality of 1S1MC stacks 150 in one or more of the IMD layers 418 (e.g., as shown in FIG. 1 ). Figure 3A ).

[0055] In addition, if Figure 4B and Figure 4C, the buffer layer 134 and the data storage layer 130 each extend laterally in a first direction. In some embodiments, the outer sidewalls of the buffer layer 134 and the outer sidewalls of the data storage layer 130 are aligned with the outer sidewalls of the corresponding bit lines 404, respectively. In some embodiments, the buffer layer 134 and the data storage layer 130 extend laterally continuously over the plurality of word lines 403. In some embodiments, the third electrode 148 (not shown) of each 1S1MC stack 150 is omitted, so that the buffer layer 134 directly contacts the corresponding bit line 404 and extends continuously along the bottom surface of the corresponding bit line 404. In still other embodiments, the data storage structure of each of the memory cells 126 may be disposed within the data storage layer 130 between the corresponding bit line 404 and the underlying word line 403. In some such embodiments, the data storage structure of each of the memory cells 126 is defined by a portion of the data storage layer 130 laterally spaced apart between the outer sidewalls of the corresponding selector 146. The data storage structure of each of the memory cells 126 may have a high resistance state or a low resistance state.

[0056] Figures 5 to 11 Cross-sectional views 500 to 1100 of some embodiments of a method of forming a memory device having a memory cell including a buffer layer overlying a data storage layer are shown. Figures 5 to 11 500 to 1100 shown in FIG. 5 , however, it should be understood that Figures 5 to 11 The structure shown in is not limited to the method, but can be independently independent of the method. Figures 5 to 11 It is described as a series of actions, but it should be understood that these actions are not restrictive, the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0057] like Figure 5As shown in the cross-sectional view 500 of , a dielectric layer 120 is formed on the substrate 102, and a bottom electrode via 124 is formed in the dielectric layer 120. In some embodiments, the dielectric layer 120 may be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. In other embodiments, the method of forming the bottom electrode via 124 may include: patterning the dielectric layer 120 to form an opening in the dielectric layer 120; depositing (for example, by CVD, PVD, sputtering, electroless plating, electroplating, or another suitable deposition or growth process) a conductive material on the dielectric layer 120 so that the conductive material fills the opening; and performing a planarization process (for example, a chemical mechanical planarization (CMP) process) on the conductive material to form the bottom electrode via 124. In various embodiments, the substrate 102 may be or may include, for example, a semiconductor body such as a single crystal silicon / CMOS bulk, silicon-germanium (SiGe), silicon-on-insulator (SOI), or another suitable material.

[0058] like Figure 6 As shown in the cross-sectional view 600 of FIG. 6 , a memory cell layer stack 616 is formed over the dielectric layer 120 and the bottom electrode via 124. In some embodiments, the memory cell layer stack 616 includes a first electrode layer 602, a selector layer 604, a second electrode layer 606, a data storage structure 608, a conductive layer 610, a buffer film 612, and a third electrode layer 614. In various embodiments, the conductive layer 610 may be referred to as an active metal film or an active metal layer. In other embodiments, the buffer film 612 may be referred to as a buffer layer, a diffusion barrier film, a diffusion barrier layer, or a second conductive layer. In an alternative embodiment, the buffer film 612 extends along the top surface of the data storage structure 608 and directly contacts the top surface of the data storage structure 608. In some such embodiments, the conductive layer 610 may be omitted (not shown) so that the buffer film 612 is sandwiched between the data storage structure 608 and the third electrode layer 614. In some embodiments, the layers and / or structures within the memory cell layer stack 616 may be formed or deposited using a deposition process such as, for example, CVD, PVD, ALD, sputtering, co-sputtering, electroplating, electroless plating, or another suitable growth or deposition process. Furthermore, after forming the layers of the memory cell layer stack 616, a masking layer 618 may be formed over the memory cell layer stack 616. In various embodiments, the masking layer 618 may be or may include a photoresist, a hard mask layer, or the like.

[0059] In various embodiments, the first electrode layer 602, the second electrode layer 606, and the third electrode layer 614 may be or may include, for example, tungsten, titanium, tantalum, titanium nitride, some other suitable material, or any combination of the foregoing materials, respectively. In some embodiments, the data storage structure 608 may be or may include, for example, chalcogenide, oxide (e.g., silicon dioxide), nitride, high-k dielectric, some other suitable material, or any combination of the foregoing materials. In other embodiments, the conductive layer 610 may be or may include, for example, aluminum, copper, zirconium, tellurium, some other suitable material, or any combination of the foregoing materials. In yet other embodiments, the buffer film 612 may be or may include, for example, ruthenium, carbon, some other suitable material, or any combination of the foregoing materials. In some embodiments, the first electrode layer 602 may be referred to as a lower electrode layer, the second electrode layer 606 may be referred to as a middle electrode layer, and the third electrode layer 614 may be referred to as an upper electrode layer.

[0060] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , according to the masking layer 618, the third electrode layer ( Figure 6 614) to perform a first etching process to form a third electrode 148 on the buffer film 612. In some embodiments, the first etching process may include performing a first plasma etching process based on the mask layer 618 to remove the third electrode layer ( Figure 6 614) and exposes the upper surface of the buffer film 612 in a region laterally offset from the masking layer 618. In some such embodiments, the first plasma etching process includes: Figure 6 The first etchant 702 is exposed to one or more first etchants 702 (shown as buffer film 614). In various embodiments, the one or more first etchants 702 may include one or more fluorine-based etchants, such as, for example, nitrogen trifluoride (e.g., NF3), sulfur hexafluoride (e.g., SF6), carbon tetrafluoride (CF4), trifluoromethane (e.g., CHF3), difluoromethane (e.g., CH2F2), fluoromethane (e.g., CH3F), another suitable etchant, or any combination of the foregoing etchants. In various embodiments, since the first etching process stops on the buffer film 612, the first etching process does not contact the conductive layer 610 and / or the data storage structure 608, and will not cause the formation of byproducts (e.g., aluminum fluoride (e.g., AlF3)) on the upper surface of the conductive layer 610 and / or the upper surface of the data storage structure 608. Therefore, the buffer film 612 prevents the conductive layer 610 and / or the data storage structure 608 from being exposed to the one or more fluorine-based etchants.

[0061] In some other embodiments, the one or more fluorine-based etchants and the third electrode layer ( Figure 6614) and / or the buffer film 612, thereby forming a conductive material 704 along the upper surface of the buffer film 612, the sidewall of the third electrode 148 and / or the sidewall of the masking layer 618. In various embodiments, the conductive material 704 can be the one or more fluorine-based etchants and the third electrode layer ( Figure 6 614) and / or the buffer film 612. In still other embodiments, the buffer film 612 may be configured to prevent the conductive material 704 from diffusing into the conductive layer 610 and / or the data storage structure 608. In still other embodiments, the conductive material 704 may not be formed during the first etching process, so that the conductive material 704 is omitted (not shown).

[0062] like Figure 8 As shown in the cross-sectional view 800, Figure 7 After the first etching process, a wet cleaning process may be performed on the third electrode 148 and the buffer film 612. In various embodiments, the wet cleaning process may include removing the conductive material ( Figure 7 As shown in 704, the buffer film 612 and / or the third electrode 148 are exposed to, for example, hydrofluoric acid, deionized water or the like, thereby removing the conductive material ( Figure 7 704). Since the buffer film 612 extends continuously in the lateral direction over the upper surface of the conductive layer 610 and / or the data storage structure 608, the wet cleaning process may not damage the interface between the data storage structure 608 and the conductive layer 610 and / or the second electrode layer 606. This may alleviate the peeling between the layers of the memory cell layer stack 616 to a certain extent.

[0063] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , the buffer film ( Figure 8 612) and the underlying layers to define a 1S1MC stack 150 above the bottom electrode through hole 124. The 1S1MC stack 150 includes a memory cell 126 and a selector structure 144. In some embodiments, the memory cell 126 includes a second electrode 136, a data storage layer 130, an active metal layer 132, a buffer layer 134, and a third electrode 148. In some embodiments, the selector structure 144 includes a selector 146 and a first electrode 128. In some embodiments, the second etching process may include performing a second plasma etching process based on the masking layer 618 to remove the buffer film ( Figure 8 612), the conductive layer ( Figure 8 610), a portion of the data storage structure ( Figure 8 608), the second electrode layer ( Figure 8 606), the selector layer ( Figure 8604) and the first electrode layer ( Figure 8 In various embodiments, the second etching process includes: Figure 8 612) and the underlying layers are exposed to one or more second etchants 902. In various embodiments, the one or more second etchants 902 may be or may include, for example, chlorine (e.g., Cl2), boron trichloride (e.g., BCl3), sulfur dioxide (e.g., SO2), carbonyl sulfide (e.g., COS), hydrogen bromide (e.g., HBr), dioxygen (e.g., O2), another suitable etchant, or any combination of the foregoing etchants. In some embodiments, the one or more second etchants 902 do not contain fluorine, so that the one or more second etchants 902 do not include a fluorine-based etchant. In some such embodiments, due to the lack of a fluorine-based etchant in the one or more second etchants 902, the one or more second etchants 902 may not react with the buffer layer 134 and / or the underlying layers to form a conductive material along the sidewalls of the 1S1MC stack 150. This may, to a certain extent, reduce the shorting of the layers within the 1S1MC stack 150 together, thereby improving the performance, durability, and / or reliability of the memory cell 126. In various embodiments, the one or more first etchants ( Figure 7 702) is different from the one or more second etchants 902.

[0064] like Fig.10 As shown in the cross-sectional view 1000 of 1S1MC, a first intermetal dielectric (IMD) layer 1002 is formed above and around the 1S1MC stack 150. In some embodiments, the first IMD layer 1002 may be formed by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In other embodiments, the first IMD layer 1002 may be or may include, for example, silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, other suitable dielectric materials, or any combination of the foregoing materials. In addition, a top electrode via 138 is formed within the first IMD layer 1002 and above the 1S1MC stack 150. In various embodiments, the top electrode via 138 may be formed by a single damascene process or another suitable formation process. In some embodiments, the top electrode via 138 may be or may include, for example, copper, aluminum, tungsten, another suitable conductive material, or any combination of the foregoing materials.

[0065] like Fig.11As shown in the cross-sectional view 1100 of FIG. 1 , a second IMD layer 1102 is formed on the first IMD layer 1002. In some embodiments, the second IMD layer 1102 can be formed by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In other embodiments, the second IMD layer 1102 can be or can include, for example, silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or any combination of the foregoing materials. In addition, an upper via 140 and an upper conductive wire 142 are formed in the second IMD layer 1102 and on the top electrode through hole 138. In some embodiments, the upper via 140 and the upper conductive wire 142 can be or can include, for example, copper, aluminum, tungsten, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing materials. In other embodiments, the upper via 140 and / or the upper conductive wire 142 may each be formed by a single damascene process, a dual damascene process, or another suitable formation process.

[0066] Fig.12 A method 1200 of forming a storage device having a storage unit is shown, wherein the storage unit includes a buffer layer overlying a data storage layer. Although the method 1200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed separately or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0067] At act 1202, a bottom electrode via is formed over a substrate. Figure 5 Cross-sectional view 500 corresponding to some embodiments of act 1202 is shown.

[0068] At action 1204, a memory cell layer stack is formed on the bottom electrode via, wherein the memory cell layer stack includes a first electrode layer, a selector layer, a second electrode layer, a data storage structure, a conductive layer, a buffer film, and a third electrode layer. The buffer film is disposed on the data storage structure. Figure 6 Cross-sectional view 600 corresponding to some embodiments of act 1204 is shown.

[0069] At act 1206, a first etching process is performed on the third electrode layer to form a third electrode on the buffer film. The first etching process includes exposing the third electrode layer to one or more fluorine-based etchants. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1206 is shown.

[0070] At action 1208, a wet cleaning process is performed on the third electrode and the buffer film. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 1208 is shown.

[0071] At action 1210, a second etching process is performed on the buffer film and underlying layers to form a 1-selector 1-memory cell (1S1MC) stack above the bottom electrode via. The 1S1MC stack includes a first electrode, a selector, a second electrode, a data storage layer, an active metal layer, a buffer layer, and a third electrode. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1210 is shown.

[0072] At act 1212, a top electrode via is formed over the 1S1MC stack. Fig.10 Cross-sectional view 1000 corresponding to some embodiments of act 1212 is shown.

[0073] At act 1214, an upper via is formed over the top electrode through hole, and an upper conductive wire is formed over the upper via. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1214 is shown.

[0074] Therefore, in some embodiments, the present application relates to a memory cell including a first electrode, a data storage layer, a second electrode, and a buffer layer, wherein the buffer layer overlies the data storage layer.

[0075] In various embodiments, the present application provides a storage device, comprising: a substrate; a first electrode overlying the substrate; a data storage layer overlying the first electrode; a second electrode overlying the data storage layer, wherein a conductive bridge can be selectively formed within the data storage layer to couple the first electrode to the second electrode; an active metal layer disposed between the data storage layer and the second electrode; and a buffer layer disposed between the active metal layer and the second electrode, wherein the buffer layer has a lower reactivity with oxygen than the active metal layer.

[0076] In the above memory device, the buffer layer includes a first conductive material and the first electrode includes a second conductive material different from the first conductive material.

[0077] In the above storage device, an outer wall of the buffer layer is aligned with an outer wall of the data storage layer and an outer wall of the second electrode.

[0078] In the above storage device, the buffer layer includes a first conductive material and the active metal layer includes a second conductive material different from the first conductive material.

[0079] In the above storage device, the first conductive material includes carbon or ruthenium and the second conductive material includes aluminum, copper, zirconium or tellurium.

[0080] In the above memory device, the buffer layer directly contacts a bottom surface of the second electrode and directly contacts a top surface of the active metal layer.

[0081] The above storage device further includes: a bottom electrode through hole located below the first electrode; and a selector disposed between the bottom electrode through hole and the first electrode, wherein an outer side wall of the selector is aligned with an outer side wall of the buffer layer.

[0082] In the above-mentioned storage device, it also includes: a bit line, overlying the buffer layer and extending continuously in the laterally direction along a first direction, wherein the outer side wall of the buffer layer is aligned with the outer side wall of the bit line; and a plurality of word lines, located below the data storage layer and extending in a second direction, wherein the first direction is orthogonal to the second direction, wherein the plurality of word lines are spaced apart in the laterally direction between the outer side walls of the buffer layer.

[0083] In the above storage device, the data storage layer continuously extends in a lateral direction along the first direction, wherein an outer sidewall of the data storage layer is aligned with the outer sidewall of the buffer layer.

[0084] In various embodiments, the present application provides a storage device, which includes: a dielectric structure overlying a substrate; a selector structure disposed within the dielectric structure, wherein the selector structure includes a selector overlying a first electrode; and a first storage unit overlying the selector structure and disposed within the dielectric structure, wherein the first storage unit includes a second electrode, a data storage layer overlying the second electrode, a third electrode overlying the data storage layer, and a buffer layer disposed between the data storage layer and the third electrode, wherein the buffer layer includes a first conductive material and the third electrode includes a second conductive material different from the first conductive material.

[0085] The above-mentioned storage device also includes: a second storage unit, which is arranged in the dielectric structure and is laterally offset from the first storage unit by a non-zero distance; and an air gap, which is arranged in the dielectric structure, wherein the air gap is laterally arranged between the first storage unit and the second storage unit.

[0086] In the above memory device, the air gap continuously extends from above the top surface of the buffer layer to a point below the top surface of the selector structure.

[0087] In the above-mentioned storage device, it also includes: a dielectric layer located below the dielectric structure, wherein the dielectric layer continuously extends from the first storage unit to the second storage unit in the lateral direction, wherein the upper surface of the dielectric layer in the area directly below the air gap is U-shaped.

[0088] In the above storage device, the buffer layer contains ruthenium or carbon.

[0089] In the above storage device, an outer side wall of the buffer layer is aligned with an outer side wall of the selector.

[0090] In the above storage device, the data storage layer includes chalcogenide.

[0091] In various embodiments, the present application provides a method for forming a storage device, the method comprising: forming a bottom electrode through hole above a substrate; forming a storage cell layer stack above the bottom electrode through hole, wherein the storage cell layer stack comprises a lower electrode layer, a data storage structure, a buffer layer and an upper electrode layer, wherein the buffer layer is arranged between the data storage structure and the upper electrode layer; performing a first etching process on the upper electrode layer to form an upper electrode on the buffer layer, wherein the first etching process exposes the upper surface of the buffer layer; and performing a second etching process on the buffer layer, the data storage structure and the lower electrode layer to form a storage cell.

[0092] In the above method, the first etching process includes exposing the upper electrode layer to a first etchant, wherein the second etching process includes exposing the buffer layer, the data storage structure and the lower electrode layer to a second etchant, wherein the first etchant is different from the second etchant.

[0093] In the above method, the first etchant includes a fluorine-based etchant.

[0094] The method further includes: forming a conductive material along the upper surface of the buffer layer and the sidewall of the upper electrode by the first etching process; and performing a wet cleaning process to remove the conductive material.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device, comprising: substrate; a first electrode overlying the substrate; a data storage layer, overlying the first electrode; a second electrode overlying the data storage layer, wherein a conductive bridge can be selectively formed in the data storage layer to couple the first electrode to the second electrode; an active metal layer, disposed between the data storage layer and the second electrode; as well as a buffer layer disposed between the active metal layer and the second electrode, wherein the buffer layer has a lower reactivity with oxygen than the active metal layer, The outer wall of the buffer layer is aligned with the outer wall of the data storage layer and the outer wall of the second electrode, and the outer wall of the buffer layer, the outer wall of the data storage layer and the outer wall of the second electrode are in contact with the same dielectric layer. 2 . The memory device of claim 1 , wherein the buffer layer comprises a first conductive material and the first electrode comprises a second conductive material different from the first conductive material.

3. The storage device according to claim 1, wherein the first electrode, the data storage layer, the second electrode, the active metal layer and the buffer layer are embedded in the same dielectric layer, and the outer sidewalls of the first electrode and the active metal layer are aligned with the outer sidewall of the buffer layer. 4 . The memory device of claim 1 , wherein the buffer layer comprises a first conductive material and the active metal layer comprises a second conductive material different from the first conductive material. 5 . The memory device of claim 4 , wherein the first conductive material comprises carbon or ruthenium and the second conductive material comprises aluminum, copper, zirconium or tellurium. 6 . The memory device of claim 1 , wherein the buffer layer directly contacts a bottom surface of the second electrode and directly contacts a top surface of the active metal layer.

7. The storage device according to claim 1, further comprising: A bottom electrode through hole, located below the first electrode; as well as A selector is disposed between the bottom electrode through hole and the first electrode, wherein an outer sidewall of the selector is aligned with the outer sidewall of the buffer layer.

8. The storage device according to claim 1, further comprising: a bit line overlying the buffer layer and extending laterally continuously along a first direction, wherein the outer sidewall of the buffer layer is aligned with the outer sidewall of the bit line; as well as A plurality of word lines are located under the data storage layer and extend along a second direction, wherein the first direction is orthogonal to the second direction, wherein the plurality of word lines are laterally spaced apart between the outer sidewalls of the buffer layer. 9 . The memory device of claim 8 , wherein the data storage layer continuously extends in a laterally direction along the first direction, wherein the outer sidewall of the data storage layer is aligned with the outer sidewall of the buffer layer.

10. A storage device, comprising: a dielectric structure overlying the substrate; a selector structure disposed within the dielectric structure, wherein the selector structure includes a selector overlying the first electrode; as well as a first memory cell overlying the selector structure and disposed within the dielectric structure, wherein the first memory cell comprises a second electrode, a data storage layer overlying the second electrode, a third electrode overlying the data storage layer, and a buffer layer disposed between the data storage layer and the third electrode, wherein the buffer layer comprises a first conductive material and the third electrode comprises a second conductive material different from the first conductive material, The buffer layer extends in a first direction and has first side walls spaced apart from each other in the first direction and second side walls spaced apart from each other in a second direction orthogonal to the first direction, wherein the first side walls of the buffer layer protrude laterally beyond corresponding side walls of the selector structure, and the second side walls of the buffer layer are aligned with corresponding side walls of the selector structure.

11. The storage device according to claim 10, further comprising: a second storage unit disposed within the dielectric structure and laterally offset from the first storage unit by a non-zero distance; as well as An air gap is disposed in the dielectric structure, wherein the air gap is disposed laterally between the first memory cell and the second memory cell. 12 . The memory device of claim 11 , wherein the air gap extends continuously from above a top surface of the buffer layer to a point below a top surface of the selector structure.

13. The storage device according to claim 11, further comprising: A dielectric layer is located under the dielectric structure, wherein the dielectric layer continuously extends from the first memory cell to the second memory cell in a lateral direction, wherein an upper surface of the dielectric layer is U-shaped in a region directly below the air gap. The memory device according to claim 10 , wherein the buffer layer comprises ruthenium or carbon.

15. The memory device of claim 10, wherein the data storage layer comprises chalcogenide.

16. A method of forming a memory device, the method comprising: forming a bottom electrode via above the substrate; forming a memory cell layer stack on the bottom electrode through hole, wherein the memory cell layer stack comprises a lower electrode layer, a data storage structure, a buffer layer and an upper electrode layer, wherein the buffer layer is disposed between the data storage structure and the upper electrode layer; Performing a first etching process on the upper electrode layer to form an upper electrode on the buffer layer, wherein the first etching process exposes an upper surface of the buffer layer; as well as A second etching process is performed on the buffer layer, the data storage structure and the lower electrode layer to form a memory cell.

17. The method for forming a storage device according to claim 16, wherein the first etching process includes exposing the upper electrode layer to a first etchant, wherein the second etching process includes exposing the buffer layer, the data storage structure and the lower electrode layer to a second etchant, wherein the first etchant is different from the second etchant. 18 . The method for forming a memory device according to claim 17 , wherein the first etchant comprises a fluorine-based etchant.

19. The method for forming a memory device according to claim 18, further comprising: wherein the first etching process forms a conductive material along the upper surface of the buffer layer and the sidewall of the upper electrode; as well as A wet cleaning process is performed to remove the conductive material.

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