camera device

Abstract

An imaging device includes a first substrate, a second substrate, a third substrate, and a switching unit. The first substrate has pixels, each pixel including a photodiode and a floating diffuser for holding the charge converted by the photodiode. The second substrate has a pixel circuit for reading out a pixel signal based on the charge held in the floating diffuser of the pixel, and is stacked on the first substrate. The third substrate has a processing circuit for detecting the pixel signal read out by the pixel circuit, and is stacked on the second substrate. The switching unit enables electrical connection between the floating diffuser and the floating diffuser of another pixel in the first substrate, and is disposed in the second substrate. Therefore, the capacitance of the floating diffuser of the pixel can be switched by using the floating diffuser of another pixel, thereby switching the magnitude of the charge-to-voltage conversion efficiency.

Description

Technical Field

[0001] This invention relates to a camera device. Background Technology

[0002] In conventional technologies, miniaturization of the pixel area in two-dimensional imaging devices has been achieved due to the introduction of microfabrication processes and increased mounting density. In recent years, to further miniaturize imaging devices and increase pixel density, three-dimensional imaging devices have been developed. In three-dimensional imaging devices, for example, a semiconductor substrate comprising multiple sensor pixels and a semiconductor substrate comprising signal processing circuitry for processing signals obtained from each sensor pixel are stacked together.

[0003] List of existing literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-245506A Summary of the Invention

[0006] Technical problems to be solved

[0007] Incidentally, regarding camera devices with a three-dimensional structure, it is impractical to laminate the front surfaces of all semiconductor substrates together when stacking three layers of semiconductor chips. If three semiconductor substrates are arbitrarily stacked without sufficient consideration, the structure that electrically connects the semiconductor substrates may lead to an increase in chip size or hinder the miniaturization of pixel area. Therefore, it is desirable to provide a camera device with a three-layer structure that has a chip size equivalent to current chip sizes and does not hinder the miniaturization of pixel area.

[0008] Technical solutions to the problem

[0009] To address the aforementioned problems, the present invention provides an imaging device comprising a first substrate, a second substrate, a third substrate, and a switching unit. The first substrate includes pixels, each pixel comprising a photodiode and a floating diffuser configured to retain charge converted by the photodiode. The second substrate includes a pixel circuit that reads out a pixel signal from the pixel based on the charge retained in the floating diffuser. The second substrate is stacked on the first substrate. The third substrate includes a processing circuit that detects the pixel signal read out by the pixel circuit. The third substrate is stacked on the second substrate. The switching unit is configured to electrically connect the floating diffuser to a floating diffuser of another pixel in the first substrate. The switching unit is disposed in the second substrate.

[0010] Beneficial effects of the present invention

[0011] This invention allows for switching the FD capacitor according to the shooting environment without increasing the arrangement area of ​​the first substrate, thereby enabling the switching of the charge-to-voltage conversion efficiency. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example of the functional structure of a camera device according to an embodiment of the present invention.

[0013] Figure 2 It shows Figure 1 A schematic plan view of the general structure of the camera device shown.

[0014] Figure 3 It shows along Figure 2 A schematic diagram of the cross-sectional structure taken from line III-III′.

[0015] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0016] Figure 5 This is a diagram illustrating an example of the connection pattern between multiple pixel shared units and multiple vertical signal lines.

[0017] Figure 6 It shows Figure 3 A cross-sectional schematic diagram illustrating an example of the specific construction of the camera device shown.

[0018] Figure 7A It shows Figure 6 A schematic diagram illustrating an example of the planar structure of the main portion of the first substrate.

[0019] Figure 7B It shows Figure 7A A schematic diagram of the planar structure of the main part of the first substrate plus the pad portion.

[0020] Figure 8 It shows Figure 6 A schematic diagram of an example of a planar structure of the second substrate (semiconductor layer).

[0021] Figure 9 It shows Figure 6 The diagram shows an example of a planar structure consisting of the first wiring layer, pixel circuitry, and the main portion of the first substrate.

[0022] Figure 10 It shows Figure 6 A schematic diagram illustrating an example of the planar construction of the first and second wiring layers.

[0023] Figure 11 It shows Figure 6 A schematic diagram illustrating an example of the planar construction of the second and third wiring layers.

[0024] Figure 12 It shows Figure 6 A schematic diagram illustrating an example of the planar construction of the third and fourth wiring layers.

[0025] Figure 13 It shows the input signal to Figure 3 A schematic diagram of the circuitry of the camera device shown.

[0026] Figure 14 It shows Figure 13 A schematic diagram of the signal lines for the pixel signals of the camera device shown.

[0027] Figure 15 It shows Figure 8 A schematic diagram of a modified example of the planar structure of the second substrate (semiconductor layer) shown.

[0028] Figure 16 It shows Figure 15 The diagram shows a planar structure of the pixel circuit plus the main part of the first wiring layer and the first substrate.

[0029] Figure 17 It shows Figure 16 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0030] Figure 18 It shows Figure 17 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0031] Figure 19 It shows Figure 18 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0032] Figure 20 It shows Figure 7A A schematic diagram of a modified example of the planar structure of the first substrate shown.

[0033] Figure 21 It shows the layering in Figure 20 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0034] Figure 22 It shows Figure 21 The diagram shows an example of a planar structure for a pixel circuit plus a first wiring layer.

[0035] Figure 23 It shows Figure 22 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0036] Figure 24 It shows Figure 23 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0037] Figure 25 It shows Figure 24 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0038] Figure 26 It shows Figure 20 A schematic diagram of another example of the planar structure of the first substrate shown.

[0039] Figure 27 It shows the layering in Figure 26 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0040] Figure 28 It shows Figure 27 The diagram shows an example of a planar structure for a pixel circuit plus a first wiring layer.

[0041] Figure 29 It shows Figure 28 A schematic diagram illustrating an example of a planar configuration with a first wiring layer plus a second wiring layer.

[0042] Figure 30 It shows Figure 29 A schematic diagram illustrating an example of a planar configuration with a second wiring layer plus a third wiring layer.

[0043] Figure 31 It shows Figure 30 The diagram shows an example of a planar configuration with a third wiring layer plus a fourth wiring layer.

[0044] Figure 32 It shows Figure 3 A cross-sectional schematic diagram of another example of the camera device shown.

[0045] Figure 33 It shows the input signal to Figure 32 A schematic diagram of the circuitry of the camera device shown.

[0046] Figure 34 It shows Figure 32 A schematic diagram of the signal lines for the pixel signals of the camera device shown.

[0047] Figure 35 It shows Figure 6 A cross-sectional schematic diagram of another example of the camera device shown.

[0048] Figure 36 It shows Figure 4 A diagram of another example of the equivalent circuit shown.

[0049] Figure 37 It shows Figure 7A A schematic plan view of another example of the pixel separation section shown.

[0050] Figure 38 This is an equivalent circuit diagram showing an example of the construction of a pixel-shared unit for a comparative example.

[0051] Figure 39 This is an equivalent circuit diagram showing a construction example of the pixel sharing unit of Embodiment 2-1.

[0052] Figure 40 This is an equivalent circuit diagram showing an example of the construction of a pixel-shared unit for a comparative example.

[0053] Figure 41 This is an equivalent circuit diagram showing a construction example of the pixel sharing unit of Embodiment 3-1.

[0054] Figure 42 This diagram illustrates an example of the switching operation of the vertical signal line switch SW on the vertical signal line (the third selection transistor SEL3 is turned on).

[0055] Figure 43 This is a timing diagram illustrating an operational example of a pixel circuit.

[0056] Figure 44 This diagram illustrates an example of the switching operation of the vertical signal line switch SW on the vertical signal line (the second selection transistor SEL2 and the third selection transistor SEL3 are turned on).

[0057] Figure 45 This diagram illustrates an example of the switching operation of the vertical signal line switch SW on the vertical signal line (the first selection transistor SEL1 and the fourth selection transistor SEL4 are turned on).

[0058] Figure 46 This is an equivalent circuit diagram showing an example of the construction of the selection transistor SEL and the column signal processing unit in the pixel circuit of Embodiment 3-3.

[0059] Figure 47 This is a diagram illustrating a schematic construction example of a camera system including a camera device according to any of the foregoing embodiments and their variations.

[0060] Figure 48 It shows Figure 47 A diagram illustrating an example of the recording process of the camera system shown.

[0061] Figure 49 This is a block diagram illustrating an example of a schematic structure of a vehicle control system.

[0062] Figure 50 This diagram shows an example of the installation location of the vehicle exterior information detection unit and the camera unit.

[0063] Figure 51 This is a diagram illustrating an example of the general structure of an endoscopic surgical system.

[0064] Figure 52 This is a block diagram illustrating an example of the functional structure of a camera head and a CCU (camera control unit). Detailed Implementation

[0065] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, the same reference numerals denote the same parts, and repeated descriptions are omitted.

[0066] In the following, embodiments for carrying out the invention will be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.

[0067] 1. Example 1 (Imaging device with a stacked structure of three substrates)

[0068] 2. First variation example (planar construction example 1)

[0069] 3. Second variation (planar construction example 2)

[0070] 4. Third variation (planar construction example 3)

[0071] 5. Fourth variation (example having a substrate contact portion disposed in the central portion of the pixel array portion)

[0072] 6. Fifth variation (example with planar transmission transistor)

[0073] 7. Sixth variation (example of one pixel connected to one pixel circuit)

[0074] 8. Seventh variation (example of pixel separation section construction)

[0075] 9. Example 2

[0076] 9.1 Problems to be solved by Example 2

[0077] 9.2 Summary of Example 2

[0078] 9.3 Specific examples of Example 2-1

[0079] 9.3.1 Construction of Example 2-1

[0080] 9.3.2 Function and Effect of Example 2-1

[0081] 9.4 Modifications to Example 2

[0082] 10. Example 3

[0083] 10.1 Problems to be solved by Example 3

[0084] 10.2 Summary of Example 3

[0085] 10.3 Specific examples of Example 3-1

[0086] 10.3.1 Construction of Example 3-1

[0087] 10.3.2 Function and Effect of Example 3-1

[0088] 10.4 Specific examples of Example 3-2

[0089] 10.4.1 Construction of Example 3-2

[0090] 10.4.2 Functions and Effects of Example 3-2

[0091] 10.5 Specific examples of 3-3

[0092] 10.5.1 Construction of Example 3-3

[0093] 10.5.2 Functions and Effects of Examples 3-3

[0094] 11. Application Example (Camera System)

[0095] 12. Examples of pixel circuit applications in products

[0096] <1. Example 1>

[0097] [Functional Structure of Camera Device 1]

[0098] Figure 1 This is a block diagram illustrating an example of the functional structure of a camera device (camera device 1) according to an embodiment of the present invention.

[0099] For example, Figure 1 The camera device 1 includes an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0100] The pixel array section 540 includes pixels 541 arranged in an array-like repeating pattern. More specifically, the pixel sharing unit 539, containing multiple pixels, is a repeating unit, and it is arranged in an array-like repeating pattern in both the row and column directions. In this specification, for convenience, the row direction is sometimes referred to as the H direction, and the column direction, orthogonal to the row direction, is referred to as the V direction. Figure 1 In the example, a pixel-shared unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Pixels 541A, 541B, 541C, and 541D each include a photodiode PD (described below). Figure 6 (As shown below). Pixel sharing unit 539 shares a single pixel circuit (described below). Figure 4 The pixel array unit 540 comprises a pixel circuit 210. In other words, every four pixels (pixels 541A, 541B, 541C, and 541D) share one pixel circuit (pixel circuit 210 as described below). By operating the pixel circuit in a time-division manner, the pixel signals of each of the pixels 541A, 541B, 541C, and 541D are read out sequentially. For example, pixels 541A, 541B, 541C, and 541D are arranged in two rows × two columns. In addition to pixels 541A, 541B, 541C, and 541D, the pixel array unit 540 also includes multiple row drive signal lines 542 and multiple vertical signal lines (column readout lines) 543. The row drive signal lines 542 are used to drive the pixels 541 included in each of the multiple pixel sharing units 539 arranged side by side in the row direction in the pixel array unit 540. Thus, each pixel arranged side by side in the row direction in the pixel sharing unit 539 is driven. See below for reference. Figure 4 As detailed in the description, the pixel sharing unit 539 is provided with multiple transistors. To drive each of the multiple transistors individually, multiple row drive signal lines 542 are connected to a pixel sharing unit 539. The pixel sharing unit 539 is also connected to vertical signal lines (column readout lines) 543. Pixel signals are read out from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal lines (column readout lines) 543.

[0101] For example, the row driving unit 520 includes a row address control unit (i.e., a row decoder unit) and a row driving circuit unit, the row address control unit determining the position of the row for pixel driving, and the row driving circuit unit generating signals for driving pixels 541A, 541B, 541C and 541D.

[0102] The column signal processing unit 550 includes a load circuit section connected to the vertical signal line 543 and forming a source follower circuit together with pixels 541A, 541B, 541C, and 541D (pixel shared unit 539). The column signal processing unit 550 may include an amplifier circuit section that amplifies the signal read from the pixel shared unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing section. For example, the noise processing section removes the system noise level from the signal read from the pixel shared unit 539 as a result of photoelectric conversion.

[0103] For example, the column signal processing unit 550 includes an analog-to-digital converter (ADC). The ADC converts the signal read from the pixel sharing unit 539 or the analog signal after noise processing as described above into a digital signal. For example, the ADC includes a comparator section and a counter section. The comparator section compares the analog signal to be converted with a reference signal to be compared. The counter section is configured to count the time until the comparison result in the comparator section is inverted. The column signal processing unit 550 may include a horizontal scanning circuit section that controls the scanning of the readout column.

[0104] Based on the reference clock signal and timing control signal input to the device, the timing control unit 530 supplies signals for controlling the timing to the row drive unit 520 and the column signal processing unit 550.

[0105] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, that is, data obtained as a result of imaging operation in the imaging device 1. For example, the image signal processing unit 560 includes an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0106] An example of signal processing performed in the image signal processing unit 560 is tone curve correction processing, wherein when the image data after AD conversion is obtained by photographing a darker subject, the tone levels are increased; and when the image data after AD conversion is obtained by photographing a brighter subject, the tone levels are decreased. In this case, it is preferable that the image signal processing unit 560 pre-stores characteristic data of the tone curve in its data holding unit, which relates to which tone curve to use to correct the tone levels of the image data.

[0107] The input unit 510A is a component used to input the aforementioned reference clock signal, timing control signal, characteristic data, etc., from outside the device to the imaging device 1. For example, the timing control signal is a vertical synchronization signal, a horizontal synchronization signal, etc. For example, the characteristic data is data to be stored in the data holding section of the image signal processing unit 560. For example, the input unit 510A includes an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0108] Input terminal 511 is an external terminal for inputting data. Input circuit section 512 is a component for capturing signals input to input terminal 511 into the camera device 1. Input amplitude conversion section 513 converts the amplitude of the signal captured by input circuit section 512 into an amplitude more easily used within the camera device 1. Input data conversion circuit section 514 changes the arrangement of the data string of the input data. For example, input data conversion circuit section 514 includes a serial-to-parallel conversion circuit. This serial-to-parallel conversion circuit converts the serial signal received as input data into a parallel signal. It should be noted that input section 510A may omit input amplitude conversion section 513 and input data conversion circuit section 514. Power supply section supplies power to various voltages required within the camera device 1 based on power supplied from the outside to the camera device 1.

[0109] When the camera device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. Examples of external memory devices include flash memory, SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), etc.

[0110] The output unit 510B outputs image data to an external device. Examples of image data include image data captured by the camera device 1, and image data that has been processed by the image signal processing unit 560. For example, the output unit 510B includes an output data conversion circuit unit 515, an output amplitude conversion unit 516, an output circuit unit 517, and an output terminal 518.

[0111] For example, the output data conversion circuit 515 includes a parallel-to-serial conversion circuit. The output data conversion circuit 515 converts parallel signals used inside the camera device 1 into serial signals. The output amplitude changing unit 516 changes the amplitude of the signal used inside the camera device 1. This makes the amplitude-changed signal easier to use in external devices connected to the camera device 1. The output circuit 517 is a circuit for outputting data from inside the camera device 1 to the outside of the device. The output circuit 517 drives the wiring connected to the output terminal 518 outside the camera device 1. The output terminal 518 outputs data from the camera device 1 to the outside of the device. The output unit 510B can omit the output data conversion circuit 515 and the output amplitude changing unit 516.

[0112] When the camera device 1 is connected to an external storage device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external storage device. Examples of external storage devices include flash memory drives, SRAM, and DRAM.

[0113] [Brief Structure of Camera Device 1]

[0114] Figure 2 and Figure 3 An example of the schematic structure of the camera device 1 is shown. The camera device 1 includes three substrates (first substrate 100, second substrate 200 and third substrate 300). Figure 2 The planar structure of the first substrate 100, the second substrate 200 and the third substrate 300 is schematically shown. Figure 3 The cross-sectional structure of the first substrate 100, the second substrate 200 and the third substrate 300 stacked on top of each other is schematically shown. Figure 3 Corresponding to along Figure 2The cross-sectional structure is shown by line III-III′. The imaging device 1 is a three-dimensional structure formed by bonding three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of wiring and the interlayer insulating film surrounding the wiring included in each of the first substrate 100, second substrate 200, and third substrate 300 is collectively referred to as the wiring layers (100T, 200T, and 300T) provided in each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. Specifically, these layers are stacked in the following order in the stacking direction: semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S. The specific structures of the first substrate 100, the second substrate 200, and the third substrate 300 will be described below. Figure 3 The arrows shown indicate the incident direction of light L on the imaging device 1. For convenience, in the cross-sectional views below this specification, the light incident side of the imaging device 1 may be referred to as "lower," "below side," or "below," and the side opposite to the light incident side may be referred to as "upper," "upper side," or "above." Furthermore, for convenience, in this specification, in a substrate including a semiconductor layer and a wiring layer, the side of the substrate near the wiring layer may be referred to as the front side, and the side of the substrate near the semiconductor layer may be referred to as the back side. The descriptions in this specification are not limited to the above designations. For example, the imaging device 1 is a back-illuminated type imaging device in which light is incident from the back side of a first substrate 100 having a photodiode.

[0115] Both the pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are constructed using a first substrate 100 and a second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each of these pixels 541 includes a photodiode (hereinafter referred to as a photodiode PD) and a transmission transistor (hereinafter referred to as a transmission transistor TR). The second substrate 200 is provided with pixel circuitry (pixel circuitry 210, which will be described below) included in the pixel sharing unit 539. The pixel circuitry reads pixel signals transmitted from the photodiodes of each of the pixels 541A, 541B, 541C, and 541D via the transmission transistors, or resets the photodiodes. In addition to this pixel circuitry, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes power lines 544 extending in the row direction. For example, the third substrate 300 includes an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. For example, the row driving section 520 is disposed in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the second substrate 200. More specifically, the row driving section 520 is disposed in a region that overlaps with the end of the pixel array section 540 in the H direction in the stacking direction. Figure 2 For example, the column signal processing unit 550 is disposed in a region that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is disposed in a region that overlaps with the end of the pixel array unit 540 in the V direction in the stacking direction. Figure 2 Although not shown, the input section 510A and the output section 510B can be arranged in a portion other than the third substrate 300, for example, in the second substrate 200. Alternatively, the input section 510A and the output section 510B can be provided on the back side (light incident surface) of the first substrate 100. Incidentally, the pixel circuit provided in the second substrate 200 described above may in some cases be alternatively referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this specification, the term "pixel circuit" is used.

[0116] For example, the first substrate 100 and the second substrate 200 are connected by through electrodes (described below). Figure 6The through electrodes 120E and 121E are electrically connected. For example, the second substrate 200 and the third substrate 300 are electrically connected via contact portions 201, 202, 301, and 302. Contact portions 201 and 202 are disposed on the second substrate 200, while contact portions 301 and 302 are disposed on the third substrate 300. Contact portion 201 of the second substrate 200 contacts contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 contacts contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R including multiple contact portions 201 and a contact region 202R including multiple contact portions 202. The third substrate 300 has a contact region 301R including multiple contact portions 301 and a contact region 302R including multiple contact portions 302. Contact areas 201R and 301R are positioned between the pixel array section 540 and the row drive section 520 in the stacking direction. Figure 3 In other words, for example, contact regions 201R and 301R are disposed in or near a region in which the row drive portion 520 (on the third substrate 300) and the pixel array portion 540 (on the second substrate 200) overlap each other in the stacking direction. For example, contact regions 201R and 301R are arranged at the ends of these regions in the H direction. Figure 2 In the third substrate 300, for example, the contact region 301R is provided at a position on the third substrate 300 that overlaps with a portion of the line drive unit 520, specifically, at a position that overlaps with the end of the line drive unit 520 in the H direction. Figure 2 and Figure 3 For example, contact portions 201 and 301 connect the row drive portion 520 disposed on the third substrate 300 and the row drive signal line 542 disposed on the second substrate 200 to each other. For example, contact portions 201 and 301 can connect the input portion 510A disposed on the third substrate 300 to the power supply line 544 and the reference potential line (the reference potential line VSS described below) to each other. Contact regions 202R and 302R are disposed between the pixel array portion 540 and the column signal processing portion 550 in the stacking direction. Figure 3 In other words, for example, contact regions 202R and 302R are disposed in or near regions where the signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap each other in the stacking direction. For example, contact regions 202R and 302R are arranged at the ends of these regions in the V direction. Figure 2 In the third substrate 300, for example, the contact region 302R is provided at a position on the third substrate 300 that overlaps with a portion of the column signal processing unit 550, specifically, at a position that overlaps with the end of the column signal processing unit 550 in the V direction. Figure 2 and Figure 3 Contact portions 202 and 302 are configured to connect pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array portion 540 to a column signal processing unit 550 provided on the third substrate 300. In this way, pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0117] Figure 3 This is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connection portion suitable for electrically connecting the second substrate 200 and the third substrate 300 to each other. Specifically, contact portions 201, 202, 301, and 302 are constructed using electrodes formed of a conductive material. For example, the conductive material is formed of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). By directly joining, for example, the wiring portions formed as electrodes, contact regions 201R, 202R, 301R, and 302R electrically connect the second and third substrates to each other, thereby enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0118] An electrical connection portion for electrically connecting the second substrate 200 and the third substrate 300 to each other can be provided at a desired location. For example, such as... Figure 3 As shown in contact areas 201R, 202R, 301R, and 302R, the electrical connection portion can be located in an area that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion can be located in an area that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion can be located in an area that overlaps with the peripheral portion arranged outside the pixel array portion 540 in the stacking direction.

[0119] For example, connection holes H1 and H2 are provided in the first substrate 100 and the second substrate 200. Connection holes H1 and H2 penetrate through the first substrate 100 and the second substrate 200. Figure 3 The connecting holes H1 and H2 are located on the outer side of the pixel array section 540 (or the portion overlapping with the pixel array section 540). Figure 2For example, connection hole H1 is arranged outside the pixel array portion 540 in the H direction, while connection hole H2 is arranged outside the pixel array portion 540 in the V direction. For example, connection hole H1 reaches the input portion 510A provided in the third substrate 300, while connection hole H2 reaches the output portion 510B provided in the third substrate 300. Connection holes H1 and H2 may be hollow or may contain at least a portion of conductive material. For example, there is a configuration in which each electrode formed as the input portion 510A and / or the output portion 510B is connected to a bonding wire. Alternatively, there is a configuration in which the electrode formed as the input portion 510A and / or the output portion 510B is connected to the conductive material provided in connection holes H1 and H2. The conductive material provided in connection holes H1 and H2 may be embedded in a portion or the entirety of connection holes H1 and H2, or the conductive material may be formed on the sidewalls of connection holes H1 and H2.

[0120] Figure 3 This describes a structure in which the input portion 510A and the output portion 510B are disposed on the third substrate 300, but the present invention is not limited thereto. For example, by transmitting signals from the third substrate 300 to the second substrate 200 via wiring layers 200T and 300T, the input portion 510A and / or the output portion 510B can be disposed on the second substrate 200. Similarly, by transmitting signals from the second substrate 200 to the first substrate 100 via wiring layers 100T and 200T, the input portion 510A and / or the output portion 510B can be disposed on the first substrate 100.

[0121] Figure 4 This is an equivalent circuit diagram illustrating a construction example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 4 Four pixels 541 (i.e., pixels 541A, 541B, 541C, and 541D) are shown, along with a pixel circuit 210 connected to the plurality of pixels 541 and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes four transistors, specifically, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, by allowing the pixel circuit 210 to operate in a time-division manner, the pixel sharing unit 539 is configured to sequentially output the pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The mode in which a pixel circuit 210 is connected to a plurality of pixels 541, and the pixel signals of each of the plurality of pixels 541 are output by the pixel circuit 210 in a time-division manner, is referred to as the mode in which "a plurality of pixels 541 share a pixel circuit 210".

[0122] Pixels 541A, 541B, 541C, and 541D each contain the same constituent elements. In the following text, to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from one another, identifier 1 is assigned to the end of the symbol of the constituent element of pixel 541A, identifier 2 is assigned to the end of the symbol of the constituent element of pixel 541B, identifier 3 is assigned to the end of the symbol of the constituent element of pixel 541C, and identifier 4 is assigned to the end of the symbol of the constituent element of pixel 541D. When it is not necessary to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from one another, the identifiers at the end of the symbol of the constituent elements of pixels 541A, 541B, 541C, and 541D are omitted.

[0123] For example, pixels 541A, 541B, 541C, and 541D each include: a photodiode PD, a transmission transistor TR electrically connected to the photodiode PD, and a floating diffuser FD electrically connected to the transmission transistor TR. The photodiode PD (PD1, PD2, PD3, PD4) has: a cathode electrically connected to the source of the transmission transistor TR; and an anode electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates a charge corresponding to the amount of received light. For example, the transmission transistor TR (transmission transistor TR1, TR2, TR3, or TR4) is an N-type complementary metal-oxide-semiconductor (CMOS) transistor. The transmission transistor TR has: a drain electrically connected to the floating diffuser FD; and a gate electrically connected to a drive signal line. This drive signal line is a plurality of row drive signal lines 542 connected to a pixel shared unit 539 (see [link to pixel name]). Figure 1 Part of the p-type semiconductor layer. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffuser FD. The floating diffuser FD (including floating diffusers FD1, FD2, FD3, or FD4) is an n-type diffusion layer region formed in the p-type semiconductor layer. The floating diffuser FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD, and a charge-to-voltage conversion device that generates a voltage corresponding to the amount of charge.

[0124] The four floating diffusers FD (FD1, FD2, FD3, and FD4) included in a pixel shared unit 539 are electrically connected to each other and to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The gate of the amplifying transistor AMP is connected to the floating diffuser FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 543, and the gate of the select transistor SEL is connected to the drive signal line. The drive signal line is part of a plurality of row drive signal lines 542 connected to a pixel shared unit 539.

[0125] When the transfer transistor TR is turned on, it transfers the charge from the photodiode PD to the floating diffuser FD. This is explained below. Figure 6 As shown, the gate (transfer gate TG) of the transfer transistor TR includes an electrode referred to as a vertical electrode, and is configured to connect from the semiconductor layer (which will be described below). Figure 6 The semiconductor layer 100S extends from the front side to the depth of the PD. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffuser FD is reset to the potential of the power supply line VDD. The select transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifying transistor AMP generates a voltage signal corresponding to the level of charge held in the floating diffuser FD as a pixel signal. The amplifying transistor AMP is connected to the vertical signal line 543 via the select transistor SEL. The amplifying transistor AMP and the load circuit section in the column signal processing unit 550 connected to the vertical signal line 543 (see [link to relevant documentation]) Figure 1 Together, they form a source follower. When the select transistor SEL is turned on, the amplifying transistor AMP outputs the voltage of the floating diffuser FD to the column signal processing unit 550 via the vertical signal line 543. For example, the reset transistor RST, the amplifying transistor AMP, and the select transistor SEL are N-type CMOS transistors.

[0126] The FD gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffuser FD. Typically, when shooting in low light, the pixel signal is weak. In the case of charge-to-voltage conversion based on Q=CV, if the capacitance of the floating diffuser FD (FD capacitance C) is large, this will result in a smaller V obtained when converted to voltage by the amplifying transistor AMP. On the other hand, in bright light, the pixel signal has greater intensity, so unless the FD capacitance C is sufficiently large, it is difficult to completely retain the charge of the photodiode PD at the floating diffuser FD. Furthermore, the FD capacitance C needs to be large enough so that the V obtained when converted to voltage by the amplifying transistor AMP does not become too high (in other words, to make V small). Given these factors, when the FD gain switching transistor FDG is turned on, the FD capacitance C increases by an amount equivalent to the gate capacitance of the FDG. This causes the overall FD capacitance C to increase. Conversely, when the FD gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, switching the FD conversion gain switching transistor FDG on / off makes the FD capacitor C variable, thus allowing the conversion efficiency to be switched. For example, the FD conversion gain switching transistor FDG is an N-type CMOS transistor.

[0127] It should be noted that a configuration can also be adopted in which the FD conversion gain switching transistor FDG is not provided. In this case, for example, pixel circuit 210 includes three transistors, such as amplifying transistor AMP, selecting transistor SEL, and resetting transistor RST. For example, pixel circuit 210 includes at least one of pixel transistors such as amplifying transistor AMP, selecting transistor SEL, resetting transistor RST, and FD conversion gain switching transistor FDG.

[0128] The select transistor SEL can also be positioned between the power supply line VDD and the amplifying transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to both the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifying transistor AMP, and the gate of the select transistor SEL is electrically connected to the horizontal drive signal line 542 (see [link to relevant documentation]). Figure 1 The source of the amplifying transistor AMP (output of pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that, although not shown, the number of pixels 541 sharing a single pixel circuit 210 is not necessarily four. For example, two or eight pixels 541 may share a single pixel circuit 210.

[0129] Figure 5An example of the connection pattern between multiple pixel shared units 539 and vertical signal lines 543 is shown. For example, four pixel shared units 539 arranged in a column direction are divided into four groups, and each vertical signal line 543 is connected to a corresponding one of these four groups. For the sake of simplicity, Figure 5 An example is shown in which each of the four groups includes one pixel sharing unit 539, but each of the four groups may also include multiple pixel sharing units 539. Thus, in the imaging device 1, the multiple pixel sharing units 539 arranged in the column direction can be divided into groups, each including one or more pixel sharing units 539. For example, each vertical signal line 543 and each column signal processing unit 550 are connected to a corresponding one of these groups, thereby allowing pixel signals to be read out simultaneously from each corresponding group. Alternatively, in the imaging device 1, a vertical signal line 543 can be connected to the multiple pixel sharing units 539 arranged in the column direction. Then, pixel signals are sequentially read out from the multiple pixel sharing units 539 connected to a vertical signal line 543 in a time-division manner.

[0130] [Detailed Structure of Camera Device 1]

[0131] Figure 6 An example of the cross-sectional structure of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 in a direction perpendicular to the main surface is shown. For ease of understanding, Figure 6 The positional relationship between the constituent elements is schematically shown, and the cross-section shown may differ from the actual cross-section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 also includes a light-receiving lens 401 disposed on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may also be disposed between the light-receiving lens 401 and the first substrate 100. For example, the light-receiving lens 401 is disposed on each of pixels 541A, 541B, 541C, and 541D. For example, the imaging device 1 is a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 disposed in the central portion and a peripheral portion 540B disposed outside the pixel array portion 540.

[0132] The first substrate 100, starting from the light-receiving lens 401 side, sequentially includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. For example, the semiconductor layer 100S is formed from a silicon substrate. For example, the semiconductor layer 100S includes a p-well layer 115 disposed on a portion of its front side (the surface on the side of the wiring layer 100T) and its vicinity, and the semiconductor layer 100S includes an n-type semiconductor region 114 disposed in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode (PD). The p-well layer 115 is a p-type semiconductor region.

[0133] Figure 7A An example of a planar structure of the first substrate 100 is shown. Figure 7A The planar structure of the pixel separation section 117, photodiode PD, floating diffusion section FD, VSS contact area 118, and transmission transistor TR of the first substrate 100 is mainly shown. (Refer to...) Figure 7A And combined Figure 6 Let's explain the structure of the first substrate 100 together.

[0134] The floating diffuser FD and VSS contact region 118 are disposed near the front side of the semiconductor layer 100S. The floating diffuser FD is formed from an n-type semiconductor region disposed in the p-well layer 115. For example, the floating diffusers FD (floating diffusers FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D are disposed close to each other in the central portion of the pixel common unit 539. Figure 7A As will be described in detail below, the four floating diffusion sections (floating diffusion sections FD1, FD2, FD3, and FD4) included in the pixel common unit 539 are electrically connected to each other in the first substrate 100 (more specifically, in the wiring layer 100T) via electrical connection members (pads 120 described below). Furthermore, each floating diffusion section FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical members (through electrodes 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion sections FD are electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via these electrical members.

[0135] VSS contact area 118 is the area electrically connected to the reference potential line VSS and is arranged away from the floating diffuser FD. For example, in pixels 541A, 541B, 541C, and 541D, the floating diffuser FD is arranged at one end of the pixel in the V direction, and the VSS contact area 118 is arranged at the other end of the pixel in the V direction. Figure 7A For example, the VSS contact region 118 is formed of a p-type semiconductor region. For example, the VSS contact region 118 is connected to a ground potential or a fixed potential. This configuration allows a reference potential to be supplied to the semiconductor layer 100S.

[0136] In addition to photodiodes PD, floating diffusers FD, and VSS contact regions 118, the first substrate 100 also includes a transmission transistor TR. These photodiodes PD, floating diffusers FD, VSS contact regions 118, and transmission transistor TR are disposed in individual pixels 541A, 541B, 541C, and 541D. The transmission transistor TR is disposed on the front side of the semiconductor layer 100S (the side opposite to the light incident surface, or the side of the second substrate 200). The transmission transistor TR includes a transmission gate TG. For example, the transmission gate TG includes a horizontal portion TGb facing the front side of the semiconductor layer 100S and a vertical portion TGa disposed in the semiconductor layer 100S. The vertical portion TGa extends along the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end is disposed in the n-type semiconductor region 114. By using this vertical transistor transmission transistor TR configuration, pixel signal transmission defects can be suppressed, and pixel signal readout efficiency can be improved.

[0137] For example, the horizontal portion TGb of the transmission gate TG extends from a position facing the vertical portion TGA, for example, in the H direction toward the central portion of the pixel shared unit 539. Figure 7A According to this configuration, the position of the through electrode (hereinafter referred to as through electrode TGV) reaching the transmission gate TG in the H direction is close to the position of the through electrode (hereinafter referred to as through electrode 120E and 121E) connected to the floating diffusion portion FD and VSS contact region 118 in the H direction. For example, the plurality of pixel shared units 539 provided in the first substrate 100 have the same configuration. Figure 7A ).

[0138] The semiconductor layer 100S has a pixel separation portion 117 that separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction (the direction perpendicular to the front surface of the semiconductor layer 100S) of the semiconductor layer 100S. For example, the pixel separation portion 117 is configured to separate pixels 541A, 541B, 541C, and 541D from each other and has a grid-like planar shape. Figure 7A and Figure 7B For example, pixel separation unit 117 electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other. For example, pixel separation unit 117 includes a light-shielding film 117A and an insulating film 117B. For example, the light-shielding film 117A is formed using tungsten (W) or the like. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. For example, the insulating film 117B is formed of silicon oxide (SiO). For example, pixel separation unit 117 has a full trench isolation (FTI) structure and extends through the semiconductor layer 100S. Although not shown, pixel separation unit 117 is not limited to an FTI structure extending through the semiconductor layer 100S. For example, pixel separation unit 117 can use a deep trench isolation (DTI) structure that does not extend through the semiconductor layer 100S. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0139] For example, the semiconductor layer 100S includes a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side surface of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. For example, the first pinning region 113 and the second pinning region 116 are formed of a p-type semiconductor region.

[0140] A fixed-charge film 112 with a negative fixed charge is disposed between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of a hole accumulation layer is formed at the interface on the light-receiving surface (back side) side of the semiconductor layer 100S by the electric field induced by the fixed-charge film 112. This suppresses the generation of dark current caused by the interface energy level on the light-receiving surface side of the semiconductor layer 100S. For example, the fixed-charge film 112 is formed of an insulating film with a negative fixed charge. Examples of materials for insulating films with a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

[0141] A light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A may be continuously disposed with respect to the light-shielding film 117A constituting the pixel separation section 117. For example, the light-shielding film 117A between the fixed charge film 112 and the insulating film 111 may be selectively disposed at a position facing the pixel separation section 117 in the semiconductor layer 100S. The insulating film 111 is configured to cover the light-shielding film 117A. For example, the insulating film 111 is formed of silicon oxide.

[0142] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 sequentially includes, starting from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, the horizontal portion TGb of the transmission gate TG is disposed in the wiring layer 100T. The interlayer insulating film 119 is disposed across the entire front side of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. For example, the interlayer insulating film 119 is formed of a silicon oxide film. Note that the structure of the wiring layer 100T is not limited to the above structure and can be any structure including wiring and an insulating film.

[0143] Figure 7B It shows Figure 7A The planar structure shown includes pad portions 120 and 121. Pad portions 120 and 121 are disposed in a selective region on the interlayer insulating film 119. Pad portion 120 is configured to connect the floating diffuser portions FD (floating diffuser portions FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D to each other. For example, a pad portion 120 is provided for each pixel common unit 539, and the pad portion 120 is arranged in the central portion of the pixel common unit 539 in the plan view. Figure 7B The pad portion 120 is provided to span the pixel separation portion 117. The pad portion 120 is arranged to overlap at least a portion of each of the floating diffusion portions FD1, FD2, FD3 and FD4. Figure 6 and Figure 7BSpecifically, the pad portion 120 is formed in a region that overlaps with at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) sharing the pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) sharing the pixel circuit 210 in a direction perpendicular to the front side of the semiconductor layer 100S. A coupling via 120C for electrically connecting the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4 is provided in the interlayer insulating film 119. For example, the coupling via 120C is provided in each of pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 120 is embedded in the connecting via 120C, thereby electrically connecting the pad portion 120 to each of the floating diffuser portions FD1, FD2, FD3, and FD4.

[0144] The pad portion 121 is used to interconnect a plurality of VSS contact regions 118. For example, for two adjacent pixel sharing units 539 in the V direction, the VSS contact regions 118 of pixels 541C and 541D disposed in one of the pixel sharing units 539 and the VSS contact regions 118 of pixels 541A and 541B disposed in the other pixel sharing unit 539 are electrically connected to each other via the pad portion 121. For example, the pad portion 121 is configured to span the pixel separation portion 117. The pad portion 121 is arranged to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front side of the semiconductor layer 100S. Interlayer insulating film 119 has a connection via 121C for electrically connecting pad portion 121 to VSS contact area 118. For example, connection via 121C is provided in each of pixels 541A, 541B, 541C, and 541D. For example, a portion of pad portion 121 is buried in connection via 121C, thereby electrically connecting pad portion 121 to VSS contact area 118. For example, the pad portions 120 and 121 of multiple pixel shared units 539 arranged in the V direction are arranged at approximately the same position in the H direction. Figure 7B ).

[0145] By providing pads 120, the number of wirings used to connect each floating diffuser FD to the pixel circuit 210 (e.g., the gate electrode of the amplifying transistor AMP) is reduced. Similarly, by providing pads 121, the number of wirings used to supply potential to each VSS contact region 118 is reduced. For example, this can reduce the overall chip area, suppress electrical interference between wirings of miniaturized pixels, and / or reduce costs by reducing the number of components.

[0146] Pad portions 120 and 121 can be disposed at desired locations in the first substrate 100 and the second substrate 200. Specifically, pad portions 120 and 121 can be disposed in either the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S. When pad portions 120 and 121 are disposed in the wiring layer 100T, pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, each of pad portions 120 and 121 can be configured to be directly connected to at least a portion of the floating diffusion portion FD and / or at least a portion of the VSS contact region 118. Alternatively, a configuration can be adopted in which corresponding connection vias 120C and 121C are provided from each of the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 are disposed at desired locations in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0147] Specifically, when pads 120 and 121 are provided in wiring layer 100T, the number of wirings connecting to floating diffusion region FD and / or VSS contact region 118 in insulating region 212 of semiconductor layer 200S can be reduced. This reduces the area of ​​insulating region 212 in the second substrate 200 where pixel circuit 210 is formed, used for forming through wirings (connected from floating diffusion region FD to pixel circuit 210). Therefore, a larger area of ​​the second substrate 200 for forming pixel circuit 210 can be ensured. For example, by ensuring a larger area of ​​pixel circuit 210, larger pixel transistors can be formed, and image quality can be improved by reducing noise, etc.

[0148] In particular, when the FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion section FD and / or a VSS contact area 118 for each pixel 541. In this way, by using the construction of the pad sections 120 and 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0149] In addition, such as Figure 7BAs shown, for example, pad portions 120 connected to multiple floating diffuser portions FD and pad portions 121 connected to multiple VSS contact regions 118 are arranged alternately in a straight line in the V direction. Furthermore, pad portions 120 and 121 are formed at locations surrounded by multiple photodiodes PD, multiple transmission gates TG, and multiple floating diffuser portions FD. This allows for the free arrangement of components other than the floating diffuser portions FD and VSS contact regions 118 in the first substrate 100 where multiple components are formed. Therefore, efficient layout of the entire chip can be achieved. Additionally, the layout symmetry of components formed in the shared pixel units 539 can be ensured, and thus characteristic variations in each pixel 541 can be suppressed.

[0150] For example, pads 120 and 121 are each formed of polysilicon. More specifically, pads 120 and 121 are each formed of doped polysilicon with added impurities. Preferably, pads 120 and 121 are each formed of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This allows the pixel circuit 210 to be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason for this will be explained later. It should be noted that in the following description, the method of forming the pixel circuit 210 after the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0151] Here, another method can be conceived of forming the pixel circuit 210 in the second substrate 200 and then bonding the second substrate 200 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on the front side of the first substrate 100 (the front side of the wiring layer 100T) and the front side of the second substrate 200 (the front side of the wiring layer 200T), respectively. While bonding the first substrate 100 and the second substrate 200 to each other, the electrodes for electrical connection already formed on the front side of the first substrate 100 and the front side of the second substrate 200 come into contact with each other. Thereby, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the structure of the imaging device 1 using the second manufacturing method, for example, it is possible to manufacture using appropriate processes according to the structure of each of the first substrate 100 and the second substrate 200, and thus, a high-quality and high-performance imaging device can be manufactured.

[0152] In this second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, alignment errors may occur due to the manufacturing apparatus used for bonding. Furthermore, for example, since both the first substrate 100 and the second substrate 200 have a diameter of approximately tens of centimeters, substrate expansion and contraction may occur in microscopic regions of each portion of the first substrate 100 and the second substrate 200 when they are bonded together. This expansion and contraction is caused by a slight deviation in the timing of the substrates contacting each other. This expansion and contraction of the first substrate 100 and the second substrate 200 can sometimes lead to positional errors in the electrodes formed on the front surface of the first substrate 100 and the front surface of the second substrate 200 for electrical connections. In the second manufacturing method, it is preferable to pre-treat the substrates so that the electrodes of the first substrate 100 and the second substrate 200 can still contact each other despite such errors. Specifically, by taking these errors into account, at least one of the first substrate 100 and the second substrate 200 can have a larger electrode. More preferably, both the first substrate 100 and the second substrate 200 have larger electrodes. Therefore, if the second manufacturing method is used, the size (size in the substrate plane direction) of the electrode formed on the front side of the first substrate 100 or the second substrate 200 is larger than the size of the internal electrode extending from the interior of the first substrate 100 or the second substrate 200 to the front side along the thickness direction.

[0153] On the other hand, the first manufacturing method described above can be used by using a heat-resistant conductive material to construct each pad portion 120 and 121. In the first manufacturing method, after forming a first substrate 100 including a photodiode PD, a transmission transistor TR, etc., the first substrate 100 and a second substrate 200 (semiconductor layer 200S) are bonded together. At this time, the second substrate 200 has not yet formed patterns such as active elements and wiring layers for constituting the pixel circuit 210. Since the second substrate 200 is in a state where no pattern has been formed, even if there is an error in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause a positional alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. It should be noted that when forming a pattern on the second substrate, for example, the pattern is formed in an exposure apparatus for forming the pattern by using the pattern formed on the first substrate as the object of positional alignment. For this reason, the misalignment error between the first substrate 100 and the second substrate 200 will not be a problem when manufacturing the imaging device 1 in the first manufacturing method. For the same reason, the error caused by the expansion and contraction of the substrates in the second manufacturing method will not be a problem when manufacturing the imaging device 1 in the first manufacturing method.

[0154] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, an active element is formed on the second substrate 200. Subsequently, through electrodes 120E and 121E, and a through electrode TGV ( Figure 6 To form these through electrodes 120E and 121E and TGV, for example, the pattern of the through electrodes is formed from above the second substrate 200 by using a reduction projection exposure implemented by an exposure apparatus. Because of the use of reduction projection exposure, even if there is a positional alignment error between the second substrate 200 and the exposure apparatus, the magnitude of this error in the second substrate 200 is at most a fraction of the error magnitude in the second manufacturing method described above (the reciprocal of the reduction projection magnification). Therefore, by using the first manufacturing method to obtain the structure of the imaging device 1, it is possible to facilitate the positional alignment of the components formed on each of the first substrate 100 and the second substrate 200, and to manufacture a high-quality and high-performance imaging device.

[0155] The imaging device 1 manufactured using this first manufacturing method has features different from those of the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, each of the through electrodes 120E, 121E, and TGV has a substantially constant thickness (dimension in the plane of the substrate) from the second substrate 200 to the first substrate 100. Alternatively, when each of the through electrodes 120E, 121E, and TGV has a tapered shape, each of the through electrodes 120E, 121E, and TGV has a tapered shape with a constant slope. The imaging device 1 including such through electrodes 120E, 121E, and TGV facilitates the miniaturization of the pixels 541.

[0156] Here, when the imaging device 1 is manufactured in the first manufacturing method, the active element is formed in the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together. Therefore, the heat treatment required to form the active element also affects the first substrate 100. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided in the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200 for each pad portion 120 and 121. For example, conductive materials with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, are used for the pad portions 120 and 121. In this way, the imaging device 1 can be manufactured by using the first manufacturing method described above.

[0157] For example, the passivation film 122 is disposed across the entire front side of the semiconductor layer 100S and covers the pad portions 120 and 121. Figure 6 For example, the passivation film 122 is formed of a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pad portions 120 and 121 across the passivation film 122. This interlayer insulating film 123 is provided across the entire front side of the semiconductor layer 100S. For example, the interlayer insulating film 123 is formed of a silicon oxide (SiO) film. A bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. In other words, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided across the entire main surface of the first substrate 100. For example, the bonding film 124 is formed of a silicon nitride film.

[0158] For example, the light-receiving lens 401 is opposite to the semiconductor layer 100S through the fixed charge film 112 and the insulating film 111. Figure 6For example, each light-receiving lens 401 is disposed at a position facing the photodiode PD of each of pixels 541A, 541B, 541C and 541D.

[0159] The second substrate 200 sequentially includes a semiconductor layer 200S and a wiring layer 200T, starting from the side of the first substrate 100. The semiconductor layer 200S is formed of a silicon substrate. A well region 211 spanning the thickness direction is provided in the semiconductor layer 200S. For example, the well region 211 is a p-type semiconductor region. The second substrate 200 is provided with pixel circuits 210 arranged for each pixel common unit 539. For example, the pixel circuits 210 are provided on the front side of the semiconductor layer 200S (the wiring layer 200T side of the semiconductor layer 200S). In the imaging device 1, the second substrate 200 is attached to the first substrate 100, and the back side of the second substrate 200 (the semiconductor layer 200S side) faces the front side of the first substrate 100 (the wiring layer 100T side). In other words, the second substrate 200 and the first substrate 100 are attached in a face-to-back manner.

[0160] Figures 8 to 12 An example of the planar structure of the second substrate 200 is schematically shown. Figure 8 The structure of the pixel circuit 210 disposed near the front side of the semiconductor layer 200S is shown. Figure 9 The structure of the wiring layer 200T (specifically, the first wiring layer W1 described below), the semiconductor layer 200S connected to the wiring layer 200T, and various portions of the first substrate 100 are schematically shown. Figures 10 to 12 Examples of planar constructions for wiring layers 200T are shown below. Figures 8 to 12 In addition Figure 6 The structure of the second substrate 200 will be explained below. Figure 8 and Figure 9 The outline of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is shown in dashed lines, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 at the portion overlapping with the gate electrodes of the individual transistors constituting the pixel circuit 210 is shown in dotted lines. In the portion overlapping with the gate electrode of the amplifying transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213, and the boundary between the element isolation region 213 and the insulating region 212 are provided at one of the locations in the channel width direction.

[0161] The second substrate 200 is provided with: an insulating region 212 dividing the semiconductor layer 200S; and a component isolation region 213 disposed in a portion of the semiconductor layer 200S in the thickness direction. Figure 6For example, an insulating region 212 is disposed between two adjacent pixel circuits 210 in the H direction. The through electrodes 120E and 121E of the two pixel shared units 539 connected to these two pixel circuits 210, as well as the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4), are arranged in this insulating region 212. Figure 9 ).

[0162] The insulating region 212 has a thickness approximately the same as that of the semiconductor layer 200S. Figure 6 The semiconductor layer 200S is divided by an insulating region 212. Through electrodes 120E and 121E, as well as through electrode TGV, are disposed in the insulating region 212. For example, the insulating region 212 is formed of silicon oxide.

[0163] Through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wiring in the wiring layer 200T (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4 described below). These through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122. The lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121 (…). Figure 6 Through electrode 120E is provided for electrically connecting the pad portion 120 and the pixel circuit 210 to each other. In other words, through electrode 120E electrically connects the floating diffusion portion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200. Through electrode 121E is provided for electrically connecting the pad portion 121 to the reference potential line VSS of the wiring layer 200T to each other. In other words, through electrode 121E electrically connects the VSS contact area 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0164] A through-electrode TGV is disposed to penetrate the insulating region 212 in the thickness direction. The upper end of the through-electrode TGV is connected to the wiring in the wiring layer 200T. The through-electrode TGV is disposed to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119. The lower end of the through-electrode TGV is connected to the transmission gate TG ( Figure 6 This through-electrode TGV is configured to connect the transmission gates TG (transmission gates TG1, TG2, TG3, and TG4) of pixels 541A, 541B, 541C, and 541D to the wiring layer 200T (part of the row drive signal line 542, or more specifically, as described below). Figure 11The wirings TRG1, TRG2, TRG3, and TRG4 in the first substrate 100 are electrically connected to each other. In other words, the through electrode TGV electrically connects the transmission gate TG of the first substrate 100 to the wiring TRG of the second substrate 200, and transmits drive signals to each of the transmission transistors TR (transmission transistors TR1, TR2, TR3, and TR4).

[0165] The insulating region 212 is a region provided to insulate the aforementioned through electrodes 120E and 121E and through electrode TGV from the semiconductor layer 200S. The through electrodes 120E and 121E and through electrode TGV are used to electrically connect the first substrate 100 and the second substrate 200 to each other. For example, the insulating region 212 is provided between two adjacent pixel circuits 210 (pixel sharing unit 539) in the H direction, and the through electrodes 120E and 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to these two pixel circuits 210 are arranged in this insulating region 212. For example, the insulating region 212 is provided to extend along the V direction (…). Figure 8 and Figure 9 Here, the horizontal portion TGb of the transfer gate TG is cleverly arranged such that the position of the through electrode TGV in the H direction is closer to the positions of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGA. Figure 7A and Figure 9For example, the through electrode TGV is arranged in the H direction at a position approximately the same as that of the through electrodes 120E and 121E. This allows the through electrodes 120E and 121E, as well as the through electrode TGV, to be disposed together in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to provide the horizontal portion TGb only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa. For example, the through electrode TGV is arranged in the approximately central portion of each pixel 541 in both the H and V directions. In this case, the position of the through electrode TGV in the H direction is significantly offset from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate the through electrodes TGV and the through electrodes 120E and 121E from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is far from the positions of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide an insulating region 212 around each of the through electrodes 120E, 121E, and TGV. This allows for finer segmentation of the semiconductor layer 200S. In contrast, when the through electrodes 120E and 121E and the through electrode TGV are arranged together in the insulating region 212 extending along the V direction, the size of the semiconductor layer 200S in the H direction can be made sufficiently large. This ensures a larger area for semiconductor element formation in the semiconductor layer 200S. For example, this allows for an increase in the size of the amplification transistor AMP and noise suppression.

[0166] For reference Figure 4 As described, the pixel sharing unit 539 has the following structure: the floating diffuser portions FD disposed in each of the plurality of pixels 541 are electrically connected to each other, and the plurality of pixels 541 share a single pixel circuit 210. Furthermore, the electrical connection between these floating diffuser portions FD is achieved through pad portions 120 disposed in the first substrate 100. Figure 6 and Figure 7BThis is achieved by providing an electrical connection portion (pad portion 120) in the first substrate 100 and a pixel circuit 210 in the second substrate 200 via a through electrode 120E. As another construction example, it is also conceivable to provide an electrical connection portion between floating diffusers FD in the second substrate 200. In this case, four through electrodes connected to each of the floating diffusers FD1, FD2, FD3, and FD4 are provided in the pixel common unit 539. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the size of the insulating region 212 used to insulate the area around these through electrodes becomes larger. In contrast, the construction with a pad portion 120 in the first substrate 100... Figure 6 and Figure 7B This reduces the number of through electrodes and the size of the insulating region 212. This ensures a larger area in the semiconductor layer 200S for forming semiconductor elements. For example, this allows the amplifying transistor AMP to have a larger size and to suppress noise.

[0167] Component isolation region 213 is disposed on the front side of semiconductor layer 200S. Component isolation region 213 has a shallow trench isolation (STI) structure. In this component isolation region 213, semiconductor layer 200S is recessed in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in the recessed portion. For example, the insulating film is formed of silicon oxide. Component isolation region 213 performs component separation among multiple transistors constituting pixel circuit 210 according to the layout of pixel circuit 210. Semiconductor layer 200S (specifically, well region 211) extends below component isolation region 213 (deep within semiconductor layer 200S).

[0168] Here, refer to Figure 7A , Figure 7B and Figure 8 The differences between the shape (shape in the plane direction of the substrate) of the pixel sharing unit 539 on the first substrate 100 and the shape of the pixel sharing unit 539 on the second substrate 200 will be explained.

[0169] In the imaging device 1, a pixel sharing unit 539 is disposed in both the first substrate 100 and the second substrate 200. For example, the shape of the pixel sharing unit 539 disposed on the first substrate 100 is different from the shape of the pixel sharing unit 539 disposed on the second substrate 200.

[0170] exist Figure 7A and Figure 7BIn each of these, the outlines of pixels 541A, 541B, 541C, and 541D are shown with a single-dotted line, and the outline of the pixel sharing unit 539 is shown with a thick line. For example, the pixel sharing unit 539 in the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to them in the V direction. In other words, the pixel sharing unit 539 in the first substrate 100 includes four adjacent pixels 541 arranged in two rows × two columns. The pixel sharing unit 539 of the first substrate 100 has a generally square shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541).

[0171] exist Figure 8 and Figure 9 In each of these examples, the outlines of pixels 541A, 541B, 541C, and 541D are shown with a single-dotted line, and the outline of the pixel sharing unit 539 is shown with a thick line. For example, the outline of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and larger in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction and a size equivalent to four pixels in the V direction. In other words, the pixel sharing unit 539 of the second substrate 200 is formed to have a size equivalent to pixels arranged adjacently in one row × four columns. The pixel sharing unit 539 of the second substrate 200 has a generally rectangular outline.

[0172] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in a line in the V direction in this order. Figure 8 By setting the shape of each pixel circuit 210 to approximately rectangular as described above, it is possible to achieve this in one direction ( Figure 8 Four transistors (select transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) are arranged in a line along the V direction. This allows the drains of the amplification transistor AMP and the reset transistor RST to be shared within a single diffusion region (a diffusion region connected to the power supply line VDD). For example, the formation regions of each pixel circuit 210 can also be set to approximately square (see description below). Figure 21In this case, two transistors are arranged along one direction, and it is difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in a diffusion region. Therefore, by setting the formation region of the pixel circuit 210 to a roughly rectangular shape, it is easy to arrange the four transistors close together, and the size of the formation region of the pixel circuit 210 can be reduced. In other words, pixel miniaturization can be achieved. Furthermore, without needing to reduce the size of the formation region of the pixel circuit 210, the size of the formation region of the amplification transistor AMP can be increased, thereby suppressing noise.

[0173] For example, near the front side of semiconductor layer 200S, in addition to the selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is also provided. For example, VSS contact region 218 is formed of a p-type semiconductor region. VSS contact region 218 is electrically connected to VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) through wiring of wiring layer 200T and through electrode 121E. For example, this VSS contact region 218 is located adjacent to the source of FD conversion gain switching transistor FDG across component isolation region 213. Figure 8 ).

[0174] Next, refer to Figure 7B and Figure 8 This will be used to illustrate the positional relationship between the pixel sharing unit 539 disposed in the first substrate 100 and the pixel sharing unit 539 disposed in the second substrate 200. For example, one of the two pixel sharing units 539 arranged in the V direction on the first substrate 100 (e.g., Figure 7B The pixel sharing unit 539 on the paper side) is connected to one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, on the paper side). Figure 8 (Left side of the paper) Pixel shared unit 539. For example, one of the two pixel shared units 539 arranged in the V direction on the first substrate 100 (for example, Figure 7B The pixel sharing unit 539 on the lower side of the paper is connected to another of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, on the lower side of the paper). Figure 8 (The right side of the paper) Pixel shared unit 539.

[0175] For example, in the two pixel sharing units 539 arranged in the H direction on the second substrate 200, the internal layout (transistor arrangement, etc.) of one pixel sharing unit 539 is approximately equal to the layout obtained by reversing the internal layout of the other pixel sharing unit 539 in the V and H directions. The effects provided by this layout will be explained below.

[0176] In the two pixel sharing units 539 arranged in the V direction on the first substrate 100, each pad portion 120 is disposed at the central portion of the outer shape of the pixel sharing unit 539. In other words, each pad portion 120 is disposed at the central portion of the pixel sharing unit 539 in both the V and H directions. Figure 7B On the other hand, as described above, the pixel sharing unit 539 of the second substrate 200 has a generally rectangular shape that is longer in the V direction. Therefore, for example, the amplifying transistor AMP connected to the pad portion 120 is arranged at a position offset from the center of the pixel sharing unit 539 in the V direction towards the upper side of the paper. For example, if two pixel sharing units 539 arranged in the H direction of the second substrate 200 have the same internal layout, then the amplifying transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., Figure 7B The distance between the pad portion 120 of the pixel shared unit 539 on the upper side of the paper is relatively short. However, the amplification transistor AMP of the other pixel shared unit 539 is closer to the pad portion 120 (e.g., Figure 7B The distance between the pad portions 120 of the pixel sharing unit 539 on the lower side of the paper is relatively long. This increases the wiring area required when there is a connection between the amplifying transistor AMP and the pad portion 120. As a result, the wiring layout of the pixel sharing unit 539 may become more complex. This may affect the miniaturization of the imaging device 1.

[0177] In contrast, by reversing the internal layout of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200 at least in the V direction, the distance between the amplification transistor AMP and the pad portion 120 of both pixel-sharing units 539 can be reduced. This makes it easier to miniaturize the imaging device 1 compared to a structure in which the two pixel-sharing units 539 arranged in the H direction on the second substrate 200 have the same internal layout. It should be noted that... Figure 8 The planar layout of the multiple pixel-sharing units 539 of the second substrate 200 is shown to be symmetrical from left to right, but this is included in the following description. Figure 9 In the case of the layout of the first wiring layer W1 shown, the layout becomes asymmetrical.

[0178] Furthermore, preferably, the internal layout of the two pixel-shared units 539 arranged in the H direction on the second substrate 200 is also reversed relative to each other in the H direction. The reason for this will be explained below. Figure 9 As shown, each of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200 is connected to the pad portions 120 and 121 on the first substrate 100. For example, the pad portions 120 and 121 are arranged at the central portion in the H direction of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200 (between the two pixel-sharing units 539 arranged in the H direction). Therefore, by additionally reversing the internal layout of the two pixel-sharing units 539 arranged in the H direction on the second substrate 200, the distance between each of the multiple pixel-sharing units 539 on the second substrate 200 and the pad portions 120 and 121 can be reduced. In other words, this further facilitates the miniaturization of the imaging device 1.

[0179] Furthermore, the position of the outline of the pixel sharing unit 539 of the second substrate 200 is not necessarily consistent with the position of the outline of either of the pixel sharing units 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Figure 9 The left side of the paper) pixel shared unit 539 on one side in the V direction (e.g., the left side of the paper) Figure 9 The outline of the outer frame at the upper side of the paper surface is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the outline line on one side in the V direction (on the upper side of the paper). Additionally, one of the two pixel-shared units 539 arranged in the H direction in the second substrate 200 (for example, Figure 9 The pixel shared unit 539 on the other side of the V direction (e.g., the right side of the paper) is on the right side of the paper. Figure 9 The outline of the outer frame at the lower side of the paper is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the outline line on the other side in the V direction (the lower side of the paper). By arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 accordingly, the distance between the amplifying transistor AMP and the pad portion 120 can be reduced. This facilitates the miniaturization of the imaging device 1.

[0180] Furthermore, the outlines of the multiple pixel-sharing units 539 on the second substrate 200 do not need to be aligned with each other. For example, two pixel-sharing units 539 arranged in the H direction on the second substrate 200 can be arranged such that the outlines in the V direction are offset. This reduces the distance between the amplifying transistor AMP and the pad portion 120. This facilitates the miniaturization of the imaging device 1.

[0181] Reference Figure 7B and Figure 9 To illustrate the repeated arrangement of the pixel sharing unit 539 in the pixel array section 540. The pixel sharing unit 539 of the first substrate 100 has the size of two pixels 541 in the H direction and the size of two pixels 541 in the V direction. Figure 7B For example, in the pixel array portion 540 of the first substrate 100, these pixel sharing units 539, each having a size equivalent to the four pixels 541, are arranged adjacently in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541). Alternatively, in the pixel array portion 540 of the first substrate 100, a pair of pixel sharing units 539, including two pixel sharing units 539 arranged adjacent to each other in the V direction, may be provided. For example, in the pixel array portion 540 of the first substrate 100, a pair of adjacent pixel sharing units 539 are arranged adjacently in the H direction with a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction with a 4-pixel pitch (equivalent to the pitch of four pixels 541). The pixel sharing units 539 of the second substrate 200 have a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction. Figure 9 For example, in the pixel array section 540 of the second substrate 200, a pair of pixel sharing units 539, each including two pixel sharing units 539, are provided, and each pixel sharing unit 539 has a size equivalent to the four pixels 541. These pixel sharing units 539 are arranged to be adjacent to each other in the H direction and offset from each other in the V direction. For example, in the pixel array section 540 of the second substrate 200, the adjacent pairs of pixel sharing units 539 are arranged in a continuous arrangement without gaps in the H direction at a 2-pixel pitch (equivalent to the pitch of two pixels 541) and in the V direction at a 4-pixel pitch (equivalent to the pitch of four pixels 541). By repeating this arrangement of pixel sharing units 539, the pixel sharing units 539 can be arranged without gaps. This facilitates the miniaturization of the imaging device 1.

[0182] For example, the amplifying transistor AMP preferably has a three-dimensional structure such as a fin transistor. Figure 6This increases the effective gate width, thereby suppressing noise. For example, the select transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG have a planar construction. The amplifier transistor AMP can also have a planar construction. Alternatively, the select transistor SEL, reset transistor RST, or FD conversion gain switching transistor FDG can have a three-dimensional construction.

[0183] For example, wiring layer 200T includes a passivation film 221, an interlayer insulating film 222, and multiple wiring layers (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). For example, the passivation film 221 is in contact with the front side of the semiconductor layer 200S and covers the entire front side of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of each of the select transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 isolates the multiple wiring layers (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4) from each other. For example, the interlayer insulating film 222 is formed of silicon oxide.

[0184] For example, the wiring layer 200T, starting from the semiconductor layer 200S side, sequentially comprises a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202. All of these are electrically insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 has multiple connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to their respective underlying layers. Each connection portion is obtained by filling a connection hole provided in the interlayer insulating film 222 with a conductive material. For example, the interlayer insulating film 222 has a connection portion 218V for connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of this connection portion for interconnecting components in the second substrate 200 is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, preferably, the aperture of the connecting holes used to interconnect the components in the second substrate 200 is smaller than the aperture of each of the through electrodes 120E and 121E and the through electrode TGV. The reason for this is explained below. The depth of the connecting portions (such as connecting portion 218V) provided in the wiring layer 200T is smaller than the depth of each of the through electrodes 120E and 121E and the through electrode TGV. Therefore, it is easier to fill the connecting holes with conductive material to obtain the aforementioned connecting portions compared to the through electrodes 120E and 121E and the through electrode TGV. By forming the connecting portions with apertures smaller than the apertures of each of the through electrodes 120E and 121E and the through electrode TGV, miniaturization of the imaging device 1 is easily achieved.

[0185] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaching the source of the FD conversion gain switching transistor FDG). For example, the first wiring layer W1 connects the through electrode 121E to the connection portion 218V. This achieves electrical interconnection between the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0186] Next, refer to Figures 10 to 12 To illustrate the planar structure of the 200T wiring layer. Figure 10 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 11 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 12 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0187] For example, the third wiring layer W3 includes wiring TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending along the H direction (row direction). Figure 11 These wirings correspond to the reference. Figure 4 The multiple row drive signal lines 542 are described. Lines TRG1, TRG2, TRG3, and TRG4 are configured to transmit drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. Lines TRG1, TRG2, TRG3, and TRG4 are each connected to the transmission gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. Lines SELL, RSTL, and FDGL are configured to transmit drive signals to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, respectively. Lines SELL, RSTL, and FDGL are each connected to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and the connecting portion, respectively.

[0188] For example, the fourth wiring layer W4 includes a power line VDD, a reference potential line VSS, and a vertical signal line 543 extending along the V direction (column direction). Figure 12The power line VDD is connected to the drain of the amplifying transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Additionally, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0189] Contact portions 201 and 202 can be positioned at locations overlapping with the pixel array portion 540 in a plan view (e.g., Figure 3 Alternatively, it can be located in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 6 Contact portions 201 and 202 are disposed on the front side of the second substrate 200 (the surface on the side of the wiring layer 200T). For example, each of the contact portions 201 and 202 is formed of a metal such as Cu (copper) or Al (aluminum). The contact portions 201 and 202 are exposed from the front side of the wiring layer 200T (the surface on the side of the third substrate 300). Each of the contact portions 201 and 202 is used to electrically connect the second substrate 200 and the third substrate 300 to each other and to bond the second substrate 200 and the third substrate 300 together.

[0190] Figure 6 An example is shown in which peripheral circuitry is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuitry may include a portion of the row driving unit 520, or a portion of the column signal processing unit 550, etc. Additionally, as... Figure 3 As shown, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, but the connection holes H1 and H2 may be arranged near the pixel array portion 540.

[0191] For example, the third substrate 300 sequentially includes a wiring layer 300T and a semiconductor layer 300S starting from the second substrate 200 side. For example, the front side of the semiconductor layer 300S is disposed on the second substrate 200 side. The semiconductor layer 300S is formed of a silicon substrate. Circuitry is disposed in the front side portion of the semiconductor layer 300S. Specifically, for example, at least a portion of each of an input section 510A, a row drive section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B is disposed in the front side portion of the semiconductor layer 300S. For example, the wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. Contact portions 301 and 302 are exposed from the front side (the surface on the second substrate 200 side) of the wiring layer 300T. Contact portion 301 contacts contact portion 201 of the second substrate 200, and contact portion 302 contacts contact portion 202 of the second substrate 200. Contact portions 301 and 302 are each electrically connected to a circuit formed in the semiconductor layer 300S (e.g., at least one of input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B). For example, contact portions 301 and 302 are each formed of a metal such as Cu (copper) or aluminum (Al). For example, external terminal TA is connected to input portion 510A via connection hole H1, and external terminal TB is connected to output portion 510B via connection hole H2.

[0192] Here, the features of camera device 1 will be described.

[0193] Generally, a camera device includes photodiodes and pixel circuits as its main components. Here, when the photodiode has a larger area, the charge generated as a result of photoelectric conversion increases, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal and allowing the camera device to output better image data (image information). On the other hand, when the transistors (especially amplifying transistors) included in the pixel circuit have a larger size, the noise generated in the pixel circuit decreases, thus improving the signal-to-noise ratio of the captured signal and allowing the camera device to output better image data (image information).

[0194] However, in a camera device, if a photodiode and pixel circuit are disposed on the same semiconductor substrate, and the photodiode occupies a large area within the limited area of ​​the semiconductor substrate, then the transistors included in the pixel circuit must have a small size. Furthermore, if the transistors included in the pixel circuit have a large size, then the photodiode must have a small area.

[0195] To address the aforementioned problems, for example, the imaging device 1 according to this embodiment uses a structure in which multiple pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap with a photodiode PD. This allows for maximizing the area of ​​the photodiode PD and the size of the transistors included in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the signal-to-noise ratio (S / N) of the pixel signal and enables the imaging device 1 to output better image data (image information).

[0196] In a configuration where multiple pixels 541 share a single pixel circuit 210 and the shared pixel circuit 210 is arranged to overlap with the photodiode PD, multiple wirings connected to the single pixel circuit 210 extend from the floating diffuser FD of each of the multiple pixels 541. To ensure that the semiconductor layer 200S has a large area for forming the pixel circuit 210, for example, connecting wirings can be formed to interconnect these extended wirings and integrate them into a single unit. This also applies to the multiple wirings extending from the VSS contact region 118; that is, connecting wirings can be formed to interconnect these extended wirings and integrate them into a single unit.

[0197] For example, when a connecting wire is formed in the semiconductor layer 200S on which the pixel circuit 210 is formed to interconnect multiple wirings extending from the floating diffusion portions FD of each of the multiple pixels 541, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 can be reduced. Similarly, when a connecting wire is formed in the semiconductor layer 200S on which the pixel circuit 210 is formed to interconnect multiple wirings extending from the VSS contact regions 118 of each of the multiple pixels 541 and to combine them into one, it is conceivable that the area of ​​the transistors included in the pixel circuit 210 can be reduced.

[0198] To solve the above problems, for example, the camera device 1 according to this embodiment may have the following structure: multiple pixels 541 share a pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. Furthermore, a connection wiring for connecting the floating diffusion portions FD of each of the multiple pixels 541 to each other and forming a single connection wiring for connecting the VSS contact areas 118 of each of the multiple pixels 541 to each other and forming a single connection wiring is provided in the first substrate 100.

[0199] Here, as a manufacturing method for providing a connection wiring in the first substrate 100 for interconnecting and assembling the floating diffuser portions FD of each of the plurality of pixels 541 into a single connection wiring and for interconnecting and assembling the VSS contact areas 118 of each of the plurality of pixels 541 into a single connection wiring, when using the aforementioned second manufacturing method, it is possible to manufacture the device using appropriate processes, for example, according to the structure of the first substrate 100 and the second substrate 200. This allows for the manufacture of a high-quality and high-performance imaging device. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed using a simple process. Specifically, when using the aforementioned second manufacturing method, electrodes connected to the floating diffuser portions FD and electrodes connected to the VSS contact areas 118 are respectively provided on the front surface of the first substrate 100 and the front surface of the second substrate 200, which will become the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, preferably, the electrodes formed on the front surfaces of the two substrates (i.e., the first substrate 100 and the second substrate 200) are relatively large, so that when the first substrate 100 and the second substrate 200 are bonded together, the electrodes formed on the front surfaces of the two substrates can still contact each other even if their positions are offset from each other. In this case, it is conceivable that it would be difficult to arrange such electrodes within the limited area of ​​each pixel included in the imaging device 1.

[0200] For example, to address the problem of requiring a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, the imaging device 1 according to this embodiment can utilize the aforementioned first manufacturing method, which allows multiple pixels 541 to share a single pixel circuit 210 and arranges the shared pixel circuit 210 to overlap with the photodiode PD. This facilitates the alignment of components formed on both the first substrate 100 and the second substrate 200, thereby enabling the manufacture of a high-quality and high-performance imaging device. Furthermore, an inherent structure produced using this manufacturing method can be achieved. In other words, the imaging device can have a structure in which the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are sequentially stacked. In other words, the imaging device can have a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back. In addition, the camera device may have through electrodes 120E and 121E that penetrate the semiconductor layer 200S of the second substrate 200 and the wiring layer 100T of the first substrate 100 from the front side and reach the front side of the semiconductor layer 100S of the first substrate 100.

[0201] However, regarding the structure obtained by providing a connection wiring in the first substrate 100 for interconnecting the floating diffuser portions FD of each of the plurality of pixels 541 and forming a single connection wiring for interconnecting the VSS contact areas 118 of each of the plurality of pixels 541 and forming a single connection wiring, when the structure and the second substrate 200 are stacked using the aforementioned first manufacturing method and the pixel circuit 210 is formed in the second substrate 200, the heat treatment required to form the active element included in the pixel circuit 210 may affect the connection wiring already formed in the first substrate 100.

[0202] Therefore, in order to solve the problem that heat treatment during the formation of the aforementioned active element affects the aforementioned connection wiring, it is preferable that the imaging device 1 according to this embodiment uses a conductive material with high heat resistance in the following two types of connection wiring: a connection wiring for interconnecting the floating diffuser portions FD of each of the plurality of pixels 541 and assembling them into a single wire; and a connection wiring for interconnecting the VSS contact areas 118 of each of the plurality of pixels 541 and assembling them into a single wire. Specifically, as a conductive material with high heat resistance, a material having a melting point higher than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200 can be used.

[0203] Thus, for example, the imaging device 1 according to this embodiment includes the following structure: (1) a structure obtained by stacking the first substrate 100 and the second substrate 200 in a face-to-back manner (specifically, a structure obtained by stacking the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 in this order); (2) a structure obtained by providing through electrodes 120E and 121E that penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 200 and reach the front side of the semiconductor layer 100S of the first substrate 100; and (3) a structure obtained by using a conductive material with high heat resistance to form a connecting wire for interconnecting the floating diffusion portions FD of each of the plurality of pixels 541 and forming a single connecting wire for interconnecting the VSS contact areas 118 of each of the plurality of pixels 541 and forming a single connecting wire. With this structure, it is possible to not provide a large electrode at the interface between the first substrate 100 and the second substrate 200, and to provide in the first substrate 100 a connecting wire for interconnecting the floating diffuser portions FD of the multiple pixels 541 and forming a single wire, and a connecting wire for interconnecting the VSS contact areas 118 of the multiple pixels 541 and forming a single wire.

[0204] [Operation of Camera Device 1]

[0205] Next, we will refer to Figure 13 and Figure 14 Explain the operation of camera device 1. Figure 13 and Figure 14 It has added Figure 3 The diagram shows arrows representing the lines of each signal. Figure 13 In the diagram, arrows indicate the lines for the input signals from external sources to the camera device 1, as well as the lines for the power supply potential and the reference potential. Figure 14In the diagram, arrows indicate the signal lines for pixel signals output from the imaging device 1 to the outside. For example, input signals (e.g., pixel clock and synchronization signals) input to the imaging device 1 via the input section 510A are transmitted to the line drive section 520 of the third substrate 300, causing the line drive section 520 to generate line drive signals. The line drive signals are transmitted to the second substrate 200 via contact sections 301 and 201. Furthermore, the line drive signals reach the individual pixel common units 539 of the pixel array section 540 via the line drive signal lines 542 in the wiring layer 200T. Among the line drive signals reaching the pixel common units 539 of the second substrate 200, drive signals other than the drive signal used to transmit the gate TG are input to the pixel circuit 210 to drive the individual transistors included in the pixel circuit 210. The drive signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV to drive pixels 541A, 541B, 541C and 541D. Figure 13 Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contact sections 301 and 201, and are supplied to the pixel circuit 210 of each pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, the pixel signals obtained by photoelectric conversion of each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted via the through electrode 120E to the pixel circuit 210 provided in the second substrate 200 for each pixel common unit 539. The pixel signal based on this pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and contact sections 202 and 302. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0206] [Effect]

[0207] In this embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200, respectively). With this configuration, compared to the case where pixels 541A, 541B, 541C, and 541D and pixel circuit 210 are formed on the same substrate, the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210 can be increased. As a result, the amount of pixel signal obtained by photoelectric conversion can be increased, and the transistor noise of pixel circuit 210 can be reduced. This improves the signal-to-noise ratio of the pixel signal and enables the imaging device 1 to output better pixel data (image information). Furthermore, miniaturization of the imaging device 1 can be achieved (in other words, pixel size reduction and miniaturization of the imaging device 1 can be achieved). By reducing the pixel size, the imaging device 1 can increase the number of pixels per unit area and output high-quality images.

[0208] Furthermore, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other via through electrodes 120E and 121E disposed in the insulating region 212. For example, methods such as connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or connecting the first substrate 100 and the second substrate 200 via through wiring through the semiconductor layer (e.g., through-silicon via (TSV)). Compared to these methods, by providing through electrodes 120E and 121E in the insulating region 212, the area required to connect the first substrate 100 and the second substrate 200 can be reduced. This allows for a reduction in pixel size, and thus a smaller size for the imaging device 1. Additionally, the area of ​​each pixel becomes finer. This allows for further improvement in resolution. Without requiring chip miniaturization, the size of the areas forming pixels 541A, 541B, 541C, and 541D, as well as the area forming the pixel circuit 210, can be increased. As a result, the amount of pixel signal obtained through photoelectric conversion can be increased, and the noise of the transistors included in the pixel circuit 210 can be reduced. This improves the signal-to-noise ratio of the pixel signal and enables the imaging device 1 to output better pixel data (image information).

[0209] Furthermore, in the imaging device 1, the pixel circuit 210 is disposed on a different substrate (second substrate 200) than the substrate (third substrate 300) where the column signal processing unit 550 and the image signal processing unit 560 are located. With this configuration, compared to the case where the pixel circuit 210, column signal processing unit 550, and image signal processing unit 560 are formed on the same substrate, the area of ​​the pixel circuit 210, as well as the areas of the column signal processing unit 550 and the image signal processing unit 560, can be increased. This reduces noise generated in the column signal processing unit 550 and allows for the mounting of higher-performance image processing circuitry in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0210] Furthermore, in the imaging device 1, a pixel array section 540 is disposed in the first substrate 100 and the second substrate 200, and a column signal processing section 550 and an image signal processing section 560 are disposed in the third substrate 300. Additionally, contact sections 201, 202, 301, and 302, which connect the second substrate 200 and the third substrate 300, are formed above the pixel array section 540. This allows the contact sections 201, 202, 301, and 302 to be freely arranged without interference from the various wiring included in the pixel array. Therefore, the contact sections 201, 202, 301, and 302 can be used when electrically connecting the second substrate 200 and the third substrate 300. Due to the use of the contact sections 201, 202, 301, and 302, for example, the layout freedom of the column signal processing section 550 and the image signal processing section 560 is increased. This reduces noise generated in the column signal processing unit 550 and allows for the installation of a higher-performance image processing circuit in the image signal processing unit 560. Consequently, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0211] Furthermore, in the imaging device 1, the pixel separation section 117 penetrates the semiconductor layer 100S. Therefore, even when adjacent pixels (pixels 541A, 541B, 541C, and 541D) are closer together due to the miniaturization of each pixel area, color mixing between pixels 541A, 541B, 541C, and 541D can be suppressed. This improves the signal-to-noise ratio of the pixel signal and allows the imaging device 1 to output better pixel data (image information).

[0212] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel shared unit 539. With this configuration, compared to the case where pixel circuits 210 are provided for each of pixels 541A, 541B, 541C, and 541D, the size of the forming region of the transistors (amplifier transistor AMP, reset transistor RST, select transistor SEL, and FD conversion gain switching transistor FDG) included in the pixel circuit 210 can be increased. For example, by increasing the size of the forming region of the amplifier transistor AMP, noise can be suppressed. This improves the signal-to-noise ratio of the pixel signal and allows the imaging device 1 to output better pixel data (image information).

[0213] Furthermore, in the imaging device 1, pad portions 120 for electrically connecting the floating diffuser portions FD (floating diffuser portions FD1, FD2, FD3, and FD4) of the four pixels (pixels 541A, 541B, 541C, and 541D) to each other are provided in the first substrate 100. With this configuration, compared to providing such pad portions 120 in the second substrate 200, the number of through electrodes (through electrodes 120E) used to connect the first substrate 100 and the second substrate 200 can be reduced. Therefore, the size of the insulating region 212 can be reduced, and the formation region (semiconductor layer 200S) of the transistors included in the pixel circuit 210 can be ensured to be sufficiently large. This reduces the noise of the transistors included in the pixel circuit 210 and thus improves the signal-to-noise ratio of the pixel signal, allowing the imaging device 1 to output better pixel data (image information).

[0214] In the following description, variations of the imaging device 1 according to the foregoing embodiment will be described. In the following variations, the same reference numerals are used for the same structures as in the foregoing embodiment.

[0215] <2. First Variation>

[0216] Figures 15 to 19 A modified example of the planar structure of the camera device 1 according to the foregoing embodiment is shown. Figure 15 The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 16 The diagram schematically illustrates the structure of the first wiring layer W1 and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 17 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to that described in the foregoing embodiments. Figure 10 . Figure 18An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 19 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0217] like Figure 16 As shown, in this modified example, the internal layout of one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (e.g., on the right side of the paper in this figure) has a structure obtained by reversing the internal layout of the other pixel sharing unit 539 (e.g., on the left side of the paper in this figure) only in the H direction. Furthermore, the offset in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is greater than that in the aforementioned embodiment (…). Figure 9 The offset described in [reference to a document] can be shortened by a larger offset in the V direction. This allows for a reduction in the length of the amplifying transistor AMP of another pixel-shared unit 539 and the pad portion 120 connected to it. Figure 7B The distance between the pad portion 120 of one of the two pixel-shared units 539 arranged in the V direction (on the lower side of the paper in this figure). With this arrangement, in Figures 15 to 19 In the first variation of the imaging device 1 shown, it is not necessary to reverse the planar layout of the two pixel sharing units 539 arranged in the H direction in the V direction to achieve the same area of ​​the pixel sharing units 539 as the pixel sharing units 539 of the second substrate 200 described in the previous embodiment. Note that the planar layout of the pixel sharing units 539 of the first substrate 100 is the same as that of the previous embodiment ( Figure 7A and Figure 7B The planar layout described in the previous embodiment is the same. Therefore, the imaging device 1 of this modified example can achieve effects similar to those of the imaging device 1 described in the previous embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the previous embodiment and this modified example.

[0218] <3. Second variation>

[0219] Figures 20 to 25 A modified example of the planar structure of the camera device 1 according to the foregoing embodiment is shown. Figure 20 The planar structure of the first substrate 100 is schematically shown, and corresponds to that described in the foregoing embodiments. Figure 7A . Figure 21 The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 22 The diagram schematically illustrates the structure of the first wiring layer W1, and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 23 An example layer showing the planar structure of the first wiring layer W1 and the second wiring layer W2 is illustrated, corresponding to those described in the foregoing embodiments. Figure 10 . Figure 24 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 25 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0220] In this variant, each pixel circuit 210 has a generally square planar shape. Figure 21 (etc.). In this respect, the planar structure of the camera device 1 in this variation is different from the planar structure of the camera device 1 described in the foregoing embodiments.

[0221] For example, similar to that described in the foregoing embodiments, the pixel sharing unit 539 of the first substrate 100 is formed to span a pixel region of 2 rows × 2 columns and has a generally square planar shape. Figure 20 For example, in each pixel shared unit 539, the horizontal portions TGb of the transmission gates TG1 and TG3 of pixels 541A and 541C in one pixel column extend in the H direction toward the central portion of the pixel shared unit 539 (more specifically, toward the outer edges of pixels 541A and 541C, and toward the central portion of the pixel shared unit 539) from the position overlapping with the vertical portions TGa, while the horizontal portions TGb of the transmission gates TG2 and TG4 of pixels 541B and 541D in another pixel column extend in the H direction toward the outer side of the pixel shared unit 539 (more specifically, toward the outer edges of pixels 541B and 541D, and toward the outer side of the pixel shared unit 539) from the position overlapping with the vertical portions TGa. The pad portion 120 connected to the floating diffuser FD is provided at the central portion of the pixel shared unit 539 (the central portion of the pixel shared unit 539 in both the H and V directions), while the pad portion 121 connected to the VSS contact area 118 extends at least in the H direction ( Figure 20 In the middle, it is located at the end of the pixel sharing unit 539 in both the H and V directions.

[0222] As another arrangement example, it is conceivable to provide the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 only in the region facing the vertical portion TGa. In this case, similar to the description in the previous embodiment, the semiconductor layer 200S is easily divided into finer segments. This makes it difficult to form the transistors of the pixel circuit 210 larger. On the other hand, if the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 extend along the H direction from the position overlapping with the vertical portion TGa as described in the previous modified example, then similar to the description in the previous embodiment, the width of the semiconductor layer 200S can be increased. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transmission gates TG1 and TG3 respectively in the H direction can be arranged close to the position of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transmission gates TG2 and TG4 respectively in the H direction can be arranged close to the position of the through electrode 121E in the H direction. Figure 22 Similar to the embodiments described above, this configuration allows for an increase in the width (dimension in the H direction) of the semiconductor layer 200S extending along the V direction. This allows for an increase in the size of the transistors in the pixel circuit 210, particularly the size of the amplifying transistor AMP. As a result, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0223] For example, the pixel common unit 539 of the second substrate 200 has approximately the same size as the pixel common unit 539 of the first substrate 100 in the H and V directions, and for example, the pixel common unit 539 of the second substrate 200 is configured to span the region corresponding to a pixel region of approximately 2 rows × 2 columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in a semiconductor layer 200S extending in the V direction, while the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in a semiconductor layer 200S extending in the V direction. The semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S including the FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the H direction separated by an insulating region 212. The insulating region 212 extends in the V direction ( Figure 21 ).

[0224] Here, we will refer to Figure 21 and Figure 22 The outline of the pixel sharing unit 539 of the second substrate 200 is described. For example, Figure 20The pixel sharing unit 539 of the first substrate 100 shown is connected to one side of the pad portion 120 located in the H direction. Figure 22 The amplifying transistor AMP and the selecting transistor SEL are located on the left side of the paper, and are connected to the other side of the pad portion 120 in the H direction. Figure 22 The FD conversion gain switching transistor FDG and the reset transistor RST are located on the right side of the paper. The shape of the pixel common unit 539 of the second substrate 200, which includes an amplification transistor AMP, a selection transistor SEL, an FD conversion gain switching transistor FDG, and a reset transistor RST, is determined by the following four outer edges.

[0225] The first outer edge is one end of the semiconductor layer 200S, which includes the selection transistor SEL and the amplification transistor AMP, located in the V direction. Figure 22 The outer edge is located at the upper end of the paper surface. The first outer edge is provided at the amplifying transistor AMP used to form the pixel sharing unit 539 and the side located in the V direction of the pixel sharing unit 539. Figure 22 On the upper side of the paper, adjacent pixel shared units 539 are between the selection transistors SEL. More specifically, the first outer edge is disposed between the amplifying transistor AMP and the selection transistor SEL and at the central portion of the element isolation region 213 in the V direction. The second outer edge is the other end of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP in the V direction. Figure 22 The outer edge is located at the lower end of the paper. The second outer edge is provided at the selection transistor SEL for constituting the pixel common unit 539 and the other side located in the V direction for constituting the pixel common unit 539. Figure 22 The second outer edge is located between the amplifying transistors AMP of adjacent pixel shared units 539 (on the underside of the paper). More specifically, the second outer edge is located between the select transistor SEL and the amplifying transistor AMP and at the central portion of the element isolation region 213 in the V direction. The third outer edge is the other end of the semiconductor layer 200S, which includes the reset transistor RST and the FD conversion gain switching transistor FDG, located in the V direction. Figure 22 The outer edge is located at the lower end of the paper. The third outer edge is provided at the FD conversion gain switching transistor FDG used to form the pixel shared unit 539 and the other side located in the V direction (for forming the pixel shared unit 539). Figure 22The third outer edge is located between the reset transistors RST of adjacent pixel shared units 539 (on the underside of the paper). More specifically, the third outer edge is disposed between the FD conversion gain switching transistor FDG and the reset transistor RST and at the central portion of the element isolation region 213 in the V direction. The fourth outer edge is one end of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction. Figure 22 The fourth outer edge is located at the outer edge of the upper side of the paper surface. The fourth outer edge is provided at the reset transistor RST used to form the pixel shared unit 539 and the side located in the V direction of the pixel shared unit 539. Figure 22 The fourth outer edge is located between the FD conversion gain switching transistor FDG (not shown) of adjacent pixel shared unit 539 on the upper side of the paper. More specifically, the fourth outer edge is located between the reset transistor RST and the FD conversion gain switching transistor FDG and at the central portion of the element isolation region 213 (not shown) in the V direction.

[0226] In the outline of the pixel common unit 539 of the second substrate 200, including the aforementioned first, second, third, and fourth outer edges, the third and fourth outer edges are arranged to be offset relative to the first and second outer edges in the V direction (in other words, offset in the V direction). By using this arrangement, the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG can be positioned as close as possible to the pad portion 120. This reduces the area of ​​the wiring used to connect them, thus promoting miniaturization of the imaging device 1. Note that the VSS contact region 218 is disposed between the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, multiple pixel circuits 210 have the same arrangement.

[0227] The imaging device 1 equipped with this second substrate 200 can also achieve effects similar to those described in the foregoing embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the foregoing embodiments and this variation.

[0228] <4. Third variation>

[0229] Figures 26 to 31 A modified example of the planar structure of the camera device 1 according to the foregoing embodiment is shown. Figure 26 The planar structure of the first substrate 100 is schematically shown, and corresponds to that described in the foregoing embodiments. Figure 7B . Figure 27The planar structure near the front side of the semiconductor layer 200S of the second substrate 200 is schematically shown, corresponding to that described in the foregoing embodiments. Figure 8 . Figure 28 The diagram schematically illustrates the structure of the first wiring layer W1 and portions of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, corresponding to those described in the foregoing embodiments. Figure 9 . Figure 29 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to that described in the foregoing embodiments. Figure 10 . Figure 30 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to that described in the foregoing embodiments. Figure 11 . Figure 31 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to that described in the foregoing embodiments. Figure 12 .

[0230] In this modified example, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( Figure 28 That is, this construction roughly corresponds to... Figure 21 The structure is obtained by rotating the planar structure of the camera device 1 shown by 90 degrees.

[0231] For example, similar to that described in the foregoing embodiments, the pixel sharing unit 539 of the first substrate 100 is formed to span a pixel region of 2 rows × 2 columns and has a generally square planar shape. Figure 26 For example, in each pixel shared unit 539, the transmission gates TG1 and TG2 of pixels 541A and 541B in one pixel row extend toward the central portion of the pixel shared unit 539 in the V direction, while the transmission gates TG3 and TG4 of pixels 541C and 541D in another pixel row extend toward the outer direction of the pixel shared unit 539 in the V direction. The pad portion 120 connected to the floating diffuser FD is provided at the central portion of the pixel shared unit 539, while the pad portion 121 connected to the VSS contact area 118 extends at least in the V direction (…). Figure 26 In the middle, it is disposed at the end of the pixel common unit 539 in both the V and H directions. At this time, the positions of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 in the V direction are closer to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 of the transmission gates TG3 and TG4 in the V direction are closer to the position of the through electrode 121E in the V direction. Figure 28Therefore, for reasons similar to those described in the foregoing embodiments, the width (dimension in the V direction) of the semiconductor layer 200S extending along the H direction can be increased. This allows for an increase in the size of the amplifying transistor AMP and suppression of noise.

[0232] In each pixel circuit 210, the select transistor SEL and the amplify transistor AMP are arranged side by side in the H direction, while the reset transistor RST is arranged adjacent to the select transistor SEL in the V direction, separated by an insulating region 212. Figure 27 The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side-by-side in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends along the H direction ( Figure 30 ), and the fourth wiring layer W4 extends along the V direction ( Figure 31 ).

[0233] The imaging device 1 equipped with this second substrate 200 can also achieve effects similar to those described in the foregoing embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangements described in the foregoing embodiments and this modification. For example, the semiconductor layer 200S described in the foregoing embodiments and the first modification can extend along the H direction.

[0234] <5. Fourth Variation>

[0235] Figure 32 A modified example of the cross-sectional structure of the camera device 1 according to an exemplary embodiment is shown schematically. Figure 32 Corresponding to the embodiments described above Figure 3 In this modified example, the camera device 1 includes contact portions 203, 204, 303, and 304, in addition to contact portions 201, 202, 301, and 302, located facing the central portion of the pixel array portion 540. In this respect, the camera device 1 of this modified example differs from the camera device 1 described in the foregoing embodiments.

[0236] Contact portions 203 and 204 are disposed on the second substrate 200 and exposed at the joint surface between the second substrate 200 and the third substrate 300. Contact portions 303 and 304 are disposed on the third substrate 300 and exposed at the joint surface between the third substrate 300 and the second substrate 200. Contact portions 203 and 304 contact each other. In other words, in the imaging device 1, the second substrate 200 and the third substrate 300 are connected to each other not only by means of contact portions 201, 202, 301 and 302, but also by means of contact portions 203, 204, 303 and 304.

[0237] Next, we will refer to Figure 33 and Figure 34 Instructions for operating camera device 1. In Figure 33 In the diagram, arrows indicate the lines for the input signals from external sources to the camera device 1, as well as the lines for the power supply potential and the reference potential. Figure 34 In the diagram, arrows indicate the signal lines for pixel signals output from the imaging device 1 to the outside. For example, the input signal input to the imaging device 1 via the input section 510A is transmitted to the line drive section 520 of the third substrate 300 to allow the line drive section 520 to generate a line drive signal. The line drive signal is transmitted to the second substrate 200 via contact sections 303 and 203. Furthermore, the line drive signal reaches each pixel common unit 539 of the pixel array section 540 via the line drive signal line 542 in the wiring layer 200T. Among the line drive signals that have reached the pixel common unit 539 of the second substrate 200, drive signals other than the drive signal for the transmission gate TG are input to the pixel circuit 210 to drive each transistor included in the pixel circuit 210. The drive signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV to drive pixels 541A, 541B, 541C and 541D. Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contact sections 303 and 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via through electrode 121E. On the other hand, the pixel signals obtained by photoelectric conversion of each of the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200 for each pixel common unit 539. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via vertical signal line 543 and contact sections 204 and 304. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0238] The imaging device 1, including these contact portions 203, 204, 303, and 304, can also achieve effects similar to those described in the foregoing embodiments. The position, number, etc., of the contact portions can be changed according to the design of the destination (i.e., the circuitry of the third substrate 300, etc.) to which the wiring is connected via the contact portions 303 and 304.

[0239] <6. Fifth Variation>

[0240] Figure 35 A modified example of the cross-sectional structure of the camera device 1 according to the embodiment is shown. Figure 35 Corresponding to the embodiments described above Figure 6 In this modified example, a transmission transistor TR with a planar structure is provided in the first substrate 100. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the foregoing embodiments.

[0241] In the transfer transistor TR, the transfer gate TG consists only of the horizontal portion TGb. In other words, the transfer gate TG does not have a vertical portion TGA and is positioned to face the semiconductor layer 100S.

[0242] The imaging device 1, including the transmission transistor TR with this planar structure, can also achieve effects similar to those described in the foregoing embodiments. Furthermore, it is conceivable that by providing a planar transmission gate TG in the first substrate 100, compared to providing a vertical transmission gate TG in the first substrate 100, the photodiode PD can be formed closer to the front side of the semiconductor layer 100S, thereby increasing the saturation signal quantity (Qs). Additionally, it is considered that the method of forming a planar transmission gate TG in the first substrate 100 requires fewer manufacturing steps and is less prone to adverse effects on the photodiode PD due to manufacturing steps compared to the method of forming a vertical transmission gate TG in the first substrate 100.

[0243] <7. Sixth Variation>

[0244] Figure 36 A modified example of the pixel circuit of the camera device 1 according to the embodiment is shown. Figure 36 Corresponding to the embodiments described above Figure 4 In this variation, a pixel circuit 210 is provided for each pixel (pixel 541A). In other words, the pixel circuit 210 is not shared by multiple pixels. In this respect, the imaging device 1 of this variation differs from the imaging device 1 described in the foregoing embodiments.

[0245] The imaging device 1 of this modified example is the same as the imaging device 1 described in the foregoing embodiments in that the pixel 541A and the pixel circuit 210 are disposed on different substrates (the first substrate 100 and the second substrate 200, respectively). Therefore, the imaging device 1 according to this modified example can also achieve the same effect as that described in the foregoing embodiments.

[0246] <8. Seventh Variation>

[0247] Figure 37A modified example of the planar structure of the pixel separation portion 117 described in the foregoing embodiment is shown. Gaps may be provided in the pixel separation portion 117 surrounding each of pixels 541A, 541B, 541C, and 541D. In other words, the entire outer periphery of pixels 541A, 541B, 541C, and 541D may not be surrounded by the pixel separation portion 117. For example, gaps in the pixel separation portion 117 may be provided near pad portions 120 and 121 (see...). Figure 7B ).

[0248] Although an example of an FTI structure penetrating the semiconductor layer 100S has been described in the foregoing embodiments (see...), Figure 6 However, the pixel separation section 117 may have a structure other than the FTI structure. For example, the pixel separation section 117 may be configured not to completely penetrate the semiconductor layer 100S, and may have a structure referred to as the DTI structure.

[0249] <9. Example 2>

[0250] <9.1 Problems to be solved in Example 2>

[0251] The conversion efficiency needs to be switched by making the capacitance of the floating diffuser (FD) variable according to the shooting environment of the subject. Therefore, as a method to switch the FD capacitance according to the shooting environment, in addition to using the capacitor Cfd1 of the floating diffuser FD within the pixel, an additional capacitor Cfd2 provided within the pixel is also required. Furthermore, in the case of a darker subject, a method is needed to connect the additional capacitor Cfd2 to the floating diffuser FD.

[0252] Figure 38 This is an equivalent circuit diagram showing a construction example of the pixel sharing unit 539X of the comparative example. Figure 38 The pixel sharing unit 539X shown includes pixels 541X in the first substrate 100 and pixel circuits 210X in the second substrate. For example, pixel 541X includes four photodiodes PD, four transmission transistors TR, and a capacitor Cfd1 in the floating diffuser FD. Furthermore, pixel 541X includes an additional capacitor Cfd2 and an FD transmission transistor FDG. For example, pixel circuit 210X in the second substrate 200 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a power line (VDD), and a vertical signal line (VSL) 543. The vertical signal line 543 electrically connects each pixel circuit 210X to a column signal processing unit 550 disposed on the third substrate 300. The column signal processing unit 550 then detects pixel signals appearing in the vertical signal line 543 from each pixel circuit 210X.

[0253] Within the pixel sharing unit 539X, there exists an FD wiring FDL, which serves as a floating diffusion region FD that electrically connects the drain of the transmission transistor TR in pixel 541X to the gate of the amplification transistor AMP in pixel circuit 210X. The FD wiring FDL is electrically connected to an additional capacitor Cfd2 via the FD transmission transistor FDG. The additional capacitor Cfd2 is electrically connected to the drain of the FD transmission transistor FDG, while the FD wiring FDL is electrically connected to the source of the FD transmission transistor FDG. When shooting a darker subject, the gate of the FD transmission transistor FDG is turned on, and the FD wiring FDL is electrically connected to both the capacitor Cfd1 and the additional capacitor Cfd2. Conversely, when shooting a brighter subject, the gate of the FD transmission transistor FDG is turned off, and the electrical connection between the FD wiring FDL and the additional capacitor Cfd2 is broken.

[0254] That is, when shooting a darker subject, the gate of the FD transfer transistor FDG is turned on, and the additional capacitor Cfd2 is electrically connected to the FD wiring FDL, thereby increasing the capacitance of the floating diffuser FD. Conversely, when shooting a brighter subject, the gate of the FD transfer transistor FDG is turned off, and the electrical connection between the FD wiring FDL and the additional capacitor Cfd2 is broken, thereby decreasing the capacitance of the floating diffuser FD.

[0255] Corresponding to the switching control of the FD transfer transistor FDG, the FD wiring FDL is electrically connected not only to the floating diffuser FD, which includes capacitor Cfd1, but also to an additional capacitor Cfd2. As a result, the charge-to-voltage conversion efficiency can be switched by changing the capacitance of the floating diffuser FD.

[0256] However, in the first substrate 100, an FD transmission transistor FDG and an additional capacitor Cfd2 need to be configured for each pixel common unit 539, which results in the need to provide arrangement space for the FD transmission transistor FDG and the additional capacitor Cfd2, thus making it difficult to achieve multi-pixelation for higher resolution.

[0257] <9.2 Summary of Example 2>

[0258] Therefore, the imaging device includes a first substrate, a second substrate, a third substrate, and a switching unit. The first substrate has pixels, each pixel including a photodiode and a floating diffuser for retaining the charge converted by the photodiode. The second substrate has pixel circuitry for reading out pixel signals from the pixels based on the charge retained in the floating diffuser, and the second substrate is stacked on the first substrate. The third substrate has processing circuitry for detecting the pixel signals read out by the pixel circuitry, and the third substrate is stacked on the second substrate. The switching unit is configured to enable electrical connection between the floating diffuser and the floating diffuser of another pixel in the first substrate, and the switching unit is disposed on the second substrate.

[0259] By controlling the switching unit, the imaging device enables electrical connection between the floating diffuser of one pixel and the floating diffuser of another pixel. As a result, without the need for an additional capacitor Cfd2, the capacitance of the floating diffuser of one pixel can be switched by using the floating diffuser of another pixel, thereby allowing the switching of the charge-to-voltage conversion efficiency. Furthermore, since the switching unit is located on the second substrate instead of the first substrate, it not only helps to improve the charge-to-voltage conversion efficiency but also facilitates multi-pixel processing for higher resolution.

[0260] <9.3 Specific Examples of Example 2-1>

[0261] <9.3.1 Construction of Example 2-1>

[0262] Figure 39 This is an equivalent circuit diagram illustrating a construction example of the pixel sharing unit 539 in Embodiment 2-1. The imaging device 1 has a three-layer structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked. The first substrate 100 includes a plurality of pixels 541 that perform photoelectric conversion. The second substrate 200 includes a pixel circuit 210A for reading out pixel signals based on the charge output from the pixels 541. The third substrate 300 includes a processing circuit for processing the pixel signals. The pixel sharing unit 539 includes pixels 541 and pixel circuit 210A. Pixel 541 includes four photodiodes PD, four transfer transistors TR for transmitting the charge converted by each photodiode PD, and a floating diffusion section FD for retaining the charge transmitted by the transfer transistors TR.

[0263] For example, pixel circuit 210A includes a reset transistor RST, an amplifying transistor AMP, a select transistor SEL, a power supply line (VDD), and a vertical signal line (VSL) 543. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. The amplifying transistor AMP generates a signal having a voltage corresponding to the level of charge held in the floating diffuser FD, serving as a pixel signal. The select transistor SEL controls the connection between the drain of the amplifying transistor AMP and the vertical signal line 543. The floating diffuser FD of the first substrate is electrically connected to the gate of the amplifying transistor AMP in the pixel circuit 210A of the second substrate 200 via the FD wiring FDL.

[0264] Vertical signal lines 543 electrically connect each pixel circuit 210A to a column signal processing unit 550 disposed on the third substrate 300. Then, the column signal processing unit 550 detects the pixel signals appearing in the vertical signal lines 543 from the pixel circuits 210A.

[0265] The second substrate 200 includes an FD transfer transistor FDG1 capable of connecting a second FD line FDL2 to a first FD line FDL1. The first FD line FDL1 is a line connecting pixel 541 and a first pixel circuit 210A1 corresponding to pixel 541. The second FD line FDL2 is a line connecting another pixel 541 and a second pixel circuit 210A2 corresponding to the other pixel 541. The FD transfer transistor FDG1 electrically connects its drain to the first FD line FDL1 and its source to the second FD line FDL2. For example, the FD transfer transistor FDG1 is referred to as a switching section. Furthermore, the gate of the FD transfer transistor FDG1 is electrically connected to the row drive section 520. It is assumed that the gate-on region of the FD transfer transistor FDG1 includes a portion of the off region before and after the on region of the transfer transistor TR, which overlaps with the gate-on region of the transfer transistor TR of the currently selected pixel 541.

[0266] When shooting a brighter subject, the gate voltage of the FD transfer transistor FDG1 is turned off. When the gate voltage is turned off, the FD transfer transistor FDG1 disconnects the electrical connection between the first FD wiring FDL1 and the second FD wiring FDL2. The first FD wiring FDL1 is the wiring that connects the currently selected pixel 541 and the first pixel circuit 210A1 to each other. The second FD wiring FDL2 is the wiring that connects the currently unselected pixel 541 and the second pixel circuit 210A2 to each other. As a result, the FD capacitance of the selected pixel 541 is equivalent to the capacitance of capacitor Cfd1 corresponding to the first FD wiring FDL1.

[0267] Conversely, when shooting a darker subject, the gate voltage of the FD transfer transistor FDG1 is turned on. With the gate voltage on, the FD transfer transistor FDG1 electrically connects the first FD wiring FDL1 and the second FD wiring FDL2 to each other. As a result, in addition to having the capacitance corresponding to the first FD wiring FDL1, which includes the capacitor Cfd in the selected pixel 541, the capacitance of the capacitor Cfd1 in the currently unselected pixel 541 is also added to the FD capacitor. With the addition of the capacitance of the capacitor Cfd1 in the currently unselected pixel 541, the FD capacitance of the currently selected pixel 541 is increased compared to the capacitance of the floating diffuser FD when the FD transfer transistor FDG1 is off. That is, the FD capacitance of the currently selected pixel 541 can be switched by controlling the switching of the FD transfer transistor FDG1, thereby achieving a switch in the magnitude of the charge-to-voltage conversion efficiency.

[0268] <9.3.2 Function and Effect of Example 2-1>

[0269] In the imaging device 1 of Embodiment 2-1, an FD transmission transistor FDG1, which enables electrical connection between the first FD line FDL1 of the currently selected pixel 541 and the second FD line FDL2 of the currently unselected pixel 541, is disposed on the second substrate 200. Furthermore, the imaging device 1 performs switching control of the FD transmission transistor FDG1, thereby making the FD capacitance of the currently selected first FD line FDL1 variable. As a result, without increasing the arrangement area of ​​the first substrate 100, the FD capacitance can be switched according to the shooting environment, thereby enabling switching of the charge-to-voltage conversion efficiency. That is, with... Figure 38 Compared to the comparative example shown, the first substrate 100 does not need to provide a capacitor Cfd2 and an FD transfer transistor FDG for each pixel common unit 539, which can help to achieve multi-pixelation for higher resolution.

[0270] <9.4 Modifications to Example 2>

[0271] For example, the currently selected pixel 541 is a pixel 541 selected row by row from one or more pixels 541 arranged in the row direction. In addition, the unselected pixel 541 can be any pixel 541 other than the selected pixel 541, and can be changed appropriately.

[0272] Although the currently selected pixel 541 is selected row-wise, for example, pixel 541 could be selected column-wise from one or more pixels 541 arranged in a column direction, and this can be changed appropriately. In this case, the currently unselected pixel 541 could be any pixel 541 other than the selected pixel 541, and this can also be changed appropriately.

[0273] For example, pixel 541 includes a total of four (2×2) photodiodes (PDs), but is not limited to four photodiodes. The number of photodiodes (PDs) can be changed appropriately, as long as the number is more than one.

[0274] The above is an exemplary case in which the FD transmission transistor FDG1 electrically connects the second FD line FDL2 of a currently unselected single pixel 541 to the first FD line FDL1 of the currently selected pixel 541. However, the present invention is not limited to the second FD line FDL2 of a single pixel 541, and may also electrically connect the second FD lines FDL2 of multiple currently unselected pixels 541 to the first FD line FDL1 of the currently selected pixel 541.

[0275] Although the above is an exemplary case in which the FD transfer transistor FDG1 is configured on the second substrate 200, the FD transfer transistor FDG1 can be arranged on the third substrate 300 and can be modified as appropriate.

[0276] <10. Example 3>

[0277] <10.1 Problems to be solved in Example 3>

[0278] Figure 40 This is an equivalent circuit diagram showing a construction example of the pixel sharing unit 539Y of the comparative example. The pixel sharing unit 539Y includes pixels 541Y and pixel circuits 210Y. The selection transistor SEL in each pixel circuit 210Y is electrically connected to a vertical signal line 543, which is connected to a column signal processing unit 550 disposed on a third substrate 300. The drain of the selection transistor SEL in the pixel circuit 210Y is electrically connected to the source of the amplification transistor AMP in the pixel circuit 210Y, and the source of the selection transistor SEL is electrically connected to the vertical signal line 543. The pixel circuit 210Y corresponding to the currently selected pixel 541Y turns on the selection transistor SEL and transmits the pixel signal to the column signal processing unit 550. At this time, the pixel circuit 210Y corresponding to the currently unselected pixel 541Y turns off the selection transistor SEL.

[0279] The pixel circuit 210Y causes the pixel signal of the currently selected pixel 541 to appear in the vertical signal line 543. The column signal processing unit 550 reads the pixel signal appearing in the vertical signal line 543. At this time, the series resistance of the signal path P where the pixel signal appears, the parasitic capacitance of the vertical signal line 543 other than the signal path P, and the parasitic capacitance obtained by adding the fringe capacitance of the selection transistor SEL connected to the vertical signal line 543 and in the off state affect the readout of the above signal. As a result, VSL waveform rounding occurs on the signal path P. VSL waveform rounding on the signal path P also reduces the frame rate of the final output image. To solve this problem, it is conceivable to increase the LM current (Load MOS current) of the column signal processing unit 550 to improve VSL waveform rounding, but this will lead to increased power consumption.

[0280] <10.2 Summary of Example 3>

[0281] Therefore, the imaging device includes a first substrate, a second substrate, a third substrate, and a switching unit. The first substrate has pixels, each pixel including a photodiode and a floating diffuser for holding the charge converted by the photodiode. The second substrate includes pixel circuitry and readout wiring, the pixel circuitry reading out pixel signals from the pixels based on the charge held in the floating diffuser, the pixel signals read from each pixel circuitry appearing in the readout wiring, and the second substrate is stacked on the first substrate. The third substrate has processing circuitry for detecting pixel signals from the pixel circuitry appearing in the readout wiring, and the third substrate is stacked on the second substrate. The switching unit is disposed on the readout wiring of the second substrate and is used to disconnect the electrical connection between the pixel circuitry and the processing circuitry.

[0282] In this imaging device, a switching unit for disconnecting the electrical connection between the pixel circuit and the processing circuit is provided on the readout wiring of the second substrate. As a result, the effects of parasitic capacitance of the readout wiring other than the signal path and the parasitic capacitance of the selection transistor connected to the readout wiring other than the signal path are reduced, thus suppressing waveform rounding of the readout wiring on the signal path.

[0283] <10.3 Specific Example of Example 3-1>

[0284] <10.3.1 Construction of Example 3-1>

[0285] Figure 41This is an equivalent circuit diagram illustrating a construction example of the pixel sharing unit 539 in Embodiment 3-1. The imaging device 1 has a structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked. The first substrate 100 includes a plurality of pixels 541 that perform photoelectric conversion. The second substrate 200 includes a pixel circuit 210B for reading out pixel signals based on the charge output from the pixels 541. The third substrate 300 includes processing circuitry such as a column signal processing unit 550 for detecting the pixel signals. The pixel sharing unit 539 includes pixels 541 and pixel circuitry 210B.

[0286] Pixel 541 includes four photodiodes PD, four transfer transistors TR for transferring the charge converted by each photodiode PD, and a floating diffuser FD for holding the charge transferred by the transfer transistors TR.

[0287] For example, pixel circuit 210B includes a reset transistor RST, an amplifying transistor AMP, a select transistor SEL, a power supply line (VDD), and a vertical signal line (VSL) 543. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. The amplifying transistor AMP generates a signal having a voltage corresponding to the level of charge held in the floating diffuser FD as a pixel signal. The select transistor SEL controls the connection between the drain of the amplifying transistor AMP and the vertical signal line 543. The floating diffuser FD of the first substrate 100 is electrically connected to the gate of the amplifying transistor AMP in the pixel circuit 210B of the second substrate 200 via the FD wiring FDL.

[0288] Vertical signal line 543 electrically connects each pixel circuit 210B to a column signal processing unit 550 in a processing circuit disposed on the third substrate 300. The column signal processing unit 550 then detects pixel signals from each pixel circuit 210B appearing in the vertical signal line 543. Vertical signal line 543 is also referred to as a readout wiring.

[0289] The select transistor SEL in each pixel circuit 210B is electrically connected to the vertical signal line 543, which is connected to the column signal processing unit 550 disposed on the third substrate 300. The drain of the select transistor SEL in the pixel circuit 210B is electrically connected to the source of the amplifying transistor AMP in the pixel circuit 210B, and the source of the select transistor SEL is electrically connected to the vertical signal line 543.

[0290] Figure 41An example of the switching operation of the vertical signal line switch SW on the vertical signal line 543 related to the activation of the second selection transistor SEL2 is shown. The vertical signal line switch SW is also referred to as a switching unit. Note that, for ease of explanation, the vertical signal line 543 is electrically connected to the first selection transistor SEL1, the second selection transistor SEL2, the third selection transistor SEL3, and the fourth selection transistor SEL4. The first selection transistor SEL1 is the selection transistor SEL in the first pixel circuit 210B1, and the second selection transistor SEL2 is the selection transistor SEL in the second pixel circuit 210B2. The third selection transistor SEL3 is the selection transistor SEL in the third pixel circuit 210B3, and the fourth selection transistor SEL4 is the selection transistor SEL in the fourth pixel circuit 210B4. A plurality of vertical signal line switches SW are arranged on the vertical signal line 543 connecting the selection transistors SEL of each pixel circuit 210B to the column signal processing unit 550. Note that the vertical signal line switches SW can be arranged on the vertical signal line 543 at specific intervals, and this can be changed appropriately.

[0291] The vertical signal line switch SW can be, for example, a normally open type SW, which can use the same transistor as the selection transistor SEL and can be appropriately modified. The vertical signal line switch SW on the signal path P of the vertical signal line 543 through which the pixel signal flows from the pixel circuit 210B to the column signal processing unit 550 is in the ON state. Among the vertical signal line switches SW disposed on the vertical signal lines 543 other than the signal path P, the vertical signal line switch SW closest to the column signal processing unit 550, that is, the vertical signal line switch SW used to electrically connect the signal path P to the vertical signal lines 543 other than the signal path P, is OFF.

[0292] For example, the vertical signal line switch SW includes a first vertical signal line switch SW1 and a second vertical signal line switch SW2. The first vertical signal line switch SW1 is used to disconnect the electrical connection between the first selection transistor SEL1 on the vertical signal line 543 and the upstream side of the vertical signal line 543. The second vertical signal line switch SW2 is used to disconnect the electrical connection between the second selection transistor SEL2 and the third selection transistor SEL3 on the vertical signal line 543.

[0293] For ease of explanation, the above describes an exemplary case where the first pixel circuits 210B1 to the fourth pixel circuits 210B4 are configured as pixel circuits 210B, and the first selection transistors SEL1 to the fourth selection transistors SEL4 are configured as selection transistors SEL. Furthermore, the above describes an exemplary case where the first vertical signal line switch SW1 and the second vertical signal line switch SW2 are configured as vertical signal line switches SW. However, the number of pixel circuits 210B, selection transistors SEL, and vertical signal line switches SW is not limited to this and can be appropriately changed.

[0294] The drain of the first selection transistor SEL1 of the first pixel circuit 210B1 is electrically connected to the source of the amplification transistor AMP in the first pixel circuit 210B1, and the source of the first selection transistor SEL1 is electrically connected to the vertical signal line 543. The drain of the second selection transistor SEL2 of the second pixel circuit 210B2 is electrically connected to the source of the amplification transistor AMP in the second pixel circuit 210B2, and the source of the second selection transistor SEL2 is electrically connected to the vertical signal line 543. The drain of the third selection transistor SEL3 of the third pixel circuit 210B3 is electrically connected to the source of the amplification transistor AMP in the third pixel circuit 210B3, and the source of the third selection transistor SEL3 is electrically connected to the vertical signal line 543. The drain of the fourth selection transistor SEL4 of the fourth pixel circuit 210B4 is electrically connected to the source of the amplification transistor AMP in the fourth pixel circuit 210B4, and the source of the fourth selection transistor SEL4 is electrically connected to the vertical signal line 543.

[0295] For example, such as Figure 41 As shown, when the second selection transistor SEL2 is turned on in the second pixel circuit 210B2 corresponding to the currently selected pixel 541, the vertical signal line 543 from the second selection transistor SEL2 to the column signal processing unit 550 where a pixel signal appears is the signal path P. At this time, the first vertical signal line switch SW1, which electrically connects the signal path P to the vertical signal lines 543 other than the signal path P, is turned off. That is, the first vertical signal line switch SW1 is turned off, and the second vertical signal line switch SW2 is turned on. As a result, in the signal path P, the effects of parasitic capacitance of the vertical signal line 543 after the first vertical signal line switch SW1 and the parasitic capacitance of the selection transistor SEL can be reduced.

[0296] Figure 42 This diagram illustrates an example of the switching operation of the vertical signal line switch SW on vertical signal line 543 (the activation of the third selection transistor SEL3). Figure 42As shown, when the third selection transistor SEL3 is turned on in the third pixel circuit 210B3 corresponding to the currently selected pixel 541, the vertical signal line 543 from the third selection transistor SEL3 to the column signal processing unit 550 where a pixel signal appears is the signal path P. At this time, the second vertical signal line switch SW2, which electrically connects the signal path P to the vertical signal lines 543 other than the signal path P, is turned off. That is, the first vertical signal line switch SW1 is turned on, and the second vertical signal line switch SW2 is turned off. As a result, in the signal path P, the parasitic capacitance of the vertical signal line 543 after the second vertical signal line switch SW2, as well as the parasitic capacitance of the first selection transistor SEL1 and the second selection transistor SEL2, can be reduced.

[0297] Compared to the signal path P when the second selection transistor SEL2 is turned on, the signal path P when the third selection transistor SEL3 is turned on can further reduce the impact of parasitic capacitance. For example, the parasitic capacitance of the vertical signal line 543 other than the signal path P, the parasitic capacitance of the wiring adjacent to the vertical signal line 543, and the parasitic capacitance of the silicon substrate can be reduced. In addition, the impact of parasitic capacitance obtained by adding the edge capacitances of multiple selection transistors SEL connected to the vertical signal line 543 and currently in the off state (especially the gate edge capacitances of selection transistors SEL1 and SEL2) can be reduced.

[0298] <10.3.2 Function and Effect of Example 3-1>

[0299] In the imaging device 1 of Embodiment 3-1, the vertical signal line switch SW, which electrically connects the signal path P on the vertical signal line 543 from the pixel circuit 210B of the selected pixel 541 to the vertical signal line 543 of the column signal processing unit 550, to the vertical signal line 543 other than the signal path P, is disconnected. As a result, by reducing the parasitic capacitance of the vertical signal line 543 after the first vertical signal line switch SW1 among the vertical signal lines 543 other than the signal path P, or by reducing the parasitic capacitance of the selection transistor SEL, the rounding of the VSL waveform on the signal path P can be suppressed.

[0300] Among the multiple vertical signal line switches SW on the vertical signal line 543, by selectively using the optimal drive mode determined by the location where the vertical signal line switch SW is open, LM current is applied to the column signal processing unit 550 when reading the pixel signal of the pixel circuit 210B furthest from the column signal processing unit 550. As a result, when the pixel signal of the pixel circuit 210B close to the column signal processing unit 550 is read, VSL waveform rounding can be reduced. This allows for a shorter drive pulse or a reduction in LM current consumption.

[0301] By using multiple drive modes corresponding to the opening of the vertical signal line switch SW, the frame rate of the final output image can be improved. Furthermore, by applying multiple LM current settings corresponding to the opening of each vertical signal line switch SW, power consumption can be reduced.

[0302] During readout of the pixel circuit 210B near the column signal processing unit 550, the parasitic capacitance of the vertical signal line 543 is reduced by utilizing the vertical signal line switch SW, thereby improving the roundness of the VSL waveform on the signal path P. By applying a setting to reduce the LM current by an amount equivalent to the improvement, the total current required for readout can be reduced.

[0303] Figure 43 This is a timing diagram illustrating an operational example of the pixel circuit 210B. As the pixel circuit 210B moves closer to the column signal processing unit 550, the capacitance of the vertical signal line 543 can be reduced, thereby shortening the settling period. For example, as... Figure 43 As shown, the stabilization period of the vertical signal line voltage (VSL voltage) immediately following the high level of the reset pulse of the reset transistor RST can be shortened, as indicated by the dashed line. Similarly, the stabilization period of the vertical signal line voltage (VSL voltage) immediately following the high level of the transmission pulse of the transmission transistor TR can be shortened, as indicated by the dashed line. Switching the drive mode to one with a shorter stabilization period helps to increase the frame rate or save power on the LM current.

[0304] Note that, preferably, the vertical signal line switch SW uses transistors with low on-resistance and low parasitic capacitance. For example, when a transistor SEL structure is used as the vertical signal line switch SW, the transistors of the vertical signal line switch SW are connected in parallel in multiple configurations within a range where the parasitic capacitance does not affect the VSL waveform. As a result, the effective gate length can be increased and the on-resistance of the vertical signal line switch SW can be reduced.

[0305] The above description of the camera device 1 in Embodiment 3-1 is an exemplary case in which multiple vertical signal line switches SW are arranged on the vertical signal line 543. However, the number of vertical signal line switches SW arranged on the vertical signal line 543 may be too large. For example, if there are as many vertical signal line switches SW as the selection transistors SEL electrically connected to the vertical signal line 543, then the SW capacitance and SW resistance of the vertical signal line switches SW themselves will be factors affecting the rounding of the VSL waveform on the signal path. Therefore, it is necessary to appropriately adjust the number of vertical signal line switches SW to be configured on the vertical signal line 543.

[0306] <10.4 Specific Examples of Embodiment 3-2>

[0307] <10.4.1 Construction of Example 3-2>

[0308] Figure 44 This is a diagram illustrating an example of the switching operation of the vertical signal line switch SW on the vertical signal line 543 (the activation of the second selection transistor SEL2 and the third selection transistor SEL3). For ease of explanation, the same construction as in Embodiment 3-1 is given the same reference numerals, and repeated descriptions of the construction and operation will be omitted.

[0309] In the imaging device 1 of Embodiment 3-2, pixel signals from each pixel circuit 210B are detected by column signal processing units 550 arranged on both sides of a vertical signal line 543. The third substrate 300 includes a plurality of column signal processing units 550, for example, a first column signal processing unit 5501 and a second column signal processing unit 5502. The first column signal processing unit 5501 is connected to one end of the vertical signal line 543, and the second column signal processing unit unit 5502 is connected to the other end of the vertical signal line 543.

[0310] For ease of explanation, the above describes an exemplary case where the first pixel circuits 210B1 to the fifth pixel circuits 210B5 are configured as pixel circuits 210B, and the first selection transistors SEL1 to the fifth selection transistors SEL5 are configured as selection transistors SEL. Furthermore, the above describes an exemplary case where the first vertical signal line switches SW1 to the third vertical signal line switches SW3 are configured as vertical signal line switches SW. However, the number of pixel circuits 210B, selection transistors SEL, and vertical signal line switches SW is not limited to this and can be appropriately changed.

[0311] Each pixel circuit 210B is electrically connected to the vertical signal line 543 connected to the first column signal processing unit 5501 and the second column signal processing unit 5502. The drain of the first selection transistor SEL1 of the first pixel circuit 210B1 is electrically connected to the source of the amplification transistor AMP in the first pixel circuit 210B1, and the source of the first selection transistor SEL1 is electrically connected to the vertical signal line 543. The drain of the second selection transistor SEL2 of the second pixel circuit 210B2 is connected to the source of the amplification transistor AMP in the second pixel circuit 210B2, and the source of the second selection transistor SEL2 is electrically connected to the vertical signal line 543. The drain of the third selection transistor SEL3 of the third pixel circuit 210B3 is electrically connected to the source of the amplification transistor AMP in the third pixel circuit 210B3, and the source of the third selection transistor SEL3 is electrically connected to the vertical signal line 543. The drain of the fourth selection transistor SEL4 in the fourth pixel circuit 210B4 is electrically connected to the source of the amplification transistor AMP in the fourth pixel circuit 210B4, and the source of the fourth selection transistor SEL4 is electrically connected to the vertical signal line 543. The drain of the fifth selection transistor SEL5 in the fifth pixel circuit 210B5 is electrically connected to the source of the amplification transistor AMP in the fifth pixel circuit 210B5, and the source of the fifth selection transistor SEL5 is electrically connected to the vertical signal line 543.

[0312] Multiple vertical signal line switches SW are configured on vertical signal lines 543 that electrically connect the selection transistors SEL of each pixel circuit 210B to the column signal processing unit 550. Note that the vertical signal line switches SW can be configured on the vertical signal lines 543 at specific intervals and can be appropriately changed. The vertical signal line switches SW can be normally open. Vertical signal line switches SW on the signal path P of the vertical signal line 543 from the pixel circuit 210B to the column signal processing unit 550 where a pixel signal appears are turned on. Among the vertical signal line switches SW configured on vertical signal lines 543 other than signal path P, the vertical signal line switch SW connecting signal path P to other vertical signal lines 543 is turned off. Among the vertical signal line switches SW configured on vertical signal lines 543 other than signal path P, the vertical signal line switch SW closest to the column signal processing unit 550 on the opposite side of the readout side is turned off.

[0313] The first vertical signal line switch SW1 is configured on the vertical signal line 543 between the first selection transistor SEL1 and the second selection transistor SEL2. The second vertical signal line switch SW2 is configured on the vertical signal line 543 between the second selection transistor SEL2 and the third selection transistor SEL3. The third vertical signal line switch SW3 is configured on the vertical signal line 543 between the third selection transistor SEL3 and the fourth selection transistor SEL4.

[0314] Pixel circuit 210B activates its selection transistor SEL according to the position of the pixel 541 to be selected. For example, consider the following assumption: the second selection transistor SEL2 of the second pixel circuit 210B2 and the third selection transistor SEL3 of the third pixel circuit 210B3 are activated. In this case, the vertical signal line 543 from the second selection transistor SEL2 to the first column signal processing unit 5501 is the first signal path P1, and the vertical signal line 543 from the third selection transistor SEL3 to the second column signal processing unit 5502 is the second signal path P2. At this time, the second vertical signal line switch SW2 is deactivated to disconnect the connection between the first signal path P1 and the vertical signal lines 543 other than the first signal path P1, and to disconnect the connection between the second signal path P2 and the vertical signal lines 543 other than the second signal path P2. That is, the first vertical signal line switch SW1 is activated, the second vertical signal line switch SW2 is deactivated, and the third vertical signal line switch SW3 is activated.

[0315] As a result, in the first signal path P1, the parasitic capacitance of the vertical signal line 543 on the side of the second column signal processing unit 5502 after the second vertical signal line switch SW2 in the vertical signal line 543 other than the first signal path P1 can be reduced. Additionally, the parasitic capacitance of the third selection transistor SEL3 to the fifth selection transistor SEL5 can be reduced. In the second signal path P2, the parasitic capacitance of the vertical signal line 543 on the side of the first column signal processing unit 5501 after the second vertical signal line switch SW2 in the vertical signal line 543 other than the second signal path P2 can be reduced. Additionally, the parasitic capacitance of the first selection transistor SEL1 and the second selection transistor SEL2 can be reduced.

[0316] Figure 45This diagram illustrates an example of the switching operation of the vertical signal line switch SW on the vertical signal line 543 (the activation of the first selection transistor SEL1 and the fourth selection transistor SEL4). For example, consider the following assumption: the first selection transistor SEL1 of the first pixel circuit 210B1 and the fourth selection transistor SEL4 of the fourth pixel circuit 210B4 are activated. In this case, the vertical signal line 543 from the first selection transistor SEL1 to the first column signal processing unit 5501 is the first signal path P1, while the vertical signal line 543 from the fourth selection transistor SEL4 to the second column signal processing unit 5502 is the second signal path P2. At this time, the first vertical signal line switch SW1, which electrically connects the first signal path P1 to the vertical signal lines 543 other than the first signal path P1, is deactivated. Furthermore, the third vertical signal line switch SW3, which electrically connects the second signal path P2 to the vertical signal lines 543 other than the second signal path P2, is deactivated. That is, the first vertical signal line switch SW1 is open, the second vertical signal line switch SW2 is closed, and the third vertical signal line switch SW3 is open. For ease of explanation, the second vertical signal line switch SW2 is closed, but it can also be open, and this can be changed appropriately.

[0317] As a result, in the first signal path P1, the parasitic capacitance of the vertical signal line 543 on the side of the second column signal processing unit 5502 after the first vertical signal line switch SW1 among the vertical signal lines 543 other than the first signal path P1 can be reduced. Furthermore, the effects of parasitic capacitance, etc., of the second selection transistor SEL2 to the fifth selection transistor SEL5 can be reduced. In the second signal path P2, the effects of parasitic capacitance of the vertical signal line 543 on the side of the first column signal processing unit 5501 among the vertical signal lines 543 other than the second signal path P2 can be reduced. Furthermore, the effects of parasitic capacitance, etc., of the first selection transistor SEL1 to the third selection transistor SEL3 can be reduced.

[0318] <10.4.2 Function and Effect of Example 3-2>

[0319] In the imaging device 1 of embodiment 3-2, a pixel signal from one pixel circuit 210B is detected by the first column signal processing unit 5501 via a first signal path P1 on the vertical signal line 543. Furthermore, in the imaging device 1, a pixel signal from another pixel circuit 210B is detected by the second column signal processing unit 5502 via a second signal path P2 on the vertical signal line 543. The vertical signal line switch SW, which connects the first signal path P1 to the vertical signal lines 543 other than the first signal path P1, is disconnected from the first column signal processing unit 5501. As a result, the effects of parasitic capacitance of the vertical signal line 543 on the first column signal processing unit 5501 side after the vertical signal line switch SW, and the parasitic capacitance of the selection transistor SEL, can be reduced. Furthermore, the rounding of the VSL waveform on the first signal path P1 can be reduced.

[0320] Furthermore, the vertical signal line switch SW, which connects the second signal path P2 to the second column signal processing unit 5502 and is used to connect the second signal path P2 to the vertical signal line 543 other than the second signal path P2, is disconnected. As a result, the effects of parasitic capacitance of the vertical signal line 543 on the second column signal processing unit 5502 side after the vertical signal line switch SW, as well as the parasitic capacitance of the selection transistor SEL, can be reduced. In addition, the rounding of the VSL waveform on the second signal path P2 can be reduced.

[0321] Furthermore, by selectively using the optimal drive among the multiple vertical signal line switches SW on the vertical signal line 543, determined by the location where the vertical signal line switch SW is disconnected, LM current is applied to the column signal processing unit 550 when reading the pixel signal of the pixel circuit 210B furthest from the column signal processing unit 550. As a result, when reading the pixel signal of the pixel circuit 210B close to the column signal processing unit 550, VSL waveform rounding can be reduced, and the drive pulse can be shortened or the LM current consumption can be reduced.

[0322] For ease of explanation, it has been previously explained that the vertical signal line switch SW in Embodiment 3-2 can be an example of an N-type MOS (metal-oxide-semiconductor) transistor that is normally open. However, the vertical signal line switch SW is not limited to this and can be a P-type MOS transistor, and can be modified accordingly.

[0323] <10.5 Specific Examples of Embodiments 3-3>

[0324] <10.5.1 Construction of Example 3-3>

[0325] Figure 46This is an equivalent circuit diagram showing an example of the construction of the selection transistor SEL and the column signal processing unit 550 in the pixel circuit 210B of Embodiment 3-3. Note that the same structures as those in Embodiment 3-1 are given the same reference numerals, and repeated descriptions of the construction and operation will be omitted.

[0326] In the imaging device 1 of Embodiments 3-3, a plurality of column signal processing units 550 are disposed on a third substrate 300. Furthermore, vertical signal lines 543 for electrically connecting the pixel circuit 210B to the column signal processing units 550 are arranged in parallel on a second substrate 200 for each column signal processing unit 550. Each column signal processing unit 550 can simultaneously read pixel signals from the pixel circuit 210B for each vertical signal line 543 to be connected.

[0327] The third substrate 300 includes multiple column signal processing units 550, such as first column signal processing units 5501 to third column signal processing units 5503. The second substrate 200 includes multiple pixel circuits 210B, such as first pixel circuits 210B1 to sixth pixel circuits 210B6. Furthermore, the second substrate 200 includes multiple vertical signal lines 543, such as first vertical signal line 5431 to third vertical signal line 5433. The first vertical signal line 5431 is electrically connected to a first selection transistor SEL1 and a fourth selection transistor SEL4. The second vertical signal line 5432 is electrically connected to a second selection transistor SEL2 and a fifth selection transistor SEL5. The third vertical signal line 5433 is electrically connected to a third selection transistor SEL3 and a sixth selection transistor SEL6. It is assumed that the first vertical signal line 5431, the second vertical signal line 5432, and the third vertical signal line 5433 have the same number of selection transistors SEL connected to each vertical signal line 543, and have the same wiring length. Therefore, it is assumed that the parasitic capacitance and parasitic resistance of each vertical signal line 543 are also the same.

[0328] The drain of the first selection transistor SEL1 of the first pixel circuit 210B1 is electrically connected to the source of the amplification transistor AMP in the first pixel circuit 210B1, and the source of the first selection transistor SEL1 is electrically connected to the first vertical signal line 5431. The drain of the fourth selection transistor SEL4 of the fourth pixel circuit 210B4 is electrically connected to the source of the amplification transistor AMP in the fourth pixel circuit 210B4, and the source of the fourth selection transistor SEL4 is electrically connected to the first vertical signal line 5431. Note that the first vertical signal line 5431 is electrically connected to the first column signal processing unit 5501.

[0329] The drain of the second selection transistor SEL2 of the second pixel circuit 210B2 is electrically connected to the source of the amplification transistor AMP in the second pixel circuit 210B2, and the source of the second selection transistor SEL2 is electrically connected to the second vertical signal line 5432. The drain of the fifth selection transistor SEL5 of the fifth pixel circuit 210B5 is electrically connected to the source of the amplification transistor AMP in the fifth pixel circuit 210B5, and the source of the fifth selection transistor SEL5 is electrically connected to the second vertical signal line 5432. The second vertical signal line 5432 is electrically connected to the second column signal processing unit 5502.

[0330] The drain of the third selection transistor SEL3 in the third pixel circuit 210B3 is electrically connected to the source of the amplification transistor AMP in the third pixel circuit 210B3, and the source of the third selection transistor SEL3 is electrically connected to the third vertical signal line 5433. The drain of the sixth selection transistor SEL6 in the sixth pixel circuit 210B6 is electrically connected to the source of the amplification transistor AMP in the sixth pixel circuit 210B6, and the source of the sixth selection transistor SEL6 is electrically connected to the third vertical signal line 5433. The third vertical signal line 5433 is electrically connected to the third column signal processing unit 5503.

[0331] For example, when the first selection transistor SEL1 is turned on, the first pixel circuit 210B1 causes the pixel signal from the first selection transistor SEL1 to appear in the first vertical signal line 5431. The first column signal processing unit 5501 detects the pixel signal appearing in the first vertical signal line 5431. Furthermore, for example, when the second selection transistor SEL2 is turned on, the second pixel circuit 210B2 causes the pixel signal from the second selection transistor SEL2 to appear in the second vertical signal line 5432. The second column signal processing unit 5502 detects the pixel signal appearing in the second vertical signal line 5432. Furthermore, for example, when the third selection transistor SEL3 is turned on, the third pixel circuit 210B3 causes the pixel signal from the third selection transistor SEL3 to appear in the third vertical signal line 5433. The third column signal processing unit 5503 detects the pixel signal appearing in the third vertical signal line 5433. That is, each column signal processing unit 550 can simultaneously detect the pixel signals of the three pixel circuits 210B using the three vertical signal lines 543.

[0332] <10.5.2 Functions and Effects of Examples 3-3>

[0333] In the imaging device 1 of Embodiment 3-3, since the selection transistors SEL of the pixel circuit 210B connected to each vertical signal line 543 are arranged in an equally divided manner, the parasitic capacitance value of the signal path P connecting the selection transistors SEL and the column signal processing unit 550 is equal. As a result, it is not necessary to selectively use multiple driving modes. Furthermore, each column signal processing unit 550 can simultaneously detect pixel signals from the pixel circuit 210B via the vertical signal lines 543, thereby improving the frame rate of the output image. In addition, it is not necessary to apply multiple LM currents depending on the position of the read-out pixel.

[0334] In the camera device 1, in a circuit configuration in which multiple vertical signal lines 543 are arranged in parallel by utilizing the layout margin of the second substrate 200 having a three-layer structure, the frame rate can be increased by simultaneously reading out multiple pixel signals.

[0335] Although embodiments 3-3 have described an exemplary case in which three vertical signal lines 543 are arranged in parallel, the number is not limited to three, and the number of vertical signal lines 543 can be increased according to the number of column signal processing units 550, and can be appropriately changed.

[0336] In embodiments and variations of the present invention, examples of methods for forming the aforementioned layers, films, elements, etc., include physical vapor deposition (PVD), chemical vapor deposition (CVD), and other methods. Examples of PVD methods include: vacuum vapor deposition using resistance heating or high-frequency heating; electron beam vapor deposition (EB); various sputtering methods (magnetron sputtering, RF-DC combined bias sputtering, electron cyclotron resonance (ECR) sputtering, directed target sputtering, high-frequency sputtering, etc.); ion plating; laser ablation; molecular beam epitaxy (MBE); and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, MOCVD (metal-organic chemical vapor deposition), and photochemical CVD. In addition, other methods include: electroplating, electroless plating, and spin coating; immersion coating; casting; microcontact printing; drop casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; stamping; jetting; and various coating methods such as air knife coating, blade coating, bar coating, knife coating, extrusion coating, reverse roll coating, transfer roll coating, gravure coating, kiss coater coating, cast coater coating, spray coating, slit orifice coater coating, and calendering coater coating. Examples of patterning methods for each layer include: chemical etching such as shadow masking, laser transfer, and photolithography; and physical etching using ultraviolet light, lasers, etc. Furthermore, examples of planarization techniques include CMP (chemical mechanical polishing), laser planarization, and reflow. That is, the imaging device 1 according to the embodiments and variations of the present invention can be easily and inexpensively manufactured using existing semiconductor device manufacturing processes.

[0337] Furthermore, regarding the second substrate 200, the above example shows an example in which an amplifying transistor AMP, a reset transistor RST, and a select transistor SEL for constituting a readout circuit are formed on the same semiconductor substrate. However, at least one transistor can be formed on one semiconductor substrate, and the remaining transistors can be formed on a second semiconductor substrate different from this semiconductor substrate or the first semiconductor substrate. Regarding the second semiconductor substrate, although not shown, for example, an insulating layer, a connection portion, and a connection wiring are formed on one semiconductor substrate, and then a second semiconductor substrate is further stacked thereon. The new semiconductor substrate is stacked on the surface of the interlayer insulating film opposite to the surface stacked on the first semiconductor substrate, thereby enabling the formation of the desired transistors. As an example, an amplifying transistor AMP can be formed on one semiconductor substrate, and a reset transistor RST and / or a select transistor SEL can be formed on the second semiconductor substrate.

[0338] Alternatively, multiple new semiconductor substrates can be provided, and transistors for the desired readout circuit can be disposed on these semiconductor substrates. As an example, an amplifying transistor AMP can be formed on the semiconductor substrate. Furthermore, by stacking an insulating layer, a connection portion, and connection wiring on the semiconductor substrate, and further stacking a second semiconductor substrate on the semiconductor substrate, a reset transistor RST can be formed on the second semiconductor substrate. By stacking an insulating layer, a connection portion, and connection wiring on the second semiconductor substrate, and further stacking a third semiconductor substrate on the second semiconductor substrate, a select transistor SEL can be formed on the third semiconductor substrate. The transistors formed on the semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate can be any transistor used to construct the readout circuit.

[0339] In this way, by having a structure in which multiple semiconductor substrates are disposed on the second substrate 200, the area of ​​the semiconductor substrate occupied by a single readout circuit can be reduced. The reduction in the area of ​​each readout circuit and the miniaturization of each transistor result in a reduction in the chip area. Furthermore, the area of ​​desired transistors among the amplifying transistors, reset transistors, and select transistors used to constitute the readout circuit can be increased. In particular, by increasing the area of ​​the amplifying transistors, a noise reduction effect can also be expected.

[0340] <11. Application Examples>

[0341] Figure 47 This is a diagram illustrating an example of a schematic construction of a camera system 7 including a camera device 1 according to any embodiment or variation thereof.

[0342] The camera system 7 is an electronic device, such as a camera or video camera; or a portable terminal device such as a smartphone or tablet. For example, the camera system 7 includes a camera device 1 according to any of the foregoing embodiments and their variations, a DSP (digital signal processor) circuit 243, a frame buffer memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the camera system 7, the camera device 1, DSP circuit 243, frame buffer memory 244, display unit 245, storage unit 246, operation unit 247, and power supply unit 248 according to any of the foregoing embodiments and their variations are interconnected via a bus 249.

[0343] The imaging device 1 according to any of the foregoing embodiments and their variations outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit for processing the signals (image data) output from the imaging device 1 according to any of the foregoing embodiments and their variations. The frame buffer memory 244 temporarily stores the image data processed by the DSP circuit 243 in units of frames. For example, the display unit 245 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays moving or still images captured by the imaging device 1 according to any of the foregoing embodiments and their variations. The storage unit 246 records the image data of the moving or still images captured by the imaging device 1 according to any of the foregoing embodiments and their variations in a recording medium such as a semiconductor storage device or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to the user's operation. The power supply unit 248 appropriately supplies various power sources, which serve as operating power sources for the camera device 1, DSP circuit 243, frame buffer memory 244, display unit 245, storage unit 246, and operation unit 247 according to any of the foregoing embodiments and their variations, to these supply targets.

[0344] Next, the recording process in camera system 7 will be explained.

[0345] Figure 48 An example flowchart of the camera operation in the camera system 7 is shown. The user issues an instruction to start recording by operating the operation unit 247 (step S101). In response, the operation unit 247 sends a recording command to the camera device 1 (step S102). After receiving the recording command, the camera device 1 (specifically, the system control circuit) performs recording according to a predetermined recording method (step S103).

[0346] The imaging device 1 outputs the image data acquired through imaging to the DSP circuit 243. Here, the image data represents the data of all pixels of the pixel signal generated based on the charge temporarily held in the floating diffuser FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data after predetermined signal processing in the frame buffer memory 244, and then the frame buffer memory 244 records the image data in the storage unit 246 (step S105). In this way, imaging in the imaging system 7 is performed.

[0347] In this applicable example, the camera device 1 according to any of the foregoing embodiments and their variations is applied to the camera system 7. Therefore, miniaturization or high-definition of the camera device 1 can be achieved, thereby providing a miniaturized or high-definition camera system 7.

[0348] <12. Examples of Pixel Circuit Applications in Products>

[0349] [Example of Product Application 1]

[0350] The technology according to the present invention (the technology) is applicable to a variety of products. The technology according to the present invention can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, unmanned aerial vehicles, ships, and robots.

[0351] Figure 49 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention is applicable.

[0352] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 49 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0353] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 can function as a control device for various devices such as: drive force generating devices that generate driving force for the vehicle, such as internal combustion engines or drive motors; drive force transmission mechanisms that transmit driving force to the wheels; steering mechanisms that adjust the vehicle's steering angle; and braking devices that generate braking force for the vehicle.

[0354] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 can function as a control device for various devices such as: keyless entry systems; smart key systems; power windows; or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches transmitted from a portable device used in place of a key can be input to the body system control unit 12020. The body system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0355] The exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing based on the received images, such as detecting people, cars, obstacles, signs, and text on the road.

[0356] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0357] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 may include a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or it can determine whether the driver is drowsy.

[0358] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on vehicle interior / exterior information obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, vehicle speed control, collision warning, lane departure warning, etc.

[0359] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism, braking device, etc., based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing coordinated control aimed at achieving autonomous driving, etc., that enables the vehicle to drive autonomously without relying on the driver's operation.

[0360] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on the vehicle external information acquired by the vehicle external information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the vehicle in front or oncoming vehicles sensed by the vehicle external information detection unit 12030, thereby performing coordinated control aimed at preventing glare, such as switching the high beams to the low beams.

[0361] The audio-visual output unit 12052 sends an output signal of at least one of audio and visual information to an output device capable of visually or audibly notifying vehicle occupants or entities outside the vehicle. Figure 49 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as exemplary output devices. For example, the display unit 12062 may include at least one of an onboard display and a head-up display.

[0362] Figure 50 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0363] exist Figure 50 In the vehicle 12100, there are camera units 12101, 12102, 12103, 12104 and 12105, which serve as camera units 12031.

[0364] For example, camera units 12101, 12102, 12103, 12104, and 12105 are installed in positions on the vehicle 12100, including the front nose, side mirrors, rear bumper, trunk lid, and the upper part of the windshield inside the passenger compartment. Camera unit 12101 at the front nose and camera unit 12105 at the upper part of the windshield inside the passenger compartment primarily acquire images of the front of the vehicle 12100. Camera units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Camera unit 12104 at the rear bumper or trunk lid primarily acquires images of the rear of the vehicle 12100. The front images acquired by camera units 12101 and 12105 are mainly used to detect vehicles or pedestrians, obstacles, traffic lights, traffic signs, or lanes ahead.

[0365] Notice, Figure 50 An example showing the camera range of camera units 12101 to 12104 is illustrated. Camera range 12111 represents the camera range of camera unit 12101 located at the front nose; camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the side mirrors, respectively; and camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or trunk lid. For example, by superimposing the image data captured by camera units 12101 to 12104, a top-view image of vehicle 12100 can be obtained.

[0366] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element including pixels for phase difference detection.

[0367] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of that distance over time (relative speed to vehicle 12100). This allows it to identify three-dimensional objects as the vehicle ahead that are closest to it on the vehicle 12100's path and are traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a pre-defined distance to be maintained from the vehicle ahead and can perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. In this way, coordinated control aimed at achieving autonomous driving, such as automatic driving, can be implemented.

[0368] For example, based on distance information obtained from cameras 12101-12104, microcomputer 12051 can classify three-dimensional object data into three-dimensional object data such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that are easily visually identifiable by the driver of vehicle 12100 and obstacles that are difficult to visually identify. Subsequently, microcomputer 12051 determines the collision risk, which indicates the degree of danger of colliding with each obstacle. When the collision risk is equal to or higher than a set value and there is a possibility of collision, microcomputer 12051 can output an alarm to the driver via audio speaker 12061 or display unit 12062, or can perform forced deceleration and evasive steering via drive system control unit 12010, thereby realizing driving assistance for collision avoidance.

[0369] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, pedestrian identification is performed by the following steps: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to identify whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 to display a rectangular outline for emphasis superimposed on the identified pedestrian. In addition, the sound image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0370] Examples of mobile body control systems to which the technology according to the present invention is applicable have been described above. For example, the technology according to the present invention can be suitably applied to the camera unit 12031 in the aforementioned configuration. Specifically, the camera device 1 according to any of the foregoing embodiments and their variations can be applied to the camera unit 12031. By applying the technology according to the present invention to the camera unit 12031, high-definition captured images with very little noise can be obtained, thereby enabling high-precision control using these captured images in the mobile body control system.

[0371] [Application Example 2 of the Product]

[0372] Figure 51This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the present technology) is applicable.

[0373] Figure 51 The illustration shows a surgeon (physician) 11131 performing surgery on a patient 11132 on bed 11133 using an endoscopic surgery system 11000. As shown, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy delivery device 11112; a support arm device 11120 for supporting the endoscope 11100; and a trolley 11200 equipped with various devices for endoscopic surgery.

[0374] Endoscope 11100 includes: a tube 11101, a region of which, measured from its distal end, having a predetermined length, is inserted into a body cavity of a patient 11132; and a camera head 11102 connected to the base of the tube 11101. In the illustrated example, an endoscope 11100 is shown as a so-called rigid endoscope configured with a rigid tube 11101. However, endoscope 11100 can also be configured as a flexible endoscope with a flexible tube.

[0375] The endoscope tube 11101 has an opening at its distal end, into which the objective lens is fitted. A light source device 11203 is connected to the endoscope 11100, such that light generated by the light source device 11203 is guided to the distal end of the endoscope tube 11101 via a light guide extending inside the endoscope tube 11101, and the guided light is directed through the objective lens to illuminate the object of observation within the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a direct-viewing endoscope, or it can be an oblique-viewing endoscope or a lateral-viewing endoscope.

[0376] An optical system and an image sensor are housed inside the camera head 11102. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW (raw) data to the camera control unit (CCU) 11201.

[0377] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations on the image signals, such as image processing (de-mosaicing), for displaying images based on the image signals.

[0378] Under the control of CCU 11201, display device 11202 displays an image based on an image signal that has undergone image processing by CCU 11201.

[0379] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 11100 when imaging the surgical area, etc.

[0380] Input device 11204 is an input interface for endoscopic surgery system 11000. Users can input various information and commands into endoscopic surgery system 11000 through input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0381] The treatment tool control device 11205 controls the drive of the energy treatment tool 11112, which is used for tissue cauterization and incision, or sealing of blood vessels, etc. To inflate the patient's body cavity 11132 to ensure the field of vision of the endoscope 11100 and to ensure the operating space for the surgeon, the pneumoperitoneum device 11206 pumps gas into the patient's body cavity 11132 through the pneumoperitoneum tube 11111. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, and graphics.

[0382] For example, the light source device 11203 for supplying illumination light to the endoscope 11100 for imaging the surgical area may include, for example, an LED, a laser light source, or a white light source composed of a combination thereof. When the white light source is composed of a combination of red, green, and blue (RGB) laser light sources, the output intensity and timing of each color (each wavelength) can be controlled with high precision. Therefore, white balance adjustment of the captured image can be performed in the light source device 11203. Furthermore, in this case, by illuminating the object of observation with lasers from each of the RGB laser light sources in a time-division manner, and by controlling the driving of the imaging element of the camera head 11102 in sync with the light illumination timing, images corresponding to each of the RGB colors can be captured in a time-division manner. According to this method, color images can be obtained even when no color filter is provided in the imaging element.

[0383] Furthermore, the drive of the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined time intervals. By controlling the drive of the imaging element of the camera head 11102 in sync with the timing of the change in light intensity to acquire images in a time-division manner and synthesizing the images, a high dynamic range image without so-called underexposed shadows and overexposed highlights can be generated.

[0384] Furthermore, the light source device 11203 can be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, a so-called narrow-band light observation (narrow-band imaging) can be performed, for example, by utilizing the wavelength dependence of light absorption in body tissues, irradiating light with a narrower band than the irradiation light used in ordinary observation (i.e., white light), thereby imaging a predetermined tissue, such as blood vessels in the mucosal surface, with high contrast. Alternatively, in special light observation, fluorescence observation can be performed using images obtained by irradiating fluorescence generated by excitation light. In fluorescence observation, body tissue can be irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into the body tissue, and the body tissue can be irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to the above-described special light observation.

[0385] Figure 52 It shows Figure 51 A block diagram illustrating an example of the functional configuration of the camera head 11102 and CCU 11201.

[0386] Camera head 11102 includes lens unit 11401, imaging unit 11402, drive unit 11403, communication unit 11404, and camera head control unit 11405. CCU 11201 includes communication unit 11411, image processing unit 11412, and control unit 11413. Camera head 11102 and CCU 11201 are connected to each other via transmission cable 11400 in a manner that enables communication between them.

[0387] Lens unit 11401 is an optical system disposed at the connection point with lens barrel 11101. Observation light entering from the distal end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 is composed of a combination of multiple lenses, including zoom lenses and focusing lenses.

[0388] The camera unit 11402 includes camera elements. The number of camera elements constituting the camera unit 11402 can be one (so-called single-plate type) or multiple (so-called multi-plate type). When the camera unit 11402 is configured as a multi-plate type, for example, each camera element can generate image signals corresponding to each of the RGB colors, and a color image is obtained by synthesizing these monochrome image signals. The camera unit 11402 can also be configured to have a pair of camera elements, which respectively acquire image signals for the right eye and left eye for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of living tissue in the surgical area. It should be noted that when the camera unit 11402 is configured as a multi-plate type, multiple lens units 11401 of various systems can be provided corresponding to each camera element.

[0389] Furthermore, the camera unit 11402 does not necessarily have to be mounted on the camera head 11102. For example, the camera unit 11402 can be mounted inside the lens barrel 11101 and directly behind the objective lens.

[0390] The drive unit 11403 includes an actuator, and under the control of the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis. Through this operation, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0391] The communication unit 11404 includes communication devices for receiving various information from and sending various information to the CCU 11201. The communication unit 11404 transmits the image signal acquired from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0392] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera head 11102 and supplies the control signals to the camera head control unit 11405. The control signals include information related to imaging conditions, such as: information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image, etc.

[0393] Note that the aforementioned imaging conditions, such as frame rate, exposure value, magnification, and focus, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0394] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0395] The communication unit 11411 includes a communication device for receiving and sending various information to the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via a transmission cable 11400.

[0396] In addition, the communication unit 11411 transmits control signals for controlling the camera head 11102 to the camera head 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0397] The image processing unit 11412 performs various image processing operations on the image signal in RAW data format transmitted from the camera head 11102.

[0398] The control unit 11413 performs various controls related to imaging the surgical area, etc., through the endoscope 11100 and displaying the images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0399] Furthermore, based on the image signal that has already been processed by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image reflecting the surgical area, etc. At this time, the control unit 11413 can use various image recognition techniques to identify various objects in the captured image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living areas, bleeding, and fog when using the energy treatment tool 11112 by detecting the edge shape, color, etc. of objects contained in the captured image. When the display device 11202 is controlled to display the captured image, the control unit 11413 can use the recognition results to overlay various surgical support information onto the image of the surgical area. By overlaying and presenting surgical support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0400] The transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable that supports electrical signal communication, an optical fiber that supports optical communication, or a composite cable thereof.

[0401] Here, although an example of wired communication using transmission cable 11400 is shown, wireless communication between camera head 11102 and CCU 11201 is also possible.

[0402] Examples of endoscopic surgical systems to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be suitably applied to the imaging unit 11402 disposed in the camera head 11102 of the endoscope 11100 in the aforementioned configuration. By applying the technology according to the present invention to the imaging unit 11402, miniaturization and high-definition imaging of the imaging unit 11402 can be achieved, and an endoscope 11100 that achieves miniaturization or high-definition imaging can be provided.

[0403] Although the present invention has been described with reference to exemplary embodiments, variations thereof, applicable examples, and applications in various products, the present invention is not limited to the exemplary embodiments, and various modifications are possible. Note that the effects described in this specification are merely illustrative. The effects of the present invention are not limited to those described herein. The present invention may have effects other than those described herein.

[0404] Furthermore, for example, the present invention may have the following technical solutions.

[0405] (1) A camera device, comprising:

[0406] A first substrate includes a pixel, the pixel including a photodiode and a floating diffuser configured to retain the charge converted by the photodiode;

[0407] A second substrate includes a pixel circuit that reads a pixel signal in the pixel based on the charge held in the floating diffusion portion, the second substrate being stacked on the first substrate;

[0408] A third substrate, including processing circuitry that detects pixel signals read from the pixel circuitry, the third substrate being stacked on the second substrate; and

[0409] A switching unit is provided in the second substrate, which enables electrical connection between the floating diffusion portion and the floating diffusion portion of another pixel in the first substrate.

[0410] (2) The camera device according to (1), wherein,

[0411] The switching unit enables connection between the floating diffusion portion of the currently selected pixel in the first substrate and the floating diffusion portion of the currently unselected pixel in the first substrate.

[0412] (3) A camera device, comprising:

[0413] A first substrate includes a pixel, the pixel including a photodiode and a floating diffuser configured to retain the charge converted by the photodiode;

[0414] The second substrate includes pixel circuits and readout wiring, wherein the pixel circuits read out pixel signals in the pixels based on the charge held in the floating diffusion portion, and the pixel signals read out by each of the pixel circuits appear in the readout wiring, and the second substrate is stacked on the first substrate;

[0415] A third substrate, including processing circuitry that detects pixel signals from the pixel circuitry appearing in the readout wiring, the third substrate being stacked on the second substrate; and

[0416] A switching unit is disposed on the readout wiring of the second substrate and is configured to disconnect the electrical connection between the pixel circuit and the processing circuit.

[0417] (4) The camera device according to (3), wherein,

[0418] The switching unit can disconnect the electrical connection between the following two: one is the signal path on the readout wiring where a pixel signal appears between the currently selected pixel circuit and the processing circuit; the other is the readout wiring other than the signal path.

[0419] (5) The camera device according to (4), wherein,

[0420] The switching unit disconnects the electrical connection between the signal path and the readout wiring other than the signal path by using multiple drive modes corresponding to the electrical connection / disconnection between the signal path and the readout wiring other than the signal path.

[0421] (6) The camera device according to (5), wherein,

[0422] The switching unit adjusts the amount of current to be supplied to the processing circuit based on multiple drive modes corresponding to the electrical connection / disconnection between the signal path and the readout wiring other than the signal path.

[0423] (7) The camera device according to any one of (3) to (6),

[0424] The camera device is configured such that a first processing circuit in the processing circuit is connected to one end of the readout wiring, and a second processing circuit in the processing circuit is connected to the other end of the readout wiring.

[0425] The switching unit is capable of severing the electrical connection between: one, the first signal path on the readout wiring where a pixel signal appears between the currently selected first pixel circuit and the first processing circuit; and the other, all other readout wiring except for the first signal path.

[0426] Furthermore, the switching unit can disconnect the electrical connection between the following two: one is the second signal path on the readout wiring where a pixel signal appears between the currently selected second pixel circuit and the second processing circuit; the other is the readout wiring other than the second signal path.

[0427] List of reference numerals

[0428] 1: Camera device

[0429] 100: First substrate

[0430] 200: Second substrate

[0431] 210: Pixel Circuit

[0432] 300: Third substrate

[0433] 541: pixels

[0434] 543: Vertical signal line

[0435] 550: Signal Processing Unit

[0436] PD: Photodiode

[0437] FD: Floating Diffusion Section

[0438] FDL: FD wiring

[0439] AMP: Amplifying Transistor

[0440] SEL: Select Transistor

[0441] FDG1: FD transfer transistor (switching unit)

[0442] SW: Vertical signal line switch

Claims

1. A camera device, comprising: A first substrate includes a first pixel and a second pixel, the first pixel including a photodiode and a first floating diffusion portion configured to retain the charge converted by the photodiode, and the second pixel including a second floating diffusion portion; The second substrate includes a first pixel circuit and a second pixel circuit. The first pixel circuit reads out a first pixel signal in the first pixel based on the charge held in the first floating diffusion portion and includes a first selection transistor. The second pixel circuit is connected to the second pixel and includes a second selection transistor. The second substrate is stacked on the first substrate. A third substrate includes a processing circuit that detects a pixel signal read from the first pixel circuit, and the third substrate is stacked on the second substrate. and A switching unit is provided in the second substrate, which enables electrical connection between the first floating diffusion portion of the first pixel and the second floating diffusion portion of the second pixel based on the first selection transistor being in the on state and the second selection transistor being in the off state.

2. A camera device, comprising: A first substrate includes a first pixel, the first pixel including a photodiode and a first floating diffuser configured to retain the charge converted by the photodiode; The second substrate includes a plurality of pixel circuits and a readout wiring including a first readout wiring. The first pixel circuit of the plurality of pixel circuits reads out a first pixel signal based on the charge held in the first floating diffusion portion of the first pixel, and the first pixel signal read out by the first pixel circuit appears in the first readout wiring. The second substrate is stacked on the first substrate. A third substrate includes a processing circuit that detects the first pixel signal in the first readout wiring, and the third substrate is stacked on the second substrate. and A switching unit is disposed on the first readout wiring of the second substrate and is configured to: disconnect the first electrical connection between the first pixel circuit and the processing circuit; and disconnect the second electrical connection between the first signal path on the first readout wiring and the second readout wiring different from the first signal path. The first signal path is located between the first pixel circuit and the processing circuit. The first signal path and the second readout wiring are disconnected based on multiple driving modes, the multiple driving modes corresponding to the second electrical connection and the disconnection between the first signal path and the second readout wiring.

3. The camera device according to claim 2, wherein, The switching unit adjusts the amount of current to be supplied to the processing circuit according to the multiple driving modes.

4. The camera device according to claim 2 or 3, The camera device is configured such that a first processing circuit in the processing circuit is connected to one end of the first readout wiring, and a second processing circuit in the processing circuit is connected to the other end of the first readout wiring. in, The switching unit is capable of severing the electrical connection between: one, the third signal path on the first readout wiring where a pixel signal appears between the currently selected first pixel circuit and the first processing circuit; and the other, all readout wirings except for the third signal path. Furthermore, the switching unit can disconnect the electrical connection between the following two: one is the fourth signal path on the first readout wiring where a pixel signal appears between the currently selected second pixel circuit and the second processing circuit; the other is the readout wiring other than the fourth signal path.

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