Scan driving circuit and display device including the same

Abstract

The present invention relates to a scan drive circuit and a display device including the scan drive circuit. The scan drive circuit includes: a drive circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; and a mask circuit configured to stop the drive circuit from outputting the scan signal in response to a mask signal and a signal indicating an operating state of the drive circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0078741, filed on June 26, 2020, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] An aspect of some embodiments of the present disclosure herein relates to a display device. Background Art

[0004] Among display devices, organic light emitting display devices display images using organic light emitting diodes that generate light through recombination of electrons and holes. Organic light emitting display devices generally have a relatively fast response speed and are driven with relatively low power consumption.

[0005] Organic light-emitting display devices typically include pixels connected to data lines and scan lines. The pixels typically include an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing through the OLED. The circuit unit controls the amount of current flowing through the OLED from a first drive voltage to a second drive voltage in response to a data signal. In this case, light (e.g., light having a set or predetermined brightness) is generated in response to the amount of current flowing through the OLED.

[0006] As the application fields of display devices become more diverse, multiple different images can be displayed on a single display device. It is desirable to have a technology that reduces the power consumption of a display device that displays multiple images.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of some embodiments of the present disclosure herein relate to a display device, and for example, to a display device including a scan driving circuit.

[0009] Aspects of some embodiments of the inventive concept include a scan driving circuit capable of reducing power consumption and a display device including the scan driving circuit.

[0010] According to some embodiments conceived in the present invention, a scan driving circuit includes: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; and a masking circuit configured to cause the driving circuit to stop outputting the scan signal in response to a masking signal and a signal indicating an operating state of the driving circuit.

[0011] According to some embodiments, the signal indicating the operation state of the driving circuit may be any one of a carry signal and a scan signal.

[0012] According to some embodiments, the driving circuit may include: a first transistor configured to transmit a carry signal to a first node in response to a first clock signal among clock signals; and a second transistor connecting an output terminal to a first voltage terminal receiving a first voltage in response to a signal of the first node.

[0013] According to some embodiments, the masking circuit may include: a first masking transistor connected between a first node and a masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and a first voltage terminal and including a gate electrode connected to an output terminal.

[0014] According to some embodiments, the masking circuit may include: a first masking transistor connected between the first node and the masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and the first voltage terminal and including a gate electrode connected to an input terminal receiving a carry signal.

[0015] According to some embodiments, the masking circuit may include: a first masking transistor connected between a first node and a masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and a first voltage terminal and including a gate electrode connected to the first node.

[0016] According to some embodiments, the driving circuit may further include: a third transistor connected between a second voltage terminal receiving a second voltage and the output terminal and including a gate electrode connected to the second node; and a fourth transistor connected between the second voltage terminal and the second node and including a gate electrode connected to the first node.

[0017] According to some embodiments, the masking circuit may include: a first switch electrically connecting a first terminal receiving a first voltage and a second terminal in response to a scan signal; and a second switch electrically connecting an input terminal receiving a carry signal and the second terminal of the first switch in response to a masking signal.

[0018] According to some embodiments, the masking circuit may include: a first logic circuit configured to receive a scan signal and a carry signal; a second logic circuit configured to receive the carry signal and the masking signal; and a third logic circuit configured to receive an output signal of the first logic circuit and an output signal of the second logic circuit and provide the carry signal to the driving circuit.

[0019] According to some embodiments, the masking circuit may include: a first logic circuit configured to receive a masking signal and a scan signal output from a driving circuit; a second logic circuit configured to invert and output the masking signal; a third logic circuit configured to receive the scan signal output from the driving circuit, the inverted masking signal output from the second logic circuit, and output the scan signal; and a fourth logic circuit configured to receive the output signal of the first logic circuit and the output signal of the second logic circuit and output the output scan signal.

[0020] According to some embodiments conceived in the present invention, a display device includes: a display panel, including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines; a data driving circuit configured to drive the plurality of data lines; a scan driving circuit configured to drive the plurality of scan lines; and a driving controller configured to receive an image signal and a control signal and to control the data driving circuit and the scan driving circuit to display an image on the display panel, wherein the driving controller divides the display panel into a first display area and a second display area based on the image signal and outputs a mask signal indicating a starting point of the second display area, wherein the scan driving circuit includes a plurality of driving stages, each driving stage driving a corresponding scan line among the plurality of scan lines, wherein each of the plurality of driving stages includes: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal from the driving controller; and a mask circuit configured to cause the driving circuit to stop outputting the scan signal in response to the mask signal and a signal indicating the operating status of the corresponding driving stage among the plurality of driving stages.

[0021] According to some embodiments, the signal indicating the operation state of the corresponding driving stage may be any one of a carry signal and a scan signal.

[0022] According to some embodiments, a scan signal output from a j-th driving stage among a plurality of driving stages may be provided as a carry signal of a j+k-th driving stage (j and k are natural numbers).

[0023] According to some embodiments, each of the plurality of driver stages may include: a first transistor configured to transmit a carry signal to a first node in response to a first clock signal among the clock signals; and a second transistor connecting an output terminal to a first voltage terminal receiving a first voltage in response to a signal from the first node.

[0024] According to some embodiments, the masking circuit may include: a first masking transistor connected between a first node and a masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and a first voltage terminal and including a gate electrode connected to an output terminal.

[0025] According to some embodiments, when the starting point of the second display area corresponds to the jth scan line, the masking signal may be changed to a level that turns on the first masking transistor when the j-1th scan signal is at an active level and the jth scan signal is at an inactive level.

[0026] According to some embodiments, the masking circuit may include: a first masking transistor connected between the first node and the masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and the first voltage terminal and including a gate electrode connected to an input terminal receiving a carry signal.

[0027] According to some embodiments, when the starting point of the second display area corresponds to the jth scan line, the masking signal may be changed to a level for turning on the first masking transistor when the j-2th scan signal is at an active level and the j-1th scan signal is at an inactive level.

[0028] According to some embodiments, the masking circuit may include: a first masking transistor connected between a first node and a masking node and including a gate electrode connected to an input terminal receiving a masking signal; and a second masking transistor connected between the masking node and a first voltage terminal and including a gate electrode connected to the first node.

[0029] According to some embodiments, the driving circuit may further include: a third transistor connected between a second voltage terminal receiving a second voltage and the output terminal and including a gate electrode connected to the second node; and a fourth transistor connected between the second voltage terminal and the second node and including a gate electrode connected to the first node.

[0030] According to some embodiments, the masking circuit may include: a first switch electrically connecting a first terminal receiving a first voltage and a second terminal in response to a scan signal; and a second switch electrically connecting an input terminal receiving a carry signal and the second terminal of the first switch in response to a masking signal.

[0031] According to some embodiments, the masking circuit may include: a first logic circuit configured to receive a scan signal and a carry signal; a second logic circuit configured to receive the carry signal and the masking signal; and a third logic circuit configured to receive an output signal of the first logic circuit and an output signal of the second logic circuit and provide the carry signal to the driving circuit.

[0032] According to some embodiments, the masking circuit may include: a first logic circuit configured to receive a masking signal and a scan signal output from a driving circuit; a second logic circuit configured to invert and output the masking signal; a third logic circuit configured to receive the scan signal output from the driving circuit, the inverted masking signal output from the second logic circuit, and output the scan signal; and a fourth logic circuit configured to receive the output signal of the first logic circuit and the output signal of the second logic circuit and output the output scan signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the embodiments of the present inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate aspects of some embodiments of the present inventive concept and, together with the description, serve to explain the principles of some embodiments of the present inventive concept. In the drawings:

[0034] Figure 1 is a perspective view of a display device according to some embodiments of the present inventive concept;

[0035] Figure 2 is a block diagram illustrating a display device according to some embodiments of the present inventive concept;

[0036] Figure 3 is an equivalent circuit diagram of a pixel according to some embodiments of the present inventive concept;

[0037] Figure 4 It is an icon Figure 3 A timing diagram of the operation of the pixel shown in FIG;

[0038] Figure 5 is a block diagram of a scan driving circuit according to some embodiments of the present inventive concept;

[0039] Figure 6 The diagram shows the normal mode and low power mode. Figure 5 FIG. 2 is a diagram showing a scanning signal output by the scanning driving circuit shown in FIG. 3 ;

[0040] Figure 7 shows a scanning signal in low power mode;

[0041] Figure 8 is a circuit diagram illustrating a j-th driving stage STj in a scan driving circuit according to some embodiments of the inventive concept;

[0042] Figure 9 is a timing diagram illustrating operations of the j-1th driving stage and the jth driving stage in the low power mode;

[0043] Figure 10 is a timing diagram illustrating the operation of the j-th driving stage in the low power mode;

[0044] Figure 11 is a circuit diagram illustrating a j-th driving stage in a scan driving circuit according to some embodiments of the inventive concept;

[0045] Figure 12 is a timing diagram illustrating the operation of the j-th driving stage in the low power mode;

[0046] Figure 13 is a circuit diagram illustrating a j-th driving stage in a scan driving circuit according to some embodiments of the inventive concept;

[0047] Figure 14 is a block diagram of a scan driving circuit according to some embodiments of the present inventive concept;

[0048] Figure 15 Shown with Figure 14 A circuit configuration of a j-th masking circuit corresponding to a j-th driving stage among the masking circuits illustrated in FIG;

[0049] Figure 16 shows a circuit configuration of a j-th masking circuit corresponding to a j-th driver stage; and

[0050] Figure 17 A circuit configuration of a j-th masking circuit corresponding to a j-th driving stage is shown. DETAILED DESCRIPTION

[0051] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on," "connected to" or "combined to" another component, this means that the component can be directly on, connected to or combined to the other component, or a third component may be present between the component and the other component.

[0052] The same reference numerals refer to the same elements. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description. "And / or" includes all of the one or more combinations defined by the relevant components.

[0053] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The above terms are used only to distinguish one component from another. In one embodiment, for example, a first component may be referred to as a second component, and vice versa, without departing from the scope of the present invention. Unless otherwise specified, terms in the singular may include plural forms.

[0054] In addition, terms such as "below," "lower side," "upper," and "upper side" are used to describe the relationship of the configurations shown in the drawings, and the terms are described as relative concepts based on the directions shown in the drawings.

[0055] In various embodiments of the present inventive concept, the terms “include” or “comprise” specify attributes, regions, fixed numbers, steps, processes, elements and / or parts, but do not exclude other attributes, regions, fixed numbers, steps, processes, elements and / or parts.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. Generally, terms defined in dictionaries should be considered to have the same meaning as in the context of the relevant field and should not be understood unusually or as having overly formal meanings unless explicitly defined herein.

[0057] Hereinafter, aspects of some embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device according to some embodiments of the inventive concept.

[0059] refer to Figure 1 , a portable terminal is illustrated as one of the display devices DD according to some embodiments of the present invention. The portable terminal may include a tablet PC, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, and a wristwatch-type electronic device, etc. However, the embodiments according to the present invention are not limited thereto. The present invention can be used for large electronic devices such as televisions or external billboards, and can also be used for small electronic devices such as personal computers, notebook computers, telephone booths, car navigation units, and cameras. These are only proposed as embodiments, and it is obvious that they can be adopted in other electronic devices without departing from the scope of the present invention.

[0060] like Figure 1 As shown in , the display surface on which the first image IM1 and the second image IM2 are displayed is parallel to the plane defined by the first direction DR1 and the second direction DR2. The display device DD includes a plurality of areas distinguished on the display surface. The display surface includes a display area DA in which the first image IM1 and the second image IM2 are displayed and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. As an example, the display area DA may have a rectangular form. The non-display area NDA may surround the display area DA. In addition, according to some embodiments, for example, the display device DD may have a partially curved shape. As a result, an area of ​​the display area DA may have a curved shape.

[0061] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In certain applications, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. According to some embodiments, for example, the first image IM1 may be a moving image, and the second image IM2 may be a static image or text information with a long change cycle.

[0062] The display device DD according to some embodiments may drive the first display area DA1 in which a moving image is displayed at a normal frequency, and drive the second display area DA2 in which a static image is displayed at a frequency lower than the normal frequency. The display device DD may reduce power consumption by reducing the driving frequency of the second display area DA2.

[0063] The size of each of the first display area DA1 and the second display area DA2 can be a preset size and can be changed by an application. According to some embodiments, when the first display area DA1 displays a static image and the second display area DA2 displays a moving image, the first display area DA1 can be driven at a low frequency, and the second display area DA2 can be driven at a normal frequency. In addition, the display area DA can be divided into three or more display areas, and the driving frequency of each display area in the display area can be determined according to the type of image displayed in each display area (e.g., a static image or a moving image).

[0064] Figure 2 is a block diagram illustrating a display device DD according to some embodiments of the inventive concept.

[0065] refer to Figure 2 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 and a voltage generator 300 .

[0066] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates the image data signal DATA obtained by converting the data format of the image signal RGB to meet the specifications of the interface with the data drive circuit 200. The drive controller 100 outputs a first scan control signal SCS1, a second scan control signal SCS2, an emission control signal ESC, and a data control signal DCS.

[0067] The data driving circuit 200 receives a data control signal DCS and an image data signal DATA from the driving controller 100. The data driving circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0068] The voltage generator 300 generates voltages required for the operation of the display panel DP. According to some embodiments, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT. According to some embodiments, the voltage generator 300 may operate under the control of the driving controller 100.

[0069] The display panel DP includes a first scan driving circuit SD1, a second scan driving circuit SD2, a light emitting driving circuit EDC, scan lines SCL0 to SCLn, scan lines SWL0 to SWLn, light emitting control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. According to some embodiments, the first scan driving circuit SD1 is disposed on a first side of the display panel DP.

[0070] Scan lines SCL0 to SCLn extend from a first scan drive circuit SD1 in a first direction DR1. Scan lines SWL0 to SWLn extend from a second scan drive circuit SD2 in the first direction DR1. Light emission control lines EML1 to EMLn extend from a light emission drive circuit EDC in a direction opposite to the first direction DR1. The scan lines SCL0 to SCLn, the scan lines SWL0 to SWLn, and the light emission control lines EML1 to EMLn are spaced apart from each other in a second direction DR2. Data lines DL1 to DLm extend from a data drive circuit 200 in a direction opposite to the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0071] Each pixel PX among the plurality of pixels PX is electrically connected to two corresponding scan lines among the scan lines SCL0 to SCLn and two corresponding scan lines among the scan lines SWL0 to SWLn. In addition, each pixel PX among the plurality of pixels PX is electrically connected to a corresponding one of the emission control lines EML1 to EMLn and a corresponding one of the data lines DL1 to DLm. According to some embodiments, for example, Figure 2 As shown in , the pixels PX in the first row may be connected to the scan lines SCL0 and SCL1 and the scan lines SWL0 and SWL1. In addition, the pixels PX in the second row may be connected to the scan lines SCL1 and SCL2 and the scan lines SWL1 and SWL2.

[0072] Each of the plurality of pixels PX includes an organic light emitting diode ED (refer to Figure 3 ) and a pixel circuit unit PXC (reference Figure 3 The pixel circuit unit PXC may include a capacitor and a plurality of transistors. The first scan driving circuit SD1, the second scan driving circuit SD2, and the light emitting driving circuit EDC may include transistors formed by the same process as the pixel circuit unit PXC.

[0073] Each of the pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0074] The first scan driving circuit SD1 receives a first scan control signal SCS1 from the driving controller 100. The first scan driving circuit SD1 can output scan signals to the scan lines SCL0 to SCLn in response to the first scan control signal SCS1. The second scan driving circuit SD2 receives a second scan control signal SCS2 from the driving controller 100. The second scan driving circuit SD2 can output scan signals to the scan lines SWL0 to SWLn in response to the second scan control signal SCS2. The light emitting driving circuit EDC can output light emitting control signals to the light emitting control lines EML1 to EMLn in response to the light emitting control signal ECS.

[0075] The circuit configuration and operation of the first scan driving circuit SD1 will be described in more detail later.

[0076] refer to Figure 2 The first scan drive circuit SD1 is shown and described as outputting scan signals to the scan lines SCL0 to SCLn, the second scan drive circuit SD2 is outputting scan signals to the scan lines SWL0 to SWLn, and the light emitting drive circuit EDC is outputting light emitting control signals to the light emitting control lines EML1 to EMLn. However, embodiments according to the inventive concept are not limited thereto. According to some embodiments, for example, the first scan drive circuit SD1 and the second scan drive circuit SD2 are configured as a single circuit, or the first scan drive circuit SD1, the second scan drive circuit SD2, and the light emitting drive circuit EDC can be configured as a single circuit.

[0077] The driving controller 100 according to some embodiments divides the display panel DP into a first display area DA1 (refer to FIG. Figure 1 ) and the second display area DA2 (reference Figure 1 ), and outputs at least one masking signal indicating a starting point of the second display area DA2. The at least one masking signal may be included in each of the first scan control signals SCS1.

[0078] According to some embodiments, the first scan driving circuit SD1 and the second scan driving circuit SD2 can drive the scan lines corresponding to the first display area DA1 among the scan lines SCL0 to SCLn at a first driving frequency in response to the first scan control signal SCS1, and drive the scan lines corresponding to the second display area DA2 at a second driving frequency different from the first driving frequency.

[0079] Figure 3 is an equivalent circuit diagram of a pixel according to some embodiments of the inventive concept.

[0080] Figure 3 The equivalent circuit diagram of the pixel PXij is shown. The pixel PXij is connected to Figure 2 The data lines DL1 to DLm shown in the figure include the i-th data line DLi, the j-1-th scan line SCLj-1 and the j-th scan line SCLj, the j-1-th scan line SWLj-1 and the j-th scan line SWLj, and the j-th light-emitting control line EMLj among the light-emitting control lines EML1 to EMLn.

[0081] According to some embodiments, the pixel circuit unit PXC of the pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 is an N-type transistor having an oxide semiconductor as a semiconductor layer. However, the embodiments according to the present invention are not limited thereto, and all of the first transistor T1 to the seventh transistor T7 may be N-type transistors or P-type transistors. According to some embodiments, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the others may be P-type transistors. In addition, Figure 3 The pixel circuit unit PXC shown in FIG. 1 is merely an example, and the circuit configuration of the pixel circuit unit PXC may be modified and implemented.

[0082] refer to Figure 3 According to some embodiments, a pixel PXij of a display device includes at least one organic light emitting diode ED. According to some embodiments, an example in which one pixel PXij includes one organic light emitting diode ED is described, but embodiments according to the inventive concept are not limited thereto.

[0083] For ease of description, Figure 3 and Figure 4In the description, the j-1th scan line SCLj-1, the j-th scan line SCLj, the j-1th scan line SWLj-1, the j-th scan line SWLj and the j-th light-emitting control line EMLj are respectively referred to as the first scan line SCLj-1, the second scan line SCLj, the third scan line SWLj-1, the fourth scan line SWLj and the light-emitting control line EMLj.

[0084] The first to fourth scan lines SCLj-1, SCLj, SWLj-1, and SWLj can transmit first to fourth scan signals SCj-1, SCj, SWj-1, and SWj, respectively. The first scan signal SCj-1 can turn on / off the fourth transistor T4. The second scan signal SCj can turn on / off the third transistor T3. The third scan signal SWj-1 can turn on / off the seventh transistor T7. The fourth scan signal SWj can turn on / off the second transistor T2.

[0085] The light emitting control line EMLj may transmit a light emitting control signal EMj capable of controlling the light emission of the organic light emitting diode ED included in the pixel PXij. The light emitting control signal EMj transmitted by the light emitting control line EMLj may have a waveform different from that of the first to fourth scan signals SCj-1, SCj, SWj-1, and SWj. The data line DLi transmits a data signal Di. The data signal Di may have a waveform different from that input to the display device DD (reference signal). Figure 2 ) The first to third driving voltage lines VL1, VL2, and VL3 may transmit a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT, respectively.

[0086] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the organic light emitting diode ED via the sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive a data signal Di transmitted from the data line DLi according to a switching operation of the second transistor T2 and can supply a driving current Id to the organic light emitting diode ED.

[0087] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the fourth scan line SWLj. The second transistor T2 can be turned on according to the fourth scan signal SWj received through the fourth scan line SWLj, and thus transmit the data signal Di transmitted from the data line DLi to the first electrode of the first transistor T1.

[0088] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line SCLj. The third transistor T3 can be turned on according to the second scan signal SCj received through the second scan line SCLj, and thus the gate electrode and the second electrode of the first transistor T1 are connected to each other, thereby diode-connecting the first transistor T1.

[0089] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which the initialization voltage VINT is transmitted, and a gate electrode connected to the first scan line SCLj-1. The fourth transistor T4 can be turned on according to the first scan signal SCj-1 received through the first scan line SCLj-1, and thus perform an initialization operation of initializing the voltage of the gate electrode of the first transistor T1 by transmitting the initialization voltage VINT to the gate electrode of the first transistor T1.

[0090] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the light emitting control line EMLj.

[0091] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the anode of the organic light emitting diode ED, and a gate electrode connected to the emission control line EMLj.

[0092] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EMj received through the emission control line EMLj, so that the first driving voltage ELVDD can be compensated through the diode-connected first transistor T1 and transmitted to the organic light emitting diode ED.

[0093] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4 , a second electrode connected to the second electrode of the sixth transistor T6 , and a gate electrode connected to the third scan line SWLj- 1 .

[0094] As described above, one end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the organic light emitting diode ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The structure of the pixel PXij according to some embodiments is not limited to Figure 3 The structure shown in , and the number of transistors, the number of capacitors, and the connection relationship in one pixel PXij can be variously modified.

[0095] Figure 4 It is an icon Figure 3 The timing diagram of the operation of the pixel PXij shown in FIG. Figure 3 and Figure 4 The operation of the display device according to some embodiments is described in more detail.

[0096] refer to Figure 3 and Figure 4 A high-level first scan signal SCj-1 is supplied through the first scan line SCLj-1 during the initialization period within one frame. The fourth transistor T4 is turned on in response to the high-level first scan signal SCj-1, and the initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, so that the first transistor T1 is initialized.

[0097] At the same time, the seventh transistor T7 is turned on by receiving the third scan signal SWj-1 of a low level through the third scan line SWLj-1. A portion of the driving current Id may pass through the seventh transistor T7 as a bypass current Ibp through the seventh transistor T7.

[0098] Even when the minimum current of the first transistor T1 for displaying a black image flows as the driving current, if the organic light-emitting diode ED emits light, the black image cannot be correctly displayed. Therefore, in some embodiments of the present invention, the seventh transistor T7 in the pixel PXij can distribute a portion of the minimum current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the organic light-emitting diode ED. Here, the minimum current of the first transistor T1 refers to the current when the first transistor T1 is turned off due to the gate-source voltage Vgs of the first transistor T1 being less than the threshold voltage Vth. The minimum driving current (e.g., a current of 10pA or less) when the first transistor T1 is turned off is transmitted to the organic light-emitting diode ED to be represented as a black brightness image. It can be said that when the minimum driving current for displaying a black image flows, the bypass transmission of the bypass current Ibp has a significant impact, and when a large driving current for displaying an image such as a normal image or a white image flows, the impact of the bypass current Ibp is almost non-existent. Therefore, when a driving current for displaying a black image flows, the light emitting current Ied of the organic light emitting diode ED (the amount of the bypass current Ibp exiting through the seventh transistor T7 is subtracted from the driving current Id) can have a minimum current amount at a level that can reliably represent a black image. Therefore, a precise black brightness image can be achieved by using the seventh transistor T7, so that the contrast can be improved. According to some embodiments, the bypass signal is the third scan signal SWj-1, but embodiments of the present disclosure are not limited thereto.

[0099] Next, when a high-level second scan signal SCj is supplied via the second scan line SCLj during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is diode-connected via the turned-on third transistor T3 and is biased in the forward direction. Furthermore, the second transistor T2 is turned on by a low-level fourth scan signal SWj. Then, a compensation voltage Di-Vth, which is obtained by subtracting the threshold voltage Vth of the first transistor T1 from the data signal Di supplied from the data line DLi, is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage Di-Vth.

[0100] The first driving voltage ELVDD and the compensation voltage Di-Vth are applied to both ends of the capacitor Cst, and charges corresponding to a voltage difference between the both ends may be stored in the capacitor Cst.

[0101] Next, during the light emission period, the light emission control signal EMj supplied from the light emission control line EMLj changes from a high level to a low level. During the light emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light emission control signal EMj. Then, a drive current Id corresponding to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD is generated. The drive current Id is supplied to the organic light emitting diode ED through the sixth transistor T6, causing the light emission current Ied to flow through the organic light emitting diode ED.

[0102] exist Figure 4 , it is shown that the high-level portion of the first scan signal SCj-1 and the high-level portion of the second scan signal SCj do not overlap in time. According to some embodiments, the high-level portion of the first scan signal SCj-1 and the high-level portion of the second scan signal SCj may partially overlap.

[0103] Figure 5 is a block diagram of a first scan driving circuit SD1 according to some embodiments of the inventive concept.

[0104] refer to Figure 5 , the first scan driving circuit SD1 includes driving stages ST0 to STn.

[0105] Each of the driver stages ST0 to STn drives Figure 2 The driving controller 100 shown in FIG. 1 receives a first scanning control signal SCS1. The first scanning control signal SCS1 includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a mask signal MS. Each of the driving stages ST0 to STn receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from Figure 2The voltage generator 300 shown in FIG.

[0106] The mask signal MS is a signal for driving some of the driving stages ST0 to STn at a normal frequency and driving the remaining driving stages at a low frequency. The mask signal MS may be commonly provided to all driving stages ST0 to STn in the first scan driving circuit SD1.

[0107] According to some embodiments, the driving stages ST0 to STn output scan signals SC0 to SCn. The scan signals SC0 to SCn may be provided to Figure 2 The scan lines SCL0 to SCLn are shown in FIG.

[0108] The driving stage ST0 can receive the start signal FLM as a carry signal. Each of the driving stages ST1 to STn has a dependent connection relationship in which the scan signal output from the previous driving stage is received as a carry signal. Among the driving stages ST1 to STn, the scan signal SCj output from the j-th driving stage STj can be provided as a carry signal of the j+k-th driving stage STj+k (j and k are natural numbers). According to some embodiments, for example, the driving stage ST1 receives the scan signal SC0 output from the previous driving stage ST0 as a carry signal, and the driving stage ST2 receives the scan signal SC1 output from the previous driving stage ST1 as a carry signal. Figure 5 It is illustrated that the j-th driving stage STj receives the scan signal from the j-1-th driving stage STj-1 as a carry signal, but embodiments according to the inventive concept are not limited thereto.

[0109] Figure 6 The diagram shows the normal mode and low power mode. Figure 5 FIG. 4 is a diagram showing scan signals SC0 to SCn outputted by the first scan driving circuit SD1 .

[0110] refer to Figures 5 and 6 During the normal mode N-MODE, the mask signal MS is maintained at a high level. During the normal mode N-MODE, the driving stages ST0 to STn sequentially output the scan signals SC0 to SCn at a high level in each of the frames F1, F2, and F3.

[0111] In the low power mode L-MODE, the mask signal MS changes from a high level to a low level every frame. According to some embodiments, for example, when the mask signal MS is maintained at a high level in the fourth frame F4, the scan signals SC0 to SC1920 may be sequentially output at a high level. When the mask signal MS changes to a low level in the fourth frame F4, the scan signals SC1921 to SC3840 are maintained at a low level.

[0112] Figure 7Scan signals SC0 to SC3840 are shown in the low power mode.

[0113] refer to Figure 7 , in the low power mode, the frequency of the scan signals SC0 to SC1920 is 120 Hz, and the frequency of the scan signals SC1921 to SC3840 is 1 Hz.

[0114] According to some embodiments, for example, the scan signals SC0 to SC1920 are Figure 1 , and the scanning signals SC1921 to SC3840 correspond to the first display area DA1 of the display device DD shown in FIG. 1 , and the scanning signals SC1921 to SC3840 correspond to the second display area DA2. The first display area DA1 in which a video is displayed is driven by the scanning signals SC0 to SC1920 of a normal frequency (e.g., 120 Hz), and the second display area DA2 in which a static image is displayed is driven by the scanning signals SC1921 to SC3840 of a low frequency (e.g., 1 Hz). Since only the second display area DA2 in which a static image is displayed is driven at a low frequency, it is possible to operate the display device DD (reference image) without causing the display device DD to be distorted. Figure 1 ) reduces power consumption in the case of deterioration of display quality. In the low power mode, some of the scan signals SC0 to SC3840 are driven at a normal frequency, and some of the scan signals SC0 to SC3840 are driven at a low frequency, so the low power mode can be called a multi-frequency mode.

[0115] Figure 8 is a circuit diagram illustrating a j-th driving stage STj in the first scan driving circuit SD1 according to some embodiments of the inventive concept.

[0116] Figure 8 Pictured Figure 5 The j-th driving stage STj (j is a positive integer) among the driving stages ST0 to STn shown in the figure. Figure 5 Each of the plurality of driving stages ST0 to STn illustrated in FIG may include Figure 8 The j-th driver stage STj has the same circuit configuration as that of the j-th driver stage STj shown in FIG. Hereinafter, the j-th driver stage STj is referred to as the driver stage STj.

[0117] refer to Figure 8 , the driving stage STj includes a driving circuit DC, a masking circuit MSC, first to sixth input terminals IN1 to IN6 , and an output terminal OUT1 .

[0118] The driving circuit DC includes transistors NT1 to NT12 and capacitors NC1 to NC3. Each of the transistors NT1 to NT12 is illustrated and described as a P-type transistor, but embodiments of the present inventive concept are not limited thereto. Some or all of the transistors NT1 to NT12 may be N-type transistors.

[0119] The driving circuit DC receives a carry signal CRj-1, a first clock signal CLK1, a second clock signal CLK2, a first voltage VGL, and a second voltage VGH through first to fifth input terminals IN1 to IN5 and outputs a scan signal SCj through an output terminal OUT1.

[0120] The carry signal CRj-1 received through the first input terminal IN1 may be Figure 5 The scanning signal SCj-1 output by the previous driving stage STj-1 shown in FIG. Figure 5 The carry signal CRj-1 of the driving stage ST0 shown in FIG. 5 may be the start signal FLM.

[0121] Figure 5 The fourth input terminal IN4 of each of some of the driver stages ST0 to STn (for example, odd-numbered driver stages) illustrated in FIG 1 receives the first clock signal CLK1, and the fifth input terminal IN5 receives the second clock signal CLK2. In addition, the fourth input terminal IN4 of each of some of the driver stages ST0 to STn (for example, even-numbered driver stages) receives the second clock signal CLK2, and the fifth input terminal IN5 receives the first clock signal CLK1.

[0122] The transistor NT1 is connected between the first input terminal IN1 and the first node N1 and includes a gate electrode connected to the fourth input terminal IN4. The transistor NT2 is connected between the second input terminal IN2 and the sixth node N6 and includes a gate electrode connected to the fourth node N4. The transistor NT3 is connected between the sixth node N6 and the fifth input terminal IN5 and includes a gate electrode connected to the second node N2.

[0123] Transistors NT4-1 and NT4-2 are connected in series between a fourth node N4 and a fourth input terminal IN4. Each of transistors NT4-1 and NT4-2 includes a gate electrode connected to a first node N1. Transistor NT5 is connected between a fourth node N4 and a third input terminal IN3 and includes a gate electrode connected to a fourth input terminal IN4. Transistor NT6 is connected between a third node N3 and a seventh node N7 and includes a gate electrode connected to a fifth input terminal IN5. Transistor NT7 is connected between a seventh node N7 and a fifth input terminal IN5 and includes a gate electrode connected to a fifth node N5.

[0124] Transistor NT8 is connected between the second input terminal IN2 and the third node N3 and includes a gate electrode connected to the first node N1. Transistor NT9 is connected between the second input terminal IN2 and the output terminal OUT1 and includes a gate electrode connected to the third node N3. Transistor NT10 is connected between the output terminal OUT1 and the third input terminal IN3 and includes a gate electrode connected to the second node N2. Transistor NT11 is connected between the fourth node N4 and the fifth node N5 and includes a gate electrode connected to the third input terminal IN3. Transistor NT12 is connected between the first node N1 and the second node N2 and includes a gate electrode connected to the third input terminal IN3.

[0125] The capacitor NC1 is connected between the second input terminal IN2 and the third node N3. The capacitor NC2 is connected between the fifth node N5 and the seventh node N7. The capacitor NC3 is connected between the sixth node N6 and the second node N2.

[0126] The masking circuit MSC includes transistors NT21 and NT22. The masking circuit MSC may stop (or mask) the output of the scan signal SCj in response to the masking signal MS and the scan signal SCj received through the sixth input terminal IN6.

[0127] The transistor NT21 is connected between the first node N1 and the masking node MN1 and includes a gate electrode connected to the sixth input terminal IN6. The transistor NT22 is connected between the masking node MN1 and the third input terminal IN3 and includes a gate electrode connected to the output terminal OUT1.

[0128] Figure 9 : is a timing chart showing operations of the j-1th driving stage STj- 1 and the j-th driving stage STj in the low power mode.

[0129] refer to Figure 8 and Figure 9 , the first clock signal CLK1 and the second clock signal CLK2 are signals having the same frequency and transitioning to an active level (eg, a low level) in different horizontal sections H. The horizontal section H is a period of the display panel DP (reference Figure 2 ) is driven for a time period in which pixels PX in one row in the first direction DR1 are driven.

[0130] When the masking signal MS is at a high level, since the transistor NT21 in the masking circuit MSC of the j-1th driver stage STj-1 remains in the cut-off state, the j-1th driver stage STj-1 can output the j-1th scan signal SCj-1 in response to the carry signal CRj-1, the first clock signal CLK1 and the second clock signal CLK2.

[0131] When the mask signal MS transitions from a high level to a low level in the j-2 horizontal portion Hj-2, the transistor NT21 in the mask circuit MSC of the j-1th driver stage STj-1 is turned on. At this time, since the j-1th driver stage STj-1 has already outputted the j-1th scan signal SCj-1 at a high level, the transistor NT22 in the mask circuit MSC can be kept in the off state. Therefore, the j-1th driver stage STj-1, which has already outputted the j-1th scan signal SCj-1 at a high level, can normally output the j-1th scan signal SCj-1.

[0132] When the mask signal MS transitions from a high level to a low level in the j-2 horizontal portion Hj-2, the transistor NT21 in the mask circuit MSC of the j-th driver stage STj is turned on. Furthermore, the transistor NT22 may be turned on in response to the j-th scan signal SCj of the low level. When the transistor NT22 is turned on, the first node N1 is discharged (or flows out) to the first voltage VGL through the third input terminal IN3.

[0133] In a state where the first node N1 is electrically connected to the third input terminal IN3, even if the carry signal CRj-1 (i.e., the j-1th scan signal SCj-1 from the previous stage STj-1) is turned to a high level, the first node N1 is maintained at a low level. When each of the first node N1 and the second node N2 is maintained at a low level, the transistor NT10 is turned on, so that the output terminal OUT1 outputs the j-th scan signal SCj of a low level. When the transistors NT21 and NT22 are turned on, the j-th scan signal SCj can be maintained at a low level.

[0134] The j+1th driving stage STj+1, which receives the j-th scan signal SCj of low level as the carry signal CRj, outputs the j+1-th scan signal SCj+1 of low level.

[0135] like Figure 8 and Figure 9 As shown in , when the mask signal MS transitions from a high level to a low level, the scan signal (eg, the j-1th scan signal SCj-1) that has transitioned to a high level may be output normally.

[0136] In this way, when the j-1th scan signal SCj-1 is an activation level (e.g., a high level) and the masking signal MS changes from a high level to a low level in the j-2th horizontal portion Hj-2 where the j-th scan signal SCj is an inactive level (e.g., a low level), the j-th scan signal SCj can be masked.

[0137] When the mask signal MS changes from a high level to a low level, the low-level scan signals (e.g., the j-th scan signal SCj and the j+1-th scan signal SCj+1) are maintained at a low level. Therefore, the output of the scan signals can be stopped (or masked) by adjusting the change time point of the mask signal MS.

[0138] Figure 10 is a timing diagram illustrating an operation of the j-th driving stage STj in the low power mode.

[0139] refer to Figure 8 and Figure 10 If the masking signal MS is at a low level in the j-1th horizontal portion Hj-1, the transistor NT21 in the masking circuit MSC of the j-th driver stage STj is turned on. Furthermore, the transistor NT22 can be turned on in response to the j-th scan signal SCj being at a low level. When the transistor NT22 is turned on, the first node N1 is discharged (or flows out) to the first voltage VGL through the third input terminal IN3. At this time, when the first clock signal CLK1 transitions to a low level, a current path is formed between the first input terminal IN1 and the third input terminal IN3 through the transistors NT1, NT21, and NT22, so that the carry signal CRj-1 can be discharged to the first voltage VGL. According to some embodiments, when the first clock signal CLK1 transitions to a low level, the masking signal MS can be triggered to a high level. As a result, instances of a current path being formed between the first input terminal IN1 and the third input terminal IN3 can be prevented or reduced.

[0140] Figure 11 is a circuit diagram illustrating a j-th driving stage STaj in a scan driving circuit according to some embodiments of the inventive concept.

[0141] because Figure 11 The driving circuit DC of the driving stage STaj shown in FIG has the same Figure 8 The drive circuit DC of the drive stage STj shown in FIG1 has the same configuration as that of FIG1 , so the same reference numerals are added and repeated descriptions are omitted.

[0142] The driving stage STaj includes a masking circuit MSCa. The masking circuit MSCa includes transistors NT31 and NT32. The masking circuit MSCa can stop (or mask) the output of the scan signal SCj in response to the masking signal MS1 and the carry signal CRj-1 received through the sixth input terminal IN6.

[0143] The transistor NT31 is connected between the first node N1 and the masking node MN1 and includes a gate electrode connected to the sixth input terminal IN6. The transistor NT32 is connected between the masking node MN1 and the third input terminal IN3 and includes a gate electrode connected to the first input terminal IN1.

[0144] Figure 8 The gate electrode of the transistor NT22 in the mask circuit MSC shown in FIG. 1 is connected to the output terminal OUT1, but Figure 11 The gate electrode of the transistor NT32 in the mask circuit MSCa shown in FIG. 1 is connected to the first input terminal IN1 .

[0145] Figure 12 is a timing diagram illustrating the operation of the j-th driving stage STaj in the low power mode.

[0146] refer to Figure 11 and Figure 12 , when the j-th scan signal SCj output from the j-th driving stage STaj is to be masked to a low level, the masking signal MS1 must be transitioned from a high level to a low level during the j-3 th horizontal portion Hj-3.

[0147] When the masking signal MS1 is at a low level in the j-3 horizontal portion Hj-3, the transistor NT31 in the masking circuit MSCa of the j-th driver stage STj is turned on. In addition, the transistor NT32 may also be turned on in response to the low-level carry signal CRj-1 (i.e., the j-1-th scan signal SCj-1). When the transistor NT32 is turned on, the first node N1 is discharged to the first voltage VGL through the third input terminal IN3, and the output terminal OUT1 is discharged to the first voltage VGL through the transistor NT10. As a result, the j-th scan signal SCj is maintained at a low level.

[0148] When the carry signal CRj-1 (i.e., the j-1th scan signal SCj-1) changes to a high level in the j-2th horizontal portion Hj-2, since the first clock signal CLK1 is at a high level, the first node N1 and the second node N2 can be maintained at a low level. At the same time, when the first node N1 is maintained at a low level, since the transistor NT8 is maintained in the on state, the node N3 is at a high level, and the transistor NT9 is not turned on. Therefore, the j-th scan signal SCj can be maintained at a low level.

[0149] When the first clock signal CLK1 transitions to a low level in the j-1th horizontal portion Hj-1, a high-level carry signal CRj-1 (i.e., the j-1th scan signal SCj-1) is transmitted to the first node N1 and the second node N2. The transistor NT10 is turned off in response to the high-level signal from the second node N2. The transistor NT8 is turned off in response to the high-level signal of the first node N1, but the third node N3 can be maintained at a high level by the capacitor NC1. As a result, the j-th scan signal SCj is maintained at a low level.

[0150] When the second clock signal CLK2 changes to a low level in the j-th horizontal portion Hj, the second node N2 changes to a low voltage through the capacitor NC3, so that the transistor NT10 is turned on. Therefore, the j-th scan signal SCj is maintained at a low level.

[0151] When the first clock signal CLK1 changes to a low level in the j+1th horizontal portion Hj+1, the low-level carry signal CRj-1 (i.e., the j-1th scan signal SCj-1) is transmitted to the first node N1 and the second node N2. As the transistor NT8 is turned on in response to the low-level signal from the first node N1, the transistor NT9 is turned off. As the transistor NT10 is turned on in response to the low-level signal from the second node N2, the j-th scan signal SCj is maintained at a low level.

[0152] In this way, when the j-2nd scan signal SCj-2 (i.e., the carry signal SCj-2) is at an activation level (e.g., a high level) and the masking signal MS1 is changed from a high level to a low level in the j-3rd horizontal portion Hj-3 where the j-1st scan signal SCj-1 (i.e., the carry signal SCj-1) is at an inactive level (e.g., a low level), the j-th scan signal SCj can be masked.

[0153] Figure 13 is a circuit diagram illustrating a j-th driving stage STbj in a scan driving circuit according to some embodiments of the inventive concept.

[0154] because Figure 13 The driving circuit DC of the driving stage STbj shown in FIG has the same Figure 8 The drive circuit DC of the drive stage STj shown in FIG1 has the same configuration as that of FIG1 , so the same reference numerals are added and repeated descriptions are omitted.

[0155] The driving stage STbj includes a masking circuit MSCb. The masking circuit MSCb includes transistors NT41 and NT42. The masking circuit MSCb can stop (or mask) output of the scan signal SCj in response to the masking signal MS received through the sixth input terminal IN6 and the signal of the first node N1.

[0156] The transistor NT41 is connected between the first node N1 and the masking node MN1 and includes a gate electrode connected to the sixth input terminal IN6. The transistor NT42 is connected between the masking node MN1 and the third input terminal IN3 and includes a gate electrode connected to the first node N1.

[0157] Figure 8 The gate electrode of the transistor NT22 in the mask circuit MSC shown in FIG. 1 is connected to the output terminal OUT1, but Figure 13The gate electrode of the transistor NT42 in the masking circuit MSCb shown in FIG. 1 is connected to the first node N1.

[0158] The signal of the first node N1 is similar to the carry signal CRj-1. Therefore, the mask circuit MSCb operating in response to the signal of the first node N1 and the mask signal MS can be Figure 11 The masking circuit MSCa shown in operates similarly.

[0159] Figure 8 The masking circuit MSC illustrated in FIG. 4 can cause the driving circuit DC to stop outputting the scan signal SCj in response to the masking signal MS and the scan signal SCj. Figure 11 The masking circuit MSCa illustrated in FIG. 4 may cause the driving circuit DC to stop outputting the scan signal SCj in response to the masking signal MS1 and the carry signal CRj-1. Figure 13 The masking circuit MSCb illustrated in FIG. 4 may cause the driving circuit DC to stop outputting the scan signal SCj in response to the masking signal MS and the signal of the first node N1.

[0160] The scan signal SCj, the carry signal CRj-1, and the signal of the first node N1 are all signals indicating the operating state of the driving circuit DC. That is, even if the mask signal MS or MS1 is at a low level, when the driving circuit DC outputs the scan signal SCj at an active level (e.g., a high level), the masking circuits MSC, MSCa, and MSCb allow the scan signal SCj at an active level to be normally output.

[0161] When the masking signal MS or MS1 is at a low level, if the driving circuit DC is in a state in which the scanning signal SCj of an inactive level (e.g., a low level) is output, the masking circuit MSC, the masking circuit MSCa, and the masking circuit MSCb control the driving circuit DC not to output the scanning signal SCj of an active level, that is, control the scanning signal SCj to remain at an inactive level.

[0162] As a result, the first scan driving circuit SD1 (refer to Figure 5 ) can be driven at a normal frequency from the first scan line SL1 to the j-1th scan line SCLj-1, and can be driven at a low frequency from the j-th scan line SCLj to the n-th scan line SLn. For example, even if the mask signal MS or MS1 is turned to a low level while the j-1th scan line SCLj-1 is driven at an active level (e.g., a high level), the j-1th scan line SCLj-1 can be normally driven by the scan signal SCj-1 of the normal frequency.

[0163] Figure 14 is a block diagram of a first scan driving circuit SD1 according to some embodiments of the inventive concept.

[0164] refer to Figure 14 The first scan driving circuit SD1 includes driving stages ST0 to STn and masking circuits MSC1 to MSCn. Each of the driving stages ST0 to STn may have Figure 5 The driving stages ST0 to STn in the first scan driving circuit SD1 shown in FIG.

[0165] The masking circuits MSC1 to MSCn correspond to the driving stages ST1 to STn, respectively. Each of the masking circuits MSC1 to MSCn can selectively provide a scan signal output from a previous driving stage as a carry signal to the corresponding driving stage in response to a masking signal MS and a scan signal output from a corresponding driving stage among the driving stages ST0 to STn.

[0166] Figure 15 Shown with Figure 14 1 , and 2 , which are circuit configurations of the j-th masking circuit MSCj corresponding to the j-th driving stage STj among the masking circuits MSC1 to MSCn illustrated in FIG.

[0167] refer to Figure 15 The j-th masking circuit (hereinafter, masking circuit) MSCj includes a first switch SW1 and a second switch SW2. The first switch SW1 is connected between a voltage terminal VIN1 receiving a first voltage VGL and the second switch SW2, and operates in response to the j-th scan signal SCj. The second switch SW2 is connected between the first switch SW1 and a carry node CRN receiving a carry signal CRj-1, and operates in response to the masking signal MS. The j-1-th scan signal SCj-1 output from the previous stage (i.e., the j-1-th driver stage STj-1) can be provided to the carry node CRN as the carry signal CRj-1.

[0168] If the mask signal MS is at the first level (eg, a high level), since the second switch SW2 is turned off, the carry node CRN and the voltage terminal VIN1 may be electrically isolated.

[0169] When the mask signal MS is at the second level (e.g., a low level), the second switch SW2 is turned on. At this time, if the j-th scan signal SCj is at the first level (e.g., a high level), the first switch SW1 is turned off, so the carry node CRN and the voltage terminal VIN1 can be electrically isolated. On the other hand, if the j-th scan signal SCj is at the second level (e.g., a low level), the first switch SW1 is turned on, so the carry node CRN and the voltage terminal VIN1 can be electrically connected.

[0170] In other words, if at least one of the masking signal MS and the j-th scan signal SCj is at a first level (e.g., a high level), the carry node CRN and the voltage terminal VIN1 are electrically isolated. If both the masking signal MS and the j-th scan signal SCj are at a second level (e.g., a low level), both the first switch SW1 and the second switch SW2 are turned on, so that the carry node CRN is electrically connected to the voltage terminal VIN1. Therefore, since the carry node CRN is discharged to the first voltage VGL, the j-th driving stage STj can receive the low-level carry signal CRj-1 and output the low-level scan signal STj.

[0171] Figure 16 A circuit configuration of a j-th masking circuit MSCdj corresponding to the j-th driving stage STj is shown.

[0172] refer to Figure 16 The j-th masking circuit (hereinafter, masking circuit) MSCdj includes first to third logic circuits LC11 to LC13. The first and second logic circuits LC11 to LC12 may be AND gate circuits, and the third logic circuit LC13 may be an OR gate circuit.

[0173] The first logic circuit LC11 receives the j-th scan signal SCj and the carry signal CRj-1 (i.e., the j-1-th scan signal SCj-1). The second logic circuit LC12 receives the mask signal MS and the carry signal CRj-1. The third logic circuit LC13 receives the outputs of the first logic circuit LC11 and the second logic circuit LC12 and outputs the j-1-th carry signal CRj-1.

[0174] When the mask signal MS is at a high level, the second logic circuit LC12 may output a signal corresponding to the carry signal CRj-1. Therefore, the mask circuit MSCdj may provide the carry signal CRj-1 to the driving stage STj when the mask signal MS is at a high level.

[0175] When the mask signal MS is at a low level, the second logic circuit LC12 outputs a low-level signal, and when both the j-th scan signal SCj and the carry signal CRj-1 are at a high level, the first logic circuit LC11 outputs a high-level signal. Therefore, when the mask signal MS is at a low level, the mask circuit MSCdj can provide the high-level carry signal CRj-1 to the driver stage STj only when both the j-th scan signal SCj and the carry signal CRj-1 are at a high level.

[0176] As described above, the masking circuit MSCdj including the logic gate circuit selectively provides the carry signal CRj-1 to the driving stage STj in response to the masking signal MS, the carry signal CRj-1 and the j-th scan signal SCj. In other words, Figure 16 The masking circuit MSCdj illustrated in FIG. 5 can selectively mask the input of the carry signal CRj-1 to the j-th driving stage STj.

[0177] The driving stage STj can output the scan signal SCj in response to the carry signal CRj-1, the first voltage VGL, the second voltage VGH, the first clock signal CLK1 and the second clock signal CLK2. When the carry signal CRj-1 is not activated to a high level and is maintained at a low level, the driving stage STj outputs the scan signal SCj at a low level. Therefore, the second display area DA2 (reference Figure 1 ) (eg, the j-th scan line SCLj) drives the scan signals SCj to SCn at a low frequency.

[0178] Figure 17 A circuit configuration of a j-th masking circuit MSCej corresponding to the j-th driving stage STj is shown.

[0179] refer to Figure 17 The j-th masking circuit (hereinafter, masking circuit) MSCej includes first to fourth logic circuits LC21 to LC24. The first and third logic circuits LC21 to LC23 may be AND gate circuits, the second logic circuit LC22 may be an inverter circuit, and the fourth logic circuit LC24 may be an OR gate circuit.

[0180] The first logic circuit LC21 receives the mask signal MS and the j-th scan signal Sj from the j-th driver stage STj. The second logic circuit LC22 inverts the mask signal MS and outputs it. The third logic circuit LC23 receives the j-th scan signal Sj, the inverted mask signal, and the j-th scan signal SCj (or the j-th output scan signal SCj) output from the mask circuit MSCej. The fourth logic circuit LC24 receives the outputs of the first logic circuit LC21 and the third logic circuit LC23 and outputs the j-th scan signal SCj.

[0181] When the mask signal MS is at a high level, the first logic circuit LC21 may output the jth scan signal Sj received from the jth driving stage STj. Therefore, the mask circuit MSCej may output the jth scan signal Sj from the jth driving stage STj as the jth scan signal SCj when the mask signal MS is at a high level.

[0182] When the mask signal MS is at a low level, the first logic circuit LC21 outputs a low-level signal, and when both the j-th scan signal Sj from the j-th driving stage STj and the j-th scan signal SCj from the mask circuit MSCej are at a high level, the third logic circuit LC23 outputs a high-level signal. Therefore, the mask circuit MSCej can output the j-th scan signal SCj at a high level only when both the j-th scan signal Sj and the j-th scan signal SCj are at a high level and the mask signal MS is at a low level.

[0183] Therefore, the masking circuit MSCej can output the j-th scanning signal Sj as the j-scanning signal SCj from the j-th driving stage STj when the masking signal MS is at a high level. Figure 17 The masking circuit MSCej shown in FIG. 4 can selectively mask the output of the j-th driving stage STj.

[0184] The driving stage STj can output the j-th scan signal Sj in response to the j-1-th carry signal CRj-1, the first voltage VGL, the second voltage VGH, the first clock signal CLK1, and the second clock signal CLK2. Since the masking circuit MSCej selectively outputs the j-th scan signal Sj as the j-th scan signal SCj, the second display area DA2 (reference Figure 1 ) (eg, the j-th scan line SCLj) drives the scan signals SCj to SCn at a low frequency.

[0185] A display device having such a configuration can drive a first display area displaying a moving image and a second display area displaying a static image at different drive frequencies. For example, power consumption can be reduced by lowering the drive frequency of the second display area displaying a static image compared to the drive frequency of the first display area displaying a moving image.

[0186] Although aspects of some embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments, and that those skilled in the art can make various changes and modifications within the spirit and scope of the inventive concept as claimed.

Claims

1. A scan drive circuit comprising: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; as well as a masking circuit configured to cause the driving circuit to stop outputting the scanning signal in response to a masking signal and a signal indicating an operating state of the driving circuit; Wherein, the driving circuit includes: a first transistor configured to transmit the carry signal to a first node in response to a first clock signal among the clock signals; and a second transistor connecting the output terminal to a first voltage terminal configured to receive a first voltage in response to a signal of the first node; Wherein, the masking circuit includes: a first masking transistor connected between the first node and a masking node and comprising a gate electrode connected to an input terminal configured to receive the masking signal; and A second masking transistor is connected between the masking node and the first voltage terminal and includes a gate electrode connected to one of the output terminal, an input terminal configured to receive the carry signal, and the first node.

2. The scan driving circuit according to claim 1, wherein: The signal indicating the operation state of the drive circuit is any one of the carry signal and the scan signal.

3. The scan driving circuit according to claim 1, wherein: The driving circuit further comprises: a third transistor connected between a second voltage terminal configured to receive a second voltage and the output terminal and including a gate electrode connected to the second node; and A fourth transistor is connected between the second voltage terminal and the second node and includes a gate electrode connected to the first node.

4. A scan drive circuit comprising: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; as well as a masking circuit configured to cause the driving circuit to stop outputting the scanning signal in response to a masking signal and a signal indicating an operating state of the driving circuit, Wherein, the masking circuit includes: a first switch electrically connecting a first terminal configured to receive a first voltage and a second terminal in response to the scan signal; and A second switch electrically connects an input terminal configured to receive the carry signal and the second terminal of the first switch in response to the mask signal.

5. A scan drive circuit comprising: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; as well as a masking circuit configured to cause the driving circuit to stop outputting the scanning signal in response to a masking signal and a signal indicating an operating state of the driving circuit; Wherein, the masking circuit includes: a first logic circuit configured to receive the scan signal and the carry signal; a second logic circuit configured to receive the carry signal and the mask signal; and The third logic circuit is configured to receive the output signal of the first logic circuit and the output signal of the second logic circuit, and provide the carry signal to the driving circuit.

6. A scan drive circuit comprising: a driving circuit configured to output a scan signal to an output terminal in response to a clock signal and a carry signal; as well as a masking circuit configured to cause the driving circuit to stop outputting the scanning signal in response to a masking signal and a signal indicating an operating state of the driving circuit; Wherein, the masking circuit includes: a first logic circuit configured to receive the mask signal and the scan signal output from the driving circuit; a second logic circuit configured to invert and output the mask signal; a third logic circuit configured to receive the scan signal output from the driving circuit, the inverted mask signal output from the second logic circuit, and output a scan signal; and The fourth logic circuit is configured to receive the output signal of the first logic circuit and the output signal of the second logic circuit, and output the output scan signal.

7. A display device comprising: A display panel including a plurality of pixels connected to a plurality of data lines and a plurality of scan lines, respectively; a data driving circuit configured to drive the plurality of data lines; a scan driving circuit configured to drive the plurality of scan lines; as well as a driving controller configured to receive an image signal and a control signal and control the data driving circuit and the scan driving circuit to display an image on the display panel, wherein the driving controller is configured to divide the display panel into a first display area and a second display area based on the image signal and output a mask signal indicating a starting point of the second display area, The scan driving circuit includes a plurality of driving stages, each driving stage is configured to drive a corresponding scan line among the plurality of scan lines, Each of the plurality of driver stages comprises: a driving circuit configured to output a scanning signal to an output terminal in response to a clock signal and a carry signal from the driving controller; and a masking circuit configured to cause the driving circuit to stop outputting the scanning signal in response to the masking signal and a signal indicating an operating state of a corresponding driving stage among the plurality of driving stages; Wherein, the driving circuit includes: a first transistor configured to transmit the carry signal to a first node in response to a first clock signal among the clock signals; and a second transistor connecting the output terminal to a first voltage terminal receiving a first voltage in response to a signal from the first node; Wherein, the masking circuit includes: a first masking transistor connected between the first node and a masking node and comprising a gate electrode connected to an input terminal configured to receive the masking signal; and A second masking transistor is connected between the masking node and the first voltage terminal and includes a gate electrode connected to one of the output terminal, an input terminal configured to receive the carry signal, and the first node.

8. The display device according to claim 7, wherein: The signal indicating the operation state of the corresponding driving stage is any one of the carry signal and the scan signal.

9. The display device according to claim 7, wherein: The scan signal output from the j-th driving stage among the plurality of driving stages is provided as a carry signal of the j+k-th driving stage, where j and k are natural numbers.

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