Storage system and method for operating a storage system

Abstract

This text is about a storage system and a method for operating the storage system. The storage system includes unit storage circuits. Each of the unit storage circuits is adjacent to a neighboring one in the unit storage circuits. Each of the unit storage circuits includes a first storage cell group; a second storage cell group; a first sub-word line driver for applying a first control signal to the first storage cell group via a first sub-word line extending in a direction; and a second sub-word line driver for applying a second control signal to the second storage cell group via a second sub-word line extending in the direction. The storage system includes a common word line driver that is adjacent to one of the unit storage circuits and is used to apply a common control signal to the unit storage circuits via a word line extending in the direction.

Description

Technical Field

[0001] The present disclosure relates to a storage system and a method of operating the storage system. Background Art

[0002] The development of electronic devices such as computers, portable devices, smart phones, Internet of Thing (IoT) devices, etc. has prompted an increasing demand for storage devices. Generally, storage devices can be volatile storage devices and non-volatile storage devices. A volatile storage device can store data when power is supplied, but the stored data can be lost once the power is turned off. Different from volatile storage devices, non-volatile memory devices can retain data even after the power is turned off, but can be slower than volatile storage devices. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a storage system includes a plurality of memory cells, a common word line driver, a first sub-word line driver, a second sub-word line driver, and a third sub-word line driver. The memory cells include a first memory cell group, a second memory cell group, and a third memory cell group. The common word line driver is configured to apply a common control signal to the memory cells via a common word line extending in one direction. The first sub-word line driver is configured to apply a first control signal to the first memory cell group via a first sub-word line extending in this direction, wherein the first sub-word line driver is adjacent to the common word line driver. The second sub-word line driver is configured to apply a second control signal to the second memory cell group via a second sub-word line extending in this direction. The third sub-word line driver is configured to apply a third control signal to the third memory cell group via a third sub-word line extending in this direction, wherein the third sub-word line driver is adjacent to the second sub-word line driver. The common word line driver, the first sub-word line driver, the first memory cell group, the second memory cell group, the second sub-word line driver, the third sub-word line driver, and the third memory cell group are arranged in this sequence along this direction.

[0004] According to some embodiments of the present disclosure, a storage system includes a plurality of unit storage circuits and a shared word line driver. Each of the unit storage circuits is adjacent to a neighboring one of the unit storage circuits. Each of the unit storage circuits includes a first storage cell group, a second storage cell group, a first sub-word line driver, and a second sub-word line driver. The first sub-word line driver is configured to apply a first control signal to the first storage cell group via a first sub-word line extending in a direction. The second sub-word line driver is configured to apply a second control signal to the second storage cell group via a second sub-word line extending in this direction, wherein the first sub-word line driver, the first storage cell group, the first sub-word line driver, and the second sub-word line driver are arranged in this sequence in this direction. The shared word line driver is configured to apply a shared control signal to the unit storage circuits via a shared word line extending in this direction, wherein the shared word line driver is adjacent to one of the unit storage circuits.

[0005] According to some embodiments of the present disclosure, a method of operating a storage system includes the following steps. Applying a shared control signal to a plurality of storage cell groups via a shared word line by a shared word line driver. Applying control signals to individual storage cell groups from the storage cell groups via corresponding sub-word lines by a plurality of sub-word line drivers. Protecting a first storage cell group from the storage cell groups that is closest to the shared word line driver by a first sub-word line driver among the sub-word line drivers, wherein the first sub-word line driver is adjacent to the first storage cell group. Protecting a second storage cell group from the storage cell groups that is farthest from the shared word line driver by a second sub-word line driver among the sub-word line drivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying Figure 1 drawings, aspects of the present disclosure are better understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of a storage system according to one embodiment;

[0008] Figure 2 is a diagram of a storage system including a shared word line driver and a plurality of unit storage circuits according to one embodiment;

[0009] Figure 3 is a diagram of a storage system including a shared word line driver and a plurality of unit storage circuits according to one embodiment;

[0010] Figure 4Flowchart for operating or assembling multiple memory cells according to some embodiments;

[0011] Figure 5 Exemplary block diagram of a computing system according to some embodiments.

[0012]

Symbol Explanation

[0013] BL0 to BLK: Bit lines

[0014] GL0 to GLJ: Gate lines

[0015] WL: Word line

[0016] SWLAA, SWLBA, SWLCA: Sub - word lines

[0017] SWLAB, SWLBB, SWLCB: Sub - word lines

[0018] 100: Memory system

[0019] 105: Memory controller

[0020] 110: Timing controller

[0021] 112: Bit line controller

[0022] 114: Gate line controller

[0023] 120: Memory array

[0024] 125: Memory cell / Memory cell group

[0025] 200: Memory system

[0026] 210: Common word line driver

[0027] 250A, 250B, 250C: Unit storage circuit

[0028] 252AA, 252AB, 252BA: Sub - word line driver

[0029] 252BB, 252CA, 252CB: Sub - word line driver

[0030] 255AA, 255BA, 255CA: Memory array

[0031] 255AB, 255BB, 255CB: Memory array

[0032] 258A, 258B, 258C: Word line short post

[0033] 265AA, 265BA, 265CA: Interface circuit

[0034] 265AB, 265BB, 265CB: Interface Circuit

[0035] 300: Storage System

[0036] 400: Method

[0037] 410, 420, 430, 440: Operations

[0038] 500: Computing System

[0039] 505: Host Device

[0040] 510: Storage Device

[0041] 515: Input Device

[0042] 520: Output Device

[0043] 525A, 525B, 525C: Interfaces

[0044] 530A to 530N: Central Processing Unit Core / CPU Core

[0045] 535: Standard Cell Application

[0046] 540: Storage Controller

[0047] 545: Storage Array Detailed Implementation Manner

[0048] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and configurations to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the formation of the first feature above or on the second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not substantially prescribe the relationship between the various embodiments and / or configurations discussed.

[0049] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein may likewise be interpreted accordingly.

[0050] Disclosed herein is a storage system that includes unit storage circuits. In one aspect, each of these unit storage circuits is adjacent to a neighboring one of these unit storage circuits. In one aspect, each of these unit storage circuits includes a first memory cell group, a second memory cell group, a first sub-word line driver, and a second sub-word line driver. The first sub-word line driver can apply a first control signal to the first memory cell group via a first sub-word line extending in a direction. The second sub-word line driver can apply a second control signal to the second memory cell group via a second sub-word line extending in the direction. Each sub-word line driver can include a protection circuit for protecting a corresponding memory cell group. In one aspect, the storage system includes a common word line driver that is adjacent to one of these unit storage circuits and is configured to apply a common control signal to these unit storage circuits via a common word line extending in the direction.

[0051] Advantageously, the storage system can achieve several benefits. In one aspect, the disclosed storage system implements unit storage circuits that include a pair of sub-word line drivers and a pair of memory cell groups between the pair of sub-word line drivers. Thus, the first memory cell group closest to the common word line driver can be protected by the first sub-word line driver, such that additional protection circuits can be omitted. In addition, the last memory cell group furthest from the common word line driver can be protected by the last sub-word line driver, such that additional protection circuits can be omitted. By omitting the additional protection circuits for protecting the first memory cell group and the last memory cell group, area efficiency can be achieved. In addition, the length of the common word line can be reduced, such that the RC load at the common word line can be reduced to improve the operation speed of multiple memory cells.

[0052] Figure 1Diagram of a storage system 100 according to an embodiment. In some embodiments, the storage system 100 includes a storage controller 105 and a storage array 120. The storage array 120 may include a plurality of storage circuits or storage units 125 configured in a two-dimensional or three-dimensional array. Each storage unit 125 may be connected to a corresponding gate line GL (or word line WL) and a corresponding bit line BL. The storage controller 105 may write data to the storage array 120 or read data from the storage array according to electrical signals passing through the gate line GL and the bit line BL. In other embodiments, the storage system 100 includes more, fewer, or different components than those Figure 1 shown.

[0053] The storage array 120 is a hardware component for storing data. In one aspect, the storage array 120 is embodied as a semiconductor storage device. The storage array 120 includes a plurality of storage units 125. The storage array 120 includes gate lines GL0, GL1... GLJ each extending in a first direction (e.g., the X-direction), and bit lines BL0, BL1... BLK each extending in a second direction (e.g., the Y-direction). Each gate line includes a word line and one or more control lines. The gate lines GL and the bit lines BL may be conductive metals or conductive rails. In one aspect, each storage unit 125 is connected to a corresponding gate line GL and a corresponding bit line BL, and may operate according to a voltage or current passing through the corresponding gate line GL and the corresponding bit line BL. In one aspect, each storage unit 125 may be a ferroelectric field-effect transistor (FeFET), a resistive storage unit, a non-volatile storage unit, or a volatile storage unit. In some embodiments, the storage array 120 includes additional lines (e.g., selection lines, reference lines, reference control lines, power rails, etc.). The following provides a detailed description of the configuration and operation of the storage system 100. Figures 2 to 4

[0054] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line controller 112, a gate line controller 114, and a timing controller 110. In one configuration, the gate line controller 114 is a circuit that provides a voltage or current across one or more gate lines GL of the memory array 120, and the bit line controller 112 is a circuit that provides or senses a voltage or current across one or more bit lines BL and / or select lines SL of the memory array 120. In one configuration, the timing controller 110 is a circuit that provides control signals or clock signals to synchronize the operations of the bit line controller 112 and the gate line controller 114. The bit line controller 112 may be connected to the bit lines BL and / or select lines SL of the memory array 120, and the gate line controller 114 may be connected to the gate lines GL of the memory array 120. In one example, to write data to the memory cell 125, the gate line controller 114 provides a voltage or current to the memory cell 125 via the gate line GL connected to the memory cell 125, and the bit line controller 112 applies a bias voltage to the memory cell 125 via the bit line BL and / or select line SL connected to the memory cell 125. In one example, to read data from the memory cell 125, the gate line controller 114 provides a voltage or current to the memory cell 125 via the gate line GL connected to the memory cell 125, and the bit line controller 112 senses a voltage or current corresponding to the data stored in the memory cell 125 via the bit line BL and / or select line SL connected to the memory cell 125. In some embodiments, the memory controller 105 includes more, fewer, or different components than those shown in Figure 1 more, fewer, or different components than those shown in

[0055] Figure 2 FIG. 200 is a diagram of a memory system 200 including a shared word line driver 210 and a plurality of unit storage circuits 250A, 250B, 250C according to one embodiment. In some embodiments, the memory system 200 is Figure 1 a portion of the memory system 100 of Figure 1 a portion of the memory system 100 of Figure 2 more, fewer, or different components than those shown in

[0056] In one configuration, the shared character line driver 210 and the unit storage circuits 250A, 250B, 250C are arranged in that sequence along the X-direction. In one aspect, the shared character line driver 210 abuts a first side of the unit storage circuit 250A, and a second side of the unit storage circuit 250A abuts a first side of the unit storage circuit 250B. In one aspect, a second side of the unit storage circuit 250B abuts a first side of the unit storage circuit 250C. In one configuration, the shared character line WL may extend along the X-direction across the unit storage circuits 250A, 250B, 250C.

[0057] In some embodiments, the shared character line driver 210 is a circuit or hardware component that can provide a shared control signal to the memory arrays 255AA, 255AB, 255BA, 255BB, 255CA, 255CB. The shared control signal may be a character line voltage or a character line pulse used to configure or operate the memory arrays 255AA, 255AB, 255BA, 255BB, 255CA, 255CB. In one configuration, the shared character line driver 210 is electrically coupled to the memory arrays 255AA, 255AB, 255BA, 255BB, 255CA, 255CB via the shared character line WL. By applying the character line voltage or the character line pulse to the memory arrays 255AA, 255AB, 255BA, 255BB, 255CA, 255CB via the shared character line WL, the memory arrays 255AA, 255AB, 255BA, 255BB, 255CA, 255CB can store data or output the stored data.

[0058] In some embodiments, each unit storage circuit 250X includes a pair of memory arrays 255XA, 255XB, and a pair of sub - word line drivers 252XA, 252XB. In one configuration, the sub - word line driver 252XA is disposed at a first side of the unit storage circuit 250X and the sub - word line driver 252XB is disposed at a second side of the unit storage circuit 250X. The memory arrays 255XA, 255XB may be disposed between the sub - word line drivers 252XA, 252XB, where the memory array 255XA may be adjacent to the sub - word line driver 252XA and the memory array 255XB may be adjacent to the sub - word line driver 252XB. Each memory array 255 may include a memory cell group 125. In one aspect, the sub - word line driver 252XA may be electrically coupled to the first memory cell group 125 in the memory array 255XA via a sub - word line SWLXA that extends in the X - direction across the first memory cell group 125. In one aspect, the sub - word line driver 252XB may be electrically coupled to the second memory cell group 125 in the memory array 255XB via a sub - word line SWLXB that extends in the X - direction across the second memory cell group 125. In one aspect, each sub - word line SWL is shorter than the common word line WL. The unit storage circuit 250X may include a word line stub 258X between the memory arrays 255XA, 255XB to electrically decouple or isolate the sub - word lines SWLXA, SWLXB. Through the sub - word lines SWLXA, SWLXB, the sub - word line drivers 252XA, 252XB may respectively configure or operate the memory arrays 255XA, 255XB.

[0059] In one aspect, each sub - word line driver 252XA includes an interface circuit 265XA adjacent to the memory array 255XA. The interface circuit 265XA may include a logic conversion circuit that may receive a digital signal through the sub - word line SWLXA and apply an analog control signal corresponding to the digital signal to the memory cell group 125. The interface circuit 265XA may also include a protection circuit adjacent to the side of the memory array 255XA. The protection circuit may protect the memory cell group 125 in the memory array 255XA.

[0060] Advantageously, the storage system 200 can achieve several benefits. In one aspect, the storage system 200 includes N storage arrays 255, N sub - word line drivers 252, and N / 2 word line strips 258. In one aspect, the first storage array 255AA closest to the common word line driver 210 can be protected by the first sub - word line driver 252AA, such that additional protection circuitry used to protect the first storage array 255AA can be omitted. Additionally, the last storage array 255CB farthest from the common word line driver 210 can be protected by the last sub - word line driver 252CB, such that additional protection circuitry used to protect the last storage array 255CB can be omitted. By omitting the additional protection circuitry, area efficiency can be achieved. Additionally, the length of the common word line WL can be reduced, such that the RC load at the common word line WL can be reduced to improve the operation speed of the plurality of memory cells 125.

[0061] Figure 3 FIG. is a diagram of a storage system 300 including a common word line driver 210 and a plurality of unit storage circuits 250A, 250B, 250C according to one embodiment. In some embodiments, the storage system 300 is embodied as Figure 2 the storage system 200.

[0062] In one aspect, the common word line driver 210 includes a gate word line driver (GWLDV), a local control circuit (Lctrl), and a main controller (Mctrl). The gate word line driver GWLDV, the logic control circuit Lctrl, and the main controller Mctrl can be arranged along the Y - direction transverse to the X - direction. In one aspect, the main controller Mctrl generates a global control signal to configure the plurality of memory cells 125. In one aspect, the logic control circuit Lctrl generates local control signals to separately control different portions of the memory cells 125. In one aspect, each gate word line driver GWLDV is electrically coupled to a corresponding column of the memory cells 125 via an individual common word line WL. The gate word line driver GWLDV can generate a word line pulse and apply the word line pulse to the corresponding column of the memory cells 125 via the common word line WL.

[0063] In one aspect, each memory array 255 includes a group of memory cells 125, local input / output interface circuits (LIO), and a global input / output interface circuit (GIO). The memory cells, local input / output interface circuits (LIO), and global input / output interface circuit (GIO) may be arranged along the Y-direction. The local input / output interface circuits (LIO) may receive local control signals from a local control circuit Lctrl and configure or operate individual portions of the group of memory cells 125 in the memory array 255 according to the local control signals. The global input / output interface circuit (GIO) may receive global control signals from a master control circuit Mctrl and configure or operate the group of memory cells 125 in the memory array 255 according to the global control signals.

[0064] In one aspect, the memory system 300 may achieve area efficiency. For example, the group of memory cells 125 in the first memory array 255AA closest to the common word line driver 210 may be protected by a first sub-word line driver 252AA, such that additional protection circuitry for protecting the group of memory cells 125 in the first memory array 255AA may be omitted. Additionally, the group of memory cells 125 in the last memory array 255CB furthest from the common word line driver 210 may be protected by a last sub-word line driver 252CB, such that additional protection circuitry for protecting the group of memory cells 125 in the last memory array 255CB may be omitted. By omitting the additional protection circuitry, area efficiency may be achieved.

[0065] Figure 4 FIG. 400 is a flow chart of a method 400 for configuring or operating a plurality of groups of memory cells 125. In some embodiments, method 400 is performed by the common word line driver 210 and the sub-word line driver 252. In some embodiments, method 400 is performed by other entities. In some embodiments, method 400 includes more, fewer, or different operations than those shown in Figure 4 FIG.

[0066] In operation 410, the common character line driver 210 applies a common control signal to the plurality of memory cell groups 125 through the common character line WL. The plurality of memory array groups 255 may include individual memory cell groups 125. The first memory cell group 125 in the first memory array 255AA from the plurality of group memory cells 125 may be set closest to the common character line driver 210, and the second memory cell group 125 in the second memory array 255CB from the plurality of group memory cells 125 may be set farthest from the common character line driver 210. The common character line WL may extend across the plurality of memory cell groups 125 in one direction (e.g., the X-direction).

[0067] In operation 420, each of the plurality of sub-character line drivers 252 applies a control signal to an individual memory cell group 125 through a corresponding sub-character line SWL. Each sub-character line SWL may be shorter than the common character line WL. The plurality of sub-character line drivers 252 may apply control signals to the individual memory cell groups 125 while the common character line driver 210 applies a common control signal to the plurality of memory cell groups 125.

[0068] In one example, the first sub-character line driver 252AA applies a first control signal to the first memory cell group 125 in the first memory array 255AA. The first sub-character line driver 252AA may include a first side adjacent to the common character line driver 210 and a second side adjacent to the first memory cell group 125 in the first memory array 255AA. The first sub-character line driver 252AA may apply the first control signal to the first memory cell group 125 through the first sub-character line SWLAA that extends across the first memory cell group 125 in the first memory array 255AA.

[0069] In one example, the second sub-character line driver 252CB applies a second control signal to the second memory cell group 125 in the second memory array 255CB. The second sub-character line driver 252CB may include a first side adjacent to the second memory array 255CB. The second sub-character line driver 252CB may be set farther from the common character line driver 210 compared to the second memory array 255CB. The second sub-character line driver 252CB may apply the second control signal to the second memory cell group 125 through the second sub-character line SWLCB that extends across the second memory cell group 125 in the second memory array 255CB.

[0070] In operation 430, the sub - word - line driver 252AA protects the first group of memory cells 125 in the first memory array 255AA. The sub - word - line driver 252AA may include a protection circuit adjacent to the first memory array 255AA. The protection circuit of the sub - word - line driver 252AA protects the first group of memory cells 125 in the first memory array 255AA from being damaged, for example, due to an excessive voltage or current applied to the first group of memory cells 125.

[0071] In operation 440, the sub - word - line driver 252CB protects the second group of memory cells 125 in the second memory array 255CB. The sub - word - line driver 252CB may include a protection circuit adjacent to the second memory array 255CB. The protection circuit of the sub - word - line driver 252CB protects the second group of memory cells 125 in the second memory array 255CB from being damaged, for example, due to an excessive voltage or current applied to the second group of memory cells 125.

[0072] Advantageously, the memory system 200 can be implemented in an area - efficient manner. In one aspect, each sub - word - line driver 252 may include a protection circuit for protecting the corresponding group of memory cells. Thus, the first group of memory cells 125 in the first memory array 255AA closest to the common word - line driver 210 can be protected by the first sub - word - line driver 252AA, such that an additional protection circuit can be omitted. In addition, the second group of memory cells 125 in the second memory array 255CB farthest from the common word - line driver 210 can be protected by the second sub - word - line driver 252CB, such that an additional protection circuit can be omitted. By omitting the additional protection circuits for protecting the first group of memory cells 125 and the second group of memory cells 125, area efficiency can be achieved. In addition, the length of the common word - line WL can be reduced, such that the RC load at the common word - line WL can be reduced to improve the operation speed of the plurality of memory cells 125.

[0073] Now refer to Figure 5, showing an exemplary block diagram of a computing system 500 according to some embodiments of the present disclosure. The computing system 500 can be used by circuit or layout designers in integrated circuit design. As used herein, "circuit" is an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices assembled to perform a desired function. The computing system 500 includes a host device 505 associated with a storage device 510. The host device 505 can be used to receive inputs from one or more input devices 515 and provide outputs to one or more output devices 520. The host device 505 can be used to communicate with the storage device 510, the input device 515, and the output device 520 through appropriate interfaces 525A, 525B, and 525C, respectively. The computing system 500 can be implemented in various computing devices such as a computer (e.g., desktop computer, laptop computer, server, data center, etc.), a tablet computer, a personal digital assistant, a mobile device, other handheld or portable devices, or any other computing unit suitable for performing conceptual design and / or layout design using the host device 505.

[0074] The input device 515 can include any input technology in various input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote controller, an input port, one or more buttons, a dial pad, a rocker, and any other input peripheral device that is associated with the host device 505 and that allows an external source such as a user (e.g., a circuit or layout designer) to input information (e.g., data) into the host device and send instructions to the host device. Similarly, the output device 520 can include various output technologies, such as an external memory, a printer, a speaker, a display, a microphone, a light-emitting diode, a headset, a video device, and any other output peripheral device that is used to receive information (e.g., data) from the host device 505. The "data" input into the host device 505 and / or output from the host device can include any of various types of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for being processed using the computing system 500.

[0075] The host device 505 includes one or more processing units / processors, or is associated with one or more processing units / processors, such as the CPU cores 530A - 530N. The CPU cores 530A - 530N can be implemented as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other type of processing unit. Each of the CPU cores 530A - 530N is available to execute instructions for running one or more application programs of the host device 505. In some embodiments, the instructions and data for running one or more application programs can be stored in the storage device 510. The host device 505 can also be used to store the results of running one or more application programs in the storage device 510. Thus, the host device 505 can be used to request the storage device 510 to perform various operations. For example, the host device 505 can request the storage device 510 to read data, write data, update or delete data, and / or perform administrative or other operations. One such application program that the host device 505 can be used to run can be the standard cell application program 535. The standard cell application program 535 can be part of a computer - aided design or electronic design automation software suite that can be used by a user of the host device 505 to use, create, or modify standard cells of a circuit. In some embodiments, the instructions for executing or running the standard cell application program 535 can be stored in the storage device 510. The standard cell application program 535 can be executed by one or more of the CPU cores 530A - 530N using instructions associated with the standard cell application program from the storage device 510. In one example, the standard cell application program 535 allows a user to utilize pre - generated conceptual designs and / or layout designs of the storage system 100 or a portion of the storage system 100 to assist in integrated circuit design. After the layout design of an integrated circuit is completed, multiple integrated circuits can be fabricated according to the layout design by design for manufacture, for example, including the storage system 100 or a portion of the storage system 100.

[0076] Still referring to Figure 5, the storage device 510 includes a storage controller 540 that is configured to read data from or write data to the storage array 545. The storage array 545 may include various volatile and / or non-volatile memories. For example, in some embodiments, the storage array 545 may include a NAND flash memory core. In other embodiments, the storage array 545 may include a NOR flash memory core, a SRAM core, a dynamic random access memory (DRAM) core, a magnetoresistive random access memory (MRAM) core, a phase change memory (PCM) core, a resistive random access memory (ReRAM) core, a 3D XPoint storage core, a ferroelectric random-access memory (FeRAM) core, and other types of storage cores suitable for use within the storage array. The memories within the storage array 545 may be individually and independently controlled by the storage controller 540. In other words, the storage controller 540 is configured to communicate individually and independently with each memory within the storage array 545. By communicating with the storage array 545, the storage controller 540 is configured to read data from or write data to the storage array in response to instructions received from the host device 505. Although shown as part of the storage device 510, in some embodiments, the storage controller 540 may be part of the host device 505 or part of another component of the computing system 500 and associated with the storage device. The storage controller 540 may be implemented as software, hardware, firmware, or a combination thereof as logic circuitry to perform the functions described herein. For example, in some embodiments, the storage controller 540 is configured to retrieve instructions associated with the standard cell application 535 when receiving a request from the host device 505, where these instructions are stored in the storage array 545 of the storage device 510.

[0077] It will be understood that Figure 5Only some components of computing system 500 are shown and described. However, computing system 500 may include other components such as various batteries and power sources, network interfaces, routers, switches, external storage systems, controllers, etc. Generally, computing system 500 may include any of a variety of hardware, software, and / or firmware components that are needed or considered desirable in performing the functions described herein. Similarly, host device 505, input device 515, output device 520, and storage device 510 including storage controller 540 and storage array 545 may include other hardware, software, and / or firmware components that are considered necessary or desirable in performing the functions described herein.

[0078] One aspect of the present description relates to a storage system. In some embodiments, the storage system includes a plurality of storage cells, the plurality of storage cells including a first group of storage cells, a second group of storage cells, and a third group of storage cells. In some embodiments, the storage system includes a common word line driver for applying a common control signal to the plurality of storage cells via a common word line extending in a direction. In some embodiments, the storage system includes a first sub-word line driver for applying a first control signal to the first group of storage cells via a first sub-word line extending in the direction. In some embodiments, the first sub-word line driver is adjacent to the common word line driver. In some embodiments, the storage system includes a second sub-word line driver for applying a second control signal to the second group of storage cells via a second sub-word line extending in the direction. In some embodiments, the storage system includes a third sub-word line driver for applying a third control signal to the third group of storage cells via a third sub-word line extending in the direction. In some embodiments, the third sub-word line driver is adjacent to the second sub-word line driver. In some embodiments, the common word line driver, the first sub-word line driver, the first group of storage cells, the second group of storage cells, the second sub-word line driver, the third sub-word line driver, and the third group of storage cells are arranged in that sequence in the direction.

[0079] In some embodiments, the first sub - word - line driver includes a first interface circuit, the first interface circuit being adjacent to a first memory cell group, wherein the first interface circuit protects the first memory cell group. In some embodiments, the second sub - word - line driver includes a second interface circuit, the second interface circuit being adjacent to a second memory cell group, wherein the second interface circuit protects the second memory cell group. In some embodiments, the third sub - word - line driver includes a third interface circuit, the third interface circuit being adjacent to a third memory cell group, wherein the third interface circuit protects the third memory cell group. In some embodiments, the storage system further includes a word - line strip disposed between the first memory cell group and the second memory cell group. In some embodiments, the memory cells include a fourth memory cell group, and the storage system includes a fourth sub - word - line driver for applying a fourth control signal to the fourth memory cell group via a fourth sub - word - line extending in this direction, wherein the third memory cell group, the fourth memory cell group, and the fourth sub - word - line driver are arranged in that sequence in this direction. In some embodiments, the storage system further includes a first word - line strip and a second word - line strip. The first word - line strip is disposed between the first memory cell group and the second memory cell group, and the second word - line strip is disposed between the third memory cell group and the fourth memory cell group. In some embodiments, each of the first sub - word - line, the second sub - word - line, and the third sub - word - line is shorter than the common word - line.

[0080] One aspect of this description relates to a storage system. In some embodiments, the storage system includes a plurality of unit storage circuits, wherein each of the plurality of unit storage circuits is adjacent to an adjacent one of the plurality of unit storage circuits. In some embodiments, each of the plurality of unit storage circuits includes a first memory cell group, a second memory cell group, a first sub - word - line driver, and a second sub - word - line driver. In some embodiments, the first sub - word - line driver is configured to apply a first control signal to the first memory cell group via a first sub - word - line extending in a direction. In some embodiments, the second sub - word - line driver is configured to apply a second control signal to the second memory cell group via a second sub - word - line extending in the direction. In some embodiments, the first sub - word - line driver, the first memory cell group, the first sub - word - line driver, and the second sub - word - line driver are arranged in that sequence in the direction. In some embodiments, the storage system includes a common word - line driver for applying a common control signal to the plurality of unit storage circuits via a common word - line extending in the direction. In some embodiments, the common word - line driver is adjacent to one of the plurality of unit storage circuits.

[0081] In some embodiments, the first sub - word - line driver includes a first interface circuit, the first interface circuit being adjacent to the first memory cell group, wherein the first interface circuit protects the first memory cell group. In some embodiments, the second sub - word - line driver includes a second interface circuit, the second interface circuit being adjacent to the second memory cell group, wherein the second interface circuit protects the second memory cell group. In some embodiments, the first sub - word - line driver of one of the unit storage circuits is adjacent to the common word - line driver, and the second sub - word - line driver of one of the unit storage circuits is adjacent to the first sub - word - line driver of another of the unit storage circuits. In some embodiments, the second sub - word - line driver of another of the unit storage circuits is adjacent to the first sub - word - line driver of an additional one of the unit storage circuits. In some embodiments, each of the unit storage circuits further includes a word - line strip, the word - line strip being disposed between the first memory cell group and the second memory cell group. In some embodiments, each of the first sub - word - line and the second sub - word - line is shorter than the common word - line.

[0082] One aspect of this description relates to a method of operating a memory system. In some embodiments, the method includes applying a common control signal to a plurality of memory cell groups via a common word - line by a common word - line driver. In some embodiments, the method includes applying control signals to individual memory cell groups from the plurality of memory cell groups via corresponding sub - word - lines by a plurality of sub - word - line drivers. In some embodiments, the method includes protecting a first memory cell group from the plurality of memory cell groups that is closest to the common word - line driver by a first sub - word - line driver among the plurality of sub - word - line drivers. In some embodiments, the first sub - word - line driver is adjacent to the first memory cell group. In some embodiments, the method includes protecting a second memory cell group from the plurality of memory cell groups that is farthest from the common word - line driver by a second sub - word - line driver among the plurality of sub - word - line drivers.

[0083] In some embodiments, the common word - line extends in one direction across some of the memory cell groups. In some embodiments, each of the sub - word - lines extends in this direction across an individual group from the memory cell groups, wherein each of the sub - word - lines is shorter than the common word - line. In some embodiments, the method of operating a memory system further includes the following steps. Separating a first sub - word - line extending across the first memory cell group and a second sub - word - line extending across the second memory cell group by a word - line strip disposed between the first memory cell group from the memory cell groups and the second memory cell group from the memory cell groups. In some embodiments, each of the sub - word - lines is shorter than the common word - line.

[0084] The foregoing description summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A storage system, characterized in that, it comprises: a plurality of memory cells, including a first memory cell group, a second memory cell group, and a third memory cell group; a common word line driver for applying a common control signal to the plurality of memory cells via a common word line extending in one direction; a first sub-word line driver for applying a first control signal to the first memory cell group via a first sub-word line extending in this direction, wherein the first sub-word line driver is adjacent to the common word line driver, wherein the first sub-word line driver includes a first interface circuit, the first interface circuit is adjacent to the first memory cell group, and wherein the first interface circuit protects the first memory cell group; a second sub-word line driver for applying a second control signal to the second memory cell group via a second sub-word line extending in this direction; and a third sub-word line driver for applying a third control signal to the third memory cell group via a third sub-word line extending in this direction, wherein the third sub-word line driver is adjacent to the second sub-word line driver, wherein the common word line driver, the first sub-word line driver, the first memory cell group, the second memory cell group, the second sub-word line driver, the third sub-word line driver, and the third memory cell group are arranged in this sequence along this direction.

2. The storage system according to claim 1, characterized in that, wherein the common word line extends across the first memory cell group, the second memory cell group, and the third memory cell group along this direction.

3. The storage system according to claim 2, characterized in that, wherein the second sub-word line driver includes a second interface circuit, the second interface circuit is adjacent to the second memory cell group, and wherein the second interface circuit protects the second memory cell group.

4. The storage system according to claim 3, characterized in that, wherein the third sub-word line driver includes a third interface circuit, the third interface circuit is adjacent to the third memory cell group, and wherein the third interface circuit protects the third memory cell group.

5. The storage system according to claim 1, characterized in that, further comprising: a word line strip disposed between the first memory cell group and the second memory cell group.

6. The storage system according to claim 1, characterized in that, wherein the plurality of memory cells includes a fourth memory cell group, and wherein the storage system includes a fourth sub-word line driver for applying a fourth control signal to the fourth memory cell group via a fourth sub-word line extending in this direction, wherein the third memory cell group, the fourth memory cell group, and the fourth sub-word line driver are arranged in this sequence along this direction.

7. The storage system according to claim 6, characterized in that, further comprising: a first word line strip disposed between the first memory cell group and the second memory cell group; and A second character line strip is disposed between the third storage unit group and the fourth storage unit group.

8. The storage system according to claim 1, wherein, each of the first sub-character line, the second sub-character line, and the third sub-character line is shorter than the common character line.

9. A storage system, wherein, comprising: a plurality of unit storage circuits, each of the plurality of unit storage circuits adjacent to an adjacent one of the plurality of unit storage circuits, wherein each of the plurality of unit storage circuits includes: a first storage unit group, a second storage unit group, a first sub-character line driver for applying a first control signal to the first storage unit group via a first sub-character line extending in one direction, wherein the first sub-character line driver includes a first interface circuit adjacent to the first storage unit group, wherein the first interface circuit protects the first storage unit group, and a second sub-character line driver for applying a second control signal to the second storage unit group via a second sub-character line extending in the direction, wherein the first sub-character line driver, the first storage unit group, the second storage unit group, and the second sub-character line driver are arranged in that sequence along the direction; and a common character line driver for applying a common control signal to the plurality of unit storage circuits via a common character line extending in the direction, wherein the common character line driver is adjacent to one of the plurality of unit storage circuits.

10. The storage system according to claim 9, wherein, the common character line extends in the direction across the first storage unit group, the second storage unit group, and the third storage unit group.

11. The storage system according to claim 10, wherein, the second sub-character line driver includes a second interface circuit adjacent to the second storage unit group, wherein the second interface circuit protects the second storage unit group.

12. The storage system according to claim 9, wherein, the first sub-character line driver of one of the plurality of unit storage circuits is adjacent to the common character line driver, and the second sub-character line driver of one of the plurality of unit storage circuits is adjacent to the first sub-character line driver of another one of the plurality of unit storage circuits.

13. The storage system according to claim 12, wherein, the second sub-character line driver of another one of the plurality of unit storage circuits is adjacent to the first sub-character line driver of an additional one of the plurality of unit storage circuits.

14. The storage system according to claim 9, wherein, each of the plurality of unit storage circuits further includes a character line strip disposed between the first storage unit group and the second storage unit group.

15. The storage system according to claim 9, wherein, both the first sub-character line and the second sub-character line are shorter than the common character line.

16. A method of operating a storage system, It is characterized in that it includes the following steps: Applying a common control signal to a plurality of memory cell groups via a common character line by means of a common character line driver; Applying control signals to individual memory cell groups from the plurality of memory cell groups via corresponding plurality of sub-character lines by means of a plurality of sub-character line drivers; Protecting a first memory cell group from the plurality of memory cell groups that is closest to the common character line driver by means of a first sub-character line driver among the plurality of sub-character line drivers, wherein the first sub-character line driver is adjacent to the first memory cell group; and Protecting a second memory cell group from the plurality of memory cell groups that is farthest from the common character line driver by means of a second sub-character line driver among the plurality of sub-character line drivers.

17. The method for operating a storage system according to claim 16, it is characterized in that the common character line extends in one direction across the plurality of memory cell groups.

18. The method for operating a storage system according to claim 17, it is characterized in that each of the plurality of sub-character lines extends in the direction across an individual group from the plurality of memory cell groups, wherein each of the plurality of sub-character lines is shorter than the common character line.

19. The method for operating a storage system according to claim 16, it is characterized in that it further includes the following steps: Separating a first sub-character line extending across the first memory cell group and a second sub-character line extending across the second memory cell group by means of a character line strip disposed between a first memory cell group from the plurality of memory cell groups and a second memory cell group from the plurality of memory cell groups.

20. The method for operating a storage system according to claim 16, it is characterized in that each of the plurality of sub-character lines is shorter than the common character line.

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