Page buffer and semiconductor memory device having the same

Abstract

A page buffer and a semiconductor memory device having the page buffer may be provided herein. The page buffer may include: a sensing node whose potential is controlled based on the amount of current flowing through a bit line during a data sensing operation and based on the potential of a common node of the page buffer during a data transmission operation; and a master latch component configured to latch data based on the potential of the sensing node, wherein the master latch component latches data according to a first trip voltage and the potential of the sensing node during the data transmission operation, and latches data according to a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to electronic devices, and more particularly, to a page buffer and a semiconductor memory device having the same. Background Art

[0002] Semiconductor memory devices are manufactured using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Generally, semiconductor memory devices are one of two types, volatile memory devices or nonvolatile memory devices.

[0003] In a volatile memory device, the stored data is lost when the power supply to the device is interrupted. Representative examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). In a non-volatile memory device, the stored data is maintained even when the power supply to the device is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly classified as NOR type or NAND type. Summary of the invention

[0004] Various embodiments of the present disclosure are directed to a page buffer that can improve data transmission operation performance and data sensing operation performance, and a semiconductor memory device having the same.

[0005] Embodiments of the present disclosure may provide a page buffer. The page buffer may include: a sensing node whose potential is controlled based on the amount of current flowing through a bit line during a data sensing operation and based on the potential of a common node of the page buffer during a data transmission operation; and a master latch component configured to latch data based on the potential of the sensing node, wherein the master latch component latches data according to a first trip voltage and the potential of the sensing node during the data transmission operation, and latches data according to a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

[0006] Embodiments of the present disclosure may provide a page buffer. The page buffer may include: a sensing node whose potential is controlled based on the amount of current flowing through a bit line during a data sensing operation and based on the potential of a common node of the page buffer during a data transmission operation; and a master latch component configured to latch data based on the potential of the sensing node, wherein the master latch component is further configured to: during the data transmission operation, set a first trip voltage by relatively strengthening a pull-down current path to latch data according to the set first trip voltage and the potential of the sensing node, and during the data sensing operation, set a second trip voltage higher than the first trip voltage by relatively weakening the pull-down current path to latch data according to the set second trip voltage and the potential of the sensing node.

[0007] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a first precharger coupled to a page buffer common node and configured to precharge the page buffer common node to a first potential during a data transmission operation; a cache latch component coupled to the page buffer common node and configured to maintain the potential of the page buffer common node or discharge the potential of the page buffer common node based on data stored in the cache latch component during a data transmission operation; and a page buffer coupled to the page buffer common node, wherein the page buffer includes: a sensing node, the potential of the sensing node is controlled based on the potential of the page buffer common node during a data transmission operation; and a master latch component configured to latch data based on the potential of the sensing node, and wherein the master latch component is further configured to set a first trip voltage during a data transmission operation to latch data according to the set first trip voltage and the potential of the sensing node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 It shows that Figure 1 A diagram of a semiconductor memory device included in a memory device.

[0010] Figure 3 is a diagram showing a memory block having a 3D structure.

[0011] Figure 4 It is shown in detail Figure 3 A circuit diagram of a representative one of the memory blocks is shown.

[0012] Figure 5 It shows that Figure 4 Circuit diagram of a memory string of a memory block shown.

[0013] Figure 6 It shows that Figure 2 Diagram of the read-write circuit.

[0014] Figure 7 It shows that Figure 6 Circuit diagram of the cache latch assembly and page buffer.

[0015] Figure 8 It shows that Figure 7 A waveform diagram of signals for a data transfer operation between a cache latch component and a page buffer.

[0016] Fig. 9 It shows that Figure 7 1 is a signal waveform diagram of a data sensing operation of a page buffer.

[0017] Fig.10 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0018] Fig.11 It shows that Fig.10 FIG. 1 is a signal waveform diagram of a data transfer operation between a cache latch component and a page buffer.

[0019] Fig.12 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0020] Fig.13 It shows that Fig.12 Circuit diagram of inverter IV24 of the master latch component.

[0021] Fig.14 It shows that Fig.12 FIG. 1 is a signal waveform diagram of a data transfer operation between a cache latch component and a page buffer.

[0022] Fig.15 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0023] Fig.16 is a diagram showing an embodiment of a memory system.

[0024] Fig.17 is a diagram showing an embodiment of a memory system.

[0025] Fig.18 is a diagram showing an embodiment of a memory system.

[0026] Fig.19 is a diagram showing an embodiment of a memory system. DETAILED DESCRIPTION

[0027] Specific structural and functional descriptions are provided herein to describe the embodiments of the present disclosure. However, the present invention may be configured or arranged in various other forms, so the present invention is not limited to the disclosed embodiments.

[0028] Various embodiments of the present disclosure are described more fully below with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. Throughout this specification, references to "an embodiment", "another embodiment", etc. do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. In addition, the term "embodiment" when used herein does not necessarily refer to all embodiments.

[0029] Figure 1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 , the memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 may include a plurality of semiconductor memories (or semiconductor memory devices) 100. The plurality of semiconductor memories 100 may be divided into a plurality of groups GR1 to GRn. In another embodiment of the present disclosure, the memory system 1000 may be configured to include only the controller 1200 and the memory device 1100, and the host 1300 is provided outside the memory system 1000.

[0031] exist Figure 1 , it is shown that a plurality of groups GR1 to GRn of the semiconductor memory device 100 communicate with the controller 1200 through the first channel CH1 to the nth channel CHn, respectively. Figure 2 The semiconductor memory 100 is described in detail.

[0032] The semiconductor memories 100 of a specific group may communicate with the controller 1200 through one common channel. The controller 1200 may control the semiconductor memories 100 of the memory device 1100 through a plurality of channels CH1 to CHn.

[0033] The controller 1200 is connected between the host 1300 and the memory device 1100. The controller 1200 may access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 may control a read operation, a program operation, an erase operation, and a background operation of the memory device 1100 in response to a host command Host_CMD received from the host 1300. The host 1300 may send an address ADD and data DATA to be programmed together with the host command Host_CMD during a program operation, and may send the address ADD together with the host command Host_CMD during a read operation. During a program operation, the controller 1200 may send a command corresponding to the program operation and data DATA to be programmed to the memory device 1100. During a read operation, the controller 1200 may send a command corresponding to the read operation to the memory device 1100, receive read data DATA from the memory device 1100, and send the received data DATA to the host 1300. The controller 1200 may provide an interface between the memory device 1100 and the host 1300. The controller 1200 may execute firmware for controlling the memory device 1100 .

[0034] The host 1300 may be configured as any of various portable electronic devices such as a computer, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a camera, a video camera, and / or a mobile phone. The host 1300 may request a program operation, a read operation, and an erase operation of the memory system 1000 through a host command Host_CMD. The host 1300 may send a host command Host_CMD, data DATA, and an address ADD corresponding to a program operation to the controller 1200 to perform a program operation of the memory device 1100, and may send a host command Host_CMD and an address ADD corresponding to a read operation to the controller 1200 to perform a read operation. Here, the address ADD may be a logical address of the data.

[0035] The controller 1200 and the memory device 1100 may be integrated into a single semiconductor memory device. In an embodiment, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor memory device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or MMCmicro), an SD Card (SD, miniSD, microSD or SDHC), or a Universal Flash Device (UFS).

[0036] In an embodiment, the memory system 1000 may be provided as a device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various devices forming a home network, one of various electronic devices forming a computer network, one of various electronic devices forming a telematics network, one of various elements of an electronic device of an RFID device, one of various elements forming a computing system, etc.

[0037] In an embodiment, the memory device 1100 or the memory system 1000 may be installed as any of various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged and installed in accordance with a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic chip carrier with leads (PLCC), a plastic dual in-line package (PDIP), a waffle chip package, a wafer form chip, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline package (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0038] Figure 2 It is shown Figure 1 A diagram of a semiconductor memory device (or semiconductor memory) included in a memory device.

[0039] Reference Figure 2 , the semiconductor memory 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, and a voltage generating circuit 150. The address decoder 120, the read / write circuit 130, and the voltage generating circuit 150 may be used as a peripheral circuit 160 that performs a read operation on the memory cell array 110.

[0040] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The memory blocks BLK1 to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. A memory cell connected to one word line among the plurality of memory cells may be defined as a page. The memory cell array 110 may be composed of a plurality of pages.

[0041] Each of the memory blocks BLK1 to BLKz of the memory cell array 110 includes a plurality of memory strings. Each of the memory strings may include a drain select transistor, a plurality of memory cells, and a source select transistor connected in series between a corresponding bit line and a source line. In addition, each of the memory strings may include a corresponding pass transistor between the source select transistor and the memory cell and between the drain select transistor and the memory cell, and may also include a gate transistor between the memory cells. The memory cell array 110 is described in detail below.

[0042] The address decoder 120 is coupled to the memory cell array 110 through word lines WL. The address decoder 120 may operate in response to address decoder control signals AD_signals generated by the control logic 140. The address decoder 120 receives the address ADD through an input / output buffer (not shown) provided in the semiconductor memory 100.

[0043] During a programming operation, the address decoder 120 may decode a row address among the received addresses ADDR, and may apply various operating voltages (including a programming voltage Vpgm, a read voltage Vread, a pass voltage Vpass, and a verification voltage Vverify) generated by the voltage generating circuit 150 to multiple memory cells of the memory cell array 110 according to the decoded row address.

[0044] The address decoder 120 may decode the column address among the received address ADDR and may send the decoded column address Yi to the read / write circuit 130 .

[0045] The address ADDR received in a programming operation or a read operation includes a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line according to the block address and the row address. The column address can be decoded by the address decoder 120 and then provided to the read / write circuit 130.

[0046] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0047] The read / write circuit 130 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through the bit lines BL1 to BLm. During a read operation or a verification operation, the plurality of page buffers PB1 to PBm may perform a data sensing operation of sensing a programming state of a memory cell connected to the bit lines BL1 to BLm. During the data sensing operation, the plurality of page buffers PB1 to PBm may latch data based on the current amount of the corresponding bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may perform a data transmission operation of receiving data to be programmed and temporarily storing the data during a programming operation, and may control a potential level of the corresponding bit lines BL1 to BLm based on the temporarily stored data.

[0048] Each of the plurality of page buffers PB1 to PBm may include a master latch component that latches data to be programmed during a data transmission operation and latches data during a data sensing operation. The master latch component latches data based on a first trip voltage during a data transmission operation and latches data based on a second trip voltage during a data sensing operation, wherein the first trip voltage and the second trip voltage have different potentials. For example, the first trip voltage may have a potential lower than the second trip voltage. The master latch component may latch first data (e.g., “0”) or second data (e.g., “1”) during a data transmission operation depending on whether a potential of a sensing node is higher or lower than the first trip voltage, and may latch first data (e.g., “0”) or second data (e.g., “1”) during a data sensing operation depending on whether a potential of a sensing node is higher or lower than the second trip voltage.

[0049] The read and write circuit 130 may operate in response to the page buffer control signal PB_signals output from the control logic 140 .

[0050] In an implementation, the read / write circuit 130 may include a page buffer (or page register), a column selection circuit, and the like.

[0051] The control logic 140 may be coupled to the address decoder 120, the read / write circuit 130, and the voltage generation circuit 150. The control logic 140 may receive a command CMD through an input / output buffer (not shown) of the semiconductor memory 100. The control logic 140 may control the overall operation of the semiconductor memory 100 in response to the command CMD. For example, the control logic 140 may receive a command CMD corresponding to a program operation, and may generate and output an address decoder control signal AD_signals for controlling the address decoder 120, a page buffer control signal PB_signals for controlling the read / write circuit 130, and a voltage generation circuit control signal VG_signals for controlling the voltage generation circuit 150 in response to the received command CMD. In addition, the control logic 140 can receive a command CMD corresponding to a read operation, and can generate and output an address decoder control signal AD_signals for controlling the address decoder 120, a page buffer control signal PB_signals for controlling the read and write circuit 130, and a voltage generating circuit control signal VG_signals for controlling the voltage generating circuit 150 in response to the received command CMD.

[0052] During a program operation, the voltage generation circuit 150 may generate a program voltage Vpgm, a pass voltage Vpass, and a verification voltage Vverify under the control of a voltage generation circuit control signal VG_signals output from the control logic 140, and may output the generated voltages to the address decoder 120. In addition, during a read operation, the voltage generation circuit 150 may generate a read voltage Vread and a pass voltage Vpass under the control of a voltage generation circuit control signal VG_signals output from the control logic 140, and may output the generated voltages to the address decoder 120.

[0053] Figure 3 is a diagram showing a memory block having a 3D structure.

[0054] Reference Figure 3 , the memory blocks BLK1 to BLKz having a 3D structure may be spaced apart from each other along a direction Y in which the bit lines BL1 to BLm extend. For example, the memory blocks BLK1 to BLKz may be spaced apart from each other along a direction Y, and each such memory block may include a plurality of memory cells stacked along a direction Z. Figure 4 and Figure 5 The configuration of any one of the memory blocks BLK1 to BLKz is described in detail.

[0055] Figure 4 It is shown in detail Figure 3 Circuit diagram of any memory block shown.

[0056] Figure 5 It is shown Figure 4 Circuit diagram of the memory string shown.

[0057] Reference Figure 4 and Figure 5 , each memory string ST may be coupled between the bit lines BL1 to BLm and the source line SL. The memory string ST coupled between the first bit line BL1 and the source line SL is described as an example.

[0058] The memory string ST may include a source selection transistor SST, memory cells F1 to Fn (where n is a positive integer), and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. The gates of the source selection transistors SST included in different memory strings ST connected to different bit lines BL1 to BLm may be connected to a first source selection line SSL0 and a second source selection line SSL1. For example, among the source selection transistors SST, source selection transistors adjacent to each other in a direction Y may be connected to the same source selection line. For example, assuming that the source selection transistors SST are arranged in sequence along a direction Y, the gates of the source selection transistors SST arranged in a direction X from the first source selection transistor SST and included in different memory strings ST and the gates of the source selection transistors SST arranged in a direction X from the second source selection transistor SST and included in different memory strings ST may be connected to the first source selection line SSL0. In addition, gates of source select transistors SST arranged in direction X and included in different memory strings ST from the third source select transistor SST and gates of source select transistors SST arranged in direction X and included in different memory strings ST from the fourth source select transistor SST may be coupled to the second source select line SSL1.

[0059] Gates of the memory cells F1 to Fn may be coupled to the word lines WL1 to WLn, and a gate of the drain select transistor DST may be coupled to any one of the first to fourth drain select lines DSL0 to DSL3 .

[0060] The gates of the transistors arranged in the direction X among the drain selection transistors DST may be commonly connected to the same drain selection line (e.g., DSL0), but the gates of the transistors arranged in the direction Y may be connected to different drain selection lines DSL1 to DSL3. For example, assuming that the drain selection transistors DST are sequentially arranged along the direction Y, the gates of the drain selection transistors DST arranged in the direction X from the first drain selection transistor DST and included in the different memory strings ST may be connected to the first drain selection line DSL0. The drain selection transistors DST arranged in the direction Y from the drain selection transistor DST connected to the first drain selection line DSL0 may be sequentially connected to the second drain selection line DSL1 to the fourth drain selection line DSL3. Therefore, in the selected memory block, the memory string ST connected to the selected drain selection line may be selected, and the memory strings ST connected to the remaining drain selection lines (i.e., the unselected drain selection lines) may not be selected.

[0061] Memory cells connected to the same word line may form a page PG. Here, the term "page" means a physical page. For example, among the memory strings ST connected to the first bit line BL1 to the mth bit line BLm, a group of memory cells connected in the same word line in the direction X is called a page PG. For example, among the first memory cells F1 connected to the first word line WL1, the memory cells arranged in the direction X may form a page PG. Among the first memory cells F1 commonly connected to the first word line WL1, the memory cells arranged in the direction Y may be divided into different pages. Therefore, when the first drain selection line DSL0 is the selected drain selection line and the first word line WL1 is the selected word line, the page connected to the first drain selection line DSL0 among the multiple page PGs connected to the first word line WL1 may be the selected page. The page commonly connected to the word line WL1 but connected to the unselected second drain selection line DSL1 to the fourth drain selection line DSL3 may be the unselected page.

[0062] Although in the drawings, one source select transistor SST and one drain select transistor DST are shown as being included in one memory string ST, according to the semiconductor memory, a plurality of source select transistors SST and a plurality of drain select transistors DST may be included in one memory string ST. In addition, according to the semiconductor memory, a dummy cell may be included between the source select transistor SST, the memory cells F1 to Fn, and the drain select transistor DST. The dummy cell does not store user data like the normal memory cells F1 to Fn, but can be used to improve the electrical characteristics of each memory string ST. However, since the dummy cell is an optional component, its detailed description is omitted here.

[0063] Figure 6 It is shown Figure 2 Diagram of the read-write circuit.

[0064] Reference Figure 6 , the read / write circuit 130 may include a plurality of page buffers 131A to 131C, a plurality of cache latch components 132A to 132C, and a plurality of transistors TR1 to TR9 and TR11 to TR18. The plurality of cache latch components 132A to 132C may be coupled to an input / output pad (not shown) of the semiconductor memory.

[0065] The plurality of page buffers 131A to 131C may correspond to the plurality of cache latch components 132A to 132C, respectively. For example, page buffer PB1 may correspond to cache latch component C-LATCH1, and page buffer PB8 may correspond to cache latch component C-LATCH8.

[0066] A plurality of transistors TR1 to TR8 may be coupled between the corresponding page buffers 131A to 131C and the page buffer common node PBUS, and each of the transistors TR1 to TR8 may operate in response to any one of the page buffer transfer signals TRANPB<7:0>. For example, the transistor TR1 may be coupled between the page buffer PB1 and the page buffer common node PBUS. In response to the page buffer transfer signal TRANPB<7:0>, the transistor TR1 may be coupled between the page buffer PB1 and the page buffer common node PBUS. <0> , the transistor TR1 can send the data stored in the page buffer PB1 to the page buffer common node PBUS or send the data to the page buffer PB1 through the page buffer common node PBUS. In addition, the transistor TR8 can be connected between the page buffer PB8 and the page buffer common node PBUS. In response to the page buffer transfer signal TRANPB <7> , the transistor TR8 can send data stored in the page buffer PB8 to the page buffer common node PBUS or send data to the page buffer PB8 through the page buffer common node PBUS.

[0067] The transistor TR9 may be coupled between the power supply voltage VDD and the page buffer common node PBUS, and may precharge the page buffer common node PBUS by applying the power supply voltage VDD to the page buffer common node PBUS in response to the common node precharge signal PBUS_LPRE. Here, the power supply voltage VDD may be applied to the page buffer common node PBUS only when the voltage level of the common node precharge signal PBUS_LPRE is equal to or greater than the voltage level "VDD+Vth" (representing the sum of the threshold voltage Vth of the transistor TR9 and the power supply voltage VDD).

[0068] A plurality of transistors TR11 to TR18 may be coupled between corresponding cache latch components 132A to 132C and a page buffer common node PBUS, and each of the plurality of transistors TR11 to TR18 may operate in response to any one of cache latch transmission signals TRANC<7:0>. For example, transistor TR11 may be coupled between cache latch component C-LATCH1 and page buffer common node PBUS. In response to cache latch transmission signal TRANC<7:0>, transistor TR11 may be coupled between cache latch component C-LATCH1 and page buffer common node PBUS. <0> , the transistor TR11 can send the data stored in the cache latch component C-LATCH1 to the page buffer common node PBUS or send the data to the cache latch component C-LATCH1 through the page buffer common node PBUS. In addition, the transistor TR18 can be connected between the cache latch component C-LATCH8 and the page buffer common node PBUS. In response to the cache latch transmission signal TRANC <7> The transistor TR18 can send data stored in the cache latch component C-LATCH8 to the page buffer common node PBUS or send data to the cache latch component C-LATCH8 through the page buffer common node PBUS.

[0069] As described above, the plurality of page buffers 131A to 131C and the plurality of cache latch components 132A to 132C may be connected to the page buffer common node PBUS of the read / write circuit 130. In order to transmit data stored in the plurality of page buffers 131A to 131C to the plurality of cache latch components 132A to 132C or transmit data stored in the plurality of cache latch components 132A to 132C to the plurality of page buffers 131A to 131C, the page buffer common node PBUS is precharged to a set level using transistor TR9.

[0070] A plurality of page buffers 131A to 131C and a plurality of cache latch components 132A to 132C may be arranged at a set distance from each other in the layout, and may be connected to each other through a page buffer common node PBUS, so that the page buffer common node PBUS may have a relatively large wiring load. Therefore, the current consumption during the precharge operation and discharge operation of the page buffer common node PBUS may increase. In order to reduce the current consumption during the precharge operation and discharge operation of the page buffer common node PBUS, a low precharge scheme for precharging the page buffer common node PBUS may be used, wherein the precharge level of the page buffer common node PBUS is lower than the precharge level of the power supply voltage VDD. Here, the power supply voltage VDD may be applied to the page buffer common node PBUS only when the voltage level of the common node precharge signal PBUS_LPRE is equal to or greater than the voltage level "VDD+Vth" (representing the sum of the threshold voltage Vth of the transistor TR9 and the power supply voltage VDD). When the plurality of page buffers 131A to 131C receive and latch data stored in the plurality of cache latch components 132A to 132C through the page buffer common node PBUS, a relatively low trip voltage should be used to latch the data.

[0071] Figure 7 It is shown Figure 6 Circuit diagram of the cache latch assembly and page buffer.

[0072] Figure 6 Each of the plurality of page buffers 131A to 131C may have a similar structure, and each of the plurality of cache latch components 132A to 132C may have a similar structure. Therefore, the page buffer 131A and the cache latch component 132A are described as an example.

[0073] Reference Figure 7 , the page buffer 131A may include a bit line controller 231 , a bit line discharger 232 , a sensing node precharger 233 , a sub latch component 234 , and a main latch component 235 .

[0074] During a data sensing operation of a read operation or a verification operation, the bit line controller 231 may control a potential level of the sensing node SO based on a current amount of the bit line BL1 that changes according to a program state of a memory cell coupled to the bit line BL1 .

[0075] The bit line controller 231 may include a plurality of NMOS transistors N1 and N3 to N6 and a plurality of PMOS transistors P1 and P2 .

[0076] The NMOS transistor N1 may be coupled between the bit line BL1 and the node ND1 , and may electrically couple the bit line BL1 to the node ND1 in response to the page buffer selection signal PBSEL.

[0077] The NMOS transistor N3 may be coupled between the node ND1 and the common node CSO, and may electrically couple the node ND1 to the common node CSO in response to the page buffer sense signal PB_SENSE.

[0078] The PMOS transistor P1 and the PMOS transistor P2 may be coupled in series between a power supply voltage VDD and a sensing node SO, and may be turned on in response to a signal at a node QS of the sub-latch component 234 and a precharge signal SA_PRECH_N, respectively.

[0079] The NMOS transistor N4 may be coupled between a node between the PMOS transistors P1 and P2 and a common node CSO, and may provide a power supply voltage VDD provided through the PMOS transistor P1 to the common node CSO in response to a control signal SA_CSOC.

[0080] The NMOS transistor N5 may be coupled between the sensing node SO and the common node CSO, and may electrically couple the sensing node SO to the common node CSO in response to a transmission signal TRANSO.

[0081] The NMOS transistor N6 may be coupled between the common node CSO and the node ND2 of the sub latch component 234 , and may electrically couple the common node CSO to the node ND2 in response to the discharge signal SA_DISCH.

[0082] The operation of the bit line controller 231 during the data sensing operation is described below.

[0083] In response to the signal at the node QS of the sub-latch component 234 and the precharge signal SA_PRECH_N both being at a logic low level, the PMOS transistor P1 and the PMOS transistor P2 may precharge the sensing node SO to the level of the power supply voltage VDD. The NMOS transistor N5 may be turned on in response to the transmission signal TRANSO at a logic high level, and the common node CSO may be precharged to the level "VDD-Vth".

[0084] Thereafter, during the interval from when the precharge signal SA_PRECH_N is changed to a logic high level to when the transmission signal TRANSO is changed to a logic low level, an evaluation operation may be performed. The PMOS transistor P2 may be turned off in response to the precharge signal SA_PRECH_N being changed to a logic high level, thereby interrupting the power supply voltage VDD applied to the sensing node SO. The potential levels of the sensing node SO and the common node CSO may change according to the programming state of the memory cell connected to the bit line BL1. For example, when the memory cell is in a programming state where the threshold voltage of the memory cell is higher than the read voltage or the verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current does not flow through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be maintained at the precharge level. On the contrary, when the memory cell is in an erased state where the threshold voltage of the memory cell is lower than the read voltage or the verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current flows through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be reduced from the precharge level to the discharge level SA_CSOC-Vth.

[0085] The bit line discharger 232 may be coupled to the node ND1 of the bit line controller 231 to discharge a potential level of the bit line BL1 .

[0086] The bit line discharger 232 may include an NMOS transistor N2 coupled between the node ND1 and the ground power source VSS, and the NMOS transistor N2 may apply the ground power source VSS to the node ND1 in response to the bit line discharge signal BL_DIS.

[0087] The sensing node precharger 233 may be coupled between the sensing node SO and the power supply voltage VDD to precharge the sensing node SO to a level of the power supply voltage VDD.

[0088] The sense node precharger 233 may include a PMOS transistor P3 , and the PMOS transistor P3 may apply the power supply voltage VDD to the sense node SO in response to a sense node precharge signal PRECHSO_N.

[0089] The sub-latch component 234 may include a plurality of NMOS transistors N7 to N11 and inverters IV1 and IV2 .

[0090] Inverters IV1 and IV2 may be coupled in parallel between the node QS and the node QS_N in opposite directions, thus forming a latch.

[0091] NMOS transistors N7 and NMOS transistors N8 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N7 is turned on in response to a transmission signal TRANS and NMOS transistor N8 is turned on or off according to a potential level of a node QS.

[0092] The NMOS transistor N9 may be coupled between the node QS and the node ND3, and then the node QS may be electrically coupled to the node ND3 in response to the reset signal SRST. The NMOS transistor N10 may be coupled between the node QS_N and the node ND3, and then the node QS_N may be electrically coupled to the node ND3 in response to the set signal SSET. The NMOS transistor N11 may be coupled between the node ND3 and the ground power supply VSS, and may be turned on according to the potential of the sensing node SO to electrically couple the node ND3 to the ground power supply VSS. For example, when the reset signal SRST of a logic high level is applied to the NMOS transistor N9 in a state where the sensing node SO is precharged to a high level, the node QS and the node QS_N may be initialized to a logic low level and a logic high level, respectively. In addition, when the set signal SSET of a logic high level is applied to the NMOS transistor N10 in a state where the sensing node SO is precharged to a logic high level, the node QS and the node QS_N may be set to a logic high level and a logic low level, respectively. During a data sensing operation, the node QS may be set to a logic low level.

[0093] The master latch component 235 may include a plurality of NMOS transistors N12 to N17 and inverters IV3 and IV4 .

[0094] Inverters IV3 and IV4 may be coupled in parallel in opposite directions between the node QM and the node QM_N, thus forming a latch.

[0095] NMOS transistors N12 and NMOS transistors N13 may be coupled in series between the sensing node SO and the ground power source VSS, wherein the NMOS transistor N12 is turned on in response to the transmission signal TRANM and the NMOS transistor N13 is turned on or off according to a potential level of the node QM.

[0096] NMOS transistor N14 and NMOS transistor N15 may be connected in parallel between nodes QM and ND4, wherein NMOS transistor N15 is turned on or off in response to a first reset signal MRST1, and NMOS transistor N14 is turned on or off in response to a second reset signal MRST2. NMOS transistor N16 may be connected between node QM_N and node ND4, and then may electrically connect node QM_N to node ND4 in response to a set signal MSET. NMOS transistor N17 may be connected between node ND4 and a ground power source VSS, and may connect node ND4 to the ground power source VSS according to the potential of the sensing node SO.

[0097] The size of the NMOS transistor N15 may be larger than the size of the NMOS transistor N16. That is, the NMOS transistor N15 may be designed to have an on-resistance lower than that of the NMOS transistor N16. In addition, a pull-down current path (e.g., a first current path) between the node QM and the node ND4 formed when the NMOS transistor N14 and the NMOS transistor N15 are simultaneously turned on has a lower resistance than a pull-down current path (e.g., a second current path) between the node QM and the node ND4 formed when only one transistor (i.e., the NMOS transistor N15 or the NMOS transistor N14) is turned on.

[0098] The master latch component 235 can latch data based on the potential level of the sensing node SO during the data transmission operation and the data sensing operation. For example, during the data transmission operation, the NMOS transistor N17 can be turned on or off based on the potential level of the sensing node SO, and the NMOS transistor N15 and the NMOS transistor N14 can form a first current path in response to the first reset signal MRST1 and the second reset signal MRST2. In addition, during the data sensing operation, the NMOS transistor N17 can be turned on or off based on the potential level of the sensing node SO, and only the NMOS transistor N15 of the NMOS transistors N14 and N15 can be turned on in response to the first reset signal MRST1 to form a second current path. Therefore, the potential level of the node QM can be controlled to a logic low level or a logic high level according to the potential level of the sensing node SO, so that the data can be latched.

[0099] Cache latch component 132A may include NMOS transistor N19 and inverters IV5 and IV6.

[0100] Inverters IV5 and IV6 may be coupled in parallel between the node QC and the node QC_N in opposite directions, thus forming a latch. The NMOS transistor N19 may be coupled between the node QC and a ground power source VSS, and may be turned on in response to a reset signal CRST.

[0101] During a data transmission operation of transmitting data stored in the cache latch component 132A to the master latch component 235 of the page buffer 131A, the page buffer common node PBUS may be precharged to a level lower than that of the power supply voltage VDD through the transistor TR9. Therefore, the sensing node SO of the page buffer 131A may be precharged to the level of the power supply voltage VDD, but the potential level of the sensing node SO may be discharged to the ground level or may be reduced to the same level as the precharge level of the page buffer common node PBUS according to the data transmitted from the cache latch component 132A during the data transmission operation.

[0102] In contrast, during a data sensing operation of sensing the state of a memory cell coupled to the bit line BL1 , the sensing node SO may be maintained at the level of the power supply voltage VDD (ie, a precharge level) or may be discharged to a discharge level VSA_CSOC-Vth.

[0103] Therefore, the master latch component 235 may use a relatively low trip voltage during a data transmission operation and may use a relatively high trip voltage during a data sensing operation, thus improving the accuracy of a data latch operation.

[0104] In an embodiment of the present disclosure, the master latch component 235 may include at least two NMOS transistors N14 and N15 connected in parallel between the node QM and the node ND4, and the at least two NMOS transistors N14 and N15 may be turned on during a data transmission operation to relatively reduce the resistance of a pull-down current path between the node QM and the node ND4, and only one of the at least two NMOS transistors N14 and N15 may be turned on during a data sensing operation to relatively increase the resistance of the pull-down current path between the node QM and the node ND4. That is, the master latch component 235 may set a first trip voltage having a relatively low potential by strengthening the pull-down current path of the node QM during a data transmission operation, and may set a second trip voltage having a relatively high potential by weakening the pull-down current path of the node QM during a data sensing operation. Therefore, the master latch component 235 may perform a data latch operation using a relatively low first trip voltage during a data transmission operation, and may perform a data latch operation using a relatively high second trip voltage during a data sensing operation.

[0105] Figure 8 It is shown Figure 7 A waveform diagram of signals for a data transfer operation between a cache latch component and a page buffer.

[0106] Refer to the following Figure 7 and Figure 8 A data transfer operation between the cache latch component 132A and the page buffer 131A is described.

[0107] The sensing node precharger 233 may apply the power supply voltage VDD to the sensing node SO in response to the sensing node precharge signal PRECHSO_N of a logic low level (ground: GND) during a set period of time. Thus, the sensing node SO is precharged to the level of the power supply voltage VDD. After the set period of time has passed, the sensing node precharge signal PRECHSO_N turns to a logic high level VDD, and then the PMOS transistor P3 is turned off.

[0108] Transistor TR9 applies power supply voltage VDD to page buffer common node PBUS in response to common node precharge signal PBUS_LPRE of low precharge level VPBUS_LPRE for a set period of time. Therefore, page buffer common node PBUS can be precharged to first level VPBUS_LPRE-Vth. First level VPBUS_LPRE-Vth is lower than level VDD to which sensing node SO is precharged.

[0109] The transistor TR11 responds to the cache latch transfer signal TRANC. <0> The transistor TR1 is turned on in response to the page buffer transfer signal TRANPB. <0> Therefore, the page buffer common node PBUS is electrically connected to the sensing node SO, so that according to the data stored in the cache latch component 132A, the page buffer common node PBUS is maintained at the first level VPBUS_LPRE-Vth or is discharged to the logic low level GND, and the sensing node SO is reduced to the first level VPBUS_LPRE-Vth (precharge level of the page buffer common node PBUS), or is discharged to the logic low level GND. For example, when the node QC_N of the cache latch component 132A is at a logic low level (QC_N=0), the page buffer common node PBUS and the sensing node SO may be discharged to the logic low level GND. When the node QC_N of the cache latch component 132A is at a logic high level (QC_N=1), the potential of each of the page buffer common node PBUS and the sensing node SO may be the first level VPBUS_LPRE-Vth.

[0110] The NMOS transistor N17 of the master latch component 235 may be turned on or off according to the potential level of the sensing node SO, and the NMOS transistor N15 and the NMOS transistor N14 may be turned on in response to the first reset signal MRST1 and the second reset signal MRST2 to form a first current path. Therefore, the first trip voltage Vtrip1 of the master latch component 235 is set to a potential between the logic low level GND and the first level VPBUS_LPRE-Vth, and the master latch component 235 may latch the first data (e.g., "0") and the second data (e.g., "1") based on the set potential level of the first trip voltage Vtrip1 and the potential level of the sensing node SO.

[0111] Fig. 9 It is shown Figure 7 1 is a waveform diagram of signals of a data sensing operation of a page buffer.

[0112] Refer to the following Figure 7 and Fig. 9 A data sensing operation of the page buffer 131A is described.

[0113] In response to the signal at the node QS of the sub-latch component 234 and the precharge signal SA_PRECH_N both being at a logic low level, the PMOS transistor P1 and the PMOS transistor P2 may precharge the sensing node SO to the level of the power supply voltage VDD. The NMOS transistor N5 may be turned on in response to the transmission signal TRANSO of a logic high level, and the common node CSO may be precharged to a level of "VDD-Vth". The NMOS transistor N3 may be turned on in response to the page buffer sense signal PB_SENSE of a logic high level VPB_SENSE. The NMOS transistor N1 may be turned on in response to the page buffer select signal PBSEL, and then the bit line BL1 may be precharged to a precharge level VPB_SENSE-Vth by supplying current to the bit line BL1.

[0114] Thereafter, when the precharge signal SA_PRECH_N is changed to a logic high level VDD, the PMOS transistor P2 is turned off in response to the precharge signal SA_PRECH_N changed to a logic high level, thereby interrupting the application of the power supply voltage VDD to the sensing node SO. The potential levels of the sensing node SO and the common node CSO may change according to the programming state of the memory cell connected to the bit line BL1. For example, when the memory cell is in a programming state (PGM cell) in which the threshold voltage of the memory cell is higher than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current does not flow through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be maintained at the precharge level. On the contrary, when the memory cell is in an erased state (erase cell) in which the threshold voltage of the memory cell is lower than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current flows through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be reduced from the precharge level to the second level VSA_CSOC-Vth.

[0115] The NMOS transistor N17 of the master latch component 235 may be turned on or off according to the potential level of the sensing node SO, and one of the NMOS transistor N15 and the NMOS transistor N14 may be turned on in response to the first reset signal RST1 or the second reset signal MRST2 to form a second current path. Therefore, the second trip voltage Vtrip2 of the master latch component 235 may be set to a value between the power supply voltage level VDD (precharge level of the sensing node SO) and the second level VSA_CSOC-Vth (discharge level). The master latch component 235 may latch the first data (e.g., "0") and the second data (e.g., "1") based on the set potential level of the second trip voltage Vtrip2 and the potential level of the sensing node SO.

[0116] Fig.10 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0117] Reference Fig.10 , the page buffer 131A may include a bit line controller 331 , a bit line discharger 332 , a sensing node precharger 333 , a sub latch component 334 , and a main latch component 335 .

[0118] During a data sensing operation of a read operation or a verification operation, the bit line controller 331 may control a potential level of the sensing node SO based on a current amount of the bit line BL1 that changes according to a program state of a memory cell coupled to the bit line BL1 .

[0119] The bit line controller 331 may include a plurality of NMOS transistors N21 and N23 to N26 and a plurality of PMOS transistors P21 and P22 .

[0120] The NMOS transistor N21 may be coupled between the bit line BL1 and the node ND11 , and may electrically couple the bit line BL1 to the node ND1 in response to the page buffer selection signal PBSEL.

[0121] The NMOS transistor N23 may be coupled between the node ND11 and the common node CSO, and may electrically couple the node ND11 to the common node CSO in response to the page buffer sense signal PB_SENSE.

[0122] The PMOS transistor P21 and the PMOS transistor P22 may be coupled in series between the power supply voltage VDD and the sensing node SO, and may be turned on in response to a signal at the node QS of the sub-latch component 334 and the precharge signal SA_PRECH_N, respectively.

[0123] The NMOS transistor N24 may be coupled between a node between the PMOS transistors P21 and P22 and the common node CSO, and may provide the power supply voltage VDD provided through the PMOS transistor P21 to the common node CSO in response to a control signal SA_CSOC.

[0124] The NMOS transistor N25 may be coupled between the sensing node SO and the common node CSO, and may electrically couple the sensing node SO to the common node CSO in response to a transmission signal TRANSO.

[0125] The NMOS transistor N26 may be coupled between the common node CSO and the node ND12 of the sub latch component 334 , and may electrically couple the common node CSO to the node ND12 in response to the discharge signal SA_DISCH.

[0126] The operation of the bit line controller 331 during the data sensing operation is described below.

[0127] In response to the signal at the node QS of the sub-latch component 334 and the precharge signal SA_PRECH_N both being at a logic low level, the PMOS transistor P21 and the PMOS transistor P22 may precharge the sensing node SO to the level of the power supply voltage VDD. The NMOS transistor N25 may be turned on in response to the transmission signal TRANSO at a logic high level, and the common node CSO may be precharged to a level "VDD-Vth".

[0128] Thereafter, during the interval from when the precharge signal SA_PRECH_N is changed to a logic high level to when the transmission signal TRANSO is changed to a logic low level, an evaluation operation may be performed. The PMOS transistor P22 may be turned off in response to the precharge signal SA_PRECH_N that has been changed to a logic high level, thereby interrupting the power supply voltage VDD applied to the sensing node SO. The potential levels of the sensing node SO and the common node CSO may change according to the programming state of the memory cell connected to the bit line BL1. For example, when the memory cell is in a programming state where the threshold voltage of the memory cell is higher than the read voltage or the verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current does not flow through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be maintained at a precharge level. On the contrary, when the memory cell is in an erased state where the threshold voltage of the memory cell is lower than the read voltage or the verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current flows through the bit line BL1. Therefore, the potentials of the common node CSO and the sensing node SO may decrease from the precharge level to the discharge level VSA_CSOC-Vth.

[0129] The bit line discharger 332 may be coupled to the node ND11 of the bit line controller 331 to discharge a potential level of the bit line BL1 .

[0130] The bit line discharger 332 may include an NMOS transistor N22 coupled between the node ND11 and the ground power source VSS, and the NMOS transistor N22 may apply the ground power source VSS to the node ND11 in response to the bit line discharge signal BL_DIS.

[0131] The sensing node precharger 333 may be coupled between the sensing node SO and the power supply voltage VDD to precharge the sensing node SO to a level of the power supply voltage VDD.

[0132] The sense node precharger 333 may include a PMOS transistor P23 , and the PMOS transistor P23 may apply the power supply voltage VDD to the sense node SO in response to a sense node precharge signal PRECHSO_N.

[0133] The sub-latch component 334 may include a plurality of NMOS transistors N27 to N31 and inverters IV11 and IV12 .

[0134] Inverters IV11 and IV12 may be coupled in parallel between the node QS and the node QS_N in opposite directions, thus forming a latch.

[0135] NMOS transistor N27 and NMOS transistor N28 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N27 is turned on in response to a transmission signal TRANS and NMOS transistor N28 is turned on or off according to a potential level of a node QS.

[0136] The NMOS transistor N29 may be coupled between the node QS and the node ND13, and then the node QS may be electrically coupled to the node ND13 in response to the reset signal SRST. The NMOS transistor N30 may be coupled between the node QS_N and the node ND13, and then the node QS_N may be electrically coupled to the node ND13 in response to the set signal SSET. The NMOS transistor N31 may be coupled between the node ND13 and the ground power supply VSS, and may be turned on according to the potential of the sensing node SO to electrically couple the node ND13 to the ground power supply VSS. For example, when the reset signal SRST of a logic high level is applied to the NMOS transistor N29 in a state where the sensing node SO is precharged to a high level, the node QS and the node QS_N may be initialized to a logic low level and a logic high level, respectively. In addition, when the set signal SSET of a logic high level is applied to the NMOS transistor N30 in a state where the sensing node SO is precharged to a logic high level, the node QS and the node QS_N may be set to a logic high level and a logic low level, respectively. During a data sensing operation, the node QS may be set to a logic low level.

[0137] The master latch component 335 may include a plurality of NMOS transistors N32 to N38 and inverters IV13 and IV14 .

[0138] Inverters IV13 and IV14 may be coupled in parallel between the node QM and the node QM_N in opposite directions, thus forming a latch.

[0139] NMOS transistor N32 and NMOS transistor N33 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N32 is turned on in response to a transmission signal TRANM and NMOS transistor N33 is turned on or off according to a potential level of a node QM.

[0140] NMOS transistor N34 may be coupled between node QM and node ND14 and then may electrically couple node QM to node ND14 in response to reset signal MRST. NMOS transistor N35 may be coupled between node QM_N and node ND14 and then may electrically couple node QM_N to node ND14 in response to set signal MSET.

[0141] NMOS transistor N36 and NMOS transistor N38 may be connected in series between node ND14 and ground power supply VSS. NMOS transistor N36 may be turned on or off according to the potential of sensing node SO, and NMOS transistor N38 may be turned on or off in response to enable signal EN. NMOS transistor N37 may be connected between node ND14 and ground power supply VSS, and may be turned on or off according to the potential of sensing node SO. That is, NMOS transistor N36 and NMOS transistor N38 connected in series may form a structure connected in parallel with NMOS transistor N37. When NMOS transistor N36, NMOS transistor N37 and NMOS transistor N38 are turned on at the same time, the pull-down current path (e.g., the first current path) formed between node ND14 and ground power supply VSS has a resistance value smaller than the pull-down current path (e.g., the second current path) formed by only one transistor (i.e., NMOS transistor N37).

[0142] During the data transmission operation and the data sensing operation, the master latch component 335 may latch data based on the potential level of the sensing node SO. For example, during the data transmission operation, the NMOS transistor N38 is turned on in response to the enable signal EN of the logic high level, and the NMOS transistor N36 and the NMOS transistor N37 are turned on or off based on the potential level of the sensing node SO, so that the master latch component 335 may or may not form a first current path, and then the data may be latched. In addition, during the data sensing operation, the NMOS transistor N38 is turned off in response to the enable signal EN of the logic low level, and the NMOS transistor N36 and the NMOS transistor N37 are turned on or off based on the potential level of the sensing node SO, so that the master latch component 335 may or may not form a second current path, and then the data may be latched.

[0143] Since the structure of cache latch component 132A is similar to that of reference Figure 7 The structures of the cache latch components described are the same, so their detailed description is omitted here.

[0144] During a data transmission operation of transmitting data stored in the cache latch component 132A to the master latch component 335 of the page buffer 131A, the page buffer common node PBUS may be precharged to a level lower than that of the power supply voltage VDD through the transistor TR9. Therefore, the sensing node SO of the page buffer 131A may be precharged to the level of the power supply voltage VDD, but the potential level of the sensing node SO may be discharged to the ground level or may be reduced to the same level as the precharge level of the page buffer common node PBUS according to the data transmitted from the cache latch component 132A during the data transmission operation.

[0145] In contrast, during a data sensing operation of sensing the state of a memory cell coupled to the bit line BL1 , the sensing node SO may be maintained at the level of the power supply voltage VDD (precharge level) or may be discharged to a discharge level VSA_CSOC-Vth.

[0146] Therefore, the master latch component 335 may use a relatively low trip voltage during a data transmission operation and may use a relatively high trip voltage during a data sensing operation, thus improving the accuracy of a data latch operation.

[0147] The master latch component 335 according to an embodiment of the present disclosure may include two or more NMOS transistors N36 and N37 connected in parallel between the node ND14 and the ground power supply VSS, and the two or more NMOS transistors N36 and N37 may operate according to the potential of the sensing node SO. In addition, the NMOS transistor N38 driven in response to the enable signal EN enabled to be a logic high level only during the data transmission operation may be provided between the NMOS transistor N36 and the ground power supply VSS. As a result, in the master latch component 335, a first current path in which a current flows into the ground power supply VSS through the NMOS transistors N36 and N37 during the data transmission operation may be formed, and thus a first trip voltage having a relatively low potential may be set by relatively strengthening the pull-down current path of the node QM. In addition, in the master latch component 335, a second current path in which a current flows into the ground power supply VSS through the NMOS transistor N37 during the data sensing operation may be formed, and thus a second trip voltage having a relatively high potential may be set by relatively weakening the pull-down current path of the node QM. Therefore, the master latch component 335 may perform a data latch operation using a relatively low first trip voltage during a data transmission operation, and may perform a data latch operation using a relatively high second trip voltage during a data sensing operation.

[0148] Fig.11 It is shown Fig.10 A waveform diagram of signals for a data transfer operation between a cache latch component and a page buffer.

[0149] Refer to the following Fig.10 and Fig.11 A data transfer operation between the cache latch component 132A and the page buffer 131A is described.

[0150] During the data transmission operation, an enable signal EN of a logic high level may be applied to the NMOS transistor N38 , and thus the NMOS transistor N38 may remain turned on.

[0151] The sensing node precharger 333 may apply the power supply voltage VDD to the sensing node SO in response to the sensing node precharge signal PRECHSO_N of the logic low level (GND) during the set period. Therefore, the sensing node SO is precharged to the level of the power supply voltage VDD. After the set period of time has passed, the sensing node precharge signal PRECHSO_N is converted to the logic high level VDD, and then the PMOS transistor P23 is turned off.

[0152] Transistor TR9 applies power supply voltage VDD to page buffer common node PBUS in response to common node precharge signal PBUS_LPRE of low precharge level VPBUS_LPRE for a set period of time. Therefore, page buffer common node PBUS can be precharged to first level VPBUS_LPRE-Vth. First level VPBUS_LPRE-Vth is lower than level VDD to which sensing node SO is precharged.

[0153] The transistor TR11 responds to the cache latch transfer signal TRANC. <0> The transistor TR1 is turned on in response to the page buffer transfer signal TRANPB. <0> Therefore, the page buffer common node PBUS is electrically connected to the sensing node SO, so that according to the data stored in the cache latch component 132A, the page buffer common node PBUS is maintained at the first level VPBUS_LPRE-Vth or is discharged to the logic low level GND, and the sensing node SO is reduced to the first level VPBUS_LPRE-Vth (precharge level of the page buffer common node PBUS), or is discharged to the logic low level GND. For example, when the node QC_N of the cache latch component 132A is at a logic low level (QC_N=0), the page buffer common node PBUS and the sensing node SO may be discharged to the logic low level GND. When the node QC_N of the cache latch component 132A is at a logic high level (QC_N=1), the potential of the page buffer common node PBUS and the sensing node SO may be the first level VPBUS_LPRE-Vth.

[0154] The NMOS transistor N36 and the NMOS transistor N37 of the master latch component 335 may be turned on or off according to the potential level of the sensing node SO, and the NMOS transistor N34 may be turned on in response to the reset signal MRST.

[0155] When the NMOS transistors N36 and N37 are turned on according to the potential level of the sensing node SO, a first current path may be formed, the first current path including a current path in which a current flows from the node ND14 to the ground power source VSS through the NMOS transistors N36 and N38 and a current path in which a current flows from the node ND14 to the ground power source VSS through the NMOS transistors N37. Therefore, the first trip voltage Vtrip1 of the master latch component 335 is set to a potential between the logic low level GND and the first level VPBUS_LPRE-Vth, and the master latch component 335 may latch the first data (e.g., “0”) and the second data (e.g., “1”) based on the set potential level of the first trip voltage Vtrip1 and the potential level of the sensing node SO.

[0156] Fig.12 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0157] Reference Fig.12 , the page buffer 131A may include a bit line controller 431 , a bit line discharger 432 , a sensing node precharger 433 , a sub latch component 434 , and a main latch component 435 .

[0158] During a data sensing operation of a read operation or a verification operation, the bit line controller 431 may control a potential level of the sensing node SO based on a current amount of the bit line BL1 that changes according to a program state of a memory cell coupled to the bit line BL1 .

[0159] The bit line controller 431 may include a plurality of NMOS transistors N41 and N43 to N46 and a plurality of PMOS transistors P31 and P32 .

[0160] The NMOS transistor N41 may be coupled between the bit line BL1 and the node ND21 , and may electrically couple the bit line BL1 to the node ND21 in response to the page buffer selection signal PBSEL.

[0161] The NMOS transistor N43 may be coupled between the node ND21 and the common node CSO, and may electrically couple the node ND21 to the common node CSO in response to the page buffer sense signal PB_SENSE.

[0162] The PMOS transistor P31 and the PMOS transistor P32 may be coupled in series between the power supply voltage VDD and the sensing node SO, and may be turned on in response to a signal at the node QS of the sub-latch component 434 and the precharge signal SA_PRECH_N, respectively.

[0163] The NMOS transistor N44 may be coupled between a node between the PMOS transistor P31 and the PMOS transistor P32 and the common node CSO, and may provide the power supply voltage VDD provided through the PMOS transistor P31 to the common node CSO in response to a control signal SA_CSOC.

[0164] The NMOS transistor N45 may be coupled between the sensing node SO and the common node CSO, and may electrically couple the sensing node SO to the common node CSO in response to a transmission signal TRANSO.

[0165] The NMOS transistor N46 may be coupled between the common node CSO and the node ND22 of the sub latch component 434 , and may electrically couple the common node CSO to the node ND22 in response to the discharge signal SA_DISCH.

[0166] The operation of the bit line controller 431 during the data sensing operation is described below.

[0167] In response to both the node QS of the sub-latch component 434 and the precharge signal SA_PRECH_N being at a logic low level, the PMOS transistor P31 and the PMOS transistor P32 may precharge the sensing node SO to the level of the power supply voltage VDD. The NMOS transistor N45 may be turned on in response to the transmission signal TRANSO of a logic high level, and the common node CSO may be precharged to a level "VDD-Vth".

[0168] Thereafter, during the interval from when the precharge signal SA_PRECH_N is changed to a logic high level to when the transmission signal TRANSO is changed to a logic low level, an evaluation operation may be performed. The PMOS transistor P32 may be turned off in response to the precharge signal SA_PRECH_N that has been changed to a logic high level, thereby interrupting the power supply voltage VDD applied to the sensing node SO. The potential levels of the sensing node SO and the common node CSO may change according to the programming state of the memory cell connected to the bit line BL1. For example, when the memory cell is in a programming state where the threshold voltage of the memory cell is higher than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current does not flow through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be maintained at a precharge level. On the contrary, when the memory cell is in an erased state where the threshold voltage of the memory cell is lower than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current flows through the bit line BL1. Therefore, the potentials of the common node CSO and the sensing node SO may decrease from the precharge level to the discharge level VSA_CSOC-Vth.

[0169] The bit line discharger 432 may be coupled to the node ND21 of the bit line controller 431 to discharge a potential level of the bit line BL1 .

[0170] The bit line discharger 432 may include an NMOS transistor N42 coupled between the node ND21 and the ground power source VSS, and the NMOS transistor N42 may apply the ground power source VSS to the node ND21 in response to the bit line discharge signal BL_DIS.

[0171] The sensing node precharger 433 may be coupled between the sensing node SO and the power supply voltage VDD to precharge the sensing node SO to a level of the power supply voltage VDD.

[0172] The sense node precharger 433 may include a PMOS transistor P33 , and the PMOS transistor P33 may apply the power supply voltage VDD to the sense node SO in response to a sense node precharge signal PRECHSO_N.

[0173] The sub-latch component 434 may include a plurality of NMOS transistors N47 to N51 and inverters IV21 and IV22 .

[0174] Inverters IV21 and IV22 may be coupled in parallel between the node QS and the node QS_N in opposite directions, thus forming a latch.

[0175] NMOS transistor N47 and NMOS transistor N48 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N47 is turned on in response to a transmission signal TRANS and NMOS transistor N48 is turned on or off according to a potential level of a node QS.

[0176] The NMOS transistor N49 may be coupled between the node QS and the node ND23, and then the node QS may be electrically coupled to the node ND23 in response to the reset signal SRST. The NMOS transistor N50 may be coupled between the node QS_N and the node ND23, and then the node QS_N may be electrically coupled to the node ND23 in response to the set signal SSET. The NMOS transistor N51 may be coupled between the node ND23 and the ground power supply VSS, and may be turned on according to the potential of the sensing node SO to electrically couple the node ND23 to the ground power supply VSS. For example, when the reset signal SRST of a logic high level is applied to the NMOS transistor N49 in a state where the sensing node SO is precharged to a high level, the node QS and the node QS_N may be initialized to a logic low level and a logic high level, respectively. In addition, when the set signal SSET of a logic high level is applied to the NMOS transistor N50 in a state where the sensing node SO is precharged to a logic high level, the node QS and the node QS_N may be set to a logic high level and a logic low level, respectively. During a data sensing operation, the node QS may be set to a logic low level.

[0177] The master latch component 435 may include a plurality of NMOS transistors N52 to N56 and inverters IV23 and IV24 .

[0178] Inverters IV23 and IV24 may be connected in parallel between nodes QM and QM_N in opposite directions, thereby forming a latch. In inverter IV24 that controls the potential of node QM by inverting the potential level of node QM_N, the pull-up current path may be blocked during the data transmission operation. Therefore, during the data transmission operation, the pull-up current path of node QM may be weakened, so the first trip voltage of the main latch component 435 may be relatively reduced. In addition, in inverter IV24, the pull-up current path may operate normally during the data sensing operation and may be strengthened compared to during the data transmission operation, so the second trip voltage of the main latch component 435 may be relatively high.

[0179] Reference Fig.13 The inverter IV24 is described in detail.

[0180] NMOS transistor N52 and NMOS transistor N53 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N52 is turned on in response to a transmission signal TRANM and NMOS transistor N53 is turned on or off according to a potential level of a node QM.

[0181] NMOS transistor N54 may be coupled between node QM and node ND24 and then may electrically couple node QM to node ND24 in response to reset signal MRST. NMOS transistor N55 may be coupled between node QM_N and node ND24 and then may electrically couple node QM_N to node ND24 in response to set signal MSET.

[0182] The NMOS transistor N56 may be coupled between the node ND24 and the ground power source VSS, and may be turned on or off according to the potential of the sensing node SO. The master latch component 435 may set the potential of the node QM so that the potential of QM is a logic high level during the initialization operation of the data transmission operation and the data sensing operation. For example, when a setting signal MSET of a logic high level is applied to the NMOS transistor N55 in a state where the sensing node SO is precharged to a logic high level, the node QM and the node QM_N may be set to a logic high level and a logic low level, respectively.

[0183] Since the structure of cache latch component 132A is similar to that of reference Figure 7 The structures of the cache latch components described are the same, so their detailed description is omitted here.

[0184] During a data transmission operation of transmitting data stored in the cache latch component 132A to the master latch component 435 of the page buffer 131A, the page buffer common node PBUS may be precharged to a level lower than that of the power supply voltage VDD through the transistor TR9. Therefore, the sensing node SO of the page buffer 131A may be precharged to the level of the power supply voltage VDD, but the potential level of the sensing node SO may be discharged to the ground level or may be reduced to the same level as the precharge level of the page buffer common node PBUS according to the data transmitted from the cache latch component 132A during the data transmission operation.

[0185] In contrast, during a data sensing operation of sensing the states of memory cells coupled to the bit line BL1 , the sensing node SO may be maintained at the level of the power supply voltage VDD (precharge level) or may be discharged to a discharge level VSA_CSOC-Vth.

[0186] Therefore, the master latch component 435 may use a relatively low trip voltage during a data transmission operation and may use a relatively high trip voltage during a data sensing operation, thus improving the accuracy of a data latch operation.

[0187] Fig.13 It is shown Fig.12 Circuit diagram of inverter IV24 of the master latch component.

[0188] Reference Fig.13, the inverter IV24 may include PMOS transistors P41 and P42 and an NMOS transistor N61 connected in series between the power supply voltage VDD and the ground power supply VSS.

[0189] PMOS transistors P41 and P42 are connected in series between the power supply voltage VDD and the output node Q2 connected to the node QM. The PMOS transistor P41 is turned on or off in response to the inverted enable signal EN_N, thereby providing or interrupting the power supply voltage VDD to the PMOS transistor P42. The inverted enable signal EN_N of a logic high level may be applied during the data transmission operation, and the inverted enable signal EN_N of a logic low level may be applied when the data transmission operation is not performed (for example, when the data sensing operation is performed). The gate of the PMOS transistor P42 is connected to the input node Q1 connected to the node QM_N, and is turned on or off based on the potential level of the node QM_N. The NMOS transistor N61 is connected between the output node Q2 and the ground power supply VSS, wherein the gate of the NMOS transistor N61 is connected to the node QM_N, and then turned on or off based on the potential level of the node QM_N.

[0190] When the data transmission operation is not performed, for example, when another operation such as a data sensing operation is performed, an inverted enable signal EN_N of a logic low level is applied, and then the PMOS transistor P41 is turned on. When the potential level of the input node Q1 is applied as a logic high level, the NMOS transistor N61 is turned on to form a pull-down current path in which the current flows from the output node Q2 to the ground power supply VSS, and the PMOS transistor P42 is turned off to prevent the formation of a pull-up current path. Therefore, the output node Q2 is a logic low level. On the contrary, when the potential level of the input node Q1 is applied as a logic low level, the NMOS transistor N61 is turned off to prevent the formation of a pull-down current path, and the PMOS transistor P42 is turned on to form a pull-up current path. Therefore, the output node Q2 is a logic high level. That is, when the data transmission operation is not performed, for example, when a data sensing operation is performed, a pull-up current path or a pull-down current path can be formed based on the potential of the input node Q1.

[0191] During the data transmission operation, the inverted enable signal EN_N of the logic high level may be applied, and then the PMOS transistor P41 may be turned off. Therefore, no matter how the potential level of the input node Q1 is, the pull-up current path is not formed. That is, during the data transmission operation, no matter how the potential of the input node Q1 is, the pull-up current path is not formed.

[0192] In an embodiment of the present disclosure, during a data transmission operation, a first trip voltage having a relatively low potential can be set by blocking a pull-up current path of the inverter IV24 that controls the potential level of the node QM of the master latch component 435. That is, during a data transmission operation, a first trip voltage having a relatively low potential can be set by weakening the pull-up current path of the node QM. In addition, when a data transmission operation is not performed, for example, when another operation such as a data sensing operation is performed, the inverter IV24 can form a pull-up current path and a pull-down current path based on the potential of the node QM_N, thereby setting a second trip voltage having a relatively high potential. Therefore, the master latch component 335 can perform a data latch operation using a relatively low first trip voltage during a data transmission operation, and can perform a data latch operation using a relatively high second trip voltage during a data sensing operation.

[0193] Fig.14 It is shown Fig.12 A waveform diagram of signals for a data transfer operation between a cache latch component and a page buffer.

[0194] Refer to the following Figure 12 to Figure 14 A data transfer operation between the cache latch component 132A and the page buffer 131A is described.

[0195] During a data transmission operation, an inverted enable signal EN_N of a logic high level may be applied, and thus a pull-up current path that applies current to the node QM of the master latch component 435 is interrupted.

[0196] The sensing node precharger 433 may apply the power supply voltage VDD to the sensing node SO in response to the sensing node precharge signal PRECHSO_N of the logic low level (GND) during the set period. Therefore, the sensing node SO is precharged to the level of the power supply voltage VDD. After the set period of time has passed, the sensing node precharge signal PRECHSO_N is converted to the logic high level VDD, and then the PMOS transistor P33 is turned off.

[0197] Transistor TR9 applies power supply voltage VDD to page buffer common node PBUS in response to common node precharge signal PBUS_LPRE of low precharge level VPBUS_LPRE for a set period of time. Therefore, page buffer common node PBUS can be precharged to first level VPBUS_LPRE-Vth. First level VPBUS_LPRE-Vth is lower than level VDD to which sensing node SO is precharged.

[0198] The transistor TR11 responds to the cache latch transfer signal TRANC. <0> The transistor TR1 is turned on in response to the page buffer transfer signal TRANPB. <0> Therefore, the page buffer common node PBUS is electrically connected to the sensing node SO, so that according to the data stored in the cache latch component 132A, the page buffer common node PBUS is maintained at the first level VPBUS_LPRE-Vth or is discharged to the logic low level GND, and the sensing node SO is reduced to the first level VPBUS_LPRE-Vth (precharge level of the page buffer common node PBUS), or is discharged to the logic low level GND. For example, when the node QC_N of the cache latch component 132A is at a logic low level (QC_N=0), the page buffer common node PBUS and the sensing node SO may be discharged to the logic low level GND. When the node QC_N of the cache latch component 132A is at a logic high level (QC_N=1), the potential of the page buffer common node PBUS and the sensing node SO may be the first level VPBUS_LPRE-Vth.

[0199] The NMOS transistor N56 of the master latch component 435 may be turned on or off according to the potential level of the sensing node SO, and the NMOS transistor N54 may be turned on in response to the reset signal MRST.

[0200] When the NMOS transistor N56 is turned on according to the potential level of the sensing node SO, a current path is formed in which the current flows from the node ND24 to the ground power supply VSS through the NMOS transistor N56. In a state where the pull-up current path of the inverter IV24 is blocked, a current path is formed in which the current flows from the node ND24 to the ground power supply VSS through the NMOS transistor N56. Therefore, the first trip voltage Vtrip1 of the master latch component 435 is set to a potential between the logic low level GND and the first level VPBUS_LPRE-Vth. The master latch component 435 can latch the first data (e.g., "0") and the second data (e.g., "1") based on the set first trip voltage Vtrip1 and the potential level of the sensing node SO.

[0201] Fig.15 is a circuit diagram showing a page buffer according to an embodiment of the present disclosure.

[0202] Reference Fig.15 , the page buffer 131A may include a bit line controller 531 , a bit line discharger 532 , a sensing node precharger 533 , a sub latch component 534 , and a main latch component 535 .

[0203] During a data sensing operation of a read operation or a verification operation, the bit line controller 531 may control a potential level of the sensing node SO based on a current amount of the bit line BL1 that changes according to a program state of a memory cell coupled to the bit line BL1 .

[0204] The bit line controller 531 may include a plurality of NMOS transistors N81 and N83 to N86 and a plurality of PMOS transistors P51 and P52 .

[0205] The NMOS transistor N81 may be coupled between the bit line BL1 and the node ND31 , and may electrically couple the bit line BL1 to the node ND31 in response to the page buffer selection signal PBSEL.

[0206] The NMOS transistor N83 may be coupled between the node ND31 and the common node CSO, and may electrically couple the node ND31 to the common node CSO in response to the page buffer sense signal PB_SENSE.

[0207] The PMOS transistor P51 and the PMOS transistor P52 may be coupled in series between the power supply voltage VDD and the sensing node SO, and may be turned on in response to a signal at the node QS of the sub-latch component 534 and the precharge signal SA_PRECH_N, respectively.

[0208] The NMOS transistor N84 may be coupled between a node between the PMOS transistors P51 and P52 and the common node CSO, and may provide a power supply voltage VDD provided through the PMOS transistor P51 to the common node CSO in response to a control signal SA_CSOC.

[0209] The NMOS transistor N85 may be coupled between the sensing node SO and the common node CSO, and may electrically couple the sensing node SO to the common node CSO in response to a transmission signal TRANSO.

[0210] The NMOS transistor N86 may be coupled between the common node CSO and the node ND32 of the sub latch component 534 and may electrically couple the common node CSO to the node ND32 in response to the discharge signal SA_DISCH.

[0211] The operation of the bit line controller 531 during the data sensing operation is described below.

[0212] In response to both the node QS of the sub-latch component 534 and the precharge signal SA_PRECH_N being at a logic low level, the PMOS transistor P51 and the PMOS transistor P52 may precharge the sensing node SO to the level of the power supply voltage VDD. The NMOS transistor N85 may be turned on in response to the transmission signal TRANSO of a logic high level, and the common node CSO may be precharged to a level "VDD-Vth".

[0213] Thereafter, during the interval from when the precharge signal SA_PRECH_N is changed to a logic high level to when the transmission signal TRANSO is changed to a logic low level, an evaluation operation may be performed. The PMOS transistor P52 may be turned off in response to the precharge signal SA_PRECH_N that has been changed to a logic high level, thereby interrupting the power supply voltage VDD applied to the sensing node SO. The potential levels of the sensing node SO and the common node CSO may change according to the programming state of the memory cell connected to the bit line BL1. For example, when the memory cell is in a programming state where the threshold voltage of the memory cell is higher than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current does not flow through the bit line BL1. Therefore, the potential of the common node CSO and the sensing node SO may be maintained at a precharge level. On the contrary, when the memory cell is in an erased state where the threshold voltage of the memory cell is lower than the read voltage or verification voltage of the word line applied to the memory cell during a read operation or a verification operation, the current flows through the bit line BL1. Therefore, the potentials of the common node CSO and the sensing node SO may decrease from the precharge level to the discharge level VSA_CSOC-Vth.

[0214] The bit line discharger 532 may be coupled to the node ND31 of the bit line controller 531 to discharge a potential level of the bit line BL1 .

[0215] The bit line discharger 532 may include an NMOS transistor N82 coupled between the node ND31 and the ground power source VSS, and the NMOS transistor N82 may apply the ground power source VSS to the node ND31 in response to the bit line discharge signal BL_DIS.

[0216] The sensing node precharger 533 may be coupled between the sensing node SO and the power supply voltage VDD to precharge the sensing node SO to a level of the power supply voltage VDD.

[0217] The sense node precharger 533 may include a PMOS transistor P53 , and the PMOS transistor P53 may apply the power supply voltage VDD to the sense node SO in response to a sense node precharge signal PRECHSO_N.

[0218] The sub-latch component 534 may include a plurality of NMOS transistors N87 to N91 and inverters IV31 and IV32.

[0219] Inverters IV31 and IV32 may be coupled in parallel between the node QS and the node QS_N in opposite directions, thus forming a latch.

[0220] NMOS transistor N87 and NMOS transistor N88 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N87 is turned on in response to a transmission signal TRANS and NMOS transistor N88 is turned on or off according to a potential level of the node QS.

[0221] The NMOS transistor N89 may be coupled between the node QS and the node ND33, and then the node QS may be electrically coupled to the node ND33 in response to the reset signal SRST. The NMOS transistor N90 may be coupled between the node QS_N and the node ND33, and then the node QS_N may be electrically coupled to the node ND33 in response to the set signal SSET. The NMOS transistor N91 may be coupled between the node ND33 and the ground power supply VSS, and may be turned on according to the potential of the sensing node SO to electrically couple the node ND33 to the ground power supply VSS. For example, when the reset signal SRST of a logic high level is applied to the NMOS transistor N89 in a state where the sensing node SO is precharged to a high level, the node QS and the node QS_N may be initialized to a logic low level and a logic high level, respectively. In addition, when the set signal SSET of a logic high level is applied to the NMOS transistor N90 in a state where the sensing node SO is precharged to a logic high level, the node QS and the node QS_N may be set to a logic high level and a logic low level, respectively. During a data sensing operation, the node QS may be set to a logic low level.

[0222] The master latch component 535 may include a plurality of NMOS transistors N92 to N99 and inverters IV33 and IV34 .

[0223] Inverters IV33 and IV34 may be connected in parallel between the node QM and the node QM_N in opposite directions, thus forming a latch. Inverter IV34 may be connected in parallel with Fig.131 and 1 . In the inverter IV34 that controls the potential of the node QM by inverting the potential level of the node QM_N, the pull-up current path can be blocked during the data transmission operation. Therefore, during the data transmission operation, the pull-up current path of the node QM can be weakened, so the first trip voltage of the master latch component 535 can be relatively reduced. In addition, in the inverter IV34, the pull-up current path can operate normally during the data sensing operation and can be strengthened compared to the data transmission operation, so the second trip voltage of the master latch component 535 can be relatively high.

[0224] NMOS transistor N92 and NMOS transistor N93 may be coupled in series between the sensing node SO and the ground power source VSS, wherein NMOS transistor N92 is turned on in response to a transmission signal TRANM and NMOS transistor N93 is turned on or off according to a potential level of a node QM.

[0225] NMOS transistor N94 and NMOS transistor N95 may be connected in parallel between node QM and ND34, wherein NMOS transistor N94 is turned on or off in response to a first reset signal MRST1, and NMOS transistor N95 is turned on or off in response to a second reset signal MRST2. NMOS transistor N96 may be connected between node QM_N and node ND34, and then node QM_N may be electrically connected to node ND34 in response to a set signal MSET. NMOS transistor N94 may be designed to have a size larger than that of NMOS transistor N96. That is, NMOS transistor N94 may be designed to have an on-resistance smaller than that of NMOS transistor N96.

[0226] NMOS transistor N98 and NMOS transistor N99 may be connected in series between node ND34 and ground power supply VSS. NMOS transistor N98 may be turned on or off according to the potential of sensing node SO, and NMOS transistor N99 may be turned on or off in response to enable signal EN. Enable signal EN of a logic high level may be applied during data transmission operation. NMOS transistor N97 may be connected between node ND34 and ground power supply VSS, and may be turned on or off according to the potential of sensing node SO. That is, NMOS transistor N98 and NMOS transistor N99 connected in series may have a structure connected in parallel with NMOS transistor N97.

[0227] In the above-mentioned master latch component 535, the pull-down current path of the node QM during the data transmission operation can be strengthened through the NMOS transistors N94, N95, N97, N98 and N99, so the first trip voltage of the master latch component 535 can be set to a voltage lower than the second trip voltage during the data sensing operation.

[0228] Since the structure of cache latch component 132A is similar to that of reference Figure 7 The cache latch components described are the same, so their detailed description is omitted here.

[0229] The master latch component 535 in the embodiment of the present disclosure may include two or more NMOS transistors N94 and N95 connected in parallel between the node QM and the node ND34, and may include two or more NMOS transistors N97 and N98 connected in parallel between the node ND34 and the ground power supply VSS. During the data transmission operation, the NMOS transistors N94 and N95 may be turned on, so the pull-down current path of the node QM may be relatively strengthened. In addition, the two or more NMOS transistors N97 and N98 may be operated according to the potential of the sensing node SO, and the pull-down current path of the node QM and the node ND34 may be relatively strengthened. Therefore, the master latch component 535 may set a first trip voltage with a relatively low potential during the data transmission operation. In addition, during the data transmission operation, the inverter IV34 of the master latch component 535 may block the pull-up current path of the node QM, and then a trip voltage with a relatively low potential may be set. That is, the master latch component 535 may set a first trip voltage during a data transmission operation and set a second trip voltage during a data sensing operation, wherein the first trip voltage may be lower than the second trip voltage. Therefore, the master latch component 535 may perform a data latch operation using a relatively low first trip voltage during a data transmission operation, and may perform a data latch operation using a relatively high second trip voltage during a data sensing operation.

[0230] Fig.16 is a diagram showing an embodiment of a memory system.

[0231] Reference Fig.16 , the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control a data access operation (e.g., a program operation, an erase operation, or a read operation) of the memory device 1100 under the control of the processor 3100.

[0232] The data programmed to the memory device 1100 may be output via the display 3200 under the control of the memory controller 1200 .

[0233] The radio transceiver 3300 may exchange radio signals through the antenna ANT. For example, the radio transceiver 3300 may convert the radio signal received through the antenna ANT into a signal that may be processed by the processor 3100. Therefore, the processor 3100 may process the signal output from the radio transceiver 3300, and may send the processed signal to the storage controller 1200 or the display 3200. The storage controller 1200 may program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 may convert the signal output from the processor 3100 into a radio signal, and output the radio signal to an external device through the antenna ANT. The input device 3400 may be used to input a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 may be implemented as a pointing device, a keypad, or a keyboard such as a touch pad or a computer mouse. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output via the display 3200 .

[0234] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 or as a chip provided separately from the processor 3100. In addition, the memory controller 1200 may be configured to control the operation of the memory device 1100 by, for example, Figure 1 The controller 1200 shown is implemented.

[0235] Fig.17 is a diagram showing an embodiment of a memory system.

[0236] Reference Fig.17 , the memory system 40000 may be specifically implemented in a personal computer, a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0237] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0238] The processor 4100 may output data stored in the memory device 1100 via the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0239] The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or as a chip provided separately from the processor 4100. In addition, the memory controller 1200 may be configured to control the operation of the memory device 1100 by, for example, Figure 1 The controller 1200 shown is implemented.

[0240] Fig.18 is a diagram showing an embodiment of a memory system.

[0241] Reference Fig.18 , the memory system 50000 may be implemented as an image processing device, for example, a digital camera, a mobile phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

[0242] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0243] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal, and the converted digital signal may be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the digital signal may be output via the display 5300, or may be stored in the memory device 1100 through the memory controller 1200. In addition, the data stored in the memory device 1100 may be output via the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0244] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100 or as a chip provided separately from the processor 5100. In addition, the memory controller 1200 may be implemented as a part of the processor 5100 or as a chip provided separately from the processor 5100. Figure 1 The controller 1200 shown is implemented.

[0245] Fig.19 is a diagram showing an embodiment of a memory system.

[0246] Reference Fig.19 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0247] The storage controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface. Figure 1 The controller 1200 shown is implemented.

[0248] In addition, the card interface 7100 may interface data exchange between the host 60000 and the storage controller 1200 according to the protocol of the host 60000. In an embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC) USB protocol. Here, the card interface 7100 may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method executed by the hardware.

[0249] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the storage controller 1200 under the control of the microprocessor 6100.

[0250] According to the present disclosure, a trip voltage of a latch component in a data transmission operation and a trip voltage of a latch component in a data sensing operation may be optimized and set, and thus performance of a data transmission operation and a data sensing operation of a page buffer may be improved.

[0251] Although various embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible without departing from the scope and spirit of the invention. The present invention encompasses all such variations that fall within the scope of the appended claims.

[0252] CROSS-REFERENCE TO RELATED APPLICATIONS

[0253] This application claims priority to Korean Patent Application No. 10-2020-0077974, filed on Jun. 25, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A page buffer, comprising: a sensing node whose potential is controlled based on an amount of current flowing through the bit line during a data sensing operation and is controlled based on a potential of a page buffer common node during a data transmission operation; as well as a master latch component configured to latch data based on a potential of the sensing node, The master latch component latches the data according to a first trip voltage and a potential of the sensing node during the data transmission operation, and latches the data according to a second trip voltage and a potential of the sensing node during the data sensing operation, wherein the first trip voltage and the second trip voltage are different.

2. The page buffer according to claim 1, wherein: The first trip voltage is lower than the second trip voltage.

3. The page buffer according to claim 1, wherein: The master latch assembly includes a latch including a first node and a second node, and The first node is configured such that a resistance of a first pull-down current path during the data transmission operation is smaller than a resistance of a second pull-down current path during the data sensing operation.

4. The page buffer according to claim 3, wherein: The master latch assembly also includes: a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions; two or more first transistors coupled in parallel between the first node and a third node; and A second transistor is coupled between the third node and a ground power source and is configured to operate according to a potential of the sensing node.

5. The page buffer according to claim 4, wherein: During the data transmission operation, the two or more first transistors are turned on together in response to a control signal to form the first pull-down current path between the first node and the third node.

6. The page buffer according to claim 4, wherein: During the data sensing operation, one of the two or more first transistors is turned on in response to a control signal to form the second pull-down current path between the first node and the third node.

7. The page buffer according to claim 4, wherein: The master latch component further includes a third transistor coupled between the second node and the third node, and An on-resistance of at least one of the two or more first transistors is smaller than an on-resistance of the third transistor.

8. The page buffer according to claim 3, wherein: The master latch assembly also includes: a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions; a first transistor coupled between the first node and a third node and configured to be turned on during the data transmission operation and the data sensing operation; a second transistor and a third transistor connected in series between the third node and a ground power source; and A fourth transistor is coupled between the third node and the ground power supply.

9. The page buffer according to claim 8, wherein: The second transistor and the fourth transistor operate according to a potential of the sensing node.

10. The page buffer according to claim 8, wherein: The third transistor operates in response to an enable signal, and The enable signal is enabled during the data transmission operation and is disabled during the data sensing operation.

11. The page buffer according to claim 8, wherein: The master latch assembly is configured such that: During the data transmission operation, the first pull-down current path is formed by the second transistor, the third transistor, and the fourth transistor, and During the data sensing operation, the second pull-down current path is formed through the fourth transistor.

12. The page buffer according to claim 3, wherein: The latch includes a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions, The first inverter controls the potential level of the first node based on the potential level of the second node, and During the data transmission operation, the first inverter blocks a pull-up path of the first node.

13. A page buffer, the page buffer comprising: a sensing node whose potential is controlled based on an amount of current flowing through the bit line during a data sensing operation and is controlled based on a potential of a page buffer common node during a data transmission operation; as well as a master latch component configured to latch data based on a potential of the sensing node, Wherein, the master latch component is further configured as: During the data transmission operation, a first trip voltage is set by relatively strengthening the pull-down current path to latch the data according to the set first trip voltage and the potential of the sensing node, and During the data sensing operation, a second trip voltage higher than the first trip voltage is set by relatively weakening the pull-down current path to latch the data according to the set second trip voltage and the potential of the sensing node.

14. A semiconductor memory device, the semiconductor memory device comprising: a first precharger coupled to the page buffer common node and configured to precharge the page buffer common node to a first potential during a data transfer operation; a cache latch component coupled to the page buffer common node and configured to maintain or discharge the potential of the page buffer common node based on data stored in the cache latch component in the data transfer operation; as well as a page buffer coupled to the page buffer common node, Wherein, the page buffer comprises: a sensing node whose potential is controlled based on the potential of the page buffer common node during the data transmission operation; and a master latch component configured to latch data based on a potential of the sensing node, and The master latch component is further configured to set a first trip voltage during the data transmission operation to latch the data according to the set first trip voltage and the potential of the sensing node.

15. The semiconductor memory device according to claim 14, wherein: The page buffer further includes: A second precharger is configured to precharge the sensing node to a second potential higher than the first potential before performing the data transmission operation.

16. The semiconductor memory device according to claim 14, wherein: The potential of the sense node is further controlled based on the amount of current flowing through the bit line during a data sensing operation.

17. The semiconductor memory device according to claim 16, wherein: During the data sensing operation, the master latch component latches the data according to a second trip voltage and a potential of the sensing node, the first trip voltage and the second trip voltage being different.

18. The semiconductor memory device according to claim 17, wherein: The first trip voltage is lower than the second trip voltage.

19. The semiconductor memory device according to claim 16, wherein: The master latch assembly includes a latch including a first node and a second node, and The first node is configured such that a resistance of a first pull-down current path during the data transmission operation is smaller than a resistance of a second pull-down current path during the data sensing operation.

20. The semiconductor memory device according to claim 19, wherein The master latch assembly also includes: a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions; two or more first transistors coupled in parallel between the first node and a third node; and A second transistor is coupled between the third node and a ground power source and is configured to operate according to a potential of the sensing node.

21. The semiconductor memory device according to claim 20, wherein: During the data transmission operation, the two or more first transistors are turned on together in response to a control signal to form the first pull-down current path between the first node and the third node.

22. The semiconductor memory device according to claim 20, wherein: During the data sensing operation, one of the two or more first transistors is turned on in response to a control signal to form the second pull-down current path between the first node and the third node.

23. The semiconductor memory device according to claim 20, wherein: The master latch component further includes a third transistor coupled between the second node and the third node, and An on-resistance of at least one of the two or more first transistors is smaller than an on-resistance of the third transistor.

24. The semiconductor memory device according to claim 19, wherein: The master latch assembly also includes: a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions; a first transistor coupled between the first node and a third node and configured to be turned on during the data transmission operation and the data sensing operation; a second transistor and a third transistor connected in series between the third node and a ground power source; and A fourth transistor is coupled between the third node and the ground power supply.

25. The semiconductor memory device according to claim 24, wherein: The second transistor and the fourth transistor operate according to a potential of the sensing node.

26. The semiconductor memory device according to claim 24, wherein: The third transistor operates in response to an enable signal, and The enable signal is enabled during the data transmission operation and is disabled during the data sensing operation.

27. The semiconductor memory device according to claim 24, wherein: The master latch assembly is configured such that: During the data transmission operation, the first pull-down current path is formed by the second transistor, the third transistor, and the fourth transistor, and During the data sensing operation, the second pull-down current path is formed through the fourth transistor.

28. The semiconductor memory device according to claim 19, wherein: The latch includes a first inverter and a second inverter coupled in parallel between the first node and the second node in opposite directions, The first inverter controls the potential level of the first node based on the potential level of the second node, and During the data transmission operation, the first inverter blocks a pull-up path of the first node.

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