A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

The application discloses a semiconductor device and a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductor manufacturing. The semiconductor device is used for increasing the contact area between a storage contact and a corresponding active region and reducing the contact resistance between the storage contact and the corresponding active region. The semiconductor device comprises a substrate, a bit line structure, a storage contact and an isolation portion. The substrate has an active region. The bit line structure is formed on the active region. The storage contact and the isolation portion are formed between two adjacent bit line structures. The isolation portion is used for isolating the two adjacent storage contacts. Each active region has an overlapping region which overlaps with the corresponding storage contact. The contact area between each storage contact and the corresponding active region is greater than a preset threshold. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the application is applied to the electronic device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and specifically relates to a semiconductor device, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] The contact structure is a structure that can interconnect the active region in the semiconductor device and the metal lead outside the dielectric layer. The electrical signal in the active region or the electrical signal in the metal lead can be transmitted through the contact structure, so as to realize the corresponding operation of the semiconductor device. As can be seen, the quality of the contact structure directly affects the interconnection quality of the active region in the semiconductor device and the metal lead.

[0003] However, in the existing semiconductor device, the contact area between the storage contact part and the corresponding active region is small, so that the contact resistance between the storage contact part and the active region is large, thereby the performance of the semiconductor device is poor. SUMMARY

[0004] The present application aims to provide a semiconductor device, a manufacturing method thereof and an electronic device, so as to increase the contact area between the storage contact part and the corresponding active region, reduce the contact resistance between the storage contact part and the corresponding active region, and thereby improve the performance of the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, the present application provides a semiconductor device. The semiconductor device comprises:

[0006] a substrate having an active region;

[0007] a bit line structure formed on the active region;

[0008] a storage contact part and an isolation part formed between two adjacent bit line structures, the isolation part is used to isolate the two adjacent storage contact parts, each active region has an overlapping region overlapping with the corresponding storage contact part, and the contact area between each storage contact part and the corresponding active region is greater than a preset threshold.

[0009] Compared with the prior art, in the semiconductor device provided by the present application, each active region of the substrate has an overlapping region overlapping with the corresponding storage contact part, and the contact area between each storage contact part and the corresponding active region is greater than a preset threshold. In other words, the storage contact part is not only in contact with the end of the corresponding active region, thereby increasing the contact area between the storage contact part and the corresponding active region. Since the contact resistance is inversely proportional to the contact area, increasing the contact area can reduce the contact resistance. At the same time, after increasing the contact area between the storage contact part and the corresponding active region, the short circuit phenomenon existing between the adjacent contact holes in the prior art is not caused, thereby improving the conductivity of the storage contact part and the performance of the semiconductor device.

[0010] The application further provides a semiconductor device manufacturing method, comprising:

[0011] providing a substrate with active regions;

[0012] forming bit line structures on the active regions;

[0013] and forming storage contacts and isolation portions between two adjacent bit line structures, the isolation portions are used to isolate the two adjacent storage contacts, each active region has an overlapping region with a corresponding storage contact, and the contact area between each storage contact and the overlapping region of the corresponding active region is greater than a preset threshold.

[0014] Compared with the prior art, the semiconductor device manufacturing method provided by the application has the same beneficial effects as the semiconductor device provided by the above technical solution, which will not be repeated here.

[0015] The application further provides an electronic device comprising the semiconductor device provided by the above technical solution.

[0016] Compared with the prior art, the electronic device provided by the application has the same beneficial effects as the semiconductor device provided by the above technical solution, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are included to provide a further understanding of the application, form a part of the application and, along with the description, serve to explain the application. The illustrative embodiments of the application and their description serve to explain the application. They do not, however, limit the application, which is defined only by the appended claims. In the drawings:

[0018] Figure 1 is a schematic view of the storage contacts and active regions electrically connected in the prior art from the top;

[0019] Figure 2 is a schematic view of the semiconductor device structure from the top in the embodiment of the application;

[0020] Figure 3 is a schematic view of the structure after forming the bit line contacts in the embodiment of the application;

[0021] Figure 4 is a schematic view of one structure after forming the trenches in the embodiment of the application;

[0022] Figure 5 is a schematic view of another structure after forming the trenches in the embodiment of the application;

[0023] Figure 6 is a schematic view of the structure in the boxed area in the structure shown in the figure; Figure 5 is an enlarged schematic view of the structure in the boxed area in the structure shown in the figure;

[0024] Figure 7Fig. 1 is a top view of a structure formed in an embodiment of the present application to form a storage contact and a corresponding active region in electrical connection;

[0025] Figure 8 Fig. 2 is a structure schematic diagram after forming a conductor material in an embodiment of the present application;

[0026] Figure 9 Fig. 3 is a structure schematic diagram after planarizing the conductor material in an embodiment of the present application;

[0027] Figure 10 Fig. 4 is a top view of a structure shown in Fig. 3; Figure 9 Fig. 5 is a top view of a structure shown in Fig. 4;

[0028] Figure 11 Fig. 6 is a top view of a structure formed in an embodiment of the present application after forming a storage contact;

[0029] Figure 12 Fig. 7 is a top view of a structure formed in an embodiment of the present application after forming an isolation portion;

[0030] Figure 13 Fig. 8 is a top view of a structure formed in an embodiment of the present application to form a storage contact and a corresponding active region in electrical connection;

[0031] Figure 14 Fig. 9 is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present application.

[0032] Reference Signs:

[0033] 1 is a substrate, 2 is an active region, 3 is an isolation region, 4 is a dielectric layer, 5 is a trench, 6 is an overlapping region, 7 is a storage contact, 8 is an isolation portion, 9 is a horizontal overlapping portion, 10 is a vertical overlapping portion, 11 is a transition overlapping portion, 12 is an arc-shaped projection portion, 13 is a polygonal projection portion, 14 is a conductor material, 15 is a bit line structure, 16 is a bit line, and 17 is a bit line side wall. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0035] In the drawings, various structure schematic diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale in which certain details are exaggerated for the purpose of clarity and may omit certain details. The shapes of various regions, layers, and the relative size and positional relationship therebetween shown in the drawings are merely exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0036] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0038] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0039] like Figure 1 As shown, after the transistor, the dielectric layer covering the transistor, and the bit line structure in a semiconductor device are fabricated, trenches are typically formed in the dielectric layer between adjacent bit line structures. The active region of the corresponding transistor overlaps with the trench. Storage contacts are formed within the trench to contact the active region of the corresponding transistor, facilitating the transmission of electrical signals.

[0040] However, existing memory contacts are located only at one end of the corresponding active region. In other words, the memory contact only contacts the overlapping area of ​​the active region exposed within the trench, resulting in a small contact area between the memory contact and the corresponding active region. Furthermore, when the contact area between the memory contact and the active region is small, since the contact area is inversely proportional to the contact resistance, the contact resistance between the memory contact and the active region is large, leading to poor conductivity of the memory contact and thus reducing the performance of the semiconductor device.

[0041] Meanwhile, in the process of making the storage contact, the prior art generally uses the traditional damascene process to make the storage contact. Specifically, at least one trench is formed in the dielectric layer, and an oxide insulating material is deposited in each trench. Then, the oxide insulating material is etched according to the position of the overlap region of the active region and the corresponding trench to form a contact hole. The contact hole is filled with a contact material to form a storage contact. After the storage contact is formed, the oxide insulating material between adjacent storage contacts is replaced with a SiN or other material isolation portion so as not to affect subsequent processes. As can be seen, the prior art method of making the storage contact requires three formation processes and two etching processes to complete the making of the storage contact and the isolation portion, which is relatively complicated. In addition, if the length of the contact hole formed in the oxide insulating material is simply increased to increase the contact area between the storage contact and the active region, a short circuit phenomenon will occur between adjacent contact holes, thereby affecting the conductivity of the storage contact.

[0042] To solve the technical problem that the contact area between the storage contact and the corresponding active region is small, resulting in poor performance of the semiconductor device, embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device. In the semiconductor device provided by the embodiments of the present application, the contact area between the overlap region of the storage contact and the corresponding active region is greater than a preset threshold value, which increases the contact area between the storage contact and the active region, reduces the contact resistance between the storage contact and the active region, and thus improves the performance of the semiconductor device.

[0043] To solve the above problems, embodiments of the present application provide a semiconductor device which can be applied to DRAM (Dynamic Random Access Memory) or FLASH (Flash Memory) electronic devices. As shown in FIGS. 1, 2 and 3, the semiconductor device includes a substrate 1, a bit line structure 15, a storage contact 7 and an isolation portion 8. Figure 2 and Figure 9 As shown in FIGS. 1, 2 and 3, the semiconductor device includes a substrate 1, a bit line structure 15, a storage contact 7 and an isolation portion 8.

[0044] The substrate 1 has an active region 2. It should be understood that a source electrode and a drain electrode are formed on the active region 2. The number and arrangement of the active region 2 can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided by the embodiments of the present application.

[0045] In some cases, the substrate 1 also has an isolation region 3 for isolating two adjacent active regions 2. For the isolation region 3, the material contained in the isolation region 3 can be an insulating material such as silicon oxide or silicon nitride.

[0046] In some cases, the substrate 1 further has a dielectric layer 4 covering the surface of the active regions 2 and the isolation regions 3. As to whether the dielectric layer 4 is a single layer or a multi-layer, the specific type of the material contained therein can be selected as desired, which will not be described herein.

[0047] The bit line structure 15 is formed on the active region 2. It should be understood that the bit line structure 15 can include a bit line 16 and a bit line side wall 17 surrounding the sidewall of the bit line structure 15. The bit line 16 is electrically connected with the source (or drain) of the corresponding active region 2. The material contained in the bit line 16 can be a conductive material such as tungsten (W), aluminum (Al), copper (Co), nickel (Ni), or cobalt (Co). The material contained in the bit line side wall 17 is an insulating material, and common insulating materials are SiCN, SiOCN, or SiN, etc.

[0048] In some cases, the bit line structure 15 further includes a bit line contact DCC. The bit line contact DCC penetrates the dielectric layer 4, and the bit line 16 is electrically connected with the source or drain of the corresponding active region 2 through the bit line contact DCC. As to the material contained in the bit line contact DCC, it can be a conductive material such as doped polysilicon or boron-doped silicon germanium, etc.

[0049] The storage contact 7 and the isolation 8 are formed between adjacent bit line structures 15. The isolation 8 is used to isolate two adjacent storage contacts 7. Each active region 2 has an overlapping region 6 overlapping with the corresponding storage contact 7, and the contact area between each storage contact 7 and the corresponding overlapping region 6 of the active region 2 is greater than a preset threshold. It should be understood that when the bottom of a storage contact 7 is in contact with the overlapping region 6 of an active region 2, the storage contact 7 corresponds to the active region 2. As to the material contained in the storage contact 7, it can be a conductive material such as doped polysilicon or boron-doped silicon germanium, etc. As to the material contained in the isolation 8, it can be an insulating material such as SiBCN, SiCN, SiOCN, or SiN, etc. In some cases, the lower bottom surface of the isolation 8 is in the same plane as the lower bottom surface of the storage contact 7, that is, the penetration depth of the isolation 8 and the storage contact 7 in the substrate 1 is the same.

[0050] It should be noted that, as described in the foregoing prior art, the storage contact 7 is in contact with the end of the corresponding active region 2. The embodiment of the present application defines the value of the contact area between the storage contact 7 and the corresponding active region 2 in the prior art as a preset threshold. It can be envisaged that the range of the preset threshold will change with the size of the semiconductor device, and the specific range of the preset threshold can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided by the embodiment of the present application. For example, when the size of the semiconductor device is 80 nm, the preset threshold can be 500 nm 2 .

[0051] In practical applications, as shown in Figure 2 and Figure 9 When the semiconductor device is applied to a DRAM, the surface of the dielectric layer 4 formed on the active region 2 is the surface of the substrate 1. The dielectric layer 4 can include an insulating layer and a buffer layer successively covering the active region 2 and the isolation region 3. The materials contained in the insulating layer and the buffer layer can all be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The bit line structure 15 is formed on the substrate 1, the bit line contact portion DCC in the bit line structure 15 penetrates the dielectric layer 4, and the bit line 16 is electrically connected to the source (or drain) of the corresponding active region 2 through the bit line contact portion DCC. The storage contact portion 7 and the isolation portion 8 are formed between adjacent bit line structures 15. Each storage contact portion 7 penetrates the dielectric layer 4 and contacts the drain (or source) of the corresponding active region 2, realizing the electrical connection between the storage contact portion 7 and the corresponding active region 2. Moreover, the contact area between the storage contact portion 7 and the overlapping region 6 of the corresponding active region 2 is greater than a preset threshold, increasing the contact area between the storage contact portion 7 and the corresponding active region 2.

[0052] In the semiconductor device provided by the application, each active region 2 of the substrate 1 overlaps with the corresponding storage contact portion 7, and the contact area between each storage contact portion 7 and the overlapping region 6 of the corresponding active region 2 is greater than a preset threshold. In other words, the storage contact portion 7 is not only in contact with the end of the corresponding active region 2, but also increases the contact area between the storage contact portion 7 and the corresponding active region 2. Since the contact resistance is inversely proportional to the contact area, increasing the contact area can reduce the contact resistance. At the same time, after increasing the contact area between the storage contact portion 7 and the corresponding active region 2, the short circuit phenomenon existing between the adjacent contact holes in the prior art does not occur, thereby improving the conductivity of the storage contact portion 7 and enhancing the performance of the semiconductor device.

[0053] As a possible implementation manner, when the substrate 1 further has the isolation region 3, each isolation portion 8 is located on the isolation region 3. It should be understood that when the substrate 1 has the active region 2 and the isolation region 3 for defining each active region 2, the substrate 1 between adjacent bit line structures 15 is etched, and then the overlapping region 6 of the active region 2 is exposed, and the isolation region 3 between the active regions 2 is exposed. Then, the storage contact portion 7 and the isolation portion 8 between the adjacent two storage contact portions 7 are formed between the adjacent bit line structures 15. Moreover, each isolation portion 8 is located on the isolation region 3, that is, each storage contact portion 7 covers the part of the corresponding active region 2 exposed in the trench 5, further increasing the contact area between the storage contact portion 7 and the corresponding active region 2, thereby further improving the conductivity of the storage contact portion 7.

[0054] In some embodiments, as shown in Figures 4 to 6As shown, the description of the overlapping region 6 varies depending on the depth to which the storage contact portion 7 extends into the substrate 1. Examples are described below.

[0055] The first scenario: (e.g.) Figure 4 As shown, the storage contact 7 is formed only within the dielectric layer 4 of the substrate 1. In this case, the storage contact 7 extends a small depth into the substrate 1, and the bottom of the storage contact 7 just contacts the top of the active region 2. In this case, each of the aforementioned overlapping regions 6 includes an overlapping portion. This overlapping portion is the surface of the active region 2 facing away from the substrate 1, and the extending direction of this overlapping portion is parallel to the plane containing the substrate surface.

[0056] The second scenario: Figure 5 and Figure 6 As shown, when the storage contact 7 is formed both on the dielectric layer 4 of the substrate 1 and extends into a portion of the active region 2, the storage contact 7 penetrates a relatively large depth into the substrate 1, and the bottom of the storage contact 7 contacts multiple surface portions of the active region 2 after processing. In this case, if the overlapping region 6 can be divided in a direction from top to bottom of the substrate 1, then the overlapping region 6 includes multiple overlapping portions. These overlapping portions are connected together.

[0057] Because the storage contact 7 extends to different depths within the active region 2, the original single overlapping portion becomes multiple overlapping portions. This results in the overlapping region 6 having a larger area in the second case than in the first case. In other words, the contact area between the storage contact 7 and the active region 2 in the second case is larger than that in the first case, thereby further reducing the contact resistance between the storage contact 7 and the active region 2, and ultimately improving the performance of the semiconductor device.

[0058] For example, such as Figure 5 and Figure 6 As shown, when the overlapping region 6 includes three overlapping portions, these three overlapping portions are a horizontal overlapping portion 9, a vertical overlapping portion 10, and a transitional overlapping portion 11 located between the horizontal overlapping portion 9 and the vertical overlapping portion 10. It should be understood that the horizontal overlapping portion 9 refers to an overlapping portion whose extending direction is parallel to the plane containing the surface of the substrate 1. The vertical overlapping portion 10 refers to an overlapping portion whose extending direction is parallel to the thickness direction of the substrate 1. The transitional overlapping portion 11 connects the horizontal overlapping portion 9 and the vertical overlapping portion 10. The transitional overlapping portion 11 can be a planar overlapping portion or a curved overlapping portion. When the transitional overlapping portion 11 is a planar overlapping portion, the extending direction of the transitional overlapping portion 11 has a certain angle (greater than 0 and less than 90°) with the plane containing the surface of the substrate 1. When the transitional overlapping portion 11 is a curved overlapping portion, the curved overlapping portion can be an arc-shaped overlapping portion (such as a quarter-circle arc).

[0059] In addition, when the transition overlap portion 11 between the horizontal overlap portion 9 and the vertical overlap portion 10 is a curved overlap portion, and when the interval of the horizontal overlap portion 9 and the vertical overlap portion 10 in the horizontal direction is constant, the curved overlap portion has a larger effective surface area than a planar overlap portion with the same interval, and the area of the overlap region 6 can be further increased to better improve the performance of the semiconductor device.

[0060] As shown in Figure 2 and Figure 7 If the projection of the overlap region 6 on the extension direction of the surface of the substrate 1 is divided, the overlap region 6 includes an arc-shaped projection portion 12 and a polygonal projection portion 13. The polygonal projection portion 13 is a relatively broad concept, and the shape outline thereof has at least three sides. It should be understood that the shape of the orthographic projection of the overlap region 6 on the surface of the substrate 1 is affected by the shape of the bit line structure 15, the interval between adjacent bit line structures 15, and the shape of the active region 2. When the shape of the active region 2 in the extension direction of the surface of the substrate 1 is a strip shape, the overlap region 6 includes the arc-shaped projection portion 12 at the end of the strip-shaped active region 2, and the polygonal projection portion 13 formed by the tangency of the active region 2 and the edge of the bit line structure 15. The storage contact 7 covers the arc-shaped projection portion and the polygonal projection portion 13 of the corresponding overlap region 6. In other words, the storage contact 7 not only covers the end of the strip-shaped active region 2, but also covers the polygonal projection portion 13 exposed by the etching trench 5, thereby increasing the contact area of the storage contact 7 and the corresponding active region 2.

[0061] The embodiment of the present application also provides a manufacturing method of a semiconductor device, as shown in Figure 14 The manufacturing method of the semiconductor device comprises the following steps.

[0062] Step S101: providing a substrate 1 with an active region 2. The structure and number of the active region 2 can be referred to the foregoing, and will not be described here. In some cases, the above-mentioned substrate 1 also has an isolation region 3 for isolating two adjacent active regions 2. The material contained in the isolation region 3 can be referred to the foregoing.

[0063] Step S102: forming a bit line structure 15 on the active region 2. In some cases, the above-mentioned bit line structure 15 includes a bit line 16 and a bit line side wall 17. The bit line 16 is electrically connected to the source (or drain) of the corresponding active region 2. The positional relationship and the material contained in the bit line 16 and the bit line side wall 17 can be referred to the foregoing, and will not be described here.

[0064] Specifically, the bit line 16 is formed on the active region 2, and the bit line sidewall 17 is formed around the sidewall of the bit line. Then, the width of the bit line sidewall 17 is adjusted to adjust the area of the overlap region 6 of the active region 2. It should be understood that the bit line structure 15 has the bit line 16 and the bit line sidewall 17 formed on the active region 2. The greater the width of the bit line sidewall 17, the greater the area of the active region 2 covered by the bit line structure 15. By adjusting the width of the bit line structure 15, the area of the active region 2 exposed outside the bit line structure 15 can be adjusted, and the aspect ratio of the storage contact 7 formed subsequently can be adjusted.

[0065] Step S103: Forming the storage contact 7 and the isolation 8 between the adjacent two bit line structures 15, the isolation 8 is used to isolate the adjacent two storage contacts 7, each active region 2 has an overlap region 6 overlapping with the corresponding storage contact 7, and the contact area between each storage contact 7 and the overlap region 6 of the corresponding active region 2 is greater than a preset threshold.

[0066] Specifically, forming the storage contact 7 and the isolation 8 between the adjacent two bit line structures 15 includes:

[0067] Step S103.1: Etching the substrate 1 downward to expose the active region 2 between the adjacent bit line structures 15 with the bit line structure 15 as a mask. It should be understood that when the bit line structure 15 includes the bit line 16 and the bit line sidewall 17, the dielectric layer 4 of the substrate 1 can be etched downward by using a coverage etching method with the bit line sidewall 17 as a mask to form a groove 5 between the adjacent bit line structures 15, and the groove bottom of the groove 5 is in contact with the overlap region 6 of the corresponding active region 2.

[0068] It should be noted that, in order to further increase the contact area between the storage contact 7 and the corresponding active region 2, after the active region 2 between the adjacent bit line structures 15 is exposed, and before the next operation is performed, the dry cleaning method or the wet cleaning method can be used to continue etching downward to remove part of the active region 2 between the adjacent bit line structures 15 to adjust the area of the overlap region 6 of the active region 2. At this time, the overlap region 6 of the active region 2 includes a plurality of overlap regions distributed along the direction from the top to the bottom of the substrate 1. It should be understood that compared with one overlap region, when the overlap region 6 includes a plurality of overlap regions, the area of the overlap region 6 in the vertical direction is increased, thereby increasing the contact area between the storage contact 7 and the corresponding active region 2, and reducing the contact resistance between the storage contact 7 and the active region 2.

[0069] For example, when the overlapping region 6 includes three overlapping portions, these three overlapping portions are a horizontal overlapping portion 9, a vertical overlapping portion 10, and a transitional overlapping portion 11 located between the horizontal overlapping portion 9 and the vertical overlapping portion 10. Specifically, the positional relationship of the horizontal overlapping portion 9, the vertical overlapping portion 10, and the transitional overlapping portion 11, as well as their specific shapes, can be referred to the preceding text and will not be repeated here.

[0070] like Figure 2 and Figure 7 As shown, if the projection of the overlapping region 6 onto the surface of the substrate 1 is divided, the overlapping region 6 includes an arc-shaped projection portion 12 and a polygonal projection portion 13. The polygonal projection portion 13 is a broad concept, and its shape outline has at least three sides. It should be understood that the shape of the orthographic projection of the overlapping region 6 onto the surface of the substrate 1 is influenced by the shape of the bit line structure 15, the spacing between adjacent bit line structures 15, and the shape of the active region 2. When the active region 2 is strip-shaped along its extension direction on the surface of the substrate 1, the overlapping region 6 includes an arc-shaped projection portion 12 located at the end of the strip-shaped active region 2, and a polygonal projection portion 13 formed by the active region 2 being tangent to the edge of the bit line structure 15. The storage contact portion 7 covers the arc-shaped projection portion and the polygonal projection portion 13 of the corresponding overlapping region 6. In other words, the storage contact portion 7 not only covers the end of the strip-shaped active region 2, but also covers the polygonal projection portion 13 exposed by the etching trench 5, increasing the contact area between the storage contact portion 7 and the corresponding active region 2.

[0071] Step S103.2: Form conductor material 14 between two adjacent bit line structures 15. In some alternative embodiments, when the conductor material 14 is doped polysilicon, it can be formed on the active region 2 located between adjacent bit line structures 15 by epitaxial growth.

[0072] In some alternative methods, when the conductor material 14 is doped polysilicon and the conductor material 14 is formed between two adjacent bit line structures 15 by epitaxial growth, the surface of the overlapping region 6 can be pretreated by wet cleaning or dry cleaning before the conductor material 14 is formed, which is more conducive to obtaining high-quality epitaxial polysilicon.

[0073] It should be noted that when the conductor material 14 is formed between the adjacent bit line structures 15, the conductive material can also be formed above the bit line structures 15. At this time, the conductor material 14 between different bit line structures 15 is connected together. To separate the conductor material 14 between different bit line structures 15, a chemical mechanical planarization process can be used to remove the part of the conductor material 14 on the surface of the bit line structure 15, so that the conductor material 14 is only formed in the trench 5 between the adjacent bit line structures 15. At the same time, after the conductor material 14 is processed by the chemical mechanical planarization process, the top of the conductor material 14 is relatively flat, which is convenient for subsequent insulation treatment of the conductor material 14, and etching from the top of the conductor material 14 downward to form a through hole with the same depth.

[0074] Step S103.3: Insulating treatment is performed on the conductor material 14 in a predetermined region to form an isolation part 8, so that the remaining conductor material 14 forms a storage contact part 7. It should be understood that after the conductor material 14 is formed between the adjacent bit line structures 15, the conductor material 14 will be in contact with the overlapping region 6 of the plurality of active regions 2. In order to form a storage contact part 7 which is only in contact with the overlapping region 6 of the corresponding active region 2, the conductor material 14 also needs to be insulated.

[0075] Specifically, the insulating treatment is performed on the conductor material 14 in a predetermined region to form an isolation part 8, so that the remaining conductor material 14 forms a storage contact part 7, including:

[0076] Step S103.3.1: The part of the conductor material 14 outside the overlapping region 6 is removed by using a plasma etching method. It should be understood that when the substrate 1 includes the active region 2 and the isolation region 3, the conductor material 14 is formed in the trench 5 between the adjacent bit line structures 15. At this time, the conductor material 14 is not only on the active region 2, but also formed on the isolation region 3. On this basis, the part of the conductor material 14 on the isolation region 3 can be removed by using a plasma etching method, so as to only retain the conductor material 14 on the overlapping region 6.

[0077] Step S103.3.1.2: The insulating material is filled between the corresponding bit line structures 15 to form an isolation part 8, so that the remaining conductor material 14 forms a storage contact part 7. For example, the insulating material can be filled between the adjacent bit line structures 15 (specifically between the adjacent structures and between the remaining adjacent conductor material 14) by using a direct deposition method or an atomic layer deposition method to form an isolation part 8. The remaining conductor material 14 after isolation corresponds to a storage contact part 7. It is conceivable that the lower bottom surface of the formed isolation part 8 is on the same plane as the lower bottom surface of the storage contact part 7.

[0078] It is worth noting that when the substrate 1 comprises the active region 2 and the isolation region 3, if each isolation part 8 is located on the active region 2, it means that each storage contact part 7 covers the part of the corresponding active region 2 exposed in the trench 5 entirely, further increasing the contact area between the storage contact part 7 and the corresponding active region 2, thereby further improving the conductive performance of the storage contact part 7.

[0079] It should be understood that the existing method for manufacturing the storage contact part 7 is to form an oxide insulating material in the trench 5. A contact hole contacting the active region 2 at the bottom of the trench 5 is etched in the oxide insulating material, the conductor material 14 is filled in the contact hole, and the storage contact part 7 is formed. In order to facilitate subsequent operations, the remaining oxide insulating material in the trench 5 also needs to be replaced by the isolation part 8 containing SiN or the like and compatible with subsequent processes.

[0080] As can be seen from the above description, the existing method for manufacturing the storage contact part 7 is relatively complicated. Especially, as the semiconductor device is miniaturized, the aspect ratio of the storage contact part 7 is getting larger and larger, and the difficulty of manufacturing the storage contact part 7 by using the existing method is increasing. However, the manufacturing method of the semiconductor device provided by the embodiment of the present application is to directly form the conductor material 14 in the trench 5. After removing the part of the conductor material 14 located on the isolation region 3, the isolation part 8 containing SiN or the like and compatible with subsequent processes is formed between the adjacent conductor materials 14 in the same trench 5. The entire process only needs to be performed once by removing the process and twice by forming the process, so that the manufacturing of the storage contact part 7 and the isolation part 8 can be completed. The contact area between the storage contact part 7 and the active region 2 is increased, and at the same time, the manufacturing process is made more simple and the manufacturing difficulty is reduced.

[0081] The embodiment of the present application also provides an electronic device comprising the semiconductor device provided by the above-described embodiments. The electronic device can be a terminal device or a communication device, but is not limited thereto. Further, the terminal device includes a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligence device, a mobile power supply, etc. The communication device includes a base station, etc., but is not limited thereto.

[0082] The electronic device provided by the embodiment of the present application has the same beneficial effects as the semiconductor device provided by the above-described embodiments, and details are not repeated here.

[0083] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0084] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a substrate with an active region; A bit line structure is formed on the active region; And a storage contact portion and an isolation portion are formed between two adjacent bit line structures, the isolation portion is used to isolate two adjacent storage contacts, each active region has an overlapping area that overlaps with the corresponding storage contact portion, and the contact area between each storage contact portion and the overlapping area of ​​the corresponding active region is greater than a preset threshold. The process of forming a storage contact and an isolation portion between two adjacent bit line structures includes: Using the bit line structure as a mask, the substrate is etched downwards to expose the active region between adjacent bit line structures; A conductor material is formed between two adjacent bitline structures; The conductor material is insulated in a predetermined area to form the isolation portion, and the remaining conductor material forms the storage contact portion.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The bottom surface of the isolation section and the bottom surface of the storage contact section are on the same plane.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After etching the substrate downwards using the bit line structure as a mask to expose the active region between adjacent bit line structures, and before forming a conductor material between two adjacent bit line structures, the method for fabricating the semiconductor device further includes: The surface of the overlapping area is pretreated by using either wet or dry cleaning methods to facilitate the formation of the conductor material between two adjacent bit line structures.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, After etching the substrate downwards using the bit line structure as a mask to expose the active region between adjacent bit line structures, and before forming a conductor material between two adjacent bit line structures, the method for fabricating the semiconductor device further includes: Remove a portion of the active region located between adjacent bit line structures to adjust the area of ​​the overlapping region of the active region.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, A wet cleaning method or a dry cleaning method is used to remove a portion of the active region located between adjacent bit line structures.

6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The overlapping area includes a horizontal overlapping portion, a vertical overlapping portion, and a transitional overlapping portion located between the horizontal overlapping portion and the vertical overlapping portion.

7. The method for fabricating a semiconductor device according to claim 2, characterized in that, The formation of the conductor material between two adjacent bitline structures includes: The conductor material is formed on the active region located between adjacent bit line structures using an epitaxial growth method.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of insulating the conductor material in a predetermined area to form the isolation portion, such that the remaining conductor material forms the storage contact portion, includes: The portion of the conductor material located outside the overlapping region is removed using plasma etching. Insulating material is filled between the corresponding bit line structures to form the isolation portion, such that the remaining conductor material forms the storage contact portion.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The bitline structure includes bitlines and bitline sidewalls surrounding the bitline sidewalls; The formation of the bit line structure on the active region includes: Bit lines and bit line sidewalls surrounding the bit line sidewalls are formed on the active region. Adjust the width of the bit line sidewall to adjust the area of ​​the overlapping region of the active region.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate also has an isolation region for isolating two adjacent active regions; each isolation portion is located on the isolation region.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, The overlapping region includes an arc-shaped projection portion and a polygonal projection portion in the direction of extension on the substrate surface.

12. A semiconductor device, characterized in that, The semiconductor device is manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 11.

13. An electronic device, characterized in that, Includes the semiconductor device as described in claim 12.

14. The electronic device according to claim 13, characterized in that, The electronic device includes terminal equipment or communication equipment.

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