A ring oscillator and a phase-locked loop

Abstract

The application discloses a ring oscillator and a phase-locked loop. The ring oscillator comprises: the output terminals of nth and mth delay units are connected to the main input terminals of (n+1)th and 1st delay units respectively; m is an odd number, the electrode polarity of the output terminal of the nth delay unit is opposite to the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is opposite to the electrode polarity of the main input terminal of the 1st delay unit, m is an even number, the electrode polarity of the output terminal of the nth delay unit is the same as the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is the same as the electrode polarity of the main input terminal of the 1st delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input terminals of the (n+1)th and 1st delay units are connected to the main input terminals of the nth and mth delay units respectively. The technical scheme of the application can realize a ring oscillator with a high oscillation frequency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a ring oscillator and a phase-locked loop BACKGROUND

[0002] Voltage controlled oscillators are widely used in communication systems such as phase-locked loop and frequency synthesizer circuits.

[0003] Common voltage controlled oscillators include LC oscillator and ring oscillator. LC oscillator uses on-chip inductance, has the advantages of accurate frequency selection and small phase noise, but has large chip area. Ring oscillator is implemented by standard CMOS process, has the advantage of small area. However, the existing ring oscillator can only realize low oscillation frequency, and cannot be widely used in high frequency field SUMMARY

[0004] The main purpose of the embodiment of the present application is to provide a ring oscillator and a phase-locked loop, aiming at realizing a ring oscillator with high oscillation frequency.

[0005] To achieve the above purpose, the embodiment of the present application provides a ring oscillator, comprising:

[0006] The m-stage delay units are connected in a first phase configuration ring connection mode and a second phase configuration ring connection mode, and m includes an integer greater than or equal to 3;

[0007] The output end of the nth-stage delay unit is connected to the main input end of the n+1th-stage delay unit, and the output end of the mth-stage delay unit is connected to the main input end of the first-stage delay unit to form the first phase configuration ring connection mode; when m is odd, the electrode polarity of the output end of the nth-stage delay unit is opposite to the electrode polarity of the main input end of the n+1th-stage delay unit, or the electrode polarity of the output end of the mth-stage delay unit is opposite to the electrode polarity of the main input end of the first-stage delay unit; when m is even, the electrode polarity of the output end of the nth-stage delay unit is the same as the electrode polarity of the main input end of the n+1th-stage delay unit, or the electrode polarity of the output end of the mth-stage delay unit is the same as the electrode polarity of the main input end of the first-stage delay unit; n includes an integer greater than or equal to 1 and less than m;

[0008] The auxiliary input end of the n+1th-stage delay unit is connected to the main input end of the nth-stage delay unit, and the auxiliary input end of the first-stage delay unit is connected to the main input end of the mth-stage delay unit to form the second phase configuration ring connection mode.

[0009] To achieve the above purpose, the embodiment of the present application further provides a phase-locked loop, comprising the ring oscillator in any of the above technical solutions.

[0010] The ring oscillator and phase-locked loop proposed in this invention include a first-phase configuration ring connection mode and a second-phase configuration ring connection mode. The phase of the second-phase configuration ring connection mode leads the phase of the first-phase configuration ring connection mode by 180° / m. Therefore, the second-phase configuration ring connection mode reduces the delay time of each delay unit, thereby increasing the oscillation frequency of the ring oscillator. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a ring oscillator in the prior art;

[0012] Figure 2 This is a schematic diagram of a ring oscillator provided in an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of another ring oscillator provided in an embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of the structure of a delay unit provided in an embodiment of the present invention. Detailed Implementation

[0015] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0016] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no inherent meaning. Therefore, "module," "part," or "unit" may be used interchangeably.

[0017] As described in the background section above, existing ring oscillators can only achieve oscillation frequencies that are too low to be widely used in the high-frequency field. Figure 1 This is a schematic diagram of a ring oscillator in the prior art. Figure 1 In a, m is an odd number. Figure 1 In b, m is an even number. For the reason why, see [link to documentation]. Figure 1The existing ring oscillator includes m-stage delay units 10 forming a first phase configuration ring connection mode Q1, where m includes an integer greater than or equal to 3. Each stage of delay unit 10 includes an input terminal A0 and an output terminal B1. The output terminal B1 of the nth stage delay unit 10 is connected to the input terminal A0 of the (n+1)th stage delay unit, and the output terminal B1 of the mth stage delay unit is connected to the input terminal A0 of the 1st stage delay unit to form the first phase configuration ring connection mode Q1. Here, if m is an odd number, the polarity of the output terminal B1 of the mth stage delay unit is opposite to the polarity of the input terminal A0 of the 1st stage delay unit; if m is an even number, the polarity of the output terminal B1 of the mth stage delay unit is the same as the polarity of the input terminal A0 of the 1st stage delay unit; and m includes an integer greater than or equal to 1 and less than m. It can be seen that the existing ring oscillator includes a phase configuration ring connection mode. In the single phase configuration ring connection mode, it is impossible to significantly increase the oscillation frequency of the entire ring oscillator simply by changing the internal circuit structure of the ring oscillator.

[0018] To address the aforementioned technical problems, embodiments of the present invention provide a ring oscillator that significantly improves the oscillation frequency of the ring oscillator.

[0019] Figure 2 This is a schematic diagram of a ring oscillator provided in an embodiment of the present invention. Figure 2 In a, m is an odd number. Figure 2 In b, m is an even number. See also Figure 2 The ring oscillator includes: m-stage delay units 10 forming a first phase configuration ring connection mode Q1 and a second phase configuration ring connection mode Q2, where m includes an integer greater than or equal to 3; the output terminal B1 of the nth stage delay unit 10 is connected to the main input terminal A1 of the (n+1)th stage delay unit 10, and the output terminal B1 of the m-th stage delay unit 10 is connected to the main input terminal A1 of the 1st stage delay unit to form the first phase configuration ring connection mode; m is an odd number, and the polarity of the output terminal B1 of the nth stage delay unit 10 is opposite to the polarity of the main input terminal A1 of the (n+1)th stage delay unit 10, or the polarity of the output terminal B1 of the m-th stage delay unit 10 is opposite to the polarity of the main input terminal A1 of the (n+1)th stage delay unit 10. The polarity of the main input terminal A1 of the first-stage delay unit is opposite, m is an even number, the polarity of the output terminal B1 of the nth-stage delay unit 10 is the same as the polarity of the main input terminal A1 of the (n+1)th-stage delay unit 10, or the polarity of the output terminal B1 of the mth-stage delay unit 10 is the same as the polarity of the main input terminal A1 of the first-stage delay unit 10, n includes an integer greater than or equal to 1 and less than m; the auxiliary input terminal A2 of the (n+1)th-stage delay unit 10 is connected to the main input terminal A1 of the nth-stage delay unit 10, and the auxiliary input terminal A2 of the first-stage delay unit is connected to the main input terminal A1 of the mth-stage delay unit to form the second phase configuration ring connection mode Q2.

[0020] In this embodiment, the value of n includes any one of 1, 2, ..., (m-1). It should be noted that... Figure 2 Example a shows a structure where m is an odd number, and the polarity of the output terminal B1 of the m-th stage delay unit 10 is opposite to the polarity of the main input terminal A1 of the first stage delay unit. Figure 2 Example b illustrates a structure where m is an even number, and the polarity of the output terminal B1 of the m-th stage delay unit 10 is the same as the polarity of the main input terminal A1 of the first stage delay unit.

[0021] For example, the delay unit 10 includes a differential delay unit. In the first phase configuration ring connection mode Q1, m is an odd number, and the polarity of the output terminal B1 of the m-th stage delay unit 10 is opposite to the polarity of the main input terminal A1 of the first stage delay unit, satisfying the oscillation condition. The specific connection method is as follows: the positive terminal B1(+) of the output terminal B1 of the m-th stage delay unit 10 is connected to the negative terminal A1(-) of the main input terminal A1 of the first stage delay unit; correspondingly, the negative terminal B1(-) of the output terminal B1 of the m-th stage delay unit 10 is connected to the positive terminal A1(+) of the main input terminal A1 of the first stage delay unit.

[0022] m is an even number. The polarity of the output terminal B1 of the m-th stage delay unit 10 is the same as that of the main input terminal A1 of the first stage delay unit, satisfying the oscillation condition. The specific connection method is as follows: the positive terminal B1(+) of the output terminal B1 of the m-th stage delay unit 10 is connected to the positive terminal A1(+) of the main input terminal A1 of the first stage delay unit; correspondingly, the negative terminal B1(-) of the output terminal B1 of the m-th stage delay unit 10 is connected to the negative terminal A1(-) of the main input terminal A1 of the first stage delay unit.

[0023] For example, Figure 1 Only one auxiliary input terminal A2 is shown in the figure. The number of auxiliary input terminals A2 is not limited in the embodiments of the present invention.

[0024] It should be noted that, Figure 1 The thick black solid line represents the first phase configuration ring connection mode Q1, and the thin black solid line represents the second phase configuration ring connection mode Q2.

[0025] Specifically, the phase of the second-phase ring connection mode Q2 is 180° / m ahead of the phase of the first-phase ring connection mode Q1. Therefore, the second-phase ring connection mode Q2 reduces the delay time of each stage delay unit 10, thereby increasing the oscillation frequency of the ring oscillator. The oscillation frequency of existing ring oscillators is less than 10 GHz, while the ring oscillator in this embodiment can increase its oscillation frequency to over 10 GHz.

[0026] The technical solution in this embodiment includes a first phase configuration ring connection mode Q1 and a second phase configuration ring connection mode Q2. The phase of the second phase configuration ring connection mode Q2 is ahead of the phase of the first phase configuration ring connection mode Q1 by 180° / m. Therefore, the second phase configuration ring connection mode Q2 reduces the delay time of each stage delay unit 10, thereby increasing the oscillation frequency of the ring oscillator.

[0027] Figure 3 This is a schematic diagram of another ring oscillator provided in an embodiment of the present invention. Optionally, see... Figure 3 m equals 3, and the phase of the second phase configuration ring connection mode Q2 is 60° ahead of the phase of the first phase configuration ring connection mode Q1.

[0028] It should be noted that, Figure 3 The example illustrates a structure where m equals 3, and the polarity of the output terminal B1 of the third-stage delay unit 10 is opposite to the polarity of the main input terminal A1 of the first-stage delay unit. Figure 3 Only one auxiliary input terminal A2 is shown in the diagram. The number of auxiliary input terminals A2 is not limited in this embodiment. Specifically, when the ring oscillator includes three stages of delay units 10, in the first phase configuration ring connection mode Q1, the output terminal B1 of the first stage delay unit 10 is connected to the main input terminal A1 of the second stage delay unit 10, the output terminal B1 of the second stage delay unit 10 is connected to the main input terminal A1 of the third stage delay unit 10, and the output terminal B1 of the third stage delay unit 10 is connected to the main input terminal A1 of the first stage delay unit 10. The positive terminal B1(+) of the output terminal B1 of the third stage delay unit 10 is connected to the negative terminal A1(-) of the main input terminal A1 of the first stage delay unit 10, satisfying the oscillation start-up condition.

[0029] In the second phase configuration ring connection mode Q2, the auxiliary input terminal A2 of the second stage is connected to the main input terminal A1 of the first stage, the auxiliary input terminal A2 of the third stage delay unit is connected to the main input terminal A1 of the second stage delay unit, and the auxiliary input terminal A2 of the first stage delay unit is connected to the main input terminal A1 of the third stage delay unit.

[0030] The phase of the ring oscillator is 180°. In the second phase configuration ring connection mode Q2, two stages of delay units 10 can realize signal transmission. In the first phase configuration ring connection mode Q1, three stages of delay units 10 are required to realize signal transmission. Therefore, the phase of the second phase configuration ring connection mode Q2 is 60° ahead of the phase of the first phase configuration ring connection mode Q1, which reduces the delay time of each stage of delay unit 10 and thus significantly increases the oscillation frequency of the ring oscillator.

[0031] It should be noted that the more stages of delay units 10 included in the ring oscillator, the lower its corresponding oscillation frequency.

[0032] The specific structure of each delay unit 10 is described below. Figure 4 This is a schematic diagram of a delay unit provided in an embodiment of the present invention. Optionally, see... Figure 4 In this delay unit, the main input terminal A1 includes a positive terminal A1(+) and a negative terminal A1(-), the auxiliary input terminal A2 includes a positive terminal A2(+) and a negative terminal A2(-), and the output terminal B1 includes a positive terminal B1(+) and a negative terminal B1(-). The delay unit 10 includes a main input circuit 101 and an auxiliary input circuit 102. The main input circuit 101 includes a first transistor M1 and a second transistor M2. The sources of the first transistor M1 and the second transistor M2 are connected to the ground terminal VSS. The drain of the first transistor M1 is connected to the positive terminal B1(+) of the output terminal B1, and the drain of the second transistor M2 is connected to the ground terminal VSS. The gate of the first transistor M1 is connected to the negative terminal B1(-) of the output terminal B1, and the gate of the second transistor M2 is connected to the negative terminal A1(-) of the main input terminal A1. The auxiliary input circuit 102 includes a third transistor M3 and a fourth transistor M4. The sources of the third transistor M3 and the fourth transistor M4 are connected to the power supply voltage VDD. The drain of the third transistor M3 is connected to the positive terminal B1(+) of the output terminal B1, and the drain of the fourth transistor M4 is connected to the negative terminal B1(-) of the output terminal B1. The gate of the third transistor M3 is connected to the positive terminal (+) of the auxiliary input terminal A2, and the gate of the fourth transistor M4 is connected to the negative terminal A2(-) of the auxiliary input terminal A2.

[0033] For example, the first transistor M1 and the second transistor M2 constitute the main input circuit 101. N-type metal-oxide-semiconductor transistors can be selected, which is beneficial for achieving a faster charge-discharge speed in the main input circuit 101, reducing the delay time of the delay unit 10, and increasing the oscillation frequency of the ring oscillator. The third transistor M3 and the fourth transistor M4 constitute the auxiliary input circuit 102. P-type metal-oxide-semiconductor transistors can be selected, as P-type transistors have better noise performance than N-type transistors, thus improving the phase noise performance of the ring oscillator. Furthermore, the transistors in both the main input circuit 101 and the auxiliary input circuit 102 are symmetrically arranged. This helps reduce circuit power consumption and ensures that the ring oscillator outputs a symmetrical waveform, suppressing the phase noise of the ring oscillator.

[0034] Specifically, compared to the delay unit in the prior art which has only one input circuit, in the delay unit provided in this embodiment, in each stage of delay unit 10, the auxiliary input circuit 102 includes a third transistor M3 and a fourth transistor M4 to help the main input circuit 101 include a first transistor M1 and a second transistor M2 to quickly realize the rapid switching of the output signal from the positive terminal A2(+) of the auxiliary input terminal A2 to the negative terminal A2(-), reducing the switching time of the output signal from the positive terminal B1(+) of the output terminal B1 to the negative terminal B1(-), that is, increasing the switching speed from the power supply voltage VDD to the ground terminal VSS, reducing the delay time of each stage of delay unit 10, and significantly improving the oscillation frequency of the ring oscillator.

[0035] To further increase the oscillation frequency of the ring oscillator, optionally, see [reference needed]. Figure 4 The delay unit 10 also includes a frequency control circuit 103, which is connected between the power supply voltage VDD and the output terminal B1.

[0036] Specifically, the frequency control circuit 103 is used to adjust the oscillation frequency of the ring oscillator. The specific structure of the frequency control circuit 103 is detailed below. Optionally, see... Figure 4 The frequency control circuit 103 includes a fifth transistor M5 and a sixth transistor M6. The sources of the fifth transistor M5 and the sixth transistor M6 are connected to the power supply voltage VDD. The drain of the fifth transistor M5 is connected to the positive terminal B1(+) of the output terminal B1. The drain of the sixth transistor M6 is connected to the negative terminal B1(-) of the output terminal B1. The gates of the fifth transistor M5 and the sixth transistor M6 are connected to the first control voltage VC1.

[0037] Specifically, by controlling the value of the first control voltage VC1, the magnitude of the bias current flowing into the positive terminal B1(+) and the negative terminal B1(-) of output terminal B1 is controlled. The larger the bias current flowing into the positive terminal B1(+) and the negative terminal B1(-) of output terminal B1, the shorter the charging time of the positive terminal B1(+) and the negative terminal B1(-) of output terminal B1, the shorter the delay time of each stage delay unit 10, and the higher the oscillation frequency of the ring oscillator. It should be noted that the transistors included in the frequency control circuit 103 operate in the transistor region. Furthermore, the transistors in the frequency control circuit 103 are symmetrically arranged, which helps reduce circuit power consumption and, on the other hand, helps the ring oscillator output a symmetrical waveform, suppressing the phase noise of the ring oscillator.

[0038] For example, the frequency control circuit 103 may include a P-type metal-oxide-semiconductor transistor, which has better noise performance than an N-type metal-oxide-semiconductor transistor, thus improving the phase noise performance of the ring oscillator.

[0039] The power supply noise of existing delay units is relatively high, resulting in significant phase noise in the ring oscillator. To address this technical problem, this embodiment proposes the following technical solution:

[0040] Optionally, see Figure 4 The delay unit 10 also includes a power supply noise reduction circuit 104, which is connected between the power supply voltage VDD and the output terminal B1.

[0041] Specifically, the power supply noise reduction circuit 104 is connected between the power supply voltage VDD and the output terminal B1, which can attenuate power supply noise and further reduce the phase noise of the ring oscillator.

[0042] The specific structure of the power supply noise reduction circuit 104 is detailed below. Optionally, see [link to relevant documentation]. Figure 4 The power supply noise reduction circuit 104 includes a seventh transistor M7 and an eighth transistor M8. The sources of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply voltage VDD. The drain of the seventh transistor M7 is connected to the positive terminal B1(+) of the output terminal B1. The drain of the eighth transistor M8 is connected to the negative terminal B1(-) of the output terminal B1. The gates of the seventh transistor M7 and the eighth transistor M8 are connected to the ground terminal VSS.

[0043] Specifically, the sources of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply voltage VDD, the drain of the seventh transistor M7 is connected to the positive terminal B1(+) of the output B1, the drain of the eighth transistor M8 is connected to the negative terminal B1(-) of the output B1, and the gates of the seventh transistor M7 and the eighth transistor M8 are connected to the ground terminal VSS. On the one hand, this can attenuate power supply noise. On the other hand, the placement of the seventh transistor M7 increases the bias current flowing into the positive terminal B1(+) of the output B1, and the placement of the eighth transistor M8 increases the bias current flowing into the negative terminal B1(-) of the output B1, thereby reducing the charging time of the positive terminal B1(+) and the negative terminal B1(-) of the output B1, reducing the delay time of the delay unit, and thus increasing the oscillation frequency of the ring oscillator.

[0044] It should be noted that the transistors included in the power supply noise reduction circuit 104 operate in the transistor region. Furthermore, the transistors in the power supply noise reduction circuit 104 are symmetrically arranged. This arrangement helps reduce circuit power consumption and also ensures that the ring oscillator outputs a symmetrical waveform, thus suppressing the phase noise of the ring oscillator.

[0045] For example, the power supply noise reduction circuit 104 may include a P-type metal-oxide-semiconductor transistor, which has better noise performance than an N-type metal-oxide-semiconductor transistor, thus improving the phase noise performance of the ring oscillator.

[0046] To further reduce the switching time between the positive terminal B1(+) and the negative terminal B1(-) of output terminal B1, and to improve the switching speed between the positive terminal B1(+) and the negative terminal B1(-) of output terminal B1, this embodiment provides the following technical solution: Optionally, see... Figure 4 The delay unit 10 also includes a positive feedback circuit 105, which is connected between the ground terminal VSS and the output terminal B1.

[0047] Specifically, the positive feedback circuit 105 is connected between the ground terminal VSS and the output terminal B1, which reduces the switching time between the positive terminal B1(+) and the negative terminal B1(-) of the output terminal B1, and increases the switching speed between the positive terminal B1(+) and the negative terminal B1(-) of the output terminal B1, thereby reducing the phase noise of the entire ring oscillator.

[0048] The specific structure of the positive feedback circuit 105 is detailed below. Optionally, see [link to relevant documentation]. Figure 4 The positive feedback circuit 105 includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the ninth transistor M9 is connected to the drain of the tenth transistor M10, the drain of the ninth transistor M9 is connected to the gate of the tenth transistor M10, the drain of the ninth transistor M9 is connected to the positive terminal B1(+) of the output terminal B1, the drain of the tenth transistor M10 is connected to the negative terminal B1(-) of the output terminal B1, the sources of the ninth transistor M9 and the tenth transistor M10 are connected to the drain of the eleventh transistor M11, the gate of the eleventh transistor M11 is connected to the second control voltage VC2, and the source of the eleventh transistor M11 is coupled to the ground terminal VSS.

[0049] Specifically, the ninth transistor M9 and the tenth transistor M10 are active devices that provide a positive feedback system through cross-coupling. This reduces the switching time between the positive terminal B1(+) and the negative terminal B1(-) of the output terminal B1, and increases the switching speed between the positive terminal B1(+) and the negative terminal B1(-) of the output terminal B1, thereby reducing the phase noise of the entire ring oscillator.

[0050] It should be noted that the function of the eleventh transistor M11 is to reduce the equivalent resistance after the cross-coupling of the ninth transistor M9 and the tenth transistor M10 by using the second control voltage VC2, thereby increasing the oscillation frequency of the delay unit.

[0051] For example, the positive feedback circuit 105 can be selected as an N-type metal-oxide-semiconductor transistor, which is beneficial to achieve a faster charge charging and discharging speed in the positive feedback circuit 105, improve the switching speed between the positive terminal B1(+) and the negative terminal B1(-) of the output terminal B1, reduce the delay time of the delay unit 10, and increase the oscillation frequency of the ring oscillator.

[0052] See Figure 4 In this embodiment, the main input circuit 101 of the ring oscillator includes a first transistor M1 and a second transistor M2. A tail current source transistor is provided between them and the ground terminal VSS. On the one hand, this reduces the increase in phase noise caused by the flicker noise of the tail current source transistor, thereby reducing the phase noise of the ring oscillator. On the other hand, it avoids the threshold voltage of the tail current source transistor from causing the signal to be unable to be output with a large swing. The technical solution in this embodiment realizes the full swing output of the signal.

[0053] This invention also provides a phase-locked loop, which includes any of the ring oscillators described in the above technical solutions.

[0054] A phase-locked loop (PLL) can track the phase and frequency of an input signal and output a phase-locked, low-jitter frequency signal. It typically consists of five modules: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The VCO includes any of the ring oscillators described in the aforementioned technical solutions. Therefore, it possesses the beneficial effects of the aforementioned ring oscillators, which will not be elaborated further here.

[0055] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0056] In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a first-level physical component may have multiple levels of functionality, or a first-level function or step may be executed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0057] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but this does not limit the scope of the invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the present invention.

Claims

1. A ring oscillator, characterized by, The delay unit comprises: a first phase configuration ring connection mode and a second phase configuration ring connection mode are formed by a group of m-stage delay units, m comprises an integer greater than or equal to 3; the output end of the nth-stage delay unit is connected to the main input end of the n+1th-stage delay unit, and the output end of the mth-stage delay unit is connected to the main input end of the 1st-stage delay unit to form the first phase configuration ring connection mode; m is an odd number, the electrode polarity of the output end of the nth-stage delay unit is opposite to the electrode polarity of the main input end of the n+1th-stage delay unit, or the electrode polarity of the output end of the mth-stage delay unit is opposite to the electrode polarity of the main input end of the 1st-stage delay unit, m is an even number, the electrode polarity of the output end of the nth-stage delay unit is the same as the electrode polarity of the main input end of the n+1th-stage delay unit, or the electrode polarity of the output end of the mth-stage delay unit is the same as the electrode polarity of the main input end of the 1st-stage delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input end of the n+1th-stage delay unit is connected to the main input end of the nth-stage delay unit, and the auxiliary input end of the 1st-stage delay unit is connected to the main input end of the mth-stage delay unit to form the second phase configuration ring connection mode; the delay unit further comprises a power supply noise reduction circuit connected between a power supply voltage and the output end; the power supply noise reduction circuit comprises a seventh transistor and an eighth transistor, the sources of the seventh transistor and the eighth transistor are connected to the power supply voltage, the drain of the seventh transistor is connected to the positive end of the output end, the drain of the eighth transistor is connected to the negative end of the output end, and the gates of the seventh transistor and the eighth transistor are connected to a ground end.

2. The ring oscillator of claim 1, wherein, m is equal to 3, and the phase of the second phase configuration ring connection mode is ahead of the phase of the first phase configuration ring connection mode by 60°.

3. The ring oscillator of claim 1, wherein, The delay unit comprises a main input circuit and an auxiliary input circuit; the main input circuit comprises a first transistor and a second transistor, the sources of the first transistor and the second transistor are connected to a ground end, the drain of the first transistor is connected to the positive end of the output end, the drain of the second transistor is connected to the negative end of the output end, the gate of the first transistor is connected to the positive end of the main input end, and the gate of the second transistor is connected to the negative end of the main input end; the auxiliary input circuit comprises a third transistor and a fourth transistor, the sources of the third transistor and the fourth transistor are connected to a power supply voltage, the drain of the third transistor is connected to the positive end of the output end, the drain of the fourth transistor is connected to the negative end of the output end, the gate of the third transistor is connected to the positive end of the auxiliary input end, and the gate of the fourth transistor is connected to the negative end of the auxiliary input end.

4. The ring oscillator of claim 3, wherein, The delay unit further comprises a frequency control circuit connected between the power supply voltage and the output end.

5. The ring oscillator of claim 4, wherein, The frequency control circuit includes a fifth transistor and a sixth transistor, sources of the fifth transistor and the sixth transistor are connected to the power supply voltage, a drain of the fifth transistor is connected to a positive terminal of the output terminal, a drain of the sixth transistor is connected to a negative terminal of the output terminal, and gates of the fifth transistor and the sixth transistor are connected to a first control voltage.

6. The ring oscillator of claim 3, wherein, The delay unit further includes a positive feedback circuit connected between the ground terminal and the output terminal.

7. The ring oscillator of claim 6, wherein, The positive feedback circuit includes a ninth transistor, a tenth transistor and an eleventh transistor, a gate of the ninth transistor is connected to a drain of the tenth transistor, a drain of the ninth transistor is connected to a gate of the tenth transistor, a drain of the ninth transistor is connected to a positive terminal of the output terminal, a drain of the tenth transistor is connected to a negative terminal of the output terminal, sources of the ninth transistor and the tenth transistor are connected to a drain of the eleventh transistor, a gate of the eleventh transistor is connected to a second control voltage, and a source of the eleventh transistor is coupled to the ground terminal.

8. A phase-locked loop, characterized by An oscillator comprising the ring oscillator of any one of claims 1-7.

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