Multi-channel solution for addressing vector elements using vector index registers

Abstract

Disclosed herein are vector index registers for storing or loading indices of true and / or false results of conditional operations using multi-channel processing in a vector processor. Each of the vector index registers stores multiple addresses for accessing multiple locations in an operand vector in various types of operations that can utilize multi-channel processing.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application Ser. No. 16 / 417,526, filed May 20, 2019, entitled “MULTI-LANE SOLUTIONS FOR ADDRESSING VECTOR ELEMENTS USING VECTOR INDEX REGISTERS,” the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] In general, at least some embodiments disclosed herein relate to vector processors using a multi-channel solution. Furthermore, at least some embodiments disclosed herein relate to registers in a vector processor using a multi-channel solution for storing addresses to access vectors. Background Art

[0004] A vector processor can be or include a central processing unit (CPU) that implements an instruction set containing instructions that operate on arrays of data, often called vectors. This differs from a scalar processor, where instructions operate on individual data items. Compared to scalar processors, vector processors can significantly improve performance for certain workloads, particularly numerical simulations and similar tasks. Vector processors appeared in the early 1970s, and the majority of supercomputing designs were built from the 1970s to the 1990s. The price-performance ratio of more conventional microprocessor designs, such as scalar processor designs, declined rapidly, leading to a decrease in the development and manufacture of vector processors.

[0005] Generally speaking, a conventional CPU (e.g., a scalar-based CPU) can manipulate at most a few pieces of data at a time. For example, such a CPU has an instruction that essentially adds A to B and stores the result in C. The data for A, B, and C is typically pointed to by passing the address to the memory location where the data is stored. Decoding this address and obtaining the data from memory takes some time, during which time the CPU may be idle, waiting for the requested data to appear.

[0006] To shorten the time consumed by these steps, more modern CPUs use a technique called instruction pipelining, in which instructions are passed through several subunits in sequence. The first subunit reads and decodes the addresses, the next subunit retrieves the values at those addresses, and the next subunit performs the mathematical operations itself. With pipelining, the CPU begins decoding the next instruction even before the first instruction has left the CPU, similar to an assembly line. This way, the address decoder and the other mentioned components are in use simultaneously and continuously. Because of pipelining, any instruction takes the same amount of time to complete.

[0007] Vector processors improve pipelining by not only pipeline instructions, but also pipeline the data itself. Therefore, rather than the vector processor having to continually decode instructions and then fetch the data needed to complete them, the vector processor reads a single instruction from memory. This allows for faster decode times and reduced power consumption (e.g., the vector processor decodes once, rather than multiple times).

[0008] Vector processors and other types of processors such as conventional scalar processors include index registers for modifying operand addresses during programming or calculation. Indexes are commonly used and are beneficial for performing vector or array operations. The contents of the index register can be added to or subtracted from the immediate address to form the effective address of the actual data or operand. Typically, an instruction can test the index register, and if the test fails, the instruction can reset the start of the loop. In this case, the index register is used for loop control. Some instruction sets allow the use of multiple index registers.

[0009] Generally, it is known to use scalar registers for indexing. However, there are many limitations associated with using scalar registers for indexing. Moreover, some of these limitations can inhibit the performance of processors that use index registers. For example, to access multiple locations of an operand vector, a scalar index register needs to be incremented, and each increment requires a separate load by the processor to access the operand vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0011] Figure 1 An example portion of an example computing device 100 is shown, in accordance with some embodiments of the present disclosure.

[0012] Figure 2 An example portion of an example computing device 200 is shown, in accordance with some embodiments of the present disclosure.

[0013] Figure 3 and4 Each shows an example multi-channel operation for constructing index vectors to store in vector index registers (registers VIR_TRUE and VIR_FALSE) for TRUE and FALSE results (e.g., "0" and "1" results) for conditional test operations according to some embodiments of the present disclosure.

[0014] Figure 5 An example system is shown that uses multiple channels to construct an index vector to store in VIR_TRUE and VIR_FALSE according to some embodiments of the present disclosure.

[0015] Figure 6 and 7 Example operations of method 600 are shown for performing operations on elements of an operand vector using multiple lanes and according to VIR_TRUE and VIR_FALSE, in accordance with some embodiments of the present disclosure.

[0016] Figure 8 An example system including VIR_TRUE and VIR_FALSE for performing a first operation and a second operation on elements of an input operand vector using multiple lanes is shown, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] In general, at least some embodiments disclosed herein relate to vector processors utilizing a multi-channel solution. Furthermore, at least some of the embodiments disclosed herein include vector index registers in the vector processor that each store multiple addresses for accessing multiple locations in an operand vector. Furthermore, in at least some of the embodiments disclosed herein, the multi-channel solution can enhance address storage and access to multiple locations in an operand vector by the vector index registers.

[0018] Furthermore, at least some of the embodiments disclosed herein include vector index registers (VIR_TRUE and VIR_FALSE) that each store multiple addresses for accessing multiple locations in an operand vector for TRUE and / or FALSE results of one or more conditional test operations (e.g., numeric comparisons). Furthermore, at least some of the embodiments described herein relate to conditional operations in a vector processor having vector index registers VIR_TRUE and VIR_FALSE. Additionally, disclosed herein are processes, including multi-pass processes, for using VIR_TRUE and VIR_FALSE to more efficiently perform conditional operations in a vector processor.

[0019] In general, it is known that scalar index registers are used in vector processors to refer to multiple positions of a vector by changing the value stored in the scalar index register during a vector operation. However, by using a vector index register to index multiple positions of one or more operand vectors, the scalar index register can be replaced, and at least the continuous change of the value in the scalar index register during the vector operation can be avoided. This is only one example of a technical solution to the technical problem described herein. In addition, there are other limitations associated with using a scalar register or a single-entry vector for indexing. Moreover, some of these limitations can inhibit the performance of vector processors using index registers. For example, in order to access multiple positions of an operand vector, it is necessary to increment the scalar index register or the single-entry index register, and each increment needs to be loaded separately by the vector processor for accessing the operand vector. However, by using a vector index register to index multiple positions of one or more operand vector registers, the scalar index register can be replaced, and at least the continuous change of the scalar index register during the vector operation can be avoided.

[0020] Additionally, the performance of a vector processor can be enhanced even further by combining the use of vector index registers with a multi-channel solution for storing addresses to access operand vectors. Furthermore, the performance of a vector processor can be enhanced by combining the use of vector index registers with a multi-channel solution for accessing operand vectors. This is particularly true when the vector processor performs conditional operations.

[0021] Vector operations for vector processors can include a single vector or multiple vectors as input. Multiple channels of input can be used to accelerate parallel operations. For example, the operation can be the addition of vectors A and B, or the element-by-element multiplication of vectors A and B, or any other type of operation on two or more vectors. Each vector of operation can be separated into multiple channels (k channels) of parallel operations. For example, consider the multiplication of A(i)×B(i) (i=0, 1, 2, ..., (n-1)*k). This can be done in k parallel channels: for parallel channels j=0, 1, 2, ..., k-1, A(m)×B(m) (m=k×i+j, and i=0, 1, 2, ..., n-1). In general, the multiplication "×" can be replaced with another operation (e.g., addition, subtraction, bitwise OR, etc.). The result of the operation on two or more vectors can be a scalar or a vector.

[0022] Generally speaking, with or without a multi-channel solution, a vector index register (VIR) can store address components for vector operations using selective indexing. For example, using selective indexing, the VIR can store address components i_1, i_2, ..., i_n. This allows operations on vector registers to move through elements i_1, i_2, ..., i_n of the input vector, rather than i, i+1, i+2, ..., i+n of the input vector. For example, using selective indexing, the VIR can store non-sequential address components i_1, i_3, ..., i_8. This allows operations on vector registers to move through non-sequential elements of the input vector.

[0023] Specifically, utilizing a multi-channel solution, multiple channels can enhance selective indexing. When using multiple channels, by dividing the selective indexing into at least two channels, the time consumed by the selective indexing can be reduced by at least half. For example, using selective indexing and multiple channels, the VIR can store at least two address portions i_1, i_2, ..., i_n at a time. In some embodiments, every other address portion can be stored in an even-numbered position of the VIR, and the other address portions can be stored in parallel in odd-numbered positions of the VIR. By splitting the storage locations into two groups, data storage in the VIR can occur at twice the speed. Furthermore, multiple channels allow operations on vector registers to move through the elements i_1, i_2, ..., i_n of the input vector at at least twice the speed. For example, accessing elements i_1, i_2, ..., i_n of the input vector, rather than i, i+1, i+2, ..., i+n, can also occur by accessing every other address portion stored in an even-numbered position and the other portion stored in parallel in an odd-numbered position. Using selective indexing and multiple channels, the VIR can store non-sequential address portions i_1, i_3, ..., i_8, and the processor can access such portions more quickly by splitting the processing into multiple channels.

[0024] The techniques disclosed herein may provide support for at least basic or complex conditional operations. For example, the techniques may support the following basic conditional operation: if (A(i)>B(i)), then A(i)=A(i)+B(i), otherwise A(i)=A(i)-B(i). In this basic conditional operation, a single set of VIR, VIR_TRUE, and VIR_FALSE may be used to more efficiently perform the same operation via a vector processor, which executes A(VIR_TRUE(j))=A(VIR_TRUE(j))+B(VIR_TRUE(j)) and A(VIR_FALSE(k))=A(VIR_FALSE(k))-B(VIR_FALSE(k)). Furthermore, disclosed herein is a system that can support the efficient implementation of conditional operations in a vector processor using a pair of VIR_TRUE and VIR_FALSE, such as, for example, the following conditional operation: if ('test condition'), A(i)=A(i)+B(i), otherwise A(i)=A(i)-B(i). The result of the test condition can also be used to set the index in two vector index registers VIR_TRUE and VIR_FALSE.

[0025] The techniques disclosed herein can also enhance basic or complex conditional operations when using multiple channels or multi-channel vector processing. In at least some embodiments, the techniques utilize a multi-channel solution for conditional operations in a vector processor having vector index registers VIR_TRUE and VIR_FALSE. The multi-channel solution can process vector conditional operations in a vector processor more efficiently or quickly. The present disclosure provides basic conditional operations as examples for demonstrating the use of VIR with multi-channel vector processing, but it should be understood that the techniques disclosed herein can be used for more complex conditional operations. Moreover, in most cases, a dual-channel vector processing solution is shown herein; however, it should be understood that the techniques disclosed herein can also be applied to solutions with more than two channels, such as four-channel vector processing.

[0026] The following logic is a basic example of a conditional operation that can be processed by multiple lanes: If (A(i)>B(i)), then A(i)=A(i)+B(i), else A(i)=A(i)-B(i). Examples can be processed using two sets of TRUE VIRs and FALSE VIRs as dual-access VIRs, or one set of TRUE VIRs and FALSE VIRs. For example, some embodiments may include four VIRs: VIR_TRUE_Lane_0 and VIR_FALSE_Lane_0, and VIR_TRUE_Lane_1 and VIR_FALSE_Lane_1. Or, for example, some embodiments may include VIR_TRUE split into two lanes and VIR_FALSE split into two lanes. An instance of a set with TRUE VIR and FALSE VIR each split into two channels can be used to perform conditional operations more efficiently by performing the following, if (A(i)>B(i)), then A(i)=A(i)+B(i), otherwise A(i)=A(i)-B(i):

[0027] A(VIR_TRUE(j) channel 0, VIR_TRUE(j) channel 1) =

[0028] A(VIR_TRUE(j) channel 0, VIR_TRUE(j) channel 1)+

[0029] B(VIR_TRUE(j) channel 0, VIR_TRUE(j) channel 1), and

[0030] A(VIR_FALSE(k) channel 0, VIR_FALSE(k) channel 1) =

[0031] A(VIR_FALSE(k) channel 0, VIR_FALSE(k) channel 1)–

[0032] B(channel 0 of VIR_FALSE(k) and channel 1 of VIR_FALSE(k)).

[0033] For purposes of this disclosure, it should be understood that the test condition can be simple (e.g., "A(i)>0" or "A(i)>B(i)" or "A(i)>C(i)") or more complex (e.g., "(A(i)>0 and A(i)>B(i)) or (A(i)>C(i))"). Therefore, regardless of whether the test condition is simple or complex, a single set of VIR_TRUE and VIR_FALSE can be used to handle two or more operation branches selected via the conditional test operation (e.g., two operation branches include: then "A(i)=A(i)+B(i)", otherwise "A(i)=A(i)-B(i)").

[0034] For the purposes of this disclosure, it should be understood that a conditional test does not generally need to be a test for “>.” The test condition may be other types of numerical tests and / or Boolean operations.

[0035] In some embodiments, when there are complex tests and / or Boolean operations, it may be advantageous to use the Vm register to track vectors of True and False values so that different TRUE and FALSE vectors can be combined to produce the final test result. Converting complex Boolean operations into corresponding index operations such as VIR_TRUE and VIR_FALSE can be complex, so in some embodiments, using Vm as an intermediate index vector can be useful.

[0036] The index value or addressing component stored in the VIR (e.g., [2, 4, 5, 8] for accessing an element within an operand vector register (OVR)) can be converted to a storage address (e.g., a base address plus an increment for each memory location). Thus, the outputs described herein, such as the outputs of the multiplexers described herein, can be converted to storage addresses for directly accessing a vector in main memory in a manner similar to accessing an operand vector register (OVR).

[0037] In some embodiments, the technology disclosed herein can provide a method for utilizing VIR and multi-channel vector processing. In the method, the channels being processed can be implemented by even and odd positions in the operand vector. In other words, according to an example, the even positions in each operand vector can be located in the first channel and the odd positions in each operand vector can be located in the second channel. Moreover, the operand vector registers used in the method can be dual-access operand vector registers. Alternatively, multiplexers can be used to implement similar functionality in the method without dual-access operand vectors. However, such examples using conventional operand vector registers can have more complex circuit designs than examples using dual-access operand vector registers or multi-access operand vector registers.

[0038] The method may include loading one or more operand vectors by a vector load store unit of a vector processor. Each vector in the one or more operand vectors is stored in a corresponding operand vector register. The method may also include performing, by the vector processor, a conditional test operation on each element at a first lane index position of at least one of the loaded one or more operand vectors based on a first lane count stored in a first lane counter register. The conditional test operation may provide a test result vector.

[0039] The method may further include storing, based on the first channel count, in a first channel index position in a first vector index register (VIR_TRUE) for each TRUE result of the conditional test operation, a position of the TRUE result in the test result vector. The method may further include storing, based on the first channel count, in a first channel index position in a second vector index register (VIR_FALSE) for each FALSE result of the conditional test operation, a position of the FALSE result in the test result vector.

[0040] The method may also include performing, by the vector processor, a conditional test operation on each element at a second lane index position of at least one of the loaded one or more operand vectors based on a second lane count stored in a second lane counter register. Furthermore, the method may include storing a position of a TRUE result in the test result vector in the second lane index position in VIR_TRUE based on the second lane count, and storing a position of a FALSE result in the test result vector in the second lane index position in VIR_FALSE based on the second lane count.

[0041] The method may also include performing a first vector operation on a first element in the one or more operand vectors. The first element is identified by a position stored in VIR_TRUE. The method may also include performing a second vector operation on a second element in the one or more operand vectors. The second element is identified by a position stored in VIR_FALSE.

[0042] The method may also include loading, by a vector load store unit, a first input operand vector stored in a first input operand vector register, and loading, by a vector load store unit, a second input operand vector stored in a second input operand vector register. The method may also include loading, by a vector load store unit, stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to a first lane count, and loading, by a vector load store unit, stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to a second lane count. The method may also include performing a first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_TRUE. In such an example, the first input operand vector register may be a dual access operand vector register, and the second input operand vector register may be a dual access operand vector register.

[0043] The method may also include storing the result of the first operation in an output operand vector register at a location corresponding to the loaded location of the first channel and the second channel from VIR_TRUE. The method may also include continuing to perform the first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded location of the first channel and the second channel from VIR_TRUE and storing the result of the first operation in the output operand vector register at corresponding locations that match the loaded location from VIR_TRUE until the first channel count or the second channel count exceeds or equals the length of VIR_TRUE. In addition, the method may include resetting the first channel count and the second channel count when the first channel count or the second channel count exceeds or equals the length of VIR_TRUE. In such an example, the first channel count and the second channel count may each be incremented by two per loaded location from VIR_TRUE.

[0044] The method may further include, after resetting the first lane count and the second lane count, loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the first lane count. Furthermore, after resetting the first lane count and the second lane count, the method may include, by the vector load store unit, loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the second lane count. The method may further include performing a second operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_FALSE. The method may also include continuing to perform the second operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from VIR_FALSE and storing results of the first operation in the output operand vector register at corresponding positions that match the loaded positions from VIR_FALSE until the first lane count or the second lane count exceeds or equals the length of VIR_FALSE.

[0045] In such an example, the first channel count and the second channel count may each be incremented by two per loaded position from VIR_FALSE. Furthermore, in such an example, the first operation and the second operation may each include various types of numerical operations. For example, the first operation may include addition and the second operation may include subtraction.

[0046] In some embodiments, the techniques disclosed herein may provide a system utilizing VIR and multi-channel vector processing. The system may include a vector processor configured to perform conditional test operations on elements of a first loaded operand vector and a second loaded operand vector using two channels within each of the first and second loaded operand vectors. Channels in the processing performed by the system may be implemented using even and odd positions in the operand vectors. Furthermore, the operand vector registers used in the system may be dual-access operand vector registers. Alternatively, multiplexers may be used to implement similar functionality in a system without dual-access operand vectors. However, such embodiments using conventional operand vector registers may have a more complex circuit design than embodiments using dual-access operand vector registers or multi-access operand vector registers. For example, dual-access operand vector registers may be used in embodiments with dual-channel processing. Furthermore, for example, quad-access operand vector registers may be used in embodiments with four-channel processing. Using additional multiplexers rather than multi-access operand vector registers for multi-channel processing may result in a less elegant circuit design.

[0047] The system may further include a first channel counter of the vector processor configured to store a first channel count. The system may further include a second channel counter of the vector processor configured to store a second channel count. The conditional test operation performed by the vector processor may be based on the first channel count and the second channel count.

[0048] The system may also include one or more operand vector registers of the vector processor. Each operand vector register may be configured to store an operand vector. The system may also include a first vector index register (VIR_TRUE) for each TRUE result of a conditional test operation. Furthermore, the system may include a second vector index register (VIR_FALSE) for each FALSE result of a conditional test operation.

[0049] In the system, a vector processor may be configured to load one or more operand vectors from one or more operand vector registers. The vector processor may also be configured to perform a conditional test operation on each element at a first channel index position of at least one of the loaded one or more operand vectors based on a first channel count stored in a first channel counter, and to perform a conditional test operation on each element at a second channel index position of at least one of the loaded one or more operand vectors based on a second channel count stored in a second channel counter. The conditional test operation may provide a test result vector. The vector processor may also be configured to store the position of a TRUE result in the test result vector in the first channel index position in VIR_TRUE based on the first channel count, and to store the position of a FALSE result in the test result vector in the first channel index position in VIR_FALSE based on the first channel count. The vector processor may also be configured to store the position of a TRUE result in the test result vector in the second channel index position in VIR_TRUE based on the second channel count, and to store the position of a FALSE result in the test result vector in the second channel index position in VIR_FALSE based on the second channel count.

[0050] The vector processor in the system may also be configured to perform the operations of the aforementioned method. For example, the vector processor is further configured to load the first input operand vector stored in the first input operand vector register by a vector load-store unit of the vector processor, and to load the second input operand vector stored in the second input operand vector register by the vector load-store unit. Furthermore, the vector processor is further configured to load the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to the first lane count by the vector load-store unit, and to load the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to the second lane count by the vector load-store unit. The vector processor may also be configured to perform a first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_TRUE, and to store the result of the first operation in the output operand vector register at a location corresponding to the loaded locations from the first lane and the second lane in VIR_TRUE. The vector processor may be further configured to continue performing the first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from VIR_TRUE and store the results of the first operation in the output operand vector register at corresponding positions that match the loaded positions from VIR_TRUE until the first lane count or the second lane count exceeds or equals the length of VIR_TRUE. The vector processor may be further configured to reset the first lane count and the second lane count when the first lane count or the second lane count exceeds or equals the length of VIR_TRUE. The first lane count and the second lane count may each be incremented by two per loaded position from VIR_TRUE.

[0051] The vector processor may be further configured to, after resetting the first lane count and the second lane count, load, by the vector load-store unit, the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the first lane count. The vector processor may be further configured to, by the vector load-store unit, load, by the vector load-store unit, the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the second lane count. The vector processor may be further configured to perform a second operation on the corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_FALSE. The vector processor may be further configured to continue performing a second operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from VIR_FALSE and store results of the first operation in the output operand vector register at corresponding positions that match the loaded positions from VIR_FALSE until the first lane count or the second lane count exceeds or equals the length of VIR_FALSE. The first lane count and the second lane count may each be incremented by two per loaded position from VIR_FALSE.

[0052] In some embodiments, the techniques disclosed herein may provide a vector processor utilizing VIR and multi-channel vector processing. The vector processor may include an operand scalar register (OSR) configured to store elements to be used as inputs to operations of an arithmetic logic unit (ALU). The processor may include a first operand vector register (OVR) and a second OVR of a plurality of operand vector registers. Each OVR may be configured to store elements of an operand vector to be used as inputs to operations of the ALU. Each OVR may be a dual access OVR.

[0053] The vector processor may be further configured to perform a conditional test operation on elements of the first OVR and the second OVR based on a first channel count stored in the first channel count register and a second channel count stored in the second channel count register. Furthermore, the vector processor may be configured to perform a conditional test operation on elements stored in the OSR and elements of the first OVR based on the first channel count stored in the first channel count register and the second channel count stored in the second channel count register. The conditional test operation may provide a test result vector.

[0054] The vector processor may further include a first vector index register (VIR_TRUE) configured to store the position of a TRUE result in a test result vector in a first channel index position in VIR_TRUE according to the first channel count, and to store the position of a TRUE result in the test result vector in a second channel index position in VIR_TRUE according to the second channel count. The processor may further include a second vector index register (VIR_FALSE) configured to store the position of a FALSE result in the test result vector in a first channel index position in VIR_FALSE according to the first channel count, and to store the position of a FALSE result in the test result vector in a second channel index position in VIR_FALSE according to the second channel count. Furthermore, for such embodiments, the vector processor may be configured to perform the operations of the aforementioned method.

[0055] The combination of VIR and multi-channel vector processing has many applications. Generally speaking, the embodiments disclosed herein can provide specific technical solutions to at least the technical problems mentioned in the background section and other sections of this application, as well as other technical problems not described herein but recognized by those skilled in the art.

[0056] Figure 1 An example portion of an example computing device 100 is shown, in accordance with some embodiments of the present disclosure. As shown, the device 100 may be communicatively coupled to one or more networks 112. The device 100 includes a vector processor 102, in accordance with some embodiments of the present disclosure. The device 100 also includes at least one bus 104, a main memory 106, a data storage system 108, and a network interface 110. The bus 104 communicatively couples the vector processor 102, the main memory 106, the data storage system 108, and the network interface 110. The device 100 includes a computer system that includes at least the vector processor 102, the main memory 106 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and the data storage system 108, in communication with each other via the bus 104 (which may include multiple buses).

[0057] in other words, Figure 11 is a block diagram of an example apparatus 100 having a computer system in which embodiments of the present disclosure may be operated. In some embodiments, the computer system may include a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein when executed. In such embodiments, the machine may be connected (e.g., via a network interface 110) to other machines in a LAN, an intranet, an extranet, and / or the Internet (e.g., network 112). The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment (such as the peer-to-peer network described herein) or as a server or a client machine in a cloud computing infrastructure or environment.

[0058] The vector processor 102 represents one or more vector processors according to some embodiments of the present disclosure. The vector processor 102 may include a microprocessor, a central processing unit, or the like. More specifically, the vector processor 102 may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or a processor implementing a combination of instruction sets, as long as the processor uses: vector instructions, vector registers, vector priority, and a multi-channel configuration. The vector processor 102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a graphics processing unit (GPU), a network processor, or the like. The vector processor 102 may be configured to execute instructions for performing the operations and steps discussed herein. The vector processor 102 may further include a network interface device, such as a network interface 110, for communicating via one or more communication networks (such as a network 112).

[0059] The data storage system 108 may include a machine-readable storage medium (also referred to as a computer-readable medium) having one or more instruction sets or software stored thereon and may embody at least some aspects of one or more of the methods or functions described herein. The data storage system 108 may include a non-volatile storage device. Instructions may also reside, in whole or in part, within the main memory 106 and / or within the vector processor 102 during their execution by the computer system, with the main memory 106 and the vector processor 102 also constituting machine-readable storage media. Although the memory, vector processor, and data storage device portions are each shown as a single unit in the example embodiment, each unit should be considered to include a single unit or multiple units that can store instructions and perform their corresponding operations. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0060] Figure 2 An example portion of an example computing device 200 is shown in accordance with some embodiments of the present disclosure. As shown, the computing device 200 includes a vector processor 102 and a bus 104 and a main memory 106 (e.g., see Figure 1 ). The computing device 200 may also be or include the computing device 100.

[0061] like Figure 2 , the vector processor 102 includes vector registers 202, scalar registers 204, a bus 206, an arithmetic logic unit 208 (ALU 208), and a vector load-store unit 210. Other embodiments of the computing device 200 may include scalar registers 204 external to the vector processor 102 or in a unit of the vector processor separate from the unit of the vector processor having the vector registers 202. Bus 206 communicatively couples the vector registers 202, scalar registers 204, arithmetic logic unit (ALU) 208, and vector load-store unit 210, and such components may communicate with each other via bus 206 (which may include multiple buses). Vector registers 202 include multiple vector registers. Furthermore, ALU 208 includes multiple ALUs, such as arithmetic logic unit (ALU) 0, ALU 1, and ALU N.

[0062] The vector processor 102 includes at least one vector index register. The vector processor 102 may be or include one or more central processing units (CPUs) that execute instructions that operate on one-dimensional arrays of data, referred to as vectors.

[0063] The vector registers 202 in the vector processor 102 may include operand vector registers (i.e., input vector registers), result vector registers (i.e., output vector registers), and vector index registers that store values for accessing elements in the operand vector registers and / or result vector registers. The values in the accessed elements of the operand vector registers and / or result vector registers may be used as inputs to one or more ALUs, such as the ALU 208.

[0064] Generally speaking, the vector processor 102 may include index registers, which may include scalar index registers and vector index registers, such as Figure 5 and 8 The vector index register shown in .

[0065] The scalar registers 204 of the vector processor 102 may include a scalar index register, as well as operand scalar registers (i.e., input scalar registers) and result scalar registers (i.e., output scalar registers). At least some of the scalar registers may provide index and control values for many different types of operations on scalars and vectors. Furthermore, the scalar registers may also provide values used by vector instructions. For example, a vector provided by a vector register may be multiplied by a scalar provided by a scalar register.

[0066] At least some of the scalar registers 204 and the vector registers 202 may be connected to corresponding ALUs of the ALU 208. The ALUs in the ALU 208 may include combinational digital electronic circuits that perform arithmetic and bitwise operations on integer binary numbers. In the vector processor 102, if the output vector register is providing feedback during operation, the ALUs in the ALU 208 may be connected to the input vector registers and, in some cases, to the output vector registers. In such cases, the output vector registers are both the input vector and the output vector.

[0067] Furthermore, scalar registers 204 may include programmable scalar registers. Programmable scalar registers may be used so that a vector provided by a vector register (e.g., one of vector registers 202) may operate on a scalar provided by and programmed into one of the programmable scalar registers. For example, one of the operations may include multiplying a vector by a scalar value (e.g., vector A(i) x scalar p).

[0068] The depicted bus 206 may be configured to communicatively couple the vector load store unit 210, the vector registers 202, the scalar registers 204, and the arithmetic logic unit 208. The bus 206 may include a 2:1 multiplexer, a 3:1 multiplexer, or an N:1 multiplexer configured to receive input from a vector index register and output an address or address component for accessing an operand vector (e.g., see Figure 8 ).

[0069] The vector load store unit 210 includes circuitry for executing load and store instructions, generating addresses for load and store vector operations, and loading data from memory or storing data back to memory from registers of the vector processor 102. The vector load store unit 210 can perform many of the operations described herein, including Figure 3 、 4 and many operations of methods 300, 400, and 600 in 6 to 7.

[0070] Each of the computing devices described herein may be a machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Figure 1 and 2 Each of the illustrated computing devices illustrates a single machine, but the term "machine" shall also be taken to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies or operations discussed herein. Furthermore, each of the illustrated computing devices may each include at least a bus and / or motherboard, one or more controllers (such as one or more CPUs), a main memory that may include a temporary data storage device, at least one type of network interface, a storage system that may include a permanent data storage device, and / or any combination thereof.

[0071] In the discussion Figure 3 、 4 and methods 300, 400, and 600 as described in 6 to 7 and Figure 5 and 8Before describing the systems 500 and 800 depicted in the accompanying drawings, it is important to understand that elements in an operand vector register (OVR) can be addressed using at least an index from a vector index register (VIR) or another type of register, such as a counter register. Generally, when a counter register is used, the counter adds 1 or another number to itself for each iteration or step in a DO or FOR loop, thereby generating an address for the next iteration or step. In multi-channel processing, when a counter register is used, the counter can add 2 or another number that is a multiple of two to itself for each iteration or step in a DO or FOR loop, thereby generating an address for the next iteration or step. The counter can be incremented by 2 in dual-channel processing. The number of current counters added to each increment of the counter number can depend on the number of channels used by the vector processor. For example, the number added to the counter number can be equal to the number of channels used. In systems 500 and 800, 2 is added to the counter for each increment of the counter, and both channels are used in both systems.

[0072] In some embodiments, the VIR need not be driven by a counter, but it may be useful to have one or more counters drive the VIR. A common counter may provide an address input to the VIR and may provide separate address inputs to a receiving multiplexer that outputs address components used to access operand vectors in vector operations.

[0073] For example, a VIR may store a vector VMX, where VMX(i) and i = 0, 1, ..., n-1. A simple example of an application using a VIR would be a compression operation such as B(i) = A(VMX(i)), where, for example, the elements of A(i) are compared to a scalar and the TRUE result of the comparison is output to B(i). Furthermore, when another vector register stores a vector A, the elements of A are A(i), where i = 0, 1, 2, ..., n. In normal mode (such as when a counter output is selected for use by a multiplexer), the processor may perform A+a, where "a" is a scaler from the counter through the multiplexer. The result is stored in output vector register B, where B(i) = A(i)+a, where i = 0, 1, ..., n-1. In a mode using a VIR (e.g., alternative selection control of the multiplexer), the processor may perform A(VMX)+a using an address generated from the output of the VIR. Thus, the output vector register has B, where B(i)=A(VMX(i))+a, and where i=0, 1, ..., n-1. Also, for example, a vector processor may be configured to operate on two vectors, such as B(i)=Function(A(VMX(i)), C(VMX(i)), where "Function" is implemented via the ALU.

[0074] Figure 3 and 4 Each shows an example multi-channel operation for two channels for constructing index vectors to store TRUE and FALSE results (e.g., "0" and "1" results) for conditional test operations according to some embodiments of the present disclosure. Figure 3 and 4 An example difference between the methods in Figure 3 The method 300 in includes performing a conditional test operation using at least one operand scalar and at least one operand vector, and Figure 4 The method 400 includes performing a conditional test operation using at least two operand vectors.

[0075] Method 300 begins at step 302 by loading at least one operand vector and at least one operand scalar by a vector load store unit of a vector processor (e.g., see vector load store unit 210). In some embodiments, each operand vector is stored in a corresponding dual access operand vector register (e.g., see Figure 5 504 or 506). Moreover, each scalar may be stored in a corresponding operand scalar register (e.g., see scalar register 204). Moreover, in some embodiments, even positions in the vector are in the first lane and odd positions are in the second lane, or vice versa.

[0076] In step 304a, the method 300 continues with a conditional test operation by the vector processor on a scalar having an element located at a first lane (lane 0) index position (e.g., position "0," "2," etc.) of the at least one operand vector based on a first lane count (lane 0 count). The first lane count may be stored in a first lane counter of the vector processor (e.g., see Figure 5 0 counter 508a depicted in FIG. 304b. Furthermore, in step 304b, method 300 continues with a conditional test operation by the vector processor on a scalar having an element at a second channel (channel 1) index position (e.g., position "1," "3," etc.) of the at least one operand vector based on a second channel count (channel 1 count). The second channel count may be stored in a second channel counter of the vector processor (e.g., see FIG. Figure 5 In the channel 1 counter 508b) depicted in .

[0077] exist Figure 3In the embodiment of the present invention, a conditional test operation is performed on at least one scalar from a scalar register and an element of at least one of the loaded one or more operand vectors according to a first channel count and a second channel count stored in a corresponding counter. The counter can be part of a scalar register and a vector processor. Circuitry is not depicted in the figures showing the operand scalar register and the operand vector register; however, it should be understood that except that one of the operand vector registers (e.g., register 504 or 506) will be replaced with an operand scalar register, Figure 5 The system 500 depicted in includes components that can support the method 300 .

[0078] In step 306a, the method 300 continues by identifying, by the vector processor, whether the result of the conditional test operation in step 304a is a TRUE result. In other words, in step 306a, the method 300 continues by identifying whether the result of the conditional test operation in step 304a is TRUE or FALSE (e.g., a Boolean "1" or "0"). If the result of the operation in step 304a is TRUE, then the method 300 continues in step 308a by counting the number of the first channel (e.g., according to the first channel TRUE counter stored in the first channel, e.g., see Figure 5 1 channel TRUE counter 5160a) stores the position of the element of the loaded operand vector in the first channel index position in the vector index register (VIR_TRUE) for the TRUE result of the conditional test operation. If the result of the test operation of step 304a is FALSE, then the method 300 continues in step 310a with the first channel count (as determined by the first channel TRUE counter stored in the first channel FALSE counter, e.g., see Figure 5 The first channel FALSE count in the first channel FALSE counter 5160b depicted in FIG. 5 ) continues with storing the position of the element of the loaded operand vector in the first channel index position in the vector index register (VIR_FALSE) for the FALSE result of the comparison.

[0079] In step 306b, the method 300 continues by identifying, by the vector processor, whether the result of the conditional test operation in step 304b is a TRUE result. In other words, in step 306b, the method 300 continues by identifying whether the result of the conditional test operation in step 304b is TRUE or FALSE (e.g., a Boolean "1" or "0"). If the result of the operation in step 304b is TRUE, then the method 300 continues in step 308b by counting the number of the second channel (e.g., according to the value stored in the second channel TRUE counter, e.g., see Figure 5_TRUE) in the first channel TRUE counter 5161a as depicted in FIG. 304b. If the result of the test operation at step 304b is FALSE, then the method 300 continues at step 310b with the second channel count (e.g., as determined by the first channel TRUE counter 5161a stored in the second channel FALSE counter, e.g., see FIG. 304b). Figure 5 The second channel FALSE count in the second channel FALSE counter 5161b depicted in FIG. 5 ) continues with the location where the element of the loaded operand vector is stored in the second channel index location in VIR_FALSE.

[0080] In step 312, the first channel count and the second channel count are each incremented by two. Method 300 repeats steps 304a, 304b, 306a, 306b, 308a, 308b, 310a, 310b, and 312 until either the first count or the second count equals or exceeds the vector length (VL) of at least one of the operand vectors. By incrementing the counts until one of the counts equals or exceeds VL, the vector processor can store the positions of the elements of the loaded operand vectors according to the counts, continuing until the positions of the elements of the loaded operand vectors are stored in VIR_TRUE or VIR_FALSE. In other words, method 300 continues to store the positions of the elements of the loaded operand vectors according to the counts until the positions of the elements of the loaded operand vectors are stored in VIR_TRUE or VIR_FALSE.

[0081] In step 314, method 300 continues by identifying whether the first channel count or the second channel count equals or exceeds the VL of at least one of the operand vectors. In some embodiments, method 300 may continue by identifying whether the VL of one of the OVRs accessed by the conditional test operation equals the result of adding the VL of VIR_TRUE to the VL of VIR_FALSE, which may be another way to identify whether one of the counts equals or exceeds the VL of the operand vector stored in the OVR. These example alternatives for identifying whether the count equals the VL of at least one of the operand vectors may illustrate using all elements of the OVR accessed by the test operation in the conditional test operation.

[0082] If both the first count and the second count are less than VL of one of the operand vectors, then the method continues in steps 304a and 304b. Otherwise, the method 300 has completed construction of the index vectors for storage in VIR_TRUE and VIR_FALSE.

[0083] After completing the construction of the index vector stored in VIR_TRUE and VIR_FALSE, method 300 continues in step 316 by loading the stored first channel position and the stored second channel position of the elements of the one or more loaded operand vectors from VIR_TRUE and / or VIR_FALSE by the vector load storage unit. Moreover, in step 318, method 300 continues by iterating one or more vector operations on the elements of the loaded operand vector according to the loaded positions stored in VIR_TRUE and / or VIR_FALSE. In some embodiments, the number of iterations of step 318 is equal to VL (as shown in step 312). In such embodiments, two corresponding registers can be loaded with the new vector lengths of VIR_TRUE and VIR_FALSE (e.g., VL_VIR_TRUE and VL_VIR_FALSE). In other words, one VL register for the number of entries is stored in VIR_TRUE and one register for the number of entries is stored in VIR_FALSE. In such embodiments, the corresponding VL registers can also be loaded with the vector length of OVR. Thus, in such embodiments, when method 300 continues in step 318 by iterating one or more vector operations over the elements of the loaded operand vector based on the loaded positions stored in VIR_TRUE and / or VIR_FALSE, the vector processor may determine the number of iterations of OVR and / or VIR based on the respective VL values of OVR and / or VIR in the respective VL registers.

[0084] Apart from some minor differences, Figure 3 and 4 The methods 300 and 400 in FIG. 3 are similar to some extent. As mentioned herein, Figure 3 and 4 An example difference between the methods in Figure 3 The method 300 in includes performing a conditional test operation using at least one operand scalar and at least one operand vector, and Figure 4 The method 400 includes performing a conditional test operation using at least two operand vectors.

[0085] exist Figure 4 In the embodiment, method 400 begins at step 402 by loading at least two operand vectors by a vector load store unit of a vector processor. In some embodiments, each operand vector is stored in a corresponding dual access operand vector register (e.g., see Figure 5 Furthermore, in some embodiments, even positions in the vector are in the first lane and odd positions are in the second lane, or vice versa.

[0086] In step 404a, the method 400 continues with the vector processor performing a conditional test operation based on a first lane count using corresponding elements at similar first lane (lane 0) index positions (e.g., positions "0," "2," etc.) of the at least two operand vectors. The first lane count may be stored in a first lane counter of the vector processor (e.g., see Figure 5 0 counter 508a) depicted in FIG. Furthermore, in step 404b, method 400 continues with a conditional test operation by the vector processor using corresponding elements at similar second channel (channel 1) index positions (e.g., positions "0," "2," etc.) of the at least two operand vectors based on the second channel count. The second channel count may be stored in a second channel counter of the vector processor (e.g., see FIG. Figure 5 In the channel 1 counter 508b) depicted in .

[0087] In step 406a, the method 400 continues by identifying by the vector processor whether the result of the conditional test operation in step 404a is a TRUE result. If the result of the operation in step 404a is TRUE, then the method 400 continues in step 408a by counting the first channel (e.g., according to the first channel TRUE counter stored in the first channel, see for example). Figure 5 _TRUE) in the first channel TRUE counter 5160a depicted in FIG. 4 . If the result of the test operation at step 404a is FALSE, then the method 400 continues at step 410a with the first channel count (e.g., as determined by the first channel TRUE counter stored in the first channel FALSE counter, e.g., see FIG. 4 ). Figure 5 The first channel FALSE count in the first channel FALSE counter 5160b depicted in FIG. 5 ) continues with the location where the element of the loaded operand vector is stored in the first channel index location in VIR_FALSE.

[0088] In step 406b, the method 400 continues by the vector processor identifying whether the result of the conditional test operation in step 404b is a TRUE result. If the result of the operation in step 404b is TRUE, then the method 400 continues in step 408b by counting the number of the second channel (e.g., according to the value stored in the second channel TRUE counter, see e.g., Figure 5_TRUE) in the second channel TRUE counter 5161a depicted in FIG. 4 . If the result of the test operation at step 404b is FALSE, then the method 400 continues at step 410b with the second channel count (e.g., as determined by the second channel TRUE counter stored in the second channel FALSE counter, e.g., see FIG. 4 ). Figure 5 The second channel FALSE count in the second channel FALSE counter 5161b depicted in FIG. 5 ) continues with the location where the element of the loaded operand vector is stored in the second channel index location in VIR_FALSE.

[0089] In step 412, the first channel count and the second channel count are each incremented by two. Method 400 repeats steps 404a, 404b, 406a, 406b, 408a, 408b, 410a, 410b, and 412 until either the first count or the second count equals or exceeds the vector length (VL) of at least one of the operand vectors. By incrementing the counts until one of the counts equals or exceeds the VL, the vector processor can store the position of the element of the loaded operand vector according to the counts, continuing until the position of the element of the loaded operand vector is stored in VIR_TRUE or VIR_FALSE. In step 414, method 400 continues by identifying whether the first channel count or the second channel count equals or exceeds the VL of at least one of the operand vectors. In some embodiments, method 400 can continue by identifying whether the VL of one of the OVRs accessed by the conditional test operation is equal to the result of adding the VL of VIR_TRUE to the VL of VIR_FALSE. If both the first count and the second count are less than VL of one of the operand vectors, then the method continues in steps 404a and 404b. Otherwise, the method 400 has completed construction of the index vectors for storage in VIR_TRUE and VIR_FALSE.

[0090] After completing the construction of the index vector stored in VIR_TRUE and VIR_FALSE, method 400 continues with loading the stored first lane positions and the stored second lane positions of one or more elements of the loaded operand vector from VIR_TRUE and / or VIR_FALSE by the vector load storage unit in step 416. Furthermore, in step 418, method 400 continues with iterating one or more vector operations on the elements of the loaded operand vector according to the loaded positions stored in VIR_TRUE and / or VIR_FALSE.

[0091] Figure 5An example system 500 is shown for constructing an index vector for storage in VIR_TRUE 502a and VIR_FALSE 502b, according to some embodiments of the present disclosure. System 500 can implement many operations and aspects of methods 300 and 400, and system 500 can be part of one or more vector processors. System 500 includes VIR_TRUE 502a and VIR_FALSE 502b. The system also includes a first OVR 504 and a second OVR 506, as described in the description of method 400.

[0092] The system 500 further includes a first channel counter 508 a, which may be partially implemented by a counter register and may be the first channel counter described in the description of the method 400. The system 500 further includes a second channel counter 508 b, which may be partially implemented by a counter register and may be the second channel counter described in the description of the method 400.

[0093] The system 500 further includes a first channel conditional test operation 5100 that can perform a conditional test operation, such as a comparison of values stored in the first channel of the first OVR 504 and the second OVR 506. The system 500 further includes a second channel conditional test operation 5101 that can perform a conditional test operation, such as a comparison of values stored in the second channel of the first OVR 504 and the second OVR 506.

[0094] Conditional test operations 5100 and 5101 may be the same test operation or different test operations, and many different types of conditional test operations may be performed, such as many different types of comparisons of one or more of OVRs 504 and 506 or OVRs compared to a scalar, for example, 1st OVR(i) < 2nd OVR(i), 1st OVR(i) = 2nd OVR(i), 1st OVR(i) > 2nd OVR(i), 1st OVR(i) ≤ 2nd OVR(i), 1st OVR(i) ≥ 2nd OVR(i), 1st OVR(i) < scalar value, 1st OVR(i) = scalar value, 1st OVR(i) > scalar value, 1st OVR(i) ≤ scalar value, or 1st OVR(i) ≥ scalar value, etc.

[0095] The first lane conditional test operation 5100 may perform a test or comparison once or once per cycle for elements of two vectors with similar addresses (e.g., similar index or iteration i) in the first lane. At each iteration i (which also represents the address or address component i), the first lane counter 508a provides the first lane conditional test operation 5100 with the address i for accessing the OVRs 504 and 506. In the system 500, the index "i" of the first lane is incremented by two. For example, by incrementing by two, the index "i" may open the OVR at an initial position and then increment every other position, such that the first lane includes even-numbered positions (e.g., i=0, 2, 4, etc.) of the OVRs 504 and 506. In some examples, the elements / outputs of the OVRs 504 and 506 at iteration or address i are compared to each other or to a value from another register, such as a scalar register (e.g., see method 300). The first channel condition test operation 5100 produces a single output, which is either TRUE or FALSE (eg, "1" or "0").

[0096] The second lane conditional test operation 5101 can perform a test or comparison once or once per cycle for elements of two vectors with similar addresses (e.g., similar index or iteration j) in the second lane. At each iteration j (which also represents the address or address component j), the second lane counter 508b provides the second lane conditional test operation 5101 with the address j for accessing the OVRs 504 and 506. In the system 500, the index "j" of the second lane is incremented by two. For example, by incrementing by two, the index "j" can open the OVR at the second position and then increment every other position, so that the second lane includes the odd-numbered positions of the OVRs 504 and 506 (e.g., j = 1, 3, 5, etc.). In some examples, the elements / outputs of the OVRs 504 and 506 at iteration or address j are compared to each other or to a value from another register, such as a scalar register (e.g., see method 300). The second channel condition test operation 5101 produces a single output, which is either TRUE or FALSE (eg, "1" or "0").

[0097] Conditional test operations 5100 and 5101 can be configured to perform test operations in steps 304a and 304b, respectively, or can be configured to perform test operations in steps 404a and 404b, respectively. In other words, first channel conditional test operation 5100 and second channel conditional test operation 5101 can be configured to be performed on the elements of the loaded operand vector based on corresponding counts stored in corresponding counter registers, such as counters 508a and 508b. Conditional test operations 5100 and 5101 can also be configured to identify a TRUE or FALSE result in steps 306a or 306b, respectively, or in steps 406a or 406b, respectively. In other words, conditional test operations 5100 and 5101 can be configured to identify whether the result of the conditional test operation is TRUE or FALSE. Conditional test operations 5100 and 5101 can be configured to output a TRUE or FALSE result, such as a "1" for a TRUE result or a "0" for a FALSE result. The output of each of the conditional test operations 5100 and 5101 is input into the corresponding write enable of each of VIR_TRUE 502a and VIR_FALSE 502b (e.g., see write enables 5120a, 5120b, 5121a, and 5121b). In other words, the system 500 includes a write enable 5120a for the first channel position of VIR_TRUE 502a, a write enable 5120b for the first channel position of VIR_FALSE 502b, a write enable 5121a for the second channel position of VIR_TRUE 502a, and a write enable 5121b for the second channel position of VIR_FALSE 502b.

[0098] The output from the first channel condition test operation 5100 can be directly passed to the write enable 5120a of VIR_TRUE 502a. The output from the first channel condition test operation 5100 can be indirectly passed to the write enable 5120b of VIR_FALSE 502b via an inverter 5140. Inverter 5140 is configured to invert the output of the first channel condition test operation 5100 before it reaches the write enable 5120b of VIR_FALSE 502b. For example, if the output of the first channel condition test operation 5100 is TRUE (e.g., "1"), then when the output is input into inverter 5140, the inverter inverts the value to FALSE (e.g., "0") and outputs FALSE. Similarly, the output from the second channel condition test operation 5101 can be directly passed to the write enable 5121a of VIR_TRUE 502a. The output from the second channel condition test operation 5101 may be passed indirectly to the write enable 5121b of VIR_FALSE 502b via inverter 5141. Inverter 5141 is configured to invert the output of the second channel condition test operation 5101 before it reaches the write enable 5121b of VIR_FALSE 502b.

[0099] System 500 also includes separate TRUE counters 5160a and 5160b for the first and second channels of VIR_TRUE 502a, and separate FALSE counters 5161a and 5161b for VIR_FALSE 502b. The outputs of conditional test operations 5100 and 5101 drive four counters: counters 5160a, 5160b, 5161a, and 5161b. Counters 5160a, 5160b, 5161a, and 5161b are separate from the first and second channel counters 508a and 508b that provide addresses i and j for OVRs 504 and 506. The outputs of TRUE counters 5160a and 5161a serve as the first and second channel addresses for accessing VIR_TRUE 502a. The outputs of FALSE counters 5160b and 5161b serve as the first and second channel addresses for accessing VIR_FALSE 502b. For example, when the output of the first channel condition test operation 5100 is TRUE, the output triggers write enable 5120a to write the current first channel position of OVRs 504 and 506 into VIR_TRUE 502a. Furthermore, for example, when the output of the first channel condition test operation 5100 is FALSE, the output triggers write enable 5120b to write the current first channel position from OVRs 504 and 506 into VIR_FALSE 502b. This functionality is provided via a circuit comprising an inverter 5140 and two write enables 5120a and 5120b. Furthermore, somewhat similar functionality can be provided for the second channel position of OVRs 504 and 506 via a circuit comprising an inverter 5141 and two write enables 5121a and 5121b.

[0100] The outputs of counters 2508a and 2508b also serve as the address or address component (or index) to be written into VIR_TRUE 502a at the address specified by first channel TRUE counter 5160a and second channel TRUE counter 5161a. This occurs when the output of test operations 5100 and 5101 is TRUE. In system 500, for each triggered TRUE output from test operations 5100 and 5101, respectively, the corresponding values stored in TRUE counters 5160a and 5161a are incremented by two. Similarly, the outputs of 508a and 508b also serve as the address or address component to be written into VIR_FALSE 502b at the address specified by first channel FALSE counter 5160b and second channel FALSE counter 5161b. This occurs when the output of test operations 5100 and 5101 is FALSE. In system 500, for each triggered FALSE output from test operations 5100 and 5101, respectively, the corresponding values stored in FALSE counters 5160b and 5161b are incremented by two. This overall functionality of selecting where to store the address of the OVR component is provided by circuitry that includes test operations 5100 and 5101, write enables 5120a, 5120b, 5121a, and 5121b, inverters 5140 and 5141, TRUE counters 5160a and 5161a, and FALSE counters 5160b and 5161b.

[0101] VIR_TRUE 502a and VIR_FALSE 502b are each output registers of system 500. System 500 may be part of a vector processor including a vector load store unit, such as Figure 2 Vector processor in .

[0102] System 500 is also shown as including a scalar register for vector length: vector length register 524 (VLR524). VLR 524 is configured to store the vector length (VL) of OVRs 504 and 506. The vector processor can load the VL from VLR 524 into memory to identify whether the count from one of counters 508a and 508b is equal to the VL of the corresponding operand vector stored in OVRs 504 and 506. In other words, a value is located in the register for the VL of the operand vector in OVRs 504 and 506. This is one way to implement, for example, step 314 of method 300 or step 414 of method 400. If one of the counts is less than VL, the count in the counter continues to increment per clock cycle or another trigger or iteration (e.g., see steps 312 or 412). By incrementing the count until one of the counts equals VL, the vector processor can store the positions of the elements of OVR 504 and 506, continuing until the position of the element of the OVR is stored in VIR_TRUE 502a or VIR_FALSE 502b. If one of the counts equals or exceeds VL, then the vector processor using system 500 has completed the construction of the index vector stored in VIR_TRUE 502a and VIR_FALSE 502b. When a new index vector is to be constructed, the counts in counters 508a and 508b (as well as the TRUE counter and the FALSE counter) are reset, and VL is determined and stored in VLR 524. The vector processor can initially determine the vector length of the OVR (e.g., the length of OVR 504 and 506), and then store the length in VLR 524 (which is a length) before performing method 300 or 400.

[0103] Figure 6 and 7 1 shows a method for using multiple channels and according to VIR_TRUE and VIR_FALSE (e.g., see Figure 8 802a and VIR_FALSE 802b) depicted in FIG. 6A and FIG. 6B illustrate example operations of method 600 for performing operations on elements of an operand vector.

[0104] Furthermore, the example operation of method 600 for performing operations on elements of an operand vector can be based on VIR_TRUE and VIR_FALSE accessed in parallel because, for example, according to some embodiments of the present disclosure, two occurrences of position i in VIR_TRUE and VIR_FALSE are accessed in the same clock cycle or iteration (not depicted). In such examples, the vector lengths VL_VIR_TRUE and VL_VIR_FALSE of VIR_TRUE and VIR_FALSE are not compared to a count, and the count is not reset during the execution of the operation on the operand vector. Furthermore, in such examples and other examples, step 616 can occur per clock cycle or iteration of the operation. Furthermore, in such examples where VIR is accessed in parallel, steps 606 to 612 and steps 620 to 626 can also be performed in parallel.

[0105] exist Figure 6 In step 602, method 600 begins by loading a first input operand vector stored in a first input OVR (e.g., see first OVR 804a) by a vector load store unit. The first input OVR may be a dual access OVR. In step 604, method 2100 continues by loading a second input operand vector stored in a second input OVR (e.g., see second OVR 804b) by a vector load store unit. The second input OVR may be a dual access OVR. In step 606, method 600 continues by loading a first channel count and a second channel count from corresponding counters (e.g., see first channel counter 806a and second channel counter 806b) by a vector load store unit. In some embodiments, the even-numbered positions in the vector are located in the first channel and the odd-numbered positions are located in the second channel.

[0106] In step 608a, the method 600 continues with the vector load store unit loading the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to the first lane count. In step 608b, the method 600 continues with the vector load store unit loading the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_TRUE according to the second lane count. Figure 6 As shown in , steps 608a and 608b may be performed in parallel or simultaneously.

[0107] In step 610, method 600 continues by performing a first operation (e.g., addition) on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_TRUE. Step 610 includes step 612, which includes method 600 continuing by storing results of the first operation (e.g., results from the first lane and second lane ALUs (see first lane ALU 814a and second lane ALU 814b)) in output OVRs (e.g., see output OVR 810) at locations corresponding to the loaded locations from the first lane and the second lane in VIR_TRUE.

[0108] In step 614, method 600 continues by incrementing each of the first channel count and the second channel count by two. In step 616, method 600 continues by comparing the first channel count and the second channel count to a value representing the vector length of VIR_TRUE, i.e., VL_VIR_TRUE, so that the first operation can iterate on the loaded first input operand vector and the loaded second input operand vector stored in the input operand vector register for each of the positions stored in VIR_TRUE. When one of the counts equals or exceeds the vector length of VIR_TRUE, method 600 continues in step 618 by resetting the first channel count and the second channel count in the corresponding count register.

[0109] It should be understood that VL_VIR_TRUE and VL_VIR_FALSE are pre-loaded with the vector lengths of VIR_TRUE and VIR_FALSE prior to initiating method 600. In some embodiments, VL_VIR_TRUE and VL_VIR_FALSE are loaded with the lengths of the vectors in VIR_TRUE and VIR_FALSE, while VIR_TRUE and VIR_FALSE are loaded with vector index elements.

[0110] When the count is less than the vector length, in step 616, method 600 continues by returning to step 606 (loading the first lane count and the second lane count), which is followed by steps 608a and 608b (loading the stored location from VIR_TRUE) and step 610 (performing the first operation on the elements of the loaded input operand vector). In this way, the first operation is iterated on the input OVR for each of the first lane location and the second lane location stored in VIR_TRUE.

[0111] Subsequently, in step 620, method 600 continues by loading the first channel count and the second channel count stored in the corresponding counter registers by the vector load store unit. In an example using VIR_TRUE and VIR_FALSE, the value of the first channel count in the first iteration of step 620 may be "0", and the value of the second channel count in the first iteration of step 620 may be "1". As shown, in step 628, the count is incremented by two, so in such an example, the next value of the first channel count may be "2", and the next value of the second channel count may be "3".

[0112] In step 622a, the method 600 continues with the vector load store unit loading the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the first lane count. In step 622b, the method 600 continues with the vector load store unit loading the stored locations of the corresponding elements of the loaded first input operand vector and the loaded second input operand vector from VIR_FALSE according to the second lane count.

[0113] In step 624, method 600 continues by performing a second operation (e.g., a subtraction) on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded locations from the first lane and the second lane in VIR_FALSE. Step 624 includes step 626, which includes method 600 continuing by storing results of the second operation (e.g., results from corresponding ALUs of the first lane and the second lane) in the output OVR at locations corresponding to the loaded locations from the first lane and the second lane in VIR_FALSE.

[0114] In step 628, method 600 continues by incrementing each of the first lane count and the second lane count by two. In step 630, method 600 continues by comparing the counts to a value representing the vector length of VIR_FALSE, i.e., VL_VIR_FALSE, so that the first operation can iteratively continue on the loaded first input operand vector and the loaded second input operand vector stored in the input operand vector register for each of the locations stored in VIR_FALSE. When at least one of the counts equals or exceeds the vector length of VIR_FALSE, method 600 ends. When both the first lane count and the second lane count are less than the vector length, in step 630, method 600 continues by returning to step 620 (loading the counts), which is followed by steps 622a and 622b (loading the locations from VIR_FALSE) and step 624 (performing the second operation on the elements of the loaded input operand vector). In this way, the second operation is iterated on the input OVR for each of the first channel position and the second channel position stored in VIR_FALSE.

[0115] In the methods described herein, the first operation may include addition, subtraction, multiplication, division, or any other type of operation that can be performed by one or more ALUs. Also, the second operation may include an operation different from the first operation that can be performed by one or more ALUs.

[0116] Figure 8 An example system 800 is shown including VIR_TRUE 802a and VIR_FALSE 802b for performing a first operation and a second operation on elements of an input operand vector stored in input operand vector registers 804a and 804b in multiple lanes according to some embodiments of the present disclosure. Example system 800 is one example of a system that can implement at least method 600.

[0117] As shown, VIR_TRUE 802a and VIR_FALSE 802b are dual-access VIRs. Thus, two addresses in each of the VIRs can be accessed in parallel (e.g., in one clock cycle). As shown, address "i" and address "j" from the first channel counter and the second channel counter, respectively, can be input into the two dual-access VIRs. Furthermore, VIR_TRUE 802a and VIR_FALSE 802b can each output the stored first channel element and the stored second channel element in parallel (e.g., in one clock cycle).

[0118] System 800 also includes input OVRs 804a and 804b. The input OVRs are dual-access OVRs in system 800. System 800 also includes output operand registers 810, which are also dual-access OVRs. Generally speaking, first-channel ALUs 814a and second-channel ALUs 814b can receive first-channel inputs and second-channel inputs from input OVRs 804a and 804b and output the results of numerical operations performed by the ALUs to output OVRs 810.

[0119] System 800 also includes a first channel counter 806a that outputs an index “i” and a second channel counter that outputs an index “j.” Index i can be used as the first channel count in method 600. Index j can be used as the second channel count in method 600.

[0120] System 800 also includes a first channel multiplexer 808a and a second channel multiplexer 808b. Each of multiplexers 808a and 808b can operate in a normal mode, a TRUE mode, and a FALSE mode. Multiplexers 808a and 808b allow the TRUE mode to be switched to the FALSE mode after resetting the first and second channel counters in method 600. First channel multiplexer 808a receives inputs from first channel counter 806a, the first channel of VIR_TRUE 802a, and the first channel of VIR_FALSE 802b. Multiplexer 808a outputs one of the three inputs depending on its mode. Second channel multiplexer 808b receives inputs from second channel counter 806b, the second channel of VIR_TRUE 802a, and the second channel of VIR_FALSE 802b. Multiplexer 808b outputs one of the three inputs depending on its mode.

[0121] System 800 also includes registers for vector lengths for VIR_TRUE 802a and VIR FALSE 802b. The vector lengths may be used in steps 616 and 630 of method 600, respectively.

[0122] The system 800 also includes an ALU for each channel in the dual-channel processing (e.g., a first channel ALU 814a and a second channel ALU 814b). The ALUs 814a and 814b can perform subtraction, multiplication, division, or any other type of operation that can be performed by one or more ALUs based on an opcode (e.g., opcodes 816a and 816b) received via a multiplexer 818. As shown, the output of the multiplexer 818 can be received by both the ALUs 814a and 814b.

[0123] exist Figure 8In the example system 800, VIR_TRUE 802a stores a list of the locations of input OVRs 804a and 804b. For example, "1" is stored in position "0" of VIR_TRUE 802a, which can be used as an address to access position "1" in both input OVRs 804a and 804b. In the example system 800, position "0" of VIR_TRUE, as well as positions "2," "4," and so on, are located in the first channel of VIR_TRUE. Furthermore, the other positions of VIR_TRUE are located in the second channel of VIR_TRUE. Furthermore, VIR_TRUE 802b stores a list of the locations of input OVRs 804a and 804b. For example, "0" and "2" are stored in positions "0" and "1" of VIR_FALSE 802b, respectively. These positions "0" and "1" can be used as addresses to access positions "0" and "2" in both input OVRs 804a and 804b. In the example system 800 , position “0” of VIR_FALSE, as well as positions “2”, “4”, etc., are located in the first channel of VIR_FALSE. Also, the other positions of VIR_FALSE are located in the second channel of VIR_FALSE.

[0124] exist Figure 8 In this illustrated example, the vector processor is shown performing at least two iterations of a subtraction operation and at least one iteration of an addition operation. During the first iteration of the at least two cycles of the subtraction operation, counter 806a outputs a count of "0," which is the value stored in the counter during the first cycle of the subtraction mode. During the first cycle of the subtraction mode, VIR_FALSE 802b is shown outputting the selected address "0" from position "0" of VIR_FALSE. During the first iteration of the at least one cycle of the addition operation, counter 806a also outputs a count of "0," which is the value stored in the counter during the first cycle of the addition mode. During the first cycle of the addition mode, VIR_TRUE 802a is shown outputting the selected address "1" from position "0" of VIR_TRUE. Because position "0" in both VIRs is a first-channel position and the OVR is a dual-access OVR, subtraction and addition can occur in parallel within the first channel during the first clock cycle.

[0125] The first channel multiplexer 808a selects between the address component ("0") as specified by the counter 806a in the NORMAL mode of operation, or the address component ("1") as stored in position "0" of the VIR_TRUE 802a in the TRUE mode of operation, or the address component ("0") as stored in position "0" of the VIR_FALSE 802b in the FALSE mode of operation. As mentioned, position "0" is the first channel position in the example; therefore, the first channel multiplexer 808a is used. In the second channel processing, when the initial count in the second channel counter 806b is "1", the second channel multiplexer 808b selects between the address component ("1") as specified by the counter in the NORMAL mode of operation, or the address component ("5") stored in position "1" of VIR_TRUE 802a in the TRUE mode of operation, or the address component ("2") stored in position "1" of VIR_FALSE 802b in the FALSE mode of operation, and so on. As mentioned, position "1" is the second channel position in the example; therefore, the second channel multiplexer 808b is used. In other words, the first channel multiplexer 808a and the second channel multiplexer 808b select between the outputs of the counters 806a and 808b, respectively, between the first channel and the second channel in VIR_TRUE 802a, and between the first channel and the second channel in VIR_FALSE 802b, respectively. Furthermore, the outputs provided by the first channel in VIR_TRUE 802a and VIR_FALSE 802b are based on the count of the first channel counter 806a. The outputs provided by the second channel in VIR_TRUE 802a and VIR_FALSE 802b are based on the count of the second channel counter 806b.

[0126] In method 600, multiplexers 808a and 808b can implement a switch from TRUE mode to FALSE mode after resetting the counters in step 618. Counters 806a and 806b are reset when one of the counts equals or exceeds the vector length of VIR_TRUE or VIR_FALSE (e.g., see VL_VIR_TRUE 812a and VL_VIR_FALSE 812b). This switch allows the loop of steps 606 to 616 to switch to the loop of steps 620 to 630.

[0127] It should be understood that the selections described herein may be according to programmer visible instructions and / or may be hard-wired circuitry that performs some high-level semantic operations.

[0128] When multiplexer 808a selects TRUE mode, in the first channel during the first cycle, the "1" output from VIR_TRUE 802a is the address component used to access input OVRs 804a and 804b. Thus, the corresponding outputs of element "30" at position "1" of input OVR 804a and element "25" at position "1" of input OVR 804b access input OVRs 804a and 804b. Output OVR 810 (or the third OVR) is also addressed at position "1." In this example, position "1" is output by first channel multiplexer 808a, which has been selected for TRUE mode. Furthermore, during the first cycle in TRUE mode, since position "1" in the OVR is the second channel position of the OVR, second channel ALU 814b performs an addition operation. For example, the first channel position of an OVR is position "0," "2," "4," and so on. In such examples, the second channel position of the OVR is position "1," "3," "5," and so on. In the first example, when in the first channel of the VIR and the first cycle of the counter 806a, the addition operation is based on the first opcode 816a selected by the multiplexer 818 in the TRUE mode. The output of the opcode is output 819, which can be input to both the first channel ALU 814a and the second channel ALU 814b. Specifically, as shown, the elements of the input OVRs 804a and 804b at position "1" (elements "30" and "25") are input to the second channel ALU 814b. The second channel ALU 814 adds the elements of position "1" of the OVRs 804a and 804b and outputs the result of the addition operation. The output of the addition operation is then stored at position "1" of output OVR 810 as element "55" (A(1)+B(1)=C(1) or 30+25=55).

[0129] When multiplexer 808a selects FALSE mode, in the first cycle in the first channel, the output of "0" from VIR_FALSE 802a is the address component used to access input OVRs 804a and 804b. Thus, input OVRs 804a and 804b are accessed for the corresponding outputs of element "10" at position "0" of input OVR 804a and element "20" at position "0" of input OVR 804b. As mentioned, position "0" in this example is the first channel position. Output OVR 810 (or the third OVR) is also addressed at position "0." In this example, position "0" is output by first channel multiplexer 808a, which has been selected for FALSE mode. Furthermore, in FALSE mode, since position "0" in the OVR is the first channel position of the OVR, first channel ALU 814a performs a subtraction operation. The subtraction operation is based on the second opcode 816b selected by multiplexer 818 in FALSE mode. The output of the opcode is output 819, which can be input to both the first lane ALU 814a and the second lane ALU 814b. Specifically, as shown, the elements of input OVRs 804a and 804b at position "0" (elements "10" and "20") are input to the first lane ALU 814a. The first lane ALU 814a subtracts the element at position "0" of OVR 804b from the element at position "0" of OVR 804a and outputs the result of the subtraction operation. The output of the subtraction operation is then stored at position "0" of output OVR 810 as element "-10" (A(0)-B(0)=C(0) or 10-20=-10).

[0130] It should be understood that Figure 8 The addition and subtraction operations shown in FIG are merely examples, and various operations may be performed on OVRs 804 a and 804 b depending on the addressing of VIRs 802 a and 802 b. Thus, first opcode 816 a may be an opcode for any arithmetic operation of the ALU, and second opcode 816 b may also be an opcode for any arithmetic operation of the ALU.

[0131] As mentioned, the system 800 may implement the method 600. For example, in the case where one or more operand vectors are loaded by a vector load store unit of a vector processor (in steps 602 and 604), each of the one or more operand vectors may be stored in OVRs 804a and 804b. In the case where a first channel count and a second channel count stored in respective counter registers are loaded by the vector load store unit, the counts may be stored in respective first channel counters 806a and second channel counters 806b. In the case where a stored location is loaded from a VIR by a vector load store unit of a vector processor (in steps 608a and 608b and steps 622a and 622b), the location may be stored in VIRs 802a and 802b. Execution of the first operation and the second operation in two channels in steps 610 and 624 may be performed by Figure 8 Storing the results of the operations in both channels (in steps 612 and 626) may occur at the output OVR 810. Furthermore, loops in method 600 may be controlled based on at least the lengths stored in registers 812a and 812b.

[0132] Methods 300 , 400 , and 600 include only some of the many operations that may be performed by the vector processors and systems described herein.

[0133] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. At times, primarily for common purposes, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0134] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0135] The present disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0136] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will be presented as set forth in the following description. Furthermore, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0137] The present disclosure may be provided in part as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0138] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: loading one or more operand vectors by a vector load store unit of a vector processor, each vector of the one or more operand vectors being stored in a corresponding operand vector register; performing, by the vector processor, a conditional test operation on each element at a first lane index position of at least one of the loaded one or more operand vectors based on a first lane count stored in a first lane counter register, the conditional test operation providing a test result vector; storing, based on the first channel count, a position of each TRUE result in the conditional test operation in the test result vector in a first channel index position in a first vector index register for the TRUE result; storing, based on the first channel count, a position of each FALSE result in the conditional test operation in the test result vector in a first channel index position in a second vector index register for the FALSE result; performing, by the vector processor, the conditional test operation on each element at a second lane index position of at least one of the loaded one or more operand vectors based on a second lane count stored in a second lane counter register; storing a position of the TRUE result in the test result vector in a second channel index position in the first vector index register based on the second channel count; as well as The position of the FALSE result in the test result vector is stored in a second channel index position in the second vector index register according to the second channel count. 2 . The method of claim 1 , wherein even positions in each operand vector are located in the first lane and odd positions in each operand vector are located in the second lane. 3 . The method of claim 1 , wherein each respective operand vector register is a dual access operand vector register.

4. The method according to claim 1, further comprising: performing a first vector operation on a first element of the one or more operand vectors, the first element being identified by a position stored in the first vector index register; as well as A second vector operation is performed on a second element in the one or more operand vectors, the second element being identified by a location stored in the second vector index register.

5. The method according to claim 1, further comprising: loading, by the vector load-store unit, a first input operand vector stored in a first input operand vector register; loading, by the vector load-store unit, a second input operand vector stored in a second input operand vector register; loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the first vector index register according to the first lane count; loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the first vector index register according to the second lane count; as well as A first operation is performed on the corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the first vector index register.

6. The method of claim 5, wherein the first input operand vector register is a dual access operand vector register, and wherein the second input operand vector register is a dual access operand vector register.

7. The method of claim 5, further comprising storing a result of the first operation in an output operand vector register at a location corresponding to the loaded locations of the first lane and the second lane from the first vector index register.

8. The method according to claim 7, further comprising: continuing to perform the first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the first vector index register and storing the results of the first operation in the output operand vector register at corresponding positions matching the loaded positions from the first vector index register until the first lane count or the second lane count exceeds or equals the length of the first vector index register; as well as When the first channel count or the second channel count exceeds or equals the length of the first vector index register, the first channel count and the second channel count are reset. 9 . The method of claim 8 , wherein the first lane count and the second lane count are each incremented by two per loaded position from the first vector index register.

10. The method according to claim 8, further comprising: After resetting the first channel count and the second channel count: loading, by the vector load-store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the second vector index register according to the first lane count; as well as loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the second vector index register according to the second lane count; as well as A second operation is performed on the corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the second vector index register.

11. The method according to claim 10, further comprising: Continuing to perform the second operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the second vector index register and storing the results of the first operation in the output operand vector register at corresponding positions that match the loaded positions from the second vector index register until the first lane count or the second lane count exceeds or equals the length of the second vector index register. 12 . The method of claim 11 , wherein the first lane count and the second lane count are each incremented by two per loaded position from the second vector index register.

13. The method of claim 11, wherein the first operation comprises addition and the second operation comprises subtraction.

14. A system comprising: a vector processor configured to perform a conditional test operation on elements of a first loaded operand vector and a second loaded operand vector using two lanes within each of the first loaded operand vector and the second loaded operand vector; a first channel counter of the vector processor configured to store a first channel count; a second channel counter of the vector processor configured to store a second channel count, and wherein the conditional test operation performed by the vector processor is based on the first channel count and the second channel count; one or more operand vector registers of the vector processor, each operand vector register configured to store an operand vector; a first vector index register for each TRUE result of the conditional test operation; as well as a second vector index register for each FALSE result of the conditional test operation, and wherein the vector processor is configured to: loading one or more operand vectors from the one or more operand vector registers; performing the conditional test operation on each element at a first lane index position of at least one of the loaded one or more operand vectors according to the first lane count stored in the first lane counter; as well as performing the conditional test operation on each element at a second lane index position of at least one of the loaded one or more operand vectors according to the second lane count stored in the second lane counter, the conditional test operation providing a test result vector; storing, based on the first channel count, a position of the TRUE result in the test result vector in a first channel index position in the first vector index register; storing, based on the first channel count, a position of the FALSE result in the test result vector in a first channel index position in the second vector index register; storing a position of the TRUE result in the test result vector in a second channel index position in the first vector index register based on the second channel count; as well as The position of the FALSE result in the test result vector is stored in a second channel index position in the second vector index register according to the second channel count. 15 . The system of claim 14 , wherein even positions in each operand vector are located in the first lane and odd positions in each operand vector are located in the second lane.

16. The system of claim 14, wherein each operand vector register is a dual access operand vector register.

17. The system of claim 14, wherein the vector processor is further configured to: loading, by a vector load-store unit of the vector processor, a first input operand vector stored in a first input operand vector register; loading, by the vector load-store unit, a second input operand vector stored in a second input operand vector register; loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the first vector index register according to the first lane count; loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the first vector index register according to the second lane count; performing a first operation on the corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the first vector index register; and A result of the first operation is stored in an output operand vector register at a location corresponding to the loaded location of the first lane and the second lane from the first vector index register.

18. The system of claim 17, wherein the first input operand vector register and the second input operand vector register are dual access operand vector registers, and wherein the vector processor is further configured to: continuing to perform the first operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the first vector index register and storing the results of the first operation in the output operand vector register at corresponding positions that match the loaded positions from the first vector index register until the first lane count or the second lane count exceeds or equals the length of the first vector index register; and The first and second lane counts are reset when the first and second lane counts exceed or equal the length of the first vector index register, wherein the first and second lane counts are each incremented by two per loaded position from the first vector index register.

19. The system of claim 18, wherein the vector processor is further configured to: After resetting the first channel count and the second channel count: loading, by the vector load-store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the second vector index register according to the first lane count; as well as loading, by the vector load store unit, the stored locations of corresponding elements of the loaded first input operand vector and the loaded second input operand vector from the second vector index register according to the second lane count; performing a second operation on the corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the second vector index register; as well as Continuing to perform the second operation on corresponding elements of the loaded first input operand vector and the loaded second input operand vector according to the loaded positions of the first lane and the second lane from the second vector index register and storing the results of the first operation in the output operand vector register at the corresponding positions that match the loaded positions from the second vector index register until the first lane count or the second lane count exceeds or equals the length of the second vector index register, wherein the first lane count and the second lane count are each incremented by two from each loaded position of the second vector index register.

20. A vector processor comprising: an operand scalar register configured to store an element to be used as an input to an operation of the arithmetic logic unit; a first operand vector register and a second operand vector register of the plurality of operand vector registers, Each operand vector register is configured to store an element of an operand vector to be used as an input to an operation of the arithmetic logic unit, Each operand vector register is a multiple access operand vector register, The vector processor is configured to perform any one of the following operations: performing a conditional test operation on elements of the first operand vector register and the second operand vector register according to a plurality of lane counts for a multi-lane process stored in a plurality of corresponding lane count registers, or performing the conditional test operation on elements stored in the operand scalar register and elements of the first operand vector register according to the plurality of lane counts, and The conditional test operation provides a test result vector; a first vector index register configured to store positions of TRUE results in the test result vector in index positions of different channels in the first vector index register according to the plurality of channel counts; as well as A second vector index register is configured to store positions of FALSE results in the test result vector in index positions of different channels in the second vector index register according to the plurality of channel counts.

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