Display panel, driving method and display device

Abstract

A display panel, a driving method and a display device, wherein the display panel comprises: a substrate (1000), a plurality of sub-pixels (spx), a plurality of driving lines, a plurality of data lines, and a gate driving circuit (01), comprising: a plurality of clock signal lines and a plurality of shift register units (SR2n‑3, SR2n‑2, SR2n‑1, SR2n, SR2n+1, SR2n+2, SR2n+3, SR2n+4) arranged in sequence along an extension direction (F1) of the clock signal lines; the plurality of clock signal lines are divided into a plurality of clock signal line groups; the plurality of shift register units (SR2n‑3, SR2n‑2, SR2n‑1, SR2n, SR2n+1, SR2n+2, SR2n+3, SR2n+4) are arranged in sequence along an extension direction (F1) of the clock signal lines. SR2n+4) is divided into a plurality of register unit groups; the shift register units in the same register unit group are cascaded, and two shift register units (SR2n‑3, SR2n‑2, SR2n‑1, SR2n, SR2n+1, SR2n+2, SR2n+3, SR2n+4) adjacent to each other along the extension direction (F1) of the clock signal line are located in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of the input transistor (M1) is electrically connected to a clock signal line in the corresponding clock signal line group, the second electrode of the input transistor (M1) is electrically connected to the gate of the output transistor (M3); the second electrode of the output transistor (M3) is electrically connected to at least one driving line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving method and a display device. Background Art

[0002] With the rapid development of display technology, display devices have shown a development trend of high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) gate drive circuits on the substrate of the display panel to form a scan drive for the display panel, thereby eliminating the wiring space of the bonding area of ​​the gate integrated circuit (IC) and the fan-out area, reducing product costs. Summary of the invention

[0003] The display panel provided by the embodiment of the present disclosure includes:

[0004] A substrate, comprising a display area and a non-display area;

[0005] The display area includes:

[0006] A plurality of sub-pixels are arranged in a matrix along a plurality of rows and a plurality of columns;

[0007] A plurality of driving lines, wherein a row of sub-pixels is electrically connected to at least one of the driving lines;

[0008] A plurality of data lines, wherein a column of the sub-pixels is electrically connected to at least one of the data lines;

[0009] The non-display area includes:

[0010] A gate driving circuit, comprising: a plurality of clock signal lines, and a plurality of shift register units sequentially arranged along the extending direction of the clock signal lines; wherein the plurality of clock signal lines are divided into a plurality of clock signal line groups;

[0011] The plurality of shift register units are divided into a plurality of register unit groups; the shift register units in the same register unit group are cascaded, and two shift register units adjacent to each other along the extension direction of the clock signal line are located in different register unit groups; and different register unit groups correspond to different clock signal line groups;

[0012] Each of the shift register units includes an input transistor and an output transistor; wherein the gate of the input transistor is electrically connected to a clock signal line in the corresponding clock signal line group, the first electrode of the input transistor is electrically connected to the input signal terminal, and the second electrode of the input transistor is electrically connected to the gate of the output transistor; the second electrode of the output transistor is electrically connected to at least one driving line.

[0013] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0014] A semiconductor layer, located on the substrate, and the semiconductor layer includes an active layer of the input transistor and an active layer of the output transistor; the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region;

[0015] A gate insulating layer, located on a side of the semiconductor layer away from the substrate;

[0016] a first conductive layer, located on a side of the gate insulating layer away from the base substrate, and comprising the plurality of driving lines, the plurality of first connecting lines, the plurality of second connecting lines, the gate of the input transistor and the gate of the output transistor; one shift register unit corresponds to at least one of the first connecting lines and at least one of the second connecting lines;

[0017] A first insulating layer, located on a side of the first conductive layer away from the substrate;

[0018] The second conductive layer is located on the side of the first insulating layer away from the base substrate, and the second conductive layer includes the plurality of data lines, the plurality of clock signal lines and a plurality of first transfer parts; wherein one of the first transfer parts is electrically connected to a source region of the active layer of one of the output transistors; the second conductive layer also includes: a first power line;

[0019] For one of the shift register units and the clock signal line group corresponding to the shift register unit, one end of the first connection line is directly electrically connected to the gate of the input transistor in the shift register unit, the other end of the first connection line is electrically connected to a clock signal line in the clock signal line group through a first via hole, one end of the second connection line is electrically connected to the first transfer portion through a second via hole, and the other end of the second connection line is electrically connected to another clock signal line in the clock signal line group or the first power line through a third via hole;

[0020] The first via hole, the second via hole and the third via hole penetrate the first insulating layer and are arranged at intervals.

[0021] Optionally, in an embodiment of the present disclosure, the plurality of clock signal lines are divided into two clock signal line groups, the two clock signal line groups include a first clock signal line group and a second clock signal line group; wherein the first clock signal line group includes a first clock signal line and a second clock signal line, and the second clock signal line group includes a third clock signal line and a fourth clock signal line;

[0022] The plurality of shift register units are divided into two register unit groups, the two register unit groups include a first register unit group and a second register unit group, wherein the first register unit group includes odd-numbered shift register units sequentially arranged along the extension direction of the clock signal line, and the second register unit group includes even-numbered shift register units sequentially arranged along the extension direction of the clock signal line;

[0023] For the multiple shift register units cascaded in the first register unit group, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the first clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the second clock signal line or the first power line through the corresponding second connection line; and the gate of the input transistor of the even-numbered shift register unit is electrically connected to the second clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the first clock signal line or the first power line through the corresponding second connection line;

[0024] For the multiple shift register units cascaded in the second register unit group, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the third clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the fourth clock signal line or the first power line through the corresponding second connection line; and, the gate of the input transistor of the even-numbered shift register unit is electrically connected to the fourth clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the third clock signal line or the first power line through the corresponding second connection line.

[0025] Optionally, in the embodiment of the present disclosure, each of the shift register units further includes a voltage stabilizing transistor; wherein the second electrode of the input transistor is electrically connected to the first electrode of the voltage stabilizing transistor, and the second electrode of the voltage stabilizing transistor is electrically connected to the gate of the output transistor;

[0026] The second conductive layer further includes: a first power line; the gate of each of the voltage-stabilizing transistors is electrically connected to the first power line through a fourth via hole; wherein the fourth via hole penetrates the first insulating layer.

[0027] Optionally, in the embodiment of the present disclosure, in the same gate driving circuit, the orthographic projection of the input transistor on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate;

[0028] The orthographic projection of the voltage stabilizing transistor on the substrate is located on a side of the orthographic projection of the first power line on the substrate away from the orthographic projection of the plurality of clock signal lines on the substrate;

[0029] The orthographic projection of the output transistor on the substrate is located on a side of the orthographic projection of the voltage stabilizing transistor on the substrate away from the orthographic projection of the first power line on the substrate.

[0030] Optionally, in the embodiment of the present disclosure, the shift register unit further includes a first control transistor and a second control transistor;

[0031] The semiconductor layer further includes an active layer of the first control transistor and an active layer of the second control transistor;

[0032] The first conductive layer further includes: a gate of the first control transistor and a gate of the second control transistor;

[0033] The second conductive layer further includes: a second power line, a plurality of second transfer parts, and a plurality of third transfer parts; wherein one second transfer part corresponds to one first control transistor, and one third transfer part corresponds to one second control transistor;

[0034] Furthermore, the display panel further includes:

[0035] a fourth conductive layer, located between the first insulating layer and the second conductive layer, and comprising a plurality of first conductive portions; wherein one first conductive portion corresponds to one second control transistor;

[0036] a third insulating layer, located between the fourth conductive layer and the second conductive layer;

[0037] wherein the gate of the first control transistor is directly electrically connected to the corresponding first connection line, the source region of the active layer of the first control transistor is electrically connected to the first power line through a fifth via hole, and the drain region of the active layer of the first control transistor is electrically connected to the gate of the second control transistor through the corresponding second transfer portion; wherein the fifth via hole passes through the first insulating layer and the third insulating layer;

[0038] The source region of the active layer of the second control transistor is electrically connected to one end of the corresponding third transfer portion through a sixth via, the other end of the third transfer portion is electrically connected to one end of the corresponding first conductive portion through a seventh via, the other end of the first conductive portion is electrically connected to the second power line through an eighth via, and the drain region of the active layer of the second control transistor is shared with the drain region of the active layer of the output transistor; wherein the sixth via passes through the first insulating layer and the third insulating layer, and the seventh via and the eighth via pass through the third insulating layer.

[0039] Optionally, in an embodiment of the present disclosure, the orthographic projection of the second power line on the base substrate is located between the orthographic projection of the plurality of clock signal lines on the base substrate and the orthographic projection of the gate driving circuit on the base substrate;

[0040] In the shift register unit, the orthographic projection of the first control transistor on the substrate is located between the orthographic projection of the input transistor on the substrate and the orthographic projection of the first power line on the substrate;

[0041] In the shift register unit, the orthographic projection of the second control transistor on the substrate is located on a side of the orthographic projection of the input transistor on the substrate away from the orthographic projection of the first power line on the substrate.

[0042] Optionally, in an embodiment of the present disclosure, in the shift register unit, the active layer of the output transistor and the active layer of the second control transistor are arranged in an integrated structure.

[0043] Optionally, in the embodiment of the present disclosure, the shift register unit further includes: a first capacitor and a second capacitor; wherein a first electrode of the first capacitor is electrically connected to the second power line, and a second electrode of the first capacitor is electrically connected to a gate of the second control transistor; a first electrode of the second capacitor is electrically connected to a second electrode of the output transistor, and a second electrode of the second capacitor is electrically connected to the gate of the output transistor;

[0044] The fourth conductive layer further includes a plurality of second conductive portions; wherein one second conductive portion corresponds to one output transistor;

[0045] The orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the gate of the second control transistor on the base substrate have an overlapping area, and the first conductive portion serves as a first electrode of the first capacitor, and the gate of the second control transistor serves as a second electrode of the first capacitor;

[0046] The orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the corresponding gate of the output transistor on the base substrate have an overlapping area, and the second conductive portion serves as the first electrode of the second capacitor, and the gate of the output transistor serves as the second electrode of the second capacitor.

[0047] Optionally, in the embodiment of the present disclosure, the orthographic projection of the gate of the second control transistor on the base substrate covers the orthographic projection of the first conductive portion on the base substrate.

[0048] Optionally, in the embodiment of the present disclosure, the orthographic projection of the gate of the second control transistor on the base substrate and the orthographic projection of the first conductive portion on the base substrate respectively have overlapping areas with the orthographic projection of the first power line on the base substrate.

[0049] Optionally, in the embodiment of the present disclosure, the orthographic projection of the eighth via on the substrate substrate is located between the orthographic projection of the first power line and the second power line on the substrate substrate, and the orthographic projection of the seventh via on the substrate substrate is located between the orthographic projection of the first power line on the substrate substrate and the orthographic projection of the active layer of the second control transistor on the substrate substrate.

[0050] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0051] A second insulating layer is located on a side of the second conductive layer away from the base substrate;

[0052] A third conductive layer is located on a side of the second insulating layer away from the substrate, and the second conductive layer includes: at least one auxiliary line;

[0053] One of the auxiliary lines is electrically connected to one of the clock signal lines through at least one ninth via hole, and the ninth via hole passes through the second insulating layer.

[0054] Optionally, in the embodiment of the present disclosure, the orthographic projection of the clock signal line on the base substrate covers the orthographic projection of the auxiliary line of electrical connection on the base substrate.

[0055] The embodiment of the present disclosure also provides a display device, including the above-mentioned display panel.

[0056] The embodiment of the present disclosure further provides a method for driving the display panel, including:

[0057] Within a frame scanning time, each of the shift register units is controlled to work sequentially to scan each of the drive lines row by row; wherein the odd-numbered shift register units and the even-numbered shift register units arranged in sequence along the extension direction of the clock signal line are independently driven under the control of different clock signal line groups.

[0058] The embodiment of the present disclosure further provides a method for driving the above-mentioned display panel, comprising: the time during which the signals applied to multiple clock signal lines in different clock signal line groups maintain valid levels does not overlap with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Structural schematic diagrams of some display panels provided by embodiments of the present disclosure;

[0060] Figure 2 A schematic diagram of the structure of a pixel driving circuit in some sub-pixels provided in an embodiment of the present disclosure;

[0061] Figure 3 Signal timing diagrams of some pixel driving circuits provided by embodiments of the present disclosure;

[0062] Figure 4a A schematic diagram of the structure of some shift register units provided in the embodiments of the present disclosure;

[0063] Figure 4b Signal timing diagrams of some shift register units provided in the embodiments of the present disclosure;

[0064] Figure 4c A timing diagram of signals output by some gate drive circuits provided in the embodiments of the present disclosure;

[0065] Figure 5a A schematic diagram of the structure of some other shift register units provided by the embodiments of the present disclosure;

[0066] Figure 5b Signal timing diagrams of other shift register units provided by embodiments of the present disclosure;

[0067] Figure 6 A schematic diagram of the layout structure of some gate drive circuits provided in the embodiments of the present disclosure;

[0068] Figure 7a A schematic diagram of the layout structure of some semiconductor layers provided in the embodiments of the present disclosure;

[0069] Figure 7b Schematic diagram of layout structure of some gate conductive layers provided in the embodiments of the present disclosure;

[0070] Figure 7c Schematic diagrams of layout structures of some fourth conductive layers provided in embodiments of the present disclosure;

[0071] Figure 7d Schematic diagram of the layout structure of some second conductive layers provided in the embodiments of the present disclosure;

[0072] Figure 8a for Figure 6A schematic cross-sectional view of the layout structure along the AA' direction in the schematic diagram shown;

[0073] Figure 8b for Figure 6 A schematic cross-sectional view of the layout structure along the BB' direction shown;

[0074] Fig. 9 Schematic diagrams of layout structures of some other gate drive circuits provided in the embodiments of the present disclosure;

[0075] Fig.10 Schematic diagram of the layout structure of some third conductive layers provided in the embodiments of the present disclosure;

[0076] Fig.11 for Fig. 9 A schematic cross-sectional view of the layout structure along the AA' direction in the schematic diagram shown;

[0077] Fig.12 Signal timing diagrams of some further shift register units provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0080] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0081] like Figure 1 As shown, the display panel provided by the embodiment of the present disclosure may include: a substrate 1000. The substrate 1000 may include a display area AA and a non-display area BB. The non-display area BB may surround the display area. The display area AA may include a plurality of pixel units PX, and the pixel unit PX may include a plurality of sub-pixels spx. The plurality of sub-pixels spx are arranged along a plurality of rows and a plurality of columns in a matrix.

[0082] For example, in combination Figure 1 and Figure 2 As shown, at least one sub-pixel spx among the multiple sub-pixels spx may include: a pixel driving circuit 0121 and a light-emitting device 0120. The pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction between the transistor and the capacitor, and the generated electrical signal is input into the first electrode of the light-emitting device 0120. And a corresponding voltage is applied to the second electrode of the light-emitting device 0120, so that the light-emitting device 0120 can be driven to emit light.

[0083] Combination Figure 2 As shown, the pixel driving circuit 0121 may include: a driving control circuit 0122 , a first light emitting control circuit 0123 , a second light emitting control circuit 0124 , a data writing circuit 0126 , a storage circuit 0127 , a threshold compensation circuit 0128 and a reset circuit 0129 .

[0084] The driving control circuit 0122 may include a control terminal, a first electrode, and a second electrode. The driving control circuit 0122 is configured to provide the light emitting device 0120 with a driving current for driving the light emitting device 0120 to emit light. For example, the first light emitting control circuit 0123 is connected to the first electrode and the first voltage terminal VDD of the driving control circuit 0122. The first light emitting control circuit 0123 is configured to realize the connection between the driving control circuit 0122 and the first voltage terminal VDD to be turned on or off.

[0085] The second light emitting control circuit 0124 is electrically connected to the second electrode of the driving control circuit 0122 and the first electrode of the light emitting device 0120 , and the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting device 0120 being turned on or off.

[0086] The data writing circuit 0126 is electrically connected to a first electrode of the driving control circuit 0122. And the second light emitting control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scanning line GA2.

[0087] The storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD, and the storage circuit 0127 is configured to store a data signal.

[0088] The threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122 , and the threshold compensation circuit 0128 is configured to perform threshold compensation on the driving control circuit 0122 .

[0089] The reset circuit 0129 is electrically connected to the control terminal of the driving control circuit 0122 and the first electrode of the light emitting device 0120. The reset circuit 0129 is configured to reset the control terminal of the driving control circuit 0122 and the first electrode of the light emitting device 0120 under the control of the signal on the scanning line GA1.

[0090] Among them, the light-emitting device 0120 can be set as an electroluminescent diode, such as at least one of an OLED and a QLED. Among them, the light device 0120 may include a first electrode, a light-emitting functional layer, and a second electrode that are stacked. Exemplarily, the first electrode may be an anode and the second electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Furthermore, the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the light-emitting device 0120 can be designed and determined according to the needs of the actual application environment, and is not limited here.

[0091] For example, in combination Figure 2 As shown, the driving control circuit 0122 includes: a driving transistor T1, the control end of the driving control circuit 0122 includes the gate of the driving transistor T1, the first electrode of the driving control circuit 0122 includes the first electrode of the driving transistor T1, and the second electrode of the driving control circuit 0122 includes the second electrode of the driving transistor T1.

[0092] For example, in combination Figure 2 As shown, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.

[0093] Specifically, the first electrode of the data write transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data write transistor T2 is configured to be electrically connected to the data line VD to receive a data signal, and the gate of the data write transistor T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.

[0094] A first electrode of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and a second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1 .

[0095] A first electrode of the threshold compensation transistor T3 is electrically connected to a second electrode of the driving transistor T1 , a second electrode of the threshold compensation transistor T3 is electrically connected to a gate of the driving transistor T1 , and a gate of the threshold compensation transistor T3 is configured to be electrically connected to the second scan line GA2 to receive a signal.

[0096] A first electrode of the first reset transistor T6 is electrically connected to the reset signal line VINIT to receive a reset signal, a second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1 , and a gate of the first reset transistor T6 is electrically connected to the first scan line GA1 to receive a signal.

[0097] The first electrode of the second reset transistor T7 is configured to be electrically connected to the reset signal line VINIT to receive a reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device 0120, and the gate of the second reset transistor T7 is configured to be electrically connected to the first scan line GA1 to receive a signal.

[0098] The first electrode of the first light emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light emitting control transistor T4 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal.

[0099] The first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is electrically connected to the first electrode of the light emitting device 0120, and the gate of the second light emitting control transistor T5 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal.

[0100] The second electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS. The first electrode and the second electrode of the transistor can be determined as a source electrode or a drain electrode according to actual application, which is not limited here.

[0101] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. Figure 2 In the illustrated embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage, the first voltage being a positive voltage, and the second power supply terminal VSS is a voltage source to output a constant second voltage, the second voltage being a negative voltage, etc. For example, in some examples, the second power supply terminal VSS may be grounded.

[0102] Figure 2The signal timing diagram corresponding to the pixel driving circuit shown in FIG. Figure 3 As shown. In one frame display time, the working process of the pixel driving circuit has three stages: T10 stage, T20 stage, and T30 stage. Among them, ga1 represents the signal transmitted on the first scanning line GA1, ga2 represents the signal transmitted on the second scanning line GA2, and em represents the signal transmitted on the light emitting control line EM.

[0103] In the T10 stage, the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to be turned on. The turned-on first reset transistor T6 provides the signal transmitted on the reset signal line VINIT to the gate of the driving transistor T1 to reset the gate of the driving transistor T1. The turned-on second reset transistor T7 provides the signal transmitted on the reset signal line VINIT to the first electrode of the light-emitting device 0120 to reset the first electrode of the light-emitting device 0120. In addition, in this stage, the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off. The signal em controls the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.

[0104] In the T20 stage, the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, so that the data signal transmitted on the data line VD can charge the gate of the driving transistor T1, so that the voltage of the gate of the driving transistor T1 becomes: Vdata+|Vth|. Wherein, Vth represents the threshold voltage of the driving transistor T1, and Vdata represents the voltage of the data signal. In addition, in this stage, the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to be turned off. The signal em controls the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.

[0105] In the T30 stage, the signal em controls the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on. The turned-on first light-emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T1, so that the voltage of the first electrode of the driving transistor T1 is Vdd. The driving transistor T1 generates a driving current according to its gate voltage Vdata+|Vth| and the voltage Vdd of the first electrode. The driving current is provided to the light-emitting device 0120 through the turned-on second light-emitting control transistor T5, driving the light-emitting device 0120 to emit light. In addition, in this stage, the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to be turned off. The signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.

[0106] It should be noted that in the embodiment of the present disclosure, the pixel driving circuit in the sub-pixel can be Figure 2In addition to the structure shown, the structure may also include other numbers of transistors, which is not limited in the embodiments of the present disclosure.

[0107] In the specific implementation, in the embodiment of the present disclosure, if Figure 1 As shown, the display area may include multiple drive lines and multiple data lines; wherein a row of sub-pixels is electrically connected to at least one of the drive lines, and a column of sub-pixels is electrically connected to at least one of the data lines. Exemplarily, the drive lines include at least one of a plurality of scan lines and a plurality of light-emitting control lines. wherein a row of sub-pixels is electrically connected to at least one scan line and at least one light-emitting control line, and exemplarily, if the pixel drive circuit is set to Figure 2 In the structure shown, a column of sub-pixels can be electrically connected to one data line or sub-pixels in different rows in a column of sub-pixels can be electrically connected to two data lines respectively. A row of sub-pixels corresponds to one light-emitting control line. The plurality of scan lines can include a plurality of first scan lines and a plurality of second scan lines, and a row of sub-pixels is electrically connected to two scan lines, that is, a row of sub-pixels is electrically connected to one first scan line and one second scan line. In addition, in each two adjacent rows, the second scan line electrically connected to the first row and the first scan line electrically connected to the second row are electrically connected to transmit the same signal.

[0108] In order to enable the first scan line and the second scan line to transmit signals, in a specific implementation, in the embodiment of the present disclosure, as Figure 1 and Figure 6 As shown, the non-display area BB may include: a gate drive circuit 01 and a plurality of clock signal lines. The extension direction of the clock signal line is different from the extension direction of the scan line, for example, the extension direction of the clock signal line crosses the extension direction of the scan line. The plurality of clock signal lines are arranged at intervals on the side of the gate drive circuit 01 away from the scan line. Exemplarily, the gate drive circuit 01 may include: a plurality of shift register units arranged in sequence along the extension direction F1 of the clock signal line: SR2n-3, SR2n-2, SR2n-1, SR2n, SR2n+1, SR2n+2, SR2n+3, SR2n+4 (n is an integer greater than 0). Exemplarily, the output signal end OP of a shift register unit may be electrically connected to at least one drive line. Exemplarily, the output signal end OP of a shift register unit may be electrically connected to at least one scan line. The output signal end OP of a shift register unit may also be electrically connected to at least one light-emitting control line.

[0109] Furthermore, the output signal terminals OP of the plurality of shift register units SR2n-3, SR2n-2, SR2n-1, SR2n, SR2n+1, SR2n+2, SR2n+3, and SR2n+4 arranged in sequence along the extension direction F1 of the clock signal line can output Figure 4cThe signals shown. Among them, op2n-3 is the signal output from the output signal terminal OP of the shift register unit SR2n-3, op2n-2 is the signal output from the output signal terminal OP of the shift register unit SR2n-2, op2n-1 is the signal output from the output signal terminal OP of the shift register unit SR2n-1, op2n is the signal output from the output signal terminal OP of the shift register unit SR2n, op2n+1 is the signal output from the output signal terminal OP of the shift register unit SR2n+1, op2n+2 is the signal output from the output signal terminal OP of the shift register unit SR2n+2, op2n+3 is the signal output from the output signal terminal OP of the shift register unit SR2n+3, and op2n+4 is the signal output from the output signal terminal OP of the shift register unit SR2n+4.

[0110] In the specific implementation, in the embodiment of the present disclosure, if Figure 4a As shown, the shift register unit may include: a plurality of transistors; the plurality of transistors may include: an input transistor M1, a voltage-stabilizing transistor M2, an output transistor M3, a first control transistor M4, a second control transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first capacitor C01, and a second capacitor C02. Among them, the gate of the input transistor M1 is electrically connected to the first clock signal terminal CK, the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP, and the second electrode of the input transistor M1 is electrically connected to the first electrode of the voltage-stabilizing transistor M2. The gate of the voltage-stabilizing transistor M2 is electrically connected to the first power line VGL, the second electrode of the voltage-stabilizing transistor M2 is electrically connected to the gate of the output transistor M3, the first electrode of the output transistor M3 is electrically connected to the second clock signal terminal CB, and the second electrode of the output transistor M3 is electrically connected to the output signal terminal OP, that is, the second electrode of the output transistor is electrically connected to at least one scanning line.

[0111] The gate of the first control transistor M4 is electrically connected to the gate of the input transistor M1, the first electrode of the first control transistor M4 is electrically connected to the first power line VGL, the second electrode of the first control transistor M4 is electrically connected to the gate of the second control transistor M5, the first electrode of the second control transistor M5 is electrically connected to the second power line VGH, and the second electrode of the second control transistor M5 is electrically connected to the second electrode of the output transistor.

[0112] A gate of the sixth transistor M6 is electrically connected to the second electrode of the input transistor M1 , a first electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CK, and a second electrode of the sixth transistor M6 is electrically connected to the second electrode of the first control transistor M4 .

[0113] A gate of the seventh transistor M7 is electrically connected to the second clock signal terminal CB, a first electrode of the seventh transistor M7 is electrically connected to the gate of the input transistor M1, and a second electrode of the seventh transistor M7 is electrically connected to a first electrode of the eighth transistor M8.

[0114] A gate of the eighth transistor M8 is electrically connected to the second electrode of the first control transistor M4 , and a second electrode of the eighth transistor M8 is electrically connected to the second power line VGH.

[0115] The first electrode of the first capacitor C01 is electrically connected to the second power line VGH, and the second electrode of the first capacitor C01 is electrically connected to the gate of the second control transistor M5; the first electrode of the second capacitor C02 is electrically connected to the second electrode of the output transistor, and the second electrode of the second capacitor C01 is electrically connected to the gate of the output transistor M3.

[0116] Figure 4a The signal timing diagram corresponding to the shift register shown in Figure 4b As shown. Among them, ck represents the clock signal input to the gate of the input transistor M1, cb represents the clock signal input to the first electrode of the output transistor M3, ip represents the signal of the input signal terminal IP, and op represents the signal of the output signal terminal OP. Through the cooperation of the clock signals ck and cb, the signal ip of the input signal terminal IP, each transistor, and the first capacitor C01 and the second capacitor C02, the output transistor M3 can output the signal op. It should be noted that Figure 4a The signal timing diagram corresponding to the shift register shown in the figure can be Figure 4b In addition to the signal timing diagram shown, other forms of signal timing diagrams may also be used, which can be designed and determined according to the needs of actual applications, and the embodiments of the present disclosure are not limited to this.

[0117] For example, in the embodiment of the present disclosure, the specific structure of each shift register unit in the gate drive circuit 01 can be the same as that of the present disclosure. Figure 4a The shift register units shown are identical in function and structure. This allows the gate drive circuit 01 to input signals to the first scan line GA1 and the second scan line GA2, thereby controlling the on and off of the first reset transistor T6, the second reset transistor T7, the data writing transistor T2 and the threshold compensation transistor T3.

[0118] In the specific implementation, in the embodiment of the present disclosure, if Figure 5aAs shown, the shift register unit may include: multiple transistors; the multiple transistors may include: an input transistor M1, an output transistor M3, a ninth transistor M09, a tenth transistor M010, an eleventh transistor M011, a twelfth transistor M012, a thirteenth transistor M013, a fourteenth transistor M014, a fifteenth transistor M015, a sixteenth transistor M016, a third capacitor C03, a fourth capacitor C04 and a fifth capacitor C05.

[0119] Among them, the gate of the input transistor M1 is electrically connected to the first clock signal terminal CK, the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP, the second electrode of the input transistor M1 is electrically connected to the gate of the output transistor M3, the first electrode of the output transistor M3 is electrically connected to the first power line VGL, and the second electrode of the output transistor M3 is electrically connected to the output signal terminal OP, that is, the second electrode of the output transistor is electrically connected to at least one light-emitting control line accordingly.

[0120] A gate of the ninth transistor M09 is electrically connected to the gate of the input transistor M1 , a first electrode of the ninth transistor M09 is electrically connected to the first power line VGL, and a second electrode of the ninth transistor M09 is electrically connected to the gate of the fourteenth transistor M014 .

[0121] A first electrode of the fourteenth transistor M014 is electrically connected to the second clock signal terminal CB, and a second electrode of the fourteenth transistor M014 is electrically connected to a first electrode of the sixteenth transistor M016.

[0122] A second electrode of the sixteenth transistor M016 is electrically connected to the gate of the tenth transistor M010 , and a gate of the sixteenth transistor M016 is electrically connected to the second clock signal terminal CB.

[0123] A first electrode of the tenth transistor M010 is electrically connected to the second power line VGH, and a second electrode of the tenth transistor M010 is electrically connected to the second electrode of the output transistor M3.

[0124] A gate of the eleventh transistor M011 is electrically connected to the second electrode of the input transistor M1 , a first electrode of the eleventh transistor M011 is electrically connected to the first clock signal terminal CK, and a second electrode of the eleventh transistor M011 is electrically connected to the second electrode of the ninth transistor M09 .

[0125] A gate of the twelfth transistor M012 is electrically connected to the second clock signal terminal CB, a first electrode of the twelfth transistor M012 is electrically connected to the gate of the input transistor M1, and a second electrode of the twelfth transistor M012 is electrically connected to a first electrode of the thirteenth transistor M013.

[0126] A gate of the thirteenth transistor M013 is electrically connected to the second electrode of the ninth transistor M09 , and a second electrode of the thirteenth transistor M013 is electrically connected to the second power line VGH.

[0127] The first electrode of the fifth capacitor C05 is electrically connected to the second power supply line VGH, and the second electrode of the fifth capacitor C05 is electrically connected to the gate of the tenth transistor M010; the first electrode of the third capacitor C03 is electrically connected to the second clock signal terminal CB, and the second electrode of the third capacitor C03 is electrically connected to the gate of the output transistor M3. The first electrode of the fourth capacitor C04 is electrically connected to the gate of the fourteenth transistor M014, and the second electrode of the fourth capacitor C04 is electrically connected to the second electrode of the fourteenth transistor M014.

[0128] Figure 5a The signal timing diagram corresponding to the shift register shown in Figure 5b As shown. Wherein, ck represents the clock signal input to the gate of the input transistor M1, cb represents the clock signal input to the gate of the twelfth transistor M012, ip represents the signal of the input signal terminal IP, and op represents the signal of the output signal terminal OP. Through the cooperation of the clock signals ck, cb, the signal ip of the input signal terminal IP, each transistor, and the first capacitor C01 and the second capacitor C02, the output transistor M3 can output the signal op. It should be noted that Figure 5a The signal timing diagram corresponding to the shift register shown in the figure can be Figure 5b In addition to the signal timing diagram shown, other forms of signal timing diagrams may also be used, which can be designed and determined according to the needs of actual applications, and the embodiments of the present disclosure are not limited to this.

[0129] For example, in the embodiment of the present disclosure, the specific structure of each shift register unit in the gate drive circuit 01 can be the same as that of the present disclosure. Figure 5a The shift register units shown are identical in function and structure. In this way, the gate drive circuit 01 can input a signal to the light-emitting control line, thereby controlling the on and off of the first light-emitting control transistor T4 and the second light-emitting control transistor T5.

[0130] Of course, in practical applications, the shift register unit can be used for Figure 4a and Figure 5a In addition to the structure shown in the figure, a structure including other numbers of transistors may also be used, which is not limited in the embodiments of the present disclosure. Figure 4a The structure of the shift register unit shown is described as an example.

[0131] In order to input the corresponding clock signal to each shift register unit, generally only two clock signal lines are used to input the corresponding clock signal to each shift register unit in the gate drive circuit 01, which results in a large load on the clock signal line. Especially in large-size display panels, the number of shift register units is increasing, which leads to a further increase in the load of the clock signal line, and then the signal instability output by the shift register unit increases, affecting the display effect of the display panel. Therefore, the embodiments of the present disclosure provide some display panels, especially in large-size display panels, which can reduce the number of shift register units electrically connected to each clock signal line, thereby reducing the load of the clock signal line, thereby improving the signal stability output by the shift register unit, and improving the display effect of the display panel.

[0132] In the specific implementation, in the embodiment of the present disclosure, if Figure 6 As shown, the plurality of shift register units may be divided into a plurality of register unit groups GOA-m (1≤m≤M, and m and M are both integers. M is the total number of register unit groups. Figure 6 Take M=2 as an example); wherein the shift register units in the same register unit group GOA-m are cascaded, and two shift register units adjacent to each other along the extension direction of the clock signal line are located in different register unit groups. For example, at least one remaining scan line is arranged between the scan lines electrically connected to each two adjacent shift register units in each register unit group GOA-m. In other words, the shift register units in different register unit groups are arranged alternately.

[0133] Furthermore, in the specific implementation, in the embodiments of the present disclosure, as Figure 6 As shown, multiple clock signal lines can be divided into multiple clock signal line groups GC-m, and different register unit groups correspond to different clock signal line groups, that is, one register unit group GOA-m is electrically connected to one clock signal line group GC-m. Exemplarily, the gate of the input transistor M1 is electrically connected to a clock signal line in the corresponding clock signal line group, the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP, the second electrode of the input transistor M1 is electrically connected to the first electrode of the voltage-stabilizing transistor M2; the second electrode of the voltage-stabilizing transistor M2 is electrically connected to the gate of the output transistor M3; the first electrode of the output transistor M3 is electrically connected to another clock signal line in the corresponding clock signal line group, and the second electrode of the output transistor M3 is electrically connected to at least one scanning line.

[0134] In the disclosed embodiment, the shift register units are grouped and one register unit group corresponds to one clock signal line group, so that the corresponding clock signal is loaded to the corresponding register unit group through the clock signal line group. In this way, the number of shift register units electrically connected to one clock signal line can be reduced, thereby reducing the load of the clock signal line, thereby improving the signal stability output by the shift register unit and improving the display effect of the display panel.

[0135] In a specific implementation, the structure of the shift register unit is as follows: Figure 4a As shown, one shift register unit can be electrically connected to two clock signal lines. Figure 6 As shown, the multiple shift register units in the gate drive circuit 01 can be divided into two register unit groups. The multiple clock signal lines can be divided into two clock signal line groups. Of course, the multiple shift register units in the gate drive circuit 01 can also be divided into three, four, five, six or more register unit groups, and the multiple clock signal lines can be divided into three, four, five, six or more clock signal line groups, which are not limited here.

[0136] For example, when M=2, Figure 6 As shown, the above two register unit groups may include a first register unit group GOA-1 and a second register unit group GOA-2. The above two clock signal line groups include a first clock signal line group GC-1 and a second clock signal line group GC-2. The first register unit group GOA-1 is electrically connected to the first clock signal line group GC-1, and the second register unit group GOA-2 is electrically connected to the second clock signal line group GC-2.

[0137] For example, when M=2, Figure 6As shown, the first register unit group GOA-1 may include an odd number of shift register units arranged in sequence along the extension direction F1 of the clock signal line. The first clock signal line group GC-1 includes a first clock signal line GCK1 and a second clock signal line GCB1. The shift register units in the first register unit group GOA-1 are cascaded. For example, in the first register unit group GOA-1, the input signal end of the first-stage shift register unit is electrically connected to the first frame trigger signal end, and the output signal end of the upper-stage shift register unit in each two adjacent stages of the shift register unit is electrically connected to the input signal end of the next-stage shift register unit. For example, the first register unit group GOA-1 may include shift register units SR2n-3, SR2n-1, SR2n+1, SR2n+3, etc. Among them, the output signal end of the shift register unit SR2n-3 is electrically connected to the input signal end of the shift register unit SR2n-1, the output signal end of the shift register unit SR2n-1 is electrically connected to the input signal end of the shift register unit SR2n+1, and the output signal end of the shift register unit SR2n+1 is electrically connected to the input signal end of the shift register unit SR2n+3.

[0138] Furthermore, for the multiple shift register units cascaded in the first register unit group GOA-1, the gate of the input transistor of the odd-numbered shift register unit and the first electrode of the output transistor of the even-numbered shift register unit are both electrically connected to the first clock signal line GCK1. And, the first electrode of the output transistor of the odd-numbered shift register unit and the gate of the input transistor of the even-numbered shift register unit are both electrically connected to the second clock signal line GCB1. Alternatively, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the first clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the first power line through the corresponding second connection line; and, the gate of the input transistor of the even-numbered shift register unit is electrically connected to the second clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the first power line through the corresponding second connection line.

[0139] For example, when M=2, Figure 6As shown, the second register unit group GOA-2 may include an even number of shift register units arranged in sequence along the extension direction of the clock signal line. The second clock signal line group GC-2 includes a third clock signal line GCK2 and a fourth clock signal line GCB2. The shift register units in the second register unit group GOA-2 are cascaded. For example, in the second register unit group GOA-2, the input signal end of the first-stage shift register unit is electrically connected to the second frame trigger signal end, and the output signal end of the upper-stage shift register unit in each adjacent two-stage shift register unit is electrically connected to the input signal end of the next-stage shift register unit. For example, the second register unit group GOA-2 may include shift register units SR2n-2, SR2n, SR2n+2, SR2n+4, etc. Among them, the output signal end of the shift register unit SR2n-2 is electrically connected to the input signal end of the shift register unit SR2n, the output signal end of the shift register unit SR2n is electrically connected to the input signal end of the shift register unit SR2n+2, and the output signal end of the shift register unit SR2n+2 is electrically connected to the input signal end of the shift register unit SR2n+4.

[0140] Furthermore, for the multiple shift register units cascaded in the second register unit group GOA-2, the gate of the input transistor of the odd-numbered shift register unit and the first electrode of the output transistor of the even-numbered shift register unit are both electrically connected to the third clock signal line GCK2. And, the first electrode of the output transistor of the odd-numbered shift register unit and the gate of the input transistor of the even-numbered shift register unit are both electrically connected to the fourth clock signal line GCB2. Alternatively, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the third clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the first power line through the corresponding second connection line; and, the gate of the input transistor of the even-numbered shift register unit is electrically connected to the fourth clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the first power line through the corresponding second connection line.

[0141] Figure 6 A schematic diagram of the layout structure of the gate drive circuit 01 provided in some embodiments of the present disclosure. Figures 7a to 7d A schematic diagram of each layer of the gate driving circuit 01 provided in some embodiments of the present disclosure. Figure 8a for Figure 6 The schematic diagram of the layout structure of the gate driving circuit 01 shown is a schematic diagram of the cross-sectional structure along the AA′ direction. Figure 8b for Figure 6 The schematic diagram of the layout structure of the gate driving circuit 01 is a schematic diagram of the cross-sectional structure along the BB' direction. Figures 6 to 7dThe example shown takes the shift register units SR2n-3, SR2n-1, SR2n+1, and SR2n+3 included in the first register unit group GOA-1 and the shift register units SR2n-2, SR2n, SR2n+2, and SR2n+4 included in the second register unit group GOA-2 as examples.

[0142] For example, Figure 6 , Figure 7a as well as Figure 8a , Figure 8b As shown, the semiconductor layer 500 of the gate drive circuit 01 is shown. The semiconductor layer 500 can be formed by patterning a semiconductor material. The semiconductor layer 500 can be used to make the active layers of the above-mentioned multiple transistors, for example, to prepare the active layers of the input transistor to the eighth transistor M1 to M8. Among them, each active layer may include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region M1-A of the input transistor M1, the channel region M2-A of the voltage regulator transistor M2, the channel region M3-A of the output transistor M3, the channel region M4-A of the first control transistor M4, the channel region M5-A of the second control transistor M5, the channel region M6-A of the sixth transistor M6, the channel region M7-A of the seventh transistor M7, and the channel region M8-A of the eighth transistor M8. Figure 7a The rectangular dotted box in FIG. 1 shows the channel region of the transistor.

[0143] In some embodiments, Figure 6 and Figure 7a As shown, in the same shift register unit, the active layer of the output transistor and the active layer of the second control transistor can be arranged as an integrated structure.

[0144] It should be noted that the semiconductor layer 500 is also used to make the active layer of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6 and the second reset transistor T7 in the above-mentioned pixel driving circuit.

[0145] Moreover, illustratively, the semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be conductive regions formed by doping with n-type impurities or p-type impurities.

[0146] For example, Figure 8a , Figure 8b As shown, a gate insulating layer 640 is formed on the semiconductor layer 500 to protect the semiconductor layer 500. Figure 6 , Figure 7b as well as Figure 8a , Figure 8bAs shown, the first conductive layer 100 of the gate driving circuit 01 is shown. The first conductive layer 100 is arranged on the side of the gate insulating layer 640 away from the base substrate 1000, so as to be insulated from the semiconductor layer 500. The first conductive layer 100 may include: a plurality of scanning lines, the gates of the above-mentioned plurality of transistors, a plurality of first connecting lines 110 and a plurality of second connecting lines 120. For example, the gate M1-G of the input transistor M1, the gate M2-G of the voltage regulating transistor M2, the gate M3-G of the output transistor M3, the gate M4-G of the first control transistor M4, the gate M5-G of the second control transistor M5, the gate M6-G of the sixth transistor M6, the gate M7-G of the seventh transistor M7, and the gate M8-G of the eighth transistor M8. In addition, it should be noted that the first conductive layer 100 may also include: the gates of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7 in the pixel driving circuit. The first conductive layer 100 may also include: light emitting control lines EM, etc. It should be noted that the portion where the orthographic projection of the first conductive layer 100 on the substrate 1000 overlaps with the orthographic projection of the channel region in the semiconductor layer 500 on the substrate 1000 is set as the gate of the transistor.

[0147] In some embodiments, one shift register unit corresponds to at least one first connection line 110 and at least one second connection line 120. For one shift register unit and the clock signal line group corresponding to the shift register unit, one end of the first connection line 110 is directly electrically connected to the gate of the input transistor in the shift register unit, and the other end of the first connection line 110 is electrically connected to a clock signal line in the clock signal line group through the first via H1. One end of the second connection line is electrically connected to the first transfer portion through the second via, and the other end of the second connection line is electrically connected to another clock signal line in the clock signal line group or the first power line through the third via. For example, in the first register unit group GOA-1, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the first clock signal line GCK1 through the corresponding first connection line 110, and the gate of the input transistor of the even-numbered shift register unit is electrically connected to the second clock signal line GCB1 through the corresponding first connection line 110. Furthermore, in the second register unit group GOA-2, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the third clock signal line GCK2 through the corresponding first connection line 110, and the gate of the input transistor of the even-numbered shift register unit is electrically connected to the fourth clock signal line GCB2 through the corresponding first connection line 110.

[0148] Furthermore, for a shift register unit, the gate of the first control transistor in the shift register unit is directly electrically connected to the corresponding first connection line 110, so that the gate of the first control transistor and the gate of the input transistor can be set as an integrated structure.

[0149] For example, Figure 8a , Figure 8b As shown, a first insulating layer 610 is formed on the first conductive layer 100 to protect the first conductive layer 100. Figure 6 , Figure 7c as well as Figure 8a , Figure 8b As shown, the fourth conductive layer 400 of the gate drive circuit 01 is shown. The fourth conductive layer 400 is arranged on the side of the first insulating layer 610 away from the base substrate 1000. The fourth conductive layer 400 may include: a plurality of first conductive parts C01-1 and a plurality of second conductive parts C02-1, and a plurality of third conductive parts 410. Among them, a first conductive part C01-1 and a second conductive part C02-1 are arranged in a shift register. That is, a first conductive part C01-1 corresponds to a second control transistor M5, and a second conductive part C02-1 corresponds to an output transistor M3.

[0150] Exemplarily, the orthographic projection of the first conductive portion C01-1 on the substrate and the orthographic projection of the gate M5-G of the second control transistor M5 on the substrate have an overlapping area, thereby forming a first capacitor C01. The first conductive portion C01-1 serves as the first electrode C01-1 of the first capacitor C01, and the gate M5-G of the second control transistor M5 serves as the second electrode of the first capacitor C01.

[0151] In some embodiments, the orthographic projection of the second conductive portion C02-1 on the substrate and the orthographic projection of the gate M3-G of the output transistor M3 on the substrate have an overlapping area, thereby forming a second capacitor C02. The second conductive portion C02-1 serves as the first electrode of the second capacitor C02. The gate M3-G of the output transistor M3 serves as the second electrode of the second capacitor C02.

[0152] In some embodiments, two cascaded shift register units may be electrically connected via a third conductive portion 410. For example, in the two cascaded shift register units, the first electrode of the output transistor in the previous stage shift register unit is electrically connected to the first electrode of the input transistor in the next stage shift register unit via the third conductive portion 410.

[0153] In some embodiments, the orthographic projection of the gate of the second control transistor on the substrate may cover the orthographic projection of the first conductive portion on the substrate.

[0154] It should be noted that the fourth conductive layer 400 may also include a first electrode of the storage capacitor CST in the above pixel driving circuit and a reset signal line.

[0155] For example, Figure 8a , Figure 8b As shown, a third insulating layer 630 is formed on the fourth conductive layer 400 to protect the fourth conductive layer 400. Figure 6 , Figure 7d as well as Figure 8a , Figure 8b As shown, the second conductive layer 200 of the gate driving circuit 01 is shown, and the second conductive layer 200 is arranged on the side of the third insulating layer 630 away from the base substrate 1000. The second conductive layer 200 may include: a plurality of data lines VD, a first power line VGL, a second power line VGH, a plurality of clock signal lines (for example, a first clock signal line GCK1, a second clock signal line GCB1, a third clock signal line GCK2, a fourth clock signal line GCB2), a plurality of first transfer parts 210, a plurality of second transfer parts 220, a plurality of third transfer parts 230, a plurality of fourth transfer parts 240, and a plurality of fifth transfer parts 250. Among them, a first transfer part 210, a second transfer part 220, a third transfer part 230, a fourth transfer part 240, and a fifth transfer part 250 are arranged in a shift register.

[0156] In some embodiments, Figure 6 and Figure 8b As shown, one first transfer portion 210 is provided corresponding to one output transistor, and one first transfer portion 210 is electrically connected to the source region of the active layer of one output transistor through the tenth via hole. In addition, one end of the second connection line 120 is electrically connected to the first transfer portion 210 through the second via hole H2, and the other end of the second connection line 120 is electrically connected to the clock signal line through the third via hole H3.

[0157] In some embodiments, Figure 6 As shown, a second transfer portion 220 is arranged corresponding to a first control transistor, and the drain region of the active layer of the first control transistor is electrically connected to the gate of the second control transistor through the corresponding second transfer portion 220 .

[0158] In some embodiments, Figure 6 and Figure 8aAs shown, one third adapter 230 corresponds to one second control transistor. The source region of the active layer of the second control transistor is electrically connected to one end of the corresponding third adapter 230 through the sixth via H6, the other end of the third adapter 230 is electrically connected to one end of the corresponding first conductive portion through the seventh via H7, the other end of the first conductive portion is electrically connected to the second power line through the eighth via H8, and the drain region of the active layer of the second control transistor is shared with the drain region of the active layer of the output transistor.

[0159] In some embodiments, Figure 6 and Figure 8a As shown, one fourth transfer portion 240 corresponds to one sixth transistor M6. One end of the fourth transfer portion 240 is electrically connected to the gate M1-G of the input transistor M1 through the eleventh via H11, and the other end of the fourth transfer portion 240 is electrically connected to the source region of the active layer of the sixth transistor M6 through the twelfth via.

[0160] In some embodiments, Figure 6 and Figure 8a As shown, one fifth transfer part 250 corresponds to one voltage stabilizing transistor M2. One end of the fifth transfer part 250 is electrically connected to the drain region of the active layer of the voltage stabilizing transistor M2 through the thirteenth via hole H13, and the other end of the fifth transfer part 250 is electrically connected to the gate of the output transistor M3 through the fourteenth via hole H14.

[0161] It should be noted that the electrical connection relationship between other transistors can be achieved by using other switching parts, which will not be elaborated here.

[0162] In some embodiments, Figure 6 As shown, in the first register unit group GOA-1, the first electrode of the output transistor of the odd-numbered shift register unit (e.g., the source region of the active layer of the output transistor) is electrically connected to the second clock signal line GCB1 through the corresponding second connection line 120, and the first electrode of the output transistor of the even-numbered shift register unit (e.g., the source region of the active layer of the output transistor) is electrically connected to the first clock signal line GCK1 through the corresponding second connection line 120. And, in the second register unit group GOA-2, the first electrode of the output transistor of the odd-numbered shift register unit (e.g., the source region of the active layer of the output transistor) is electrically connected to the fourth clock signal line GCB2 through the corresponding second connection line 120, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the third clock signal line GCK2 through the corresponding second connection line 120.

[0163] In some embodiments, Figure 6 and Figure 8a , Figure 8bAs shown, the gate of each voltage-stabilizing transistor is electrically connected to the first power line through the fourth via H4, so as to input a corresponding voltage signal to the gate of the voltage-stabilizing transistor.

[0164] In some embodiments, Figure 6 and Figure 8a , Figure 8b As shown, in the same gate drive circuit 01, the orthogonal projection of the input transistor on the substrate substrate is located between the orthogonal projection of the first power line on the substrate substrate and the orthogonal projection of the multiple clock signal lines on the substrate substrate. The orthogonal projection of the voltage stabilizing transistor on the substrate substrate is located on the side of the orthogonal projection of the first power line on the substrate substrate away from the orthogonal projection of the multiple clock signal lines on the substrate substrate. The orthogonal projection of the output transistor on the substrate substrate is located on the side of the orthogonal projection of the voltage stabilizing transistor on the substrate substrate away from the orthogonal projection of the first power line on the substrate substrate.

[0165] In some embodiments, Figure 6 and Figure 8a , Figure 8b As shown, the source region of the active layer of the first control transistor is electrically connected to the first power line through the fifth via hole H5, so that the source region of the active layer of the first control transistor can input a corresponding voltage signal.

[0166] In some embodiments, Figure 6 As shown, the orthographic projection of the second power line on the substrate substrate is located between the orthographic projections of the multiple clock signal lines on the substrate substrate and the orthographic projection of the gate drive circuit 01 on the substrate substrate. Furthermore, in the shift register unit, the orthographic projection of the first control transistor on the substrate substrate is located between the orthographic projection of the input transistor on the substrate substrate and the orthographic projection of the first power line on the substrate substrate. Furthermore, in the shift register unit, the orthographic projection of the second control transistor on the substrate substrate is located on the side of the orthographic projection of the input transistor on the substrate substrate away from the orthographic projection of the first power line on the substrate substrate.

[0167] In some embodiments, Figure 6 As shown, the orthographic projection of the gate of the second control transistor on the substrate and the orthographic projection of the first conductive portion on the substrate respectively have overlapping areas with the orthographic projection of the first power line on the substrate.

[0168] In some embodiments, Figure 6 As shown, the orthographic projection of the eighth via H8 on the substrate substrate is located between the orthographic projections of the first power line and the second power line on the substrate substrate, and the orthographic projection of the seventh via H7 on the substrate substrate is located between the orthographic projection of the first power line on the substrate substrate and the orthographic projection of the active layer of the second control transistor on the substrate substrate.

[0169] like Figure 8a , Figure 8bAs shown, a gate insulating layer 640 is provided between the semiconductor layer 500 and the first conductive layer 100, a first insulating layer 610 is provided between the first conductive layer 100 and the fourth conductive layer 400, a third insulating layer 630 is provided between the fourth conductive layer 400 and the second conductive layer 200, and a second insulating layer 620 is provided between the second conductive layer 200 and the third conductive layer 300. The above-mentioned vias are arranged at intervals. In addition, the first via H1, the second via H2, the third via H3, the fourth via H4, the eleventh via H11 and the fourteenth via H14 penetrate the first insulating layer and the third insulating layer. The fifth via H5, the sixth via H6, the twelfth via and the thirteenth via H13 penetrate the first insulating layer, the third insulating layer and the gate insulating layer. The seventh via H7 and the eighth via H8 penetrate the third insulating layer.

[0170] The structural diagrams of other display panels provided by the embodiments of the present disclosure are as follows: Fig. 9 As shown, the implementation of the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0171] For example, Figures 9 to 11 As shown, a second insulating layer 620 is formed on the second conductive layer 200 to protect the second conductive layer 200. Figures 9 to 11 As shown, the third conductive layer 300 of the gate driving circuit 01 is shown, and the third conductive layer 300 is arranged on the side of the second insulating layer 620 away from the substrate 1000. In addition, the third conductive layer 300 may include: at least one auxiliary line. Among them, an auxiliary line is electrically connected to a clock signal line through at least one ninth via H9, and the ninth via H9 passes through the second insulating layer 620.

[0172] In some embodiments, Fig. 9 As shown, the orthographic projection of the clock signal line on the base substrate can cover the orthographic projection of the electrically connected auxiliary line on the base substrate. Further, the orthographic projection of the clock signal line on the base substrate can overlap the orthographic projection of the electrically connected auxiliary line on the base substrate. In this way, the occupied area of ​​the auxiliary line can be reduced, thereby reducing the occupied area of ​​the non-display area BB.

[0173] In some embodiments, Fig. 9 As shown, the second conductive layer may include: a plurality of auxiliary lines; an auxiliary line is electrically connected to a clock signal line through a plurality of ninth via holes H9, so that the resistance of each clock signal line can be reduced.

[0174] In some embodiments, Fig. 9 As shown, the ninth via holes H9 of every two adjacent clock signal lines can be arranged in a staggered manner. In this way, the ninth via holes H9 can be dispersedly arranged to improve uniformity.

[0175] In some embodiments, Fig. 9 As shown, the orthographic projection of the ninth via hole H9 on the base substrate does not overlap with the orthographic projections of the first via hole H1 and the third via hole H3 on the base substrate, thereby improving the accuracy of the electrical connection.

[0176] Based on the same inventive concept, the embodiment of the present disclosure further provides a method for driving a display panel, including:

[0177] Within a frame scanning time, each shift register unit is controlled to work sequentially to scan each driving line row by row; wherein the odd-numbered shift register units and the even-numbered shift register units arranged in sequence along the extension direction of the clock signal line are independently driven under the control of different clock signal line groups.

[0178] For example, in combination Figure 4c , Figure 6 as well as Fig.12 As shown, within a frame scan time, the odd-numbered shift register units (i.e., the first register unit group GOA-1) operate under the control of the clock signals input by the first clock signal line GCK1 and the second clock signal line GCB1 to input signals to the electrically connected scan lines. In addition, the even-numbered shift register units (i.e., the second register unit group GOA-2) operate under the control of the clock signals input by the third clock signal line GCK2 and the fourth clock signal line GCB2 to input signals to the electrically connected scan lines. Thus, each scan line can be scanned line by line.

[0179] Fig.12 4 shows a signal gck1 transmitted by the first clock signal line GCK1, a signal gcb1 transmitted by the second clock signal line GCB1, a signal gck2 transmitted by the third clock signal line GCK2, and a signal gcb2 transmitted by the fourth clock signal line GCB2.

[0180] The embodiment of the present disclosure also provides a method for driving a display panel, including: the time for which the signals applied to multiple clock signal lines in different clock signal line groups maintain valid levels does not overlap. For example, Fig.12 As shown, the effective level of the signal added to the clock signal line is a low level, and the low levels of the signals added to each clock signal line do not overlap.

[0181] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above display panel provided by the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the above display panel, and the repeated parts will not be repeated.

[0182] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0183] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0184] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A substrate, comprising a display area and a non-display area; The display area includes: A plurality of sub-pixels are arranged in a matrix along a plurality of rows and a plurality of columns; A plurality of driving lines, wherein a row of sub-pixels is electrically connected to at least one of the driving lines; A plurality of data lines, wherein a column of the sub-pixels is electrically connected to at least one of the data lines; The non-display area includes: A gate driving circuit, comprising: a plurality of clock signal lines, and a plurality of shift register units sequentially arranged along the extending direction of the clock signal lines; wherein the plurality of clock signal lines are divided into a plurality of clock signal line groups; The plurality of shift register units are divided into a plurality of register unit groups; the shift register units in the same register unit group are cascaded, and two shift register units adjacent to each other along the extension direction of the clock signal line are located in different register unit groups; and different register unit groups correspond to different clock signal line groups; Each of the shift register units includes an input transistor and an output transistor; wherein the gate of the input transistor is electrically connected to a clock signal line in the corresponding clock signal line group, the first electrode of the input transistor is electrically connected to the input signal terminal, and the second electrode of the input transistor is electrically connected to the gate of the output transistor; the second electrode of the output transistor is electrically connected to at least one driving line.

2. The display panel according to claim 1, wherein: The display panel further includes: A semiconductor layer, located on the substrate, and the semiconductor layer includes an active layer of the input transistor and an active layer of the output transistor; the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region; A gate insulating layer, located on a side of the semiconductor layer away from the substrate; a first conductive layer, located on a side of the gate insulating layer away from the base substrate, and comprising the plurality of driving lines, the plurality of first connecting lines, the plurality of second connecting lines, the gate of the input transistor and the gate of the output transistor; one shift register unit corresponds to at least one of the first connecting lines and at least one of the second connecting lines; A first insulating layer, located on a side of the first conductive layer away from the substrate; The second conductive layer is located on the side of the first insulating layer away from the base substrate, and the second conductive layer includes the plurality of data lines, the plurality of clock signal lines and a plurality of first transfer parts; wherein one of the first transfer parts is electrically connected to a source region of the active layer of one of the output transistors; the second conductive layer also includes: a first power line; For one of the shift register units and the clock signal line group corresponding to the shift register unit, one end of the first connection line is directly electrically connected to the gate of the input transistor in the shift register unit, the other end of the first connection line is electrically connected to a clock signal line in the clock signal line group through a first via hole, one end of the second connection line is electrically connected to the first transfer portion through a second via hole, and the other end of the second connection line is electrically connected to another clock signal line in the clock signal line group or the first power line through a third via hole; The first via hole, the second via hole and the third via hole penetrate the first insulating layer and are arranged at intervals.

3. The display panel according to claim 2, wherein: The plurality of clock signal lines are divided into two clock signal line groups, the two clock signal line groups include a first clock signal line group and a second clock signal line group; wherein the first clock signal line group includes a first clock signal line and a second clock signal line, and the second clock signal line group includes a third clock signal line and a fourth clock signal line; The plurality of shift register units are divided into two register unit groups, the two register unit groups include a first register unit group and a second register unit group, wherein the first register unit group includes odd-numbered shift register units sequentially arranged along the extension direction of the clock signal line, and the second register unit group includes even-numbered shift register units sequentially arranged along the extension direction of the clock signal line; For the multiple shift register units cascaded in the first register unit group, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the first clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the second clock signal line or the first power line through the corresponding second connection line; and the gate of the input transistor of the even-numbered shift register unit is electrically connected to the second clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the first clock signal line or the first power line through the corresponding second connection line; For the multiple shift register units cascaded in the second register unit group, the gate of the input transistor of the odd-numbered shift register unit is electrically connected to the third clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the odd-numbered shift register unit is electrically connected to the fourth clock signal line or the first power line through the corresponding second connection line; and, the gate of the input transistor of the even-numbered shift register unit is electrically connected to the fourth clock signal line through the corresponding first connection line, and the first electrode of the output transistor of the even-numbered shift register unit is electrically connected to the third clock signal line or the first power line through the corresponding second connection line.

4. The display panel according to claim 3, wherein: Each of the shift register units further comprises a voltage-stabilizing transistor; wherein the second electrode of the input transistor is electrically connected to the first electrode of the voltage-stabilizing transistor, and the second electrode of the voltage-stabilizing transistor is electrically connected to the gate of the output transistor; The second conductive layer further includes: a first power line; the gate of each of the voltage-stabilizing transistors is electrically connected to the first power line through a fourth via hole; wherein the fourth via hole penetrates the first insulating layer.

5. The display panel according to claim 4, wherein: In the same gate driving circuit, the orthographic projection of the input transistor on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate; The orthographic projection of the voltage stabilizing transistor on the substrate is located on a side of the orthographic projection of the first power line on the substrate away from the orthographic projection of the plurality of clock signal lines on the substrate; The orthographic projection of the output transistor on the substrate is located on a side of the orthographic projection of the voltage stabilizing transistor on the substrate away from the orthographic projection of the first power line on the substrate.

6. The display panel according to any one of claims 3 to 5, wherein: The shift register unit further includes a first control transistor and a second control transistor; The semiconductor layer further includes an active layer of the first control transistor and an active layer of the second control transistor; The first conductive layer further includes: a gate of the first control transistor and a gate of the second control transistor; The second conductive layer further includes: a second power line, a plurality of second transfer parts, and a plurality of third transfer parts; wherein one second transfer part corresponds to one first control transistor, and one third transfer part corresponds to one second control transistor; Furthermore, the display panel further includes: a fourth conductive layer, located between the first insulating layer and the second conductive layer, and comprising a plurality of first conductive portions; wherein one first conductive portion corresponds to one second control transistor; a third insulating layer, located between the fourth conductive layer and the second conductive layer; wherein the gate of the first control transistor is directly electrically connected to the corresponding first connection line, the source region of the active layer of the first control transistor is electrically connected to the first power line through a fifth via hole, and the drain region of the active layer of the first control transistor is electrically connected to the gate of the second control transistor through the corresponding second transfer portion; wherein the fifth via hole passes through the first insulating layer and the third insulating layer; The source region of the active layer of the second control transistor is electrically connected to one end of the corresponding third transfer portion through a sixth via, the other end of the third transfer portion is electrically connected to one end of the corresponding first conductive portion through a seventh via, the other end of the first conductive portion is electrically connected to the second power line through an eighth via, and the drain region of the active layer of the second control transistor is shared with the drain region of the active layer of the output transistor; wherein the sixth via passes through the first insulating layer and the third insulating layer, and the seventh via and the eighth via pass through the third insulating layer.

7. The display panel according to claim 6, wherein: The orthographic projection of the second power line on the base substrate is located between the orthographic projections of the plurality of clock signal lines on the base substrate and the orthographic projection of the gate driving circuit on the base substrate; In the shift register unit, the orthographic projection of the first control transistor on the substrate is located between the orthographic projection of the input transistor on the substrate and the orthographic projection of the first power line on the substrate; In the shift register unit, the orthographic projection of the second control transistor on the substrate is located on a side of the orthographic projection of the input transistor on the substrate away from the orthographic projection of the first power line on the substrate.

8. The display panel according to claim 7, wherein: In the shift register unit, the active layer of the output transistor and the active layer of the second control transistor are arranged in an integrated structure.

9. The display panel according to any one of claims 6 to 8, wherein: The shift register unit further includes: a first capacitor and a second capacitor; wherein a first electrode of the first capacitor is electrically connected to the second power line, and a second electrode of the first capacitor is electrically connected to the gate of the second control transistor; a first electrode of the second capacitor is electrically connected to the second electrode of the output transistor, and a second electrode of the second capacitor is electrically connected to the gate of the output transistor; The fourth conductive layer further includes a plurality of second conductive portions; wherein one second conductive portion corresponds to one output transistor; The orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the gate of the second control transistor on the base substrate have an overlapping area, and the first conductive portion serves as a first electrode of the first capacitor, and the gate of the second control transistor serves as a second electrode of the first capacitor; The orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the corresponding gate of the output transistor on the base substrate have an overlapping area, and the second conductive portion serves as the first electrode of the second capacitor, and the gate of the output transistor serves as the second electrode of the second capacitor.

10. The display panel according to claim 9, wherein: The orthographic projection of the gate of the second control transistor on the base substrate covers the orthographic projection of the first conductive portion on the base substrate.

11. The display panel according to claim 10, wherein: The orthographic projection of the gate of the second control transistor on the base substrate and the orthographic projection of the first conductive portion on the base substrate respectively have overlapping areas with the orthographic projection of the first power line on the base substrate.

12. The display panel according to any one of claims 6 to 11, wherein: The orthographic projection of the eighth via hole on the substrate substrate is located between the orthographic projection of the first power line and the orthographic projection of the second power line on the substrate substrate, and the orthographic projection of the seventh via hole on the substrate substrate is located between the orthographic projection of the first power line on the substrate substrate and the orthographic projection of the active layer of the second control transistor on the substrate substrate.

13. The display panel according to any one of claims 2 to 12, wherein: The display panel further includes: A second insulating layer is located on a side of the second conductive layer away from the base substrate; A third conductive layer is located on a side of the second insulating layer away from the substrate, and the second conductive layer includes: at least one auxiliary line; One of the auxiliary lines is electrically connected to one of the clock signal lines through at least one ninth via hole, and the ninth via hole passes through the second insulating layer.

14. The display panel according to claim 13, wherein: The orthographic projection of the clock signal line on the base substrate covers the orthographic projection of the auxiliary line of electrical connection on the base substrate.

15. A display device, wherein: Comprising a display panel as described in any one of claims 1-14.

16. A method for driving a display panel according to any one of claims 1 to 14, wherein: include: Within a frame scanning time, each of the shift register units is controlled to work sequentially to scan each of the driving lines row by row; wherein the odd-numbered shift register units and the even-numbered shift register units arranged in sequence along the extension direction of the clock signal line are independently driven under the control of different clock signal line groups.

17. A method for driving a display panel as claimed in claim 16, wherein: include: The time periods during which the signals applied to the multiple clock signal lines in different clock signal line groups maintain valid levels do not overlap.

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