Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate and a sub-pixel on the substrate, the sub-pixel comprises a pixel circuit, the pixel circuit comprises a data writing sub-circuit, a storage sub-circuit, a driving sub-circuit and a resistor, the resistor is connected between the light emitting element and the driving sub-circuit, the resistor and the control electrode of the driving sub-circuit are insulatively arranged in the same layer, and the resistivity of the resistor is higher than that of the control electrode of the driving sub-circuit. The display substrate has a good effect on solving the failure problem of the pixel circuit.

Description

Technical Field

[0001] This disclosure relates to a display substrate and a display device. Background Technology

[0002] Micro OLED displays involve the combination of organic light-emitting diode (OLED) technology and CMOS technology. They are related to the cross-integration of the optoelectronics industry and the microelectronics industry, which promotes the development of next-generation micro-display technology and advances the research and development of organic electronics on silicon and even molecular electronics on silicon.

[0003] Micro OLED displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, and have broad development prospects. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate, including a substrate and sub-pixels on the substrate. Each sub-pixel includes a pixel circuit, which further includes a data writing sub-circuit, a storage sub-circuit, a driving sub-circuit, and a resistor. The data writing sub-circuit is electrically connected to a first terminal of the storage sub-circuit and configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal. The driving sub-circuit includes a control electrode, a first electrode, and a second electrode. The control electrode of the driving sub-circuit is electrically connected to the first terminal of the storage sub-circuit. The first electrode of the driving sub-circuit is configured to receive a first power supply voltage. The second electrode of the driving sub-circuit is electrically connected to the first electrode of a light-emitting element. The driving sub-circuit is configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the storage sub-circuit. The resistor and the control electrode of the driving sub-circuit are insulated from each other in the same layer, and the resistivity of the resistor is higher than that of the control electrode of the driving sub-circuit.

[0005] In some examples, the resistor and the control electrode of the drive sub-circuit are both made of polycrystalline silicon.

[0006] In some examples, the control signal includes a first control signal, the data writing sub-circuit includes a first data writing transistor, and the driving sub-circuit includes a driving transistor. The first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor, and the driving transistor is an N-type metal-oxide-semiconductor field-effect transistor. The gate of the first data writing transistor is configured to receive the first control signal, the first electrode of the first data writing transistor is configured to receive the data signal, and the second electrode of the first data writing transistor is electrically connected to the first terminal of the storage sub-circuit and the control electrode of the driving sub-circuit. The gate, first electrode, and second electrode of the driving transistor serve as the control electrode, first electrode, and second electrode of the driving sub-circuit, respectively.

[0007] In some examples, a PN junction is formed between the second electrode of the driving sub-circuit and the substrate, and the resistance value of the resistor is configured such that the PN junction is turned off when the driving transistor is operating in the saturation region.

[0008] In some examples, the resistance value of the resistor Wherein, Vs is the bias voltage of the substrate, Vcom1 is the common voltage provided to the second electrode of the light-emitting element, Von is the on-state voltage of the PN junction, and Is is the saturation current of the driving transistor.

[0009] In some examples, the storage sub-circuit includes a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode serving as the first terminal and the second terminal of the storage sub-circuit, respectively; the first capacitor electrode is insulated from the resistor in the same layer.

[0010] In some examples, the first data writing transistor and the driving transistor are located on opposite sides of the storage capacitor in a direction parallel to the surface of the substrate.

[0011] In some examples, the resistor and the first data writing transistor are located on the same side of the first capacitor electrode in a direction parallel to the surface of the substrate.

[0012] In some examples, the resistor is a U-shaped structure with the opening of the U-shaped structure facing the first capacitor electrode; the first end and the second end of the resistor are located at the two ends of the U-shaped structure, respectively.

[0013] In some examples, the second end of the resistor is closer to the driving transistor in a direction parallel to the surface of the substrate.

[0014] In some examples, the sub-pixel further includes a first connection electrode that electrically connects a first end of the resistor to a second terminal of the driving transistor.

[0015] In some examples, the first connection electrode is electrically connected to the first end of the resistor through a first via and to the second electrode of the driving transistor through a second via; in a direction parallel to the surface of the substrate, the first via and the second via are located on opposite sides of the first capacitor electrode.

[0016] In some examples, the storage capacitor further includes a third capacitor electrode; the third capacitor electrode is located on the side of the first capacitor electrode away from the second capacitor electrode in a direction perpendicular to the substrate, and is configured to be electrically connected to the second capacitor electrode.

[0017] In some examples, the third capacitor electrode is insulated from the first connecting electrode in the same layer and is made of the same material.

[0018] In some examples, the third capacitor electrode includes a first portion and a second portion spaced apart, the first portion and the second portion being located on opposite sides of the first connecting electrode and respectively configured to be electrically connected to the second capacitor electrode.

[0019] In some examples, the second capacitor electrode of the storage capacitor is a first region of the substrate and overlaps with the first capacitor electrode in a direction perpendicular to the substrate.

[0020] In some examples, the first capacitor electrode of the storage capacitor is disposed on the same layer as the gate of the driving transistor and is an integral part thereof.

[0021] In some examples, the control signal further includes a second control signal, and the data writing sub-circuit further includes a second data writing transistor, the second data writing transistor being an N-type metal-oxide-semiconductor field-effect transistor, the gate of the second data writing transistor being configured to receive the second control signal, the first terminal of the second data writing transistor being electrically connected to the first terminal of the first data writing transistor, and the second terminal of the second data writing transistor being electrically connected to the second terminal of the first data writing transistor.

[0022] In some examples, the gates of the first data write transistor and the second data write transistor are arranged side by side along a first direction and are symmetrical about an axis of symmetry along the second direction; the first direction intersects the second direction.

[0023] In some examples, the sub-pixel further includes a second connection electrode, which includes a first end, a second end, and a third end. The first end of the second connection electrode is electrically connected to the second electrode of the first data write transistor, the second end of the second connection electrode is electrically connected to the second electrode of the second data write transistor, and the third end of the second connection electrode is electrically connected to the first end of the storage sub-circuit.

[0024] In some examples, the display substrate includes four sub-pixels that form a pixel unit group. The four sub-pixels are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction. The resistors of the four sub-pixels are located in the same N-type well region in the substrate when projected onto the substrate.

[0025] In some examples, the resistors of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the resistors of adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

[0026] In some examples, the storage sub-circuit includes a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode serving as a first terminal and a second terminal of the storage sub-circuit, respectively; the first capacitor electrodes of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the first capacitor electrodes of two adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

[0027] In some examples, the first capacitive electrode of the four sub-pixels is projected onto the substrate outside the N-type well region and surrounds the N-type well region.

[0028] In some examples, the storage capacitor further includes a third capacitor electrode located on the side of the first capacitor electrode away from the second capacitor electrode in a direction perpendicular to the substrate, and configured to be electrically connected to the second capacitor electrode; the third capacitor electrodes of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the third capacitor electrodes of two adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

[0029] In some examples, the third capacitor electrode includes a first portion and a second portion spaced apart from each other in the first direction, the first portion and the second portion being configured to be electrically connected to the second capacitor electrode; the first portions of the third capacitor electrodes of two adjacent sub-pixels in the first direction are connected to each other as a single unit.

[0030] In some examples, the display substrate includes a plurality of pixel unit groups arranged along the first direction, wherein the second portion of the third capacitor electrode of the sub-pixel in each pixel unit group and the second portion of the third capacitor electrode of the sub-pixel adjacent to the sub-pixel in the pixel unit group adjacent to the pixel unit group are connected to each other in a structure.

[0031] In some examples, the control signal includes a first control signal and a second control signal; the data writing sub-circuit includes a first data writing transistor and a second data writing transistor; the gate of the first data writing transistor is configured to receive the first control signal, and the gate of the second data writing transistor is configured to receive the second control signal; the first electrode of the first data writing transistor is electrically connected to the first electrode of the second data writing transistor and is configured to receive the data signal; the second electrode of the first data writing transistor is electrically connected to the second electrode of the second data writing transistor and is electrically connected to the first terminal of the storage sub-circuit and the control electrode of the driving sub-circuit; the second data writing transistors of the four sub-pixels are all located in the same N-type well region.

[0032] In some examples, the gates of the second data write transistors of adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction and connected as a single unit; the gates of the second data write transistors in two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

[0033] In some examples, the first poles of the second data write transistors of two adjacent sub-pixels in the second direction are symmetrical about the first direction and connected as a single unit; the first poles of the second data write transistors of two adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction.

[0034] In some examples, the pixel circuit further includes a bias sub-circuit, which includes a control terminal, a first terminal, and a second terminal. The control terminal of the bias sub-circuit is configured to receive a bias signal. The first terminal of the bias sub-circuit and the second terminal of the storage sub-circuit are both configured to receive a second power supply voltage. The second terminal of the bias sub-circuit is electrically connected to the second electrode of the driving sub-circuit and the first terminal of the resistor.

[0035] At least one embodiment of this disclosure also provides a display device, including the above-described display substrate and the light-emitting element on the display substrate, wherein a first electrode of the light-emitting element is electrically connected to a second terminal of the resistor. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below only involve some embodiments of this disclosure and are not intended to limit this disclosure.

[0037] Figure 1A One of the schematic diagrams of a display substrate provided in at least one embodiment of this disclosure;

[0038] Figure 1B This is one of the pixel circuit diagrams provided in at least one embodiment of the present disclosure;

[0039] Figure 1C This is a schematic diagram of a pixel circuit structure;

[0040] Figure 2A This is a second pixel circuit diagram provided in at least one embodiment of the present disclosure;

[0041] Figure 2B This is the third pixel circuit diagram provided in at least one embodiment of the present disclosure;

[0042] Figure 2C This is a signal timing diagram of a pixel circuit provided in at least one embodiment of the present disclosure;

[0043] Figure 3A A second schematic diagram of a display substrate provided in at least one embodiment of this disclosure;

[0044] Figure 3B for Figure 3A The diagram shown is a schematic diagram of the display substrate along section line I-I'.

[0045] Figure 4A A third schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0046] Figure 4B This is an enlarged schematic diagram of a sub-pixel of a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figures 5A-5E It shows Figure 4A The diagram shows the fabrication steps of the display substrate.

[0048] Figures 6A-6B A schematic diagram of the first conductive layer of a display substrate provided in at least one embodiment of the present disclosure;

[0049] Figure 6C It shows Figure 6B A sectional view along section line IV-IV';

[0050] Figures 7A-7B A schematic diagram of the second conductive layer of a display substrate provided in at least one embodiment of the present disclosure;

[0051] Figures 8A-8B This is a schematic diagram of the third conductive layer of a display substrate provided in at least one embodiment of the present disclosure;

[0052] Figures 9A-9B A schematic diagram of the fourth conductive layer of a display substrate provided in at least one embodiment of this disclosure;

[0053] Figure 10A Fourth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0054] Figure 10B for Figure 10A An enlarged schematic diagram of the area indicated by the dashed lines on the display substrate;

[0055] Figure 10C for Figure 10B A sectional view along section line V-V';

[0056] Figure 11A Fifth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0057] Figure 11B Sixth schematic diagram of a display substrate provided for at least one embodiment of this disclosure;

[0058] Figure 11C for Figure 11B The image shows a cross-sectional view of the substrate along section line II-II'.

[0059] Figure 11D for Figure 11B The diagram shows a cross-sectional view of the substrate along section line III-III'; and

[0060] Figure 12 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0061] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Referring to the non-limiting exemplary embodiments shown in the drawings and detailed in the following description, the exemplary embodiments of this disclosure and their various features and advantageous details will be explained more fully. It should be noted that the features shown in the figures are not necessarily drawn to scale. Descriptions of known materials, components, and process technologies are omitted in this disclosure so as not to obscure the exemplary embodiments of this disclosure. The examples given are intended only to facilitate understanding of the implementation of the exemplary embodiments of this disclosure and to further enable those skilled in the art to implement the exemplary embodiments. Therefore, these examples should not be construed as limiting the scope of the embodiments of this disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0063] In the field of OLED (Organic Light-Emitting Diode) displays, the rapid development of high-resolution products has placed higher demands on the structural design of display substrates, such as the arrangement of pixels and signal lines. For example, compared to a 4K resolution OLED display, a large-size 8K resolution OLED display requires a significantly increased number of sub-pixel units, resulting in a correspondingly increased pixel density. This leads to two main issues: firstly, the linewidth of the signal lines decreases, resulting in increased resistance; secondly, the overlap between signal lines increases, leading to greater parasitic capacitance. These factors result in a larger RC load on the signal lines. Consequently, signal delay (RC delay), IR drop, and IR rise caused by this RC load become more severe. These phenomena significantly affect the display quality of the product.

[0064] Micro OLED displays typically have a size of less than 100 micrometers, such as less than 50 micrometers, and involve the combination of organic light-emitting diode (OLED) technology and CMOS technology, fabricating OLED arrays on a silicon-based substrate that includes CMOS circuitry.

[0065] Miniature OLEDs are widely used in AR and VR fields. As the technology continues to develop, higher resolution is required, which puts forward higher requirements for the structural design of the display substrate, such as the arrangement of pixels and signal lines.

[0066] The display substrate provided in at least one embodiment of this disclosure, through optimized layout and wiring design, can achieve a subpixel area of ​​5.45um × 13.6um, thereby achieving high resolution (PPI) and optimized arrangement of pixel circuit array, and has a better display effect.

[0067] Figure 1A This is a block diagram of a display substrate provided in at least one embodiment of this disclosure. For example... Figure 1A As shown, the display substrate 10 includes a plurality of sub-pixels 100 arranged in an array, a plurality of scan lines 11, and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 intersect each other in the display area to define a plurality of pixel regions arranged in an array, and a pixel circuit of a sub-pixel 100 is disposed in each pixel region. The pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, a 7T1C, etc. nTmC (n, m are positive integers) pixel circuit, and in different embodiments, the pixel circuit may further include a compensation sub-circuit, which may include an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include transistors, capacitors, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc. For example, the display substrate may also include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area. The gate driving sub-circuit 13 is connected to the pixel circuit via scan line 11 to provide various scan signals, and the data driving sub-circuit 14 is connected to the pixel circuit via data line 12 to provide data signals. Figure 1A The positional relationship of the gate drive sub-circuit 13 and data drive sub-circuit 14, scan line 11 and data line 12 in the display substrate shown is only an example. The actual arrangement can be designed as needed.

[0068] For example, the display substrate 10 may also include control circuitry (not shown). This control circuitry may be configured to control the data driving sub-circuit 14 to apply the data signal and to control the gate driving sub-circuit to apply the scan signal. An example of this control circuitry is a timing control circuit (T-con). The control circuitry can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0069] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0070] For example, a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data may also be stored in the computer-readable storage medium.

[0071] The pixel circuit may include, as needed, a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit. It may also include, as needed, a light emission control sub-circuit, a reset circuit, etc.

[0072] Figure 1B A schematic diagram of a pixel circuit is shown. (For example...) Figure 1B As shown, the pixel circuit includes a data writing sub-circuit 111, a driving sub-circuit 112, and a storage sub-circuit 113.

[0073] The data writing sub-circuit 111 is electrically connected to the first terminal of the storage sub-circuit 113 and is configured to transmit the data signal Vd to the first terminal of the storage sub-circuit 113 in response to a control signal (first control signal SEL). The second terminal of the storage sub-circuit 113 is configured, for example, to receive a second power supply voltage VSS.

[0074] The driving sub-circuit 112 includes a control electrode (control terminal) 150, a first electrode (first terminal) 151, and a second electrode (second terminal) 152. The control electrode 150 of the driving sub-circuit is electrically connected to the first terminal of the storage sub-circuit. The first electrode 151 of the driving sub-circuit 112 is configured to receive a first power supply voltage VDD. The second electrode 152 of the driving sub-circuit 112 is electrically connected to a first node S and connected to the first electrode 121 of the light-emitting element 120. The driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage at the first terminal of the storage sub-circuit. The second electrode 122 of the light-emitting element 120 is configured, for example, to receive a first common voltage Vcom1.

[0075] In at least some embodiments of this disclosure, such as Figure 1BAs shown, the pixel circuit also includes a bias sub-circuit 114. The bias sub-circuit 114 includes a control terminal, a first terminal, and a second terminal. The control terminal of the bias sub-circuit 114 is configured to receive a bias signal; the first terminal of the bias sub-circuit 114 is configured, for example, to receive a second power supply voltage VSS; and the second terminal of the bias sub-circuit 114 is electrically connected to the first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, such as 0.8V-1V. Under the action of the bias signal, the bias sub-circuit 114 is normally open and configured to provide a constant current, thereby making the voltage applied to the light-emitting element 120 linearly related to the data signal, which helps to achieve fine control of grayscale and thus improve the display effect. This will be further explained later with reference to a specific circuit.

[0076] For example, when the data signal (voltage) Vd changes from high to low, the grayscale voltage written to the first electrode 121 of the light-emitting element 120 needs to change rapidly. The bias sub-circuit 114 can also allow the first electrode 121 of the light-emitting element 120 to release charge quickly, thereby achieving better dynamic contrast.

[0077] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure use metal-oxide-semiconductor field-effect transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0078] The display substrate provided in this disclosure can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed from a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), and cyclic olefin copolymers (COC). The embodiments in this disclosure are all described using a silicon substrate as an example, that is, the pixel structure is fabricated on a silicon substrate; however, this disclosure does not limit the scope of the embodiments.

[0079] For example, the pixel circuit includes a complementary metal-oxide-semiconductor (CMOS) circuit, meaning the pixel circuit is fabricated on a single-crystal silicon substrate. Thanks to mature CMOS integrated circuit technology, silicon-based processes can achieve high precision (e.g., PPI can reach 6500 or even over 10,000).

[0080] For example, if the first electrode 121 and the second electrode 122 of the light-emitting element 120 in the sub-pixel are short-circuited due to process fluctuations in the display substrate, the voltage of the first electrode 121 of the light-emitting element 120 may be too high (e.g., the first common voltage Vcom1 is at a high potential) or too low (e.g., the first common voltage Vcom1 is at a low potential). This may cause the PN junction formed between the second electrode of the driving sub-circuit and the substrate to turn on, resulting in CMOS circuit failure and defects such as dark lines on the display substrate.

[0081] In some examples, for instance, the data writing sub-circuit includes a first data writing transistor P1, and the driving sub-circuit includes a driving transistor N2; for example, the first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), and the driving transistor N2 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS). The gate, first electrode, and second electrode of the driving transistor N2 serve as the control electrode 150, the first electrode 151, and the second electrode 152 of the driving sub-circuit 112, respectively. In this case, for example, when the first common voltage Vcom1 supplied to the second electrode 122 of the light-emitting element 120 is low, and a short circuit occurs between the first electrode 121 and the second electrode 122 of the light-emitting element 120, the potential of the second electrode of the driving transistor directly connected to the first electrode 121 will be too low.

[0082] Figure 1CThe diagram illustrates a transistor failure in the pixel circuit. The N-type active region (e.g., the second electrode) of the driving transistor N2, the P-type silicon substrate, the N-type well region where the first data writing transistor P1 is located, and the P-type active region (e.g., the first electrode) of the first data writing transistor P1 form two parasitic transistors Q1 and Q2 connected to each other, constituting an NPNP structure. When the potential of the second terminal (i.e., at the first node S) of the driving transistor N2 is too low, the PN junction (emitter junction) between the second terminal (N-type heavily doped region) of the driving transistor N2 and the P-type substrate becomes forward biased. Q1 turns on, providing a sufficiently large current to turn on the parasitic transistor Q2, which in turn feeds current back to the parasitic transistor Q1, forming a vicious cycle. In the end, most of the current flows directly from VDD through the parasitic transistor to VSS, without being controlled by the transistor gate voltage, causing the CMOS pixel circuit to fail. Furthermore, this circuit failure causes the parasitic transistor Q2 to continuously draw current from the emitter, i.e., from the data line, thereby causing a row of sub-pixels connected to the data line to fail, resulting in defects such as dark lines on the display substrate, which greatly affects the display effect.

[0083] In at least some embodiments of this disclosure, at least one sub-pixel further includes a resistor connected between the second electrode 152 of the driving sub-circuit 112 and the first electrode 121 of the light-emitting element 120. The resistor can increase or decrease the S potential of the first node, thereby mitigating or avoiding circuit failure, improving circuit reliability, and enhancing display performance.

[0084] Figure 2A This is a schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure. Figure 2A As shown, the pixel circuit also includes a resistor 130. The first end 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving sub-circuit 112, and the second end 132 is electrically connected to the first electrode 121 of the light-emitting element 120. That is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130.

[0085] For example, the resistor 130 can be a constant resistor or a variable resistor, or it can be an equivalent resistor formed by other devices (such as transistors).

[0086] For example, the resistor 130 is insulated from the control electrode 150 of the drive sub-circuit 112 in the same layer, and the resistivity of the resistor is higher than that of the control electrode of the drive sub-circuit, that is, the conductivity of the control electrode of the drive sub-circuit is higher than that of the resistor. For example, the resistivity of the resistor is more than ten times that of the control electrode.

[0087] It should be noted that, in this disclosure, "co-layered configuration" refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layered configurations may be made of the same material, while the final materials may be the same or different. "Integral structure" in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different.

[0088] This setup allows the control electrodes and resistors of the drive sub-circuit to be formed in the same patterning process, thus saving process time.

[0089] For example, both the resistor and the control electrode of the driving sub-circuit are made of polycrystalline silicon, and the doping concentration of the resistor is lower than that of the control electrode, thus the resistor has a higher resistivity than the control electrode. For example, the resistor can be intrinsic polycrystalline silicon or lightly doped polycrystalline silicon, and the control electrode can be heavily doped polycrystalline silicon.

[0090] In other examples, the materials of the control electrode and the resistor can be different. For example, the materials of the control electrode and the resistor can each include a metal and a corresponding metal oxide. For example, the metal can include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys of the above metals.

[0091] In at least one embodiment of this disclosure, the data writing sub-circuit 111 may include a transmission gate circuit consisting of two complementary transistors connected in parallel; the control signals include two inverted control signals. The transmission gate structure employed in the data writing sub-circuit 111 can facilitate lossless transmission of data signals to the first terminal of the storage sub-circuit 113.

[0092] For example, the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal, and a second terminal. The first and second control electrodes of the data writing sub-circuit are respectively configured to receive a first control signal and a second control signal. The first terminal of the data writing sub-circuit is configured to receive a data signal. The second terminal of the data writing sub-circuit is electrically connected to the first terminal of the storage sub-circuit and is configured to transmit the data signal to the first terminal of the storage sub-circuit in response to the first control signal and the second control signal.

[0093] It should be noted that in the description of the embodiments of this disclosure, the first node S does not necessarily represent an actual existing component, but rather represents the junction point of related circuit connections in the circuit diagram.

[0094] It should be noted that, in the description of the embodiments of this disclosure, the symbol Vd can represent both a data signal terminal and the level of a data signal; similarly, the symbol SEL can represent both a control signal and a control signal terminal; the symbols Vcom1 and Vcom2 can represent both a first common voltage and a second common voltage, or both a first common voltage terminal and a second common voltage terminal; the symbol VDD can represent both a first voltage terminal and a first power supply voltage; and the symbol VSS can represent both a second voltage terminal and a second power supply voltage. The following embodiments are the same and will not be described again.

[0095] Figure 2B It shows Figure 2A The circuit diagram shows a specific implementation example of the pixel circuit. For example... Figure 2B As shown, the data writing sub-circuit 111 includes a first data writing transistor P1 and a second data writing transistor N1 connected in parallel. The first data writing transistor P1 and the second data writing transistor N1 are a P-type metal-oxide-semiconductor field-effect transistor (PMOS) and an N-type metal-oxide-semiconductor field-effect transistor (NMOS), respectively. The control signals include a first control signal SEL and a second control signal SEL_B that are inversely related. The gate of the first data writing transistor P1 serves as the first control electrode of the data writing sub-circuit and is configured to receive the first control signal SEL. The gate of the second data writing transistor N1 serves as the second control electrode of the data writing sub-circuit and is configured to receive the second control signal SEL_B. The first terminal of the second data writing transistor N1 is electrically connected to the first terminal of the first data writing transistor P1, serving as the first terminal of the data writing sub-circuit and configured to receive the data signal Vd. The second terminal of the second data writing transistor N1 is electrically connected to the second terminal of the first data writing transistor P1, serving as the second terminal of the data writing sub-circuit and is electrically connected to the control electrode 150 of the driving sub-circuit 112.

[0096] For example, the first data write transistor P1 and the second data write transistor N1 are the same size and have the same channel width-to-length ratio.

[0097] The data writing sub-circuit 111 utilizes the complementary electrical characteristics of transistors, and has a low on-state resistance regardless of whether it transmits a high level or a low level, thus having the advantage of electrical signal transmission integrity, and can transmit the data signal Vd to the first terminal of the storage sub-circuit 113 without loss.

[0098] For example, such as Figure 2B As shown, the driving sub-circuit 112 includes a driving transistor N2, for example, the driving transistor N2 is an NMOS. The gate, first electrode, and second electrode of the driving transistor N2 serve as the control electrode, first electrode, and second electrode of the driving sub-circuit 112, respectively.

[0099] For example, the storage sub-circuit 113 includes a storage capacitor Cst, which includes a first capacitor electrode 141 and a second capacitor electrode 142. The first capacitor electrode 141 and the second capacitor electrode 142 serve as the first terminal and the second terminal of the storage sub-circuit 113, respectively.

[0100] For example, resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving sub-circuit 112 and the substrate. The resistance of resistor 130 is configured such that the PN junction is turned off when the driving transistor N2 operates in the saturation region, that is, when the pixel circuit operates to drive the light-emitting element 120 to emit light. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, the voltage drop across resistor 130 can protect the potential of the second electrode 152, thereby preventing circuit failure.

[0101] For example, the resistance value of resistor 130 Where Vs is the bias voltage of the substrate, Vcom1 is the first common voltage supplied to the second electrode of the light-emitting element, Von is the on-state voltage of the PN junction, and Is is the saturation current driving transistor N2 to operate in the saturation region. Where, μ n Where Cox is the carrier mobility of the driving transistor, W / L is the aspect ratio of the channel region, Vgs is the voltage difference between the gate and source of the driving transistor, and Vth is the threshold voltage of the driving transistor. For example, the on-state voltage Von is 0.6-0.7V. With the above settings, it can be ensured that when the driving transistor N2 operates in the saturation region, the PN junction formed between the second electrode 152 of the driving sub-circuit 112 and the substrate is turned off.

[0102] For example, the light-emitting element 120 is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element 120 can be a top-emitting OLED, emitting red, green, blue, or white light, etc. For example, the light-emitting element 120 is a micro OLED. The embodiments of this disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is the anode of the OLED, and the second electrode 122 is the cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of this disclosure do not limit this, and the pixel circuit can also be a common anode structure depending on the change in circuit structure.

[0103] For example, the bias sub-circuit 114 includes a bias transistor N3, the gate, first terminal, and second terminal of which serve as the control terminal, first terminal, and second terminal of the bias sub-circuit 114, respectively.

[0104] Figure 2C It shows Figure 2B The signal timing diagram of the pixel circuit shown below will be combined with the following. Figure 2B The signal timing diagram shown is for Figure 2C The working principle of the pixel circuit shown will be explained. For example, the second data writing transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data writing transistor is a P-type transistor; however, this embodiment of the present disclosure does not limit this.

[0105] Figure 2C The waveforms of each signal are shown in two consecutive display cycles T1 and T2. For example, the data signal Vd is a high grayscale voltage in display cycle T1 and a low grayscale voltage in display cycle T2.

[0106] For example, such as Figure 2C As shown, the display process of each frame of the image includes a data writing stage 1 and a light emission stage 2. One operating process of the pixel circuit includes: in the data writing stage 1, both the first control signal SEL and the second control signal SEL_B are on, the first data writing transistor P1 and the second data writing transistor N1 are turned on, and the data signal Vd is transmitted to the gate of the driving transistor N2 via the first data writing transistor P1 and the second data writing transistor N1; in the light emission stage 2, both the first control signal SEL and the second control signal SEL_B are off. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the driving transistor N2 operates in saturation and the current remains constant, driving the light-emitting element 120 to emit light. When the pixel circuit transitions from display cycle T1 to display cycle T2, the data signal Vd changes from a high grayscale voltage to a low grayscale voltage. Under the control of the second common voltage Vcom2, the bias transistor N3 generates a stable drain current. This drain current can quickly discharge the charge stored in the OLED anode when the grayscale of the OLED display needs to change rapidly. For example, the discharge process occurs during the data writing phase 1 of display cycle T2. Therefore, during the light emission phase 2 of display cycle T2, the voltage of the OLED anode drops rapidly, thereby achieving better dynamic contrast and improving the display effect.

[0107] refer to Figure 2B For example, during the light-emitting stage, the OLED light-emitting element emits light in the nanoamp range (e.g., several nanoamps) when writing grayscale data, while the bias transistor N3 operates in the saturation region under the control of the bias signal, i.e., the second common voltage Vcom2, generating a current in the microamp range (e.g., 1 microamp). Therefore, almost all the current flowing through the driving transistor N2 flows into the bias transistor N3, and the two can be considered the same, i.e. Here it is assumed that the driving transistor N2 and the bias transistor N3 have the same transistor conductivity μ. n C ox Given W / L, we get Vgs1 - Vth1 = Vgs2 - Vth2, where Vgs1 and Vth1 are the voltage difference Vgs1 between the gate and source of driving transistor N2 and the threshold voltage, respectively. Vgs2 and Vth2 are the voltage difference between the gate and source of bias transistor N3 and the threshold voltage, respectively. Since Vgs2 - Vth2 = Vcom2 - VSS - Vth2 is a constant, denoted as K0, we also have Vgs1 - Vth1 = K0, which means Vd - V0 - Vth1 = K0. Here, Vd is the data signal held at the gate of driving transistor N2 during the light-emitting stage, and V0 is the voltage at the first node S. Therefore, we can deduce that the voltage V0 at the first node S is linearly related to the data signal (data voltage) Vd.

[0108] For example, bias transistor N3 operates in the saturation region under the control of bias signal Vcom2, and the voltage difference between the gate and source of bias transistor N3 is Vcom2-VSS, which is a constant value. According to the formula for transistor current in the saturation region, the current flowing through bias transistor N3 at this time is a constant current. Therefore, bias transistor N3 can be regarded as a current source.

[0109] For example, when the first node S is directly electrically connected to the light-emitting element 120, the voltage V0 is directly applied to the first electrode 121 of the light-emitting element 120, such as the anode voltage of the OLED; when the first node S is electrically connected to the light-emitting element 120 through the resistor 130, since the current flowing through the light-emitting element 120 is extremely small, the voltage of the first node S can be approximately equal to the voltage of the first electrode 121 of the light-emitting element 120; that is, the voltage of the first electrode 121 of the light-emitting element 120 is linearly related to the data signal (data voltage) Vd, thereby enabling fine control of grayscale and improving the display effect.

[0110] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals with the same amplitude but opposite phase. This helps improve the circuit's anti-interference performance. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate drive circuit unit (such as the GOA unit), thereby simplifying the circuit.

[0111] For example, such as Figure 1AAs shown, the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14. The data driving circuit 13 is configured to output data signals as needed (e.g., an image signal from the input display device), such as the aforementioned data signal Vd. The scan driving circuit 14 is configured to output various scan signals, such as the aforementioned first control signal SEL and second control signal SEL_B, which may be, for example, an integrated circuit chip (IC) or a gate drive circuit (GOA) directly fabricated on the display substrate.

[0112] For example, the display substrate uses a silicon substrate as the substrate 101, and the pixel circuit, data driving circuit 13, and scan driving circuit 14 can all be integrated on the silicon substrate. In this case, since silicon-based circuits can achieve higher precision, the data driving circuit 13 and scan driving circuit 14 can, for example, be formed in the area corresponding to the display area of ​​the display substrate, and are not necessarily located in the non-display area.

[0113] For example, the display substrate 10 also includes a control circuit (not shown). This control circuit is configured to control the data driving circuit 13 to apply the data signal Vd, and to control the gate driving circuit 13 to apply various scan signals. An example of this control circuit is a timing control circuit (T-con). The control circuit can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0114] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0115] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 121 may execute the functions expected by the program instructions. Various application programs and various data, such as electrical characteristic parameters acquired in the above-described detection method, may also be stored in the computer-readable storage medium.

[0116] The following adopts Figure 2B The pixel circuit shown is used as an example to illustrate the display substrate provided in at least one embodiment of the present disclosure; however, the embodiments of the present disclosure are not limited thereto.

[0117] Figure 3A This is a schematic diagram of a display substrate 10 provided for at least one embodiment of the present disclosure. For example, such as... Figure 3A As shown, the display substrate 10 includes a substrate 101, and a plurality of sub-pixels 100 are located on the substrate 101. The plurality of sub-pixels 100 are arranged in a sub-pixel array, the row direction of the sub-pixel array is a first direction D1, the column direction is a second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonal. Figure 3A The example shows two rows and six columns of subpixels, namely two pixel rows 20 and six pixel columns 30, and the areas of three pixel columns spaced apart from each other are shown with dashed boxes.

[0118] For example, the substrate 101 can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), and cyclic olefin copolymers (COC). The embodiments in this disclosure are all described using a silicon substrate as an example; however, the embodiments in this disclosure are not limited to this.

[0119] For example, the substrate 101 includes monocrystalline silicon or high-purity silicon. The pixel circuit is formed on the substrate 101 using CMOS semiconductor processes. For instance, the active regions of transistors (including the channel region, first electrode, and second electrode) are formed in the substrate 101 through a doping process, and insulating layers are formed through silicon oxidation or chemical vapor deposition (CVD), and multiple conductive layers are formed through sputtering to form a wiring structure. The active regions of each transistor are located inside the substrate 101.

[0120] Figure 3B It shows Figure 3A A sectional view along section line I-I'. For clarity, Figure 3B Some traces or electrode structures that are not directly connected have been omitted.

[0121] For example, such as Figure 3BAs shown, the display substrate 10 includes a substrate 101, a first insulating layer 201, a polysilicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, sequentially located on the substrate 101. The structure of this display substrate 10 will be described layer by layer below. Figure 3B This will be used as a reference and explained together.

[0122] For clarity and ease of explanation, Figure 4A The portion of the display substrate 10 below the first conductive layer 301 is shown, namely the substrate 101 and the first insulating layer 201 and polysilicon layer 102 thereon, including each transistor (P1, N1-N3), storage capacitor Cst and resistor 130. Figure 4B It shows Figure 4A A magnified illustration of a subpixel 100; for clarity, in Figure 4A The text also shows corresponding examples. Figure 3A Mid-section line I-I'. Figures 5A-5E It shows Figure 4A The formation process of the substrate structure shown.

[0123] like Figure 4B As shown, for example, in a direction parallel to the surface of the substrate 101, the first data writing transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, for example, on opposite sides of the storage capacitor Cst in the second direction D2.

[0124] Reference Figure 1C This setup helps to increase the distance between the first data writing transistor P1 and the driving transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of circuit failure in the CMOS circuit.

[0125] For example, the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, combined with Figure 3B and Figure 4B As shown, the second capacitor electrode 142 of the storage capacitor 140 is the first region 401 of the substrate 101; for example, the substrate 101 is a P-type silicon substrate, and the material of the second capacitor electrode 142 is P-type single crystal silicon. When a voltage is applied to the first capacitor electrode 141, the semiconductor-type first region 401 located below the first capacitor electrode 141 in the substrate 101 forms an inversion region and becomes a conductor, which, together with the contact hole regions on both sides of the first region 401 (such as...), forms an inversion region. Figure 4B The contact hole regions 145a and 145b shown form an electrical connection. In this case, no additional doping or other treatment is applied to the first region 401.

[0126] In another example, the first region 401 is, for example, a conductor region in the substrate 101, such as a heavily doped region, which allows the second capacitor electrode 142 to obtain a stable and high conductivity.

[0127] For example, the substrate 101 further includes a second region 402, which is an N-type well region in the substrate 101. Figure 4B As shown, for example, the first data writing transistor P1 and resistor 130 are arranged side-by-side in the second region 402 in the second direction D2. Placing the resistor 130, made of polysilicon, in an N-type substrate helps reduce parasitic effects and improve circuit characteristics.

[0128] For example, in a direction parallel to the surface of the substrate 101, resistor (R) 130 and first data write transistor P1 are located on the same side of the second capacitor electrode 142. For example, in a direction parallel to the surface of the substrate 101, drive transistor N2 and bias transistor N3 are located on the same side of the second capacitor electrode 142.

[0129] For example, such as Figure 4B As shown, the first data write transistor P1 and the second data write transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2. For example, the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2.

[0130] For example, resistor 130 has a U-shaped structure, such as an asymmetrical U-shaped structure, where the two branches of the U-shaped structure are of unequal length. For example, as... Figure 4B As shown, the second end 132 of resistor 130 is closer to the driving transistor N2.

[0131] Setting resistor 130 in a U-shape helps save the layout area occupied by the resistor, thereby improving the space utilization of the layout and contributing to the improvement of the display substrate resolution. For example, within the same space, a U-shaped resistor can increase the length of the resistor to obtain the desired resistance value.

[0132] Furthermore, designing resistor 130 as an asymmetric structure is also to make better use of layout space, for example, as Figure 4BAs shown, a contact hole region 411a is designed above the shorter branch of the U-shaped resistor. This contact hole region 411a is parallel to the second end 132 of the resistor 130 in the first direction D1. For example, this contact hole region 411a is an N-type heavily doped region (N+). For example, this contact hole region 411a is used to bias the well region 401 where the first data writing transistor P1 is located, thereby avoiding threshold voltage changes caused by parasitic effects such as substrate bias effects and improving circuit stability. For example, refer to... Figure 3B By applying a low-voltage bias to the P-type substrate 101 and a high-voltage bias to the N-type well region 402, the parasitic PN junction between the two can be reverse-biased, thereby electrically isolating the devices, reducing parasitic effects between the devices, and improving circuit stability.

[0133] For example, the opening of the U-shaped structure faces the first capacitor electrode 141, and the first end 131 and the second end 132 of the resistor 130 are located at the two ends of the U-shaped structure, respectively. As shown in the figure, the first end 131 of the resistor 130 is provided with a contact hole area 133 for electrical connection with the gate 150 of the driving transistor N2; the second end 132 of the resistor 130 is provided with a contact hole area 134 for electrical connection with the first electrode 121 of the light-emitting element 120.

[0134] For example, the material of the resistor 130 includes polycrystalline silicon, and the contact hole regions 133 and 134 are doped regions to reduce contact resistance; the main body region of the resistor 130 other than the contact hole regions is, for example, an intrinsic region or a low-doped region, thereby obtaining the desired resistance value.

[0135] For example, the first capacitor electrode 141 of the storage capacitor 140 is insulated from the resistor 130 in the same layer and both are made of polycrystalline silicon material; the doping concentration of the first capacitor electrode 141 of the storage capacitor 140 is higher than the doping concentration of the main body region of the resistor 130. For example, the main body region of the resistor 130 is made of intrinsic polycrystalline silicon material.

[0136] For example, the gates 160, 170, 150, and 180 of each transistor P1, N1-N3 are disposed on the same layer as the first capacitor electrode 141 of the storage capacitor 140, and all are made of polycrystalline silicon material. For example, as Figure 4B As shown, the gate 150 of the driving transistor N2 and the first capacitor electrode 141 are connected to each other as a single unit.

[0137] Figure 4BThe active regions P1a, N1a, N2a and N3a of each transistor P1, N1-N3 are also shown, along with the first electrode 161 and the second electrode 162 of the first data writing transistor P1, the first electrode 171 and the second electrode 172 of the second data writing transistor N1, the first electrode 151 and the second electrode 152 of the driving transistor N2, and the first electrode 181 and the second electrode 182 of the bias transistor N3.

[0138] Figure 4B The diagram also shows the gate contact region 165, first contact region 163, and second electrode contact region 164 of the first data writing transistor P1; the gate contact region 175, first contact region 173, and second electrode contact region 174 of the second data writing transistor N1; the gate contact region 155, first contact region 153, and second electrode contact region 154 of the driving transistor N2; and the gate contact region 185, first contact region 183, and second electrode contact region 184 of the bias transistor N3. For example, each first electrode contact region is the area where the corresponding first electrode is used to form an electrical contact; each second electrode contact region is the area where the corresponding second electrode contact region is used to form an electrical contact; and each gate contact region is the area where the corresponding gate is used to form an electrical contact.

[0139] For example, the active region P1a of the first data writing transistor P1 and the active region N1a of the second data writing transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2.

[0140] like Figure 4B As shown, the area of ​​the active region N2a of the driving transistor N2 is larger than that of the active regions of other transistors, which can achieve a larger aspect ratio, thus helping to improve the driving capability of the driving transistor N2 and thereby improve the display effect.

[0141] like Figure 4B As shown, for transistors with large active regions, such as driving transistor N2 and bias transistor N3, there is enough space to set at least two contact hole regions on their first and second poles respectively, so that they can make sufficient contact with the structure to be connected and form a parallel structure, thereby reducing the contact resistance.

[0142] Figure 4B The diagram also shows a contact hole region 144 on the first capacitor electrode 141 and contact hole regions 145a and 145b configured to be electrically connected to the second capacitor electrode 142. Figure 4B As shown, the first capacitor electrode 141 and the second capacitor electrode 142 are respectively provided with at least two contact hole areas to reduce contact resistance.

[0143] Reference Figure 4AThe distribution of transistors (including the shape and size of each transistor) and storage capacitors and resistors in two adjacent sub-pixels 100 in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2. That is, the corresponding structures in the two sub-pixels are symmetrical about the axis of symmetry along the second direction D2. The distribution of transistors in two adjacent sub-pixels 100 in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1.

[0144] This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display substrate. Furthermore, this symmetrical arrangement allows for the integral formation of interconnected structures within the same layer of the substrate. Compared to separate arrangements, this results in a more compact pixel layout, improving space utilization and ultimately increasing the resolution of the display substrate.

[0145] For example, such as Figure 4A As shown, the second region 402 of two adjacent sub-pixels 100 in the first direction D1 is a single structure, and the second region 402 of two adjacent sub-pixels 100 in the second direction D2 is also a single structure. That is, the first data writing transistor P1 and resistor 130 in these four adjacent sub-pixels 100 are located in the same well region. Compared to setting separate well regions, this arrangement can make the pixel arrangement more compact while meeting design rules, which helps to improve the resolution of the display substrate.

[0146] For example, such as Figure 4A As shown, the active regions P1a of the first data writing transistors P1 of two adjacent sub-pixels on the second direction D2 are connected to each other in a structure that is, the active regions P1a of the two first data writing transistors P1 are located in the same doped region A1 (P-well) of the same second region 402, and the first poles of the two first data transistors P1 are connected to each other in a structure to receive the same data signal Vd.

[0147] For example, such as Figure 4A As shown, the active regions N1a of the second data writing transistors N1 of two adjacent sub-pixels on the second direction D2 are connected to each other in a structure that is, the active regions N1a of the two second data writing transistors N1 are located in the same doped region A2 (N-well) of the substrate 101, and the first poles of the two second data writing transistors N1 are connected to each other in a structure to receive the same data signal Vd.

[0148] For example, such as Figure 4A As shown, the gates of the first data writing transistor P1 or the second data writing transistor N2 of two adjacent sub-pixels 100 in the first direction D1 are connected to each other as a single unit.

[0149] Since the gates of the first data write transistors P1 are configured to receive the same first control signal SEL for each row of pixels, and the gates of the second data write transistors N1 are configured to receive the same second control signal SEL_B, and since the transistors of two adjacent sub-pixels in the first direction D1 are mirror symmetrical, alternating between adjacent first write transistors P1 and adjacent second write transistors N1 in the first direction D1, the gates of two adjacent first data write transistors P1 can be directly connected into a single structure to form the first control electrode group 191, and the gates of adjacent second data write transistors N1 can be directly connected into a single structure to form the second control electrode group 192. This arrangement allows for a more compact pixel arrangement while meeting design requirements, thus contributing to improved resolution of the display substrate.

[0150] like Figure 4A As shown, for two adjacent sub-pixels 100 in the first direction D1, when their driving transistors N2 are adjacent, the active regions N2a of the two driving transistors N2 are connected to each other in a single structure, that is, the active regions N2a of the two driving transistors N2 are located in the same doped region B (N-well) of the substrate 101, and the first electrodes of the two driving transistors N2 are connected to each other in a single structure, forming a third control electrode group 193 to receive the same first power supply voltage VDD; when their bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other in a single structure to receive the same second common voltage Vcom2; the active regions N3a of the two bias transistors N3 are connected to each other in a single structure, that is, the active regions N3a of the two bias transistors N3 are located in the same doped region C (N-well) of the substrate 101, and the first electrodes of the two bias transistors N3 are connected to each other in a single structure to receive the same second power supply voltage VSS.

[0151] This setup allows for a more compact pixel arrangement while still meeting design requirements, which helps improve the resolution of the display substrate.

[0152] Figures 5A-5D It shows Figure 4A For clarity, the formation process of the substrate structure shown in the figure only shows two rows and two columns of sub-pixels, that is, four adjacent sub-pixels 100, which constitute a pixel unit group. Figure 4A The pixel unit group 420 is illustrated with a dashed box. For example, the display substrate includes a plurality of pixel unit groups arranged along a first direction D1 and a second direction D2.

[0153] The following combination Figures 5A-5D The formation process of the display substrate provided in the embodiments of this disclosure is illustrated by way of example, but this is not intended to limit the disclosure.

[0154] For example, a silicon substrate is provided, such as a P-type single-crystal silicon substrate. N-type transistors (e.g., driving transistors) can be fabricated directly on this P-type silicon substrate, that is, the P-type substrate acts as the channel region of the N-type transistor, which is beneficial to taking advantage of the high speed of NMOS devices and improving circuit performance.

[0155] like Figure 5A As shown, for example, N-type doping is performed on a P-type silicon substrate to form an N-type well region, namely the second region 402, to serve as the substrate for the first data writing transistor P1 and the resistor 130.

[0156] For example, the second regions 402 of two adjacent sub-pixels in the first direction D1 can be connected to each other, and the second regions 402 of two adjacent sub-pixels in the second direction D2 can be connected to each other. For example, during the N-type doping, the undoped regions on the substrate 101 are shielded.

[0157] Combination Figure 4B and Figure 5B As shown, for example, a first insulating layer 201 is formed on the substrate 101, and then a polysilicon layer 102 is formed on the first insulating layer 201.

[0158] The first insulating layer 201 includes the gate insulating layer of each transistor and the dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 includes the first capacitor electrode 141, the resistor 130, and the gates 150, 160, 170, and 180 of each transistor (P1, N1-N3).

[0159] The gate of the first data writing transistor P1 is located in the second region 402, and the N-type well region serves as the channel region of the P-type transistor. The resistor 130 is also formed in the second region 402; that is, the orthogonal projection of the resistor 130 onto the substrate lies within this second region. Forming the polysilicon resistor 130 within the N-type substrate helps reduce parasitic effects and improve circuit characteristics. Each N-type transistor is formed directly on the P-type substrate outside the N-type well region.

[0160] For example, such as Figure 5B As shown, the orthographic projection of the first capacitive electrodes 141 of the four sub-pixels in each pixel unit group onto the substrate is located outside the second region 402 and surrounds the second region 402. For example, the second region 402 is rectangular, and the orthographic projection of the first capacitive electrodes 141 of each sub-pixel onto the substrate surrounds one corner of the rectangle; for example, each first capacitive electrode 141 includes a recessed structure with an L-shaped outline, and one corner of the rectangle extends into the orthographic projection of the recessed structure, matching the L-shaped outline.

[0161] like Figure 5B As shown, the patterns of the polysilicon layers in two adjacent sub-pixels in the first direction D1 are symmetrical about the axis of symmetry along the second direction D2; the patterns of the polysilicon layers in two adjacent sub-pixels in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1, that is, the patterns of the polysilicon layers are symmetrical patterns. For example, as... Figure 5B As shown, the resistors of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the resistors of adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction. For example, the first capacitor electrode of adjacent sub-pixels in the first direction is symmetrical about an axis of symmetry along the second direction, and the first capacitor electrode of adjacent sub-pixels in the second direction is symmetrical about an axis of symmetry along the first direction.

[0162] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two adjacent sub-pixels in the first direction D1 are symmetrical about the axis of symmetry along the second direction. For example, the gates of the first data write transistor P1 or the second data write transistor N1 of two adjacent sub-pixels in the first direction D1 are integrally formed.

[0163] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two adjacent sub-pixels in the second direction D2 are symmetrical about the axis of symmetry along the first direction.

[0164] For example, the first insulating layer is formed on a substrate by thermal oxidation. For example, the material of the first insulating layer is a silicon nitride, oxide, or oxynitride.

[0165] For example, a polysilicon material layer is formed on the first insulating layer by chemical vapor deposition (PVD), and then the polysilicon material layer is formed by photolithography to form the polysilicon layer 102.

[0166] Figure 5C The doped window region 103 of the substrate is shown (left image), and in Figure 5B The doped window region is shown on the substrate structure (right figure). For example, the doping is heavy doping to form contact hole regions for electrical connections on the substrate. For example, the doped window region includes the source and drain regions of each transistor. For example, the doped window region also includes contact hole regions of the substrate and contact hole regions of resistor 130, for example including... Figure 4B The contact hole regions shown are 400a, 400b, 411a, 411b, 145a, 145b, 133, and 134. For example, since the gate of the transistor is formed of polycrystalline silicon, it also needs to be doped. During doping, a barrier layer needs to be formed to shield the undoped areas, exposing only the corresponding doped window areas and amorphous silicon areas.

[0167] It should be noted that, Figure 5C The diagram only illustrates the doping window regions. In the actual doping process, corresponding barrier layers / mask layers are added to expose the respective doping window regions and polysilicon regions for doping. For example, the material of the barrier layer / mask layer can be photoresist or oxide material.

[0168] like Figure 5D As shown, a barrier layer 135 is formed corresponding to resistor 130. In order to protect the resistance value of resistor 130, resistor 130 needs to be shielded during the doping process to prevent resistor 130 from being damaged by doping. The barrier layer 135 shields the main body of resistor 130, exposing only the contact hole areas 133 and 134 at both ends of resistor 130.

[0169] For example, the barrier layer 135 can be a silicon nitride, oxide, or oxynitride, or it can be a photoresist material. After the doping process is completed, the barrier layer 135 can be retained in the display substrate or removed.

[0170] In other examples, the barrier layer 135 of the resistor 130 may also be formed together with the barrier layer / mask layer of other regions during doping, which is not limited in the embodiments disclosed herein.

[0171] For example, during the doping process, N-type doping and P-type doping need to be performed separately, to form the source and drain regions of an N-type transistor and the source and drain regions of a P-type transistor. During the N-type doping process, a barrier layer needs to be formed to shield the regions not doped with N-type doping; during the P-type doping process, a barrier layer needs to be formed to shield the regions not doped with P-type doping.

[0172] Figure 5E The image shows N-type doped region SN and P-type doped region SP using different shading patterns (left image), and... Figure 5D The substrate shown illustrates the N-type doped region SN and the P-type doped region SP (right figure). The N-type doped region SN and the P-type doped region SP are... Figure 4B It is also shown in the text, which can be referred to together.

[0173] For example, the N-type doping process includes forming a barrier layer to cover the P-type doped region SP, and covering the N-type doped region SN except for the doped window region and the polysilicon region, retaining only the doped window region and the polysilicon region in the N-type doped region SN, that is, the SN region and... Figure 5C The overlapping region of the doped window region 103 and the polysilicon region is shown; then an N-type doping process is performed. (Comparison) Figure 4BThis N-type doping process can be used to form the gate, first electrode, and second electrode of transistors N1-N3, as well as contact hole regions 411a, 411b, 145a, and 145b. This N-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, boron.

[0174] For example, a P-type doping process includes forming a barrier layer to cover the N-type doped region SN, and covering the P-type doped region SP except for the doped window region and the polysilicon region, retaining only the doped window region and the polysilicon region within the P-type doped region SP. That is, the SP region and... Figure 5C The overlapping region of the doped window region 103 and the polysilicon region is shown; then, a P-type doping process is performed. (Comparison) Figure 4B The gate, first electrode, and second electrode of transistor P1, as well as contact holes 400a, 400b, 133, and 134, can be formed through this P-type doping process. This P-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, phosphorus.

[0175] During doping, such as with ion implantation, the polysilicon pattern can act as a mask, ensuring that ion implantation into the silicon substrate occurs precisely on both sides of the polysilicon, thus forming the first and second electrodes of each transistor and achieving self-alignment. Furthermore, the resistivity of the originally high-resistivity polysilicon decreases after doping, making it suitable for forming the gate of each transistor and the first capacitor electrode. Therefore, using polysilicon as the resistor and gate material offers several advantages and reduces processing costs.

[0176] Thus, it was formed Figure 4A The structure of the display substrate shown includes transistors P1, N1-N3, resistor 130, and storage capacitor Cst.

[0177] For example, in two adjacent sub-pixels in the first direction D1, the corresponding transistors, resistors, and storage capacitors Cst are symmetrical about the axis of symmetry along the second direction D2; in two adjacent sub-pixels in the second direction D2, the corresponding transistors, resistors, and storage capacitors Cst are symmetrical about the axis of symmetry along the first direction D1.

[0178] It should be noted that in this embodiment, the storage capacitor Cst is a field-effect capacitor. After a voltage is applied to the first capacitor electrode 141, an inverse charge is generated in the region of the substrate 101 located below the first capacitor electrode 141, which makes the lower plate of the storage capacitor Cst, i.e., the second capacitor electrode 142, conductive.

[0179] In other embodiments, the second capacitor electrode 142 may be formed by pre-conducting (e.g., doping) the region of the substrate 101 located below the first capacitor electrode 141. This disclosure does not limit this aspect.

[0180] exist Figure 4A The substrate shown is formed by sequentially forming a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, thus forming a... Figure 3A The display substrate shown.

[0181] Figure 6A and Figure 6B The pattern of the first conductive layer 301 and the first conductive layer 301 disposed on are shown respectively. Figure 4A The situation on the substrate structure shown. Figure 6C It shows Figure 6B A sectional view along section line IV-IV'; Figure 6B The image also shows a via in the second insulating layer 202, which is connected to... Figure 4B Each contact area in the diagram corresponds one-to-one, used to electrically connect each contact hole area to the pattern in the first conductive layer 301. For clarity, only two rows and six columns of sub-pixels are shown in the figure, and the area of ​​one sub-pixel 100 is indicated by a dashed box; furthermore, in Figure 6B The text also shows corresponding examples. Figure 3A The location of the mid-section line I-I'.

[0182] like Figure 6A As shown, the pattern of the first conductive layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2; the pattern of the first conductive layer in two adjacent sub-pixels in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1. The pattern of the first conductive layer will be illustrated below using a single sub-pixel as an example.

[0183] like Figure 6A As shown, the first conductive layer 301 includes a connection electrode 313 (an example of a first connection electrode in this disclosure) for electrically connecting the first terminal 131 of the resistor 130 to the second electrode 152 of the drive sub-circuit 112.

[0184] For example, in conjunction with reference Figure 6B The first end of the connecting electrode 313 is electrically connected to the first end 131 of the resistor 130 through a via 225 (an example of a first via in this disclosure) in the second insulating layer 202; the second end of the connecting electrode 313 includes a first branch 331 and a second branch 332, combined with Figure 3BThe first branch 331 is electrically connected to the first terminal 151 of the driving transistor N2 through a via 226a (an example of a second via in this disclosure) in the second insulating layer 202, and the second branch 332 is electrically connected to the first terminal 181 of the bias transistor N3 through a via 226b in the second insulating layer 202.

[0185] For example, such as Figure 6B As shown, in the second direction D2, the via 225 and via 226a are located on opposite sides of the first capacitor electrode 141; that is, the orthogonal projection of the connecting electrode 313 on the substrate 101 passes through the orthogonal projection of the first capacitor electrode 141 on the substrate 101 in the second direction D2.

[0186] For example, at least two vias 226a and 226b can be provided to reduce contact resistance.

[0187] For example, in conjunction with reference Figure 6A and Figure 6B The first conductive layer 301 also includes a connecting electrode 314, which is electrically connected to the second end 132 of the resistor 130 through a via 229 in the second insulating layer 202. The connecting electrode 314 is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0188] For example, the connection electrode 314 is L-shaped, with one branch electrically connected to the second terminal 132 of the resistor 130 and the other branch electrically connected to the first electrode 121 of the light-emitting element 120.

[0189] For example, combining Figure 6B and Figure 6C As shown, the first conductive layer 301 further includes a third capacitor electrode 315, which overlaps with the first capacitor electrode 141 in a direction perpendicular to the substrate. The third capacitor electrode 315 is located on the side of the first capacitor electrode 141 away from the second capacitor electrode 142 and is configured to be electrically connected to the second capacitor electrode 142; that is, in a direction perpendicular to the substrate, the second capacitor electrode 142 and the third capacitor electrode 315 are located on both sides of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel capacitor structure and increasing the capacitance value of the storage capacitor Cst.

[0190] For example, combining Figure 6B and Figure 6CAs shown, the third capacitor electrode 315 includes a first portion 315a and a second portion 315b, which are spaced apart from each other in a first direction D1. For example, the first portion 315a of the third capacitor electrode 315 is electrically connected to the contact hole region 145b through a through-hole 228 in the second insulating layer 202, so as to be electrically connected to the second capacitor electrode 142; the second portion 315b is electrically connected to the contact hole region 145a through a through-hole 227 in the second insulating layer 202, so as to be electrically connected to the second capacitor electrode 142.

[0191] For example, the first part 315a and the second part 315b of the third capacitor electrode 315 are located on both sides of the connecting electrode 313 in the first direction D1, and are respectively spaced apart from the connecting electrode 313.

[0192] For example, the third capacitor electrode 315 of two adjacent sub-pixels in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2, and the third capacitor electrode 315 of two adjacent sub-pixels in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1.

[0193] For example, such as Figure 6B As shown, the first portion 315a or the second portion 315b of the third capacitor electrode 135 of two adjacent sub-pixels in the first direction D1 is integrally formed.

[0194] For example, such as Figure 6B As shown, for each pixel unit group 420, the first portion 315a of the third capacitor electrode 315 of two adjacent sub-pixels in the first direction D1 is connected to each other as a single unit.

[0195] For example, such as Figure 6B As shown, the second part 315b of the third capacitor electrode 315 of the sub-pixel in each pixel unit group 420 and the second part 315b of the third capacitor electrode 315 of the sub-pixel in the pixel unit group adjacent to the sub-pixel are connected to each other as a whole.

[0196] For example, such as Figure 6A As shown, in the first direction, the adjacent third capacitor electrodes 315 in two adjacent sub-pixels of D1 can be integrally formed to receive the same second power supply voltage VSS.

[0197] For example, at least two vias 227 and 228 can be provided to reduce contact resistance; for example, the at least two vias 227 are arranged along the second direction D2, and the at least two vias 228 are arranged along the second direction D2.

[0198] For example, the first conductive layer 301 also includes a connection electrode 317 (an example of a second connection electrode in this disclosure), which is used to electrically connect the second end of the data writing sub-circuit to the first end of the storage sub-circuit, that is, to electrically connect the second electrode 162 of the first data writing transistor P1, the second electrode 172 of the second data writing transistor N1, and the first capacitor electrode 141.

[0199] Reference Figure 6A and Figure 6B The connection electrode 317 includes three ends, for example, a T-shaped structure. (Refer to reference...) Figure 3B The first end of the connection electrode 317 is electrically connected to the second electrode of the first data writing transistor P1 through a via 261a in the second insulating layer 202, the second end of the connection electrode 317 is electrically connected to the second electrode of the second data writing transistor N1 through a via 261b in the second insulating layer 202, and the third end of the connection electrode 317 is electrically connected to the first capacitor electrode 141 through a via 261c in the second insulating layer 202.

[0200] For example, such as Figure 6B As shown, in the second direction D2, the third ends of the connecting electrode 314 and the connecting electrode 317 at least partially overlap. This arrangement makes the pixel layout more compact, thereby improving the space utilization of the display substrate and increasing the resolution of the display substrate.

[0201] Reference Figure 6A and Figure 6B The first conductive layer 301 further includes a first scan line connection portion 311 and a second scan line connection portion 312. The first scan line connection portion 311 is electrically connected to the first scan line so that the gate of the first data writing transistor P1 receives the first control signal SEL. The second scan line connection portion 312 is electrically connected to the second scan line so that the gate of the second data writing transistor N1 receives the first control signal SEL_B.

[0202] For example, the first scan line connection portion 311 is electrically connected to the gate of the first data writing transistor P1 through the via 221 in the second insulating layer 202, and the second scan line connection portion 312 is electrically connected to the gate of the second data writing transistor N1 through the via 222 in the second insulating layer 202.

[0203] For example, such as Figure 6A As shown, adjacent sub-pixels in the first direction D1 share the first scan line connection portion 311 or the second scan line connection portion 312.

[0204] For a detailed description of the first scan line connection portion and the second scan line connection portion, please refer to the following section. Figures 10A-10B The description.

[0205] like Figure 6A As shown, the first conductive layer 301 also includes a data line connection portion 245, which is used to electrically connect with the data line so that the first terminal of the first data writing transistor P1 and the first terminal of the second data writing transistor N1 receive the data signal Vd transmitted by the data line.

[0206] like Figure 6B As shown, the data line connection portion 245 is electrically connected to the first electrode 161 of the first data writing transistor P1 through the via 223 in the second insulating layer 202, and electrically connected to the first electrode 171 of the second data writing transistor N1 through the hole 224 in the second insulating layer 202.

[0207] For example, such as Figure 6A As shown, multiple data line connection portions 245 are arranged at intervals in the first direction D1, for example, located at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection portion 245.

[0208] For a detailed description of the data cable connector, please refer to the following section. Figures 8A-8B The description of the second data cable connector.

[0209] refer to Figure 6A and Figure 6B The first conductive layer 301 also includes a connection electrode 318, which is electrically connected to the first electrode of the driving transistor N2 through a via 230 in the second insulating layer 202.

[0210] refer to Figure 4A and Figure 6B The first conductive layer 301 also includes connecting electrodes 319a, 319b, and 319c. These connecting electrodes are provided for biasing the substrate of the transistor, for example, to connect the N-type substrate to the first power supply voltage terminal to receive the first power supply voltage VDD (high voltage), or to connect the P-type substrate to the second power supply voltage terminal to receive the second power supply voltage VSS (low voltage). This can avoid parasitic effects such as substrate biasing and improve the stability of the circuit.

[0211] Reference Figure 4BThe connection electrodes 319a and 319b are electrically connected to the contact hole regions 411a and 411b in the second region (N-well region) 402 of the substrate 101 through vias 262a and 262b in the second insulating layer 202, respectively. These connection electrodes 319a and 319b are used to connect to the first voltage terminal VDD to bias the N-type substrate of the first data writing transistor P1. The connection electrode 319c is electrically connected to the contact hole region 400a in the substrate 101 through via 262c in the second insulating layer 202. This connection electrode 319c is used to connect to the second voltage terminal VSS to bias the P-type substrate where the second data writing transistor N1 is located.

[0212] Reference Figures 6A-6B The first conductive layer 301 also includes a bias voltage line 250, which extends along the first direction D1 and is electrically connected to the gate of the bias transistor N3 through a via 263 in the second insulating layer 202 to provide a second common voltage Vcom2.

[0213] Reference Figure 4B , Figures 6A-6B The first conductive layer 301 also includes a power line 260 extending along a first direction D1 for transmitting a second power supply voltage VSS. The power line 260 is electrically connected to the first electrode of the bias transistor N3 through a via 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is electrically connected to the contact hole region 400b in the substrate 101 through a via 264b in the second insulating layer 202 to bias the P-type substrate where the second data writing transistor N1 is located.

[0214] Figure 7A A schematic diagram of the second conductive layer 302 is shown. Figure 7B A second conductive layer 302 is shown based on the first conductive layer 301. Figure 7B The figure also shows vias in the third insulating layer 203, which are used to connect the patterns in the first conductive layer 301 and the patterns in the second conductive layer 302. For clarity, only four rows and six columns of sub-pixels are shown in the figure, and the boundary between two sub-pixel rows is shown with dashed lines; furthermore, Figure 7B The text also shows corresponding examples. Figure 3A The location of the mid-section line I-I'.

[0215] like Figure 7A As shown, the pattern of the second conductive layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2; the pattern of the second conductive layer in two adjacent sub-pixels in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1. The pattern of the second conductive layer will be illustrated below using a single sub-pixel as an example.

[0216] like Figure 7A As shown, the second conductive layer 302 includes power lines 270a, 270b, 280a, and 280b extending along the first direction D1. Power lines 270a and 270b are used to transmit a second power supply voltage VSS, and power lines 280a and 280b are used to transmit a first power supply voltage VDD. The power lines 270a, 280a, 270b, and 280b are arranged alternately along the second direction D2.

[0217] Reference Figure 3B , Figure 7A and Figure 7B The power line 270a is electrically connected to the power line 260 in the first conductive layer 301 through a plurality of vias 235 in the third insulating layer 203, thereby forming a parallel structure and effectively reducing the resistance on the trace; the plurality of vias 235 are arranged along the first direction D1. For example, the power line 270b is electrically connected to the third capacitor electrode 315 through a via 236 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of vias 236 are arranged along the second direction D2. For example, the power line 270b is also electrically connected to the third capacitor electrode 315 (315b) through a via 267 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of vias 267 are arranged along the second direction D2.

[0218] For example, in the second direction D2, the width of the power line 270b is greater than the width of the power line 270a. This is because the first and second parts of the third capacitor electrode 315, which is electrically connected to the power line 270b, both have a large area. Setting the power line 270b to have a larger width makes it easier to form multiple connection holes 236 and 267 between it and the third capacitor electrode 315, thereby effectively reducing the contact resistance.

[0219] Reference Figure 7A and Figure 7B The power line 280a is electrically connected to the connection electrode 318 in the first conductive layer 301 through a via 237 in the third insulating layer 203, thereby connecting to the first terminal of the driving transistor N2 to provide the first power supply voltage VDD. The power line 280b is electrically connected to the connection electrode 319a in the first conductive layer 301 through a via 238 in the third insulating layer 203, thereby providing a high voltage bias to the second region (N-well region) 402 in the substrate 101; for example, a plurality of vias 238 are arranged along the second direction D2.

[0220] For example, in the second direction D2, the width of the power line 280b is greater than the width of the power line 280a. This is because the connecting electrode 319a, which is electrically connected to the power line 280b, has a larger size in the second direction D2. Setting the power line 280b to have a larger width makes it easier to form multiple connecting holes 238 between it and the connecting electrode 319a, thereby increasing the contact area with the connecting electrode 319a and effectively reducing the contact resistance.

[0221] For example, the second conductive layer 302 further includes multiple first scan lines 210 and multiple second scan lines 220 extending along the first direction D1. For example, Figure 1A The scan line 11 shown can be either the first scan line 210 or the second scan line 220.

[0222] Reference Figure 6A and Figure 6B The first scan line 210 is electrically connected to the first scan line connection portion 311 through the via 231 in the third insulating layer 203, and the second scan line 220 is electrically connected to the second scan line connection portion 312 through the via 232 in the third insulating layer 203.

[0223] For a detailed description of the first and second scan lines, please refer to the following section. Figures 10A-10B The description.

[0224] For example, in conjunction with reference Figure 3B , Figure 7A and Figure 7B The second conductive layer 302 further includes a connection electrode 323, which is electrically connected to the connection electrode 314 in the first conductive layer 301 through a via 239 in the third insulating layer 203, thereby connecting to the second terminal 132 of the resistor 130. The connection electrode 323 is used for electrical connection to the first electrode 121 of the light-emitting element 120. For example, the number of vias 239 is at least two.

[0225] For example, in conjunction with reference Figure 7A and Figure 7B The second conductive layer 302 also includes a connection electrode 324, which is electrically connected to the connection electrode 319b in the first conductive layer 301 through a via 265 in the third insulating layer 203, so as to be electrically connected to the contact hole region 411b in the second region (N-well region) 402 in the substrate 101.

[0226] For example, in conjunction with reference Figure 7A and Figure 7BThe second conductive layer 302 further includes a connection electrode 325, which is electrically connected to the connection electrode 319c in the first conductive layer 301 through a via 266 in the third insulating layer 203, so as to be electrically connected to the contact hole region 400a in the substrate 101.

[0227] For example, the connecting electrode 325 has a cross-shaped structure. For example, the connecting electrode 324 and the connecting electrode 325 are alternately distributed in the first direction D1 and are located at the boundary of two sub-pixel rows.

[0228] For example, such as Figure 7A As shown, the second conductive layer 302 also includes a data line connection portion 244. (Referring to the reference...) Figure 7B The data line connection portion 244 is electrically connected to the data line connection portion 245 in the first conductive layer 301 through the via 233.

[0229] For example, such as Figure 7A As shown, multiple data line connectors 244 are arranged at intervals in the first direction D1, and a connection electrode 324 or a connection electrode 325 is provided between each two adjacent data line connectors 244.

[0230] For example, the data line connection 244 is located at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection 244.

[0231] For example, in conjunction with reference Figure 7A and Figure 7B In the second direction D2, the data line connection portion 244 located in each column of sub-pixels is alternately located on both sides of the data line connection portion 245, and is electrically connected to the first end and the second end of the data line connection portion 245 through vias 233 and 234 respectively, in order to connect the data line connection portion 245 to different data lines.

[0232] For a detailed description of the data cable connector, please refer to the following section. Figure 11A-11D The description of the first data line connector.

[0233] Figure 8A A schematic diagram of the third conductive layer 303 is shown. Figure 8B A third conductive layer 303 is shown based on the second conductive layer 302. Figure 8B The figure also shows vias in the fourth insulating layer 204, which are used to connect the patterns in the second conductive layer 302 and the patterns in the third conductive layer 303. For clarity, only the conductive patterns corresponding to four rows and six columns of sub-pixels are shown in the figure, and are marked with dashed lines. Figure 8A The diagram shows the boundary line between the two rows of sub-pixels; furthermore, in Figure 8B The text also shows corresponding examples. Figure 3A The location of the mid-section line I-I'.

[0234] For example, the third conductive layer 303 includes multiple data lines extending along the second direction D2, which are used to connect to the first end of the data writing sub-circuit in the sub-pixel to provide a data signal Vd. For example, as Figure 8A The multiple data lines shown include multiple first data lines 241 and multiple second data lines 242, which are arranged alternately in the first direction D1. For example, Figure 1A The data line 12 shown can be either the first data line 241 or the second data line 242.

[0235] For example, the data line is divided into multiple data line groups, each including a first data line 241 and a second data line 242. For instance, each sub-pixel column is connected to a corresponding data line group, that is, connected to one first data line 241 and one second data line 242; that is, one column of sub-pixels is driven by two data lines. This helps reduce the load on each data line, thereby improving the driving capability of the data line, reducing signal latency, and improving display quality.

[0236] refer to Figure 8B The first data line 241 passes through the via 403 in the fourth insulating layer 204 and... Figure 7B The data line connection portion 244 located between the first row sub-pixels and the second row sub-pixels in the second conductive layer 302 shown is electrically connected to the first and second row sub-pixels, thereby providing data signals to the first and second row sub-pixels; the second data line 242 is connected to the fourth insulating layer 204 through the via 404 in the fourth insulating layer 204. Figure 7B The data line connection portion 244 located between the third row sub-pixels and the fourth row sub-pixels in the second conductive layer 302 shown is electrically connected, thereby providing data signals to the third and fourth row sub-pixels.

[0237] For a detailed description of the first and second data lines, please refer to the following section. Figure 11A-11D The description is in [the text]. For easy comparison, in [the text]... Figure 8B It shows Figure 11B The positions corresponding to section lines II-II' and III-III' in the diagram.

[0238] For example, the third conductive layer 303 includes power lines 330 and 340 extending along the second direction D2. Power line 330 is used to transmit a first power supply voltage VDD, and power line 340 is used to transmit a second power supply voltage VSS. Figure 8A As shown, power lines 330 and 340 are arranged alternately in the first direction D1.

[0239] refer to Figure 8BPower lines 330 are electrically connected to power lines 280a and 280b in the second conductive layer 302 via vias 405 and 406 in the fourth insulating layer 204, thereby forming a mesh-like power line structure for transmitting the first power supply voltage. This structure helps reduce the resistance on the power lines, thereby reducing the voltage drop on the power lines, and helps to uniformly deliver the first power supply voltage VDD to each sub-pixel of the display substrate. The power lines 330 are also connected to the connection electrode 324 (see reference 324) in the second conductive layer 302 via via 407 in the fourth insulating layer. Figure 7A Electrically connected to the contact hole region 411b in the second region (N-well region) 402 of the substrate 101, thereby biasing the N-type substrate where the first data writing transistor P1 and resistor 130 are located.

[0240] refer to Figure 8B The power lines 340 are electrically connected to the power lines 270a and 270b in the second conductive layer 302 via vias 408 and 409 in the fourth insulating layer 204, thereby forming a mesh-like power line structure for transmitting the second power supply voltage. This structure helps reduce the resistance on the power lines, thereby reducing the voltage rise on the power lines, and helps to uniformly deliver the second power supply voltage VSS to each sub-pixel of the display substrate. The power lines 340 are also connected to the connection electrodes 325 in the second conductive layer 302 via vias 412 in the fourth insulating layer (see figure). Figure 3B and Figure 6A Electrically connected to the contact hole region 400a in the substrate 101 to bias the P-type substrate where transistors N1-N3 are located.

[0241] like Figure 8A As shown, the third conductive layer 303 also includes a connection electrode 333, which is located between the first data line 241 and the second data line 242 in a data line group. Figure 7B As shown, the connection electrode 333 is electrically connected to the power line 270b in the second conductive layer through a via 413 in the fourth insulating layer. For example, there are at least two vias 413, so that the connection electrode 333 can make sufficient contact with the power line 270b to reduce contact resistance. By providing the connection electrode 333 in parallel with the power line 270b, the resistance on the power line 270b can be reduced, thereby reducing the voltage rise on the power line and helping to uniformly deliver the second power supply voltage VSS to each sub-pixel of the display substrate.

[0242] Combination Figure 3B , Figure 8A and Figure 8BAs shown, the third conductive layer 303 also includes a connection electrode 334, which is electrically connected to the connection electrode 323 in the second conductive layer 302 through a via 414 in the fourth insulating layer, thereby connecting to the second terminal 132 of the resistor 130. The connection electrode 334 is used for electrical connection to the first electrode 121 of the light-emitting element 120. For example, the number of vias 414 is at least two.

[0243] Combination Figure 8A and Figure 8B As shown, the third conductive layer 303 further includes a shielding electrode 341. For example, the shielding electrode 341 extends along the second direction D2 and is located between a first data line 241 and a second data line 242 in a data line group. For example, the first data line 241 and the second data line 242 are symmetrically arranged on both sides of the second data line shielding electrode 341. The shielding electrode 341 is disposed between the two data lines to provide shielding and prevent crosstalk between the signals in the two data lines. For example, the shielding electrode 341 is configured to receive a constant voltage to improve shielding capability. In this embodiment, the shielding electrode 341 is used to receive a second power supply voltage VSS.

[0244] For example, the display substrate includes a plurality of shielding electrodes 341, which are arranged one-to-one with a plurality of data line groups. Each shielding electrode is located between the first data line and the second data line of the corresponding data line group.

[0245] like Figure 8A As shown, connecting electrode 333, connecting electrode 334, and shielding electrode 341 are arranged in the second direction D2 and located between the first data line 241 and the second data line 242. The connecting electrode 333, connecting electrode 334, and shielding electrode 341 form a shielding wall, which plays a shielding role throughout the entire extension range of the first data line 241 and the second data line 242, preventing the signals in the two data lines from interfering with each other.

[0246] For example, such as Figure 8A As shown, the connecting electrode 333 and the shielding electrode 341 are located on both sides of the connecting electrode 334 and are spaced apart from the connecting electrode 334. The end of the connecting electrode 333 near the connecting electrode 334 has a protrusion 333a, which is L-shaped. Its first branch extends along the first direction D1 and connects to the main body of the connecting electrode 333. The second branch extends along the second direction D2 and is close to the connecting electrode 334. The second branch overlaps with the gap between the connecting electrode 333 and the connecting electrode 334 in the first direction D1, thereby improving the shielding effect and further avoiding signal crosstalk between the two data lines.

[0247] Similarly, the shielding electrode 341 has an L-shaped protrusion 341a at one end near the connecting electrode 334, which is used to further block the gap between the shielding electrode 341 and the connecting electrode 334 and improve the shielding effect.

[0248] In this way, the shielding wall achieves complete blockage in the second direction D2, and the first data line 241 and the second data line 242 do not have a direct face-to-face area in the first direction D1, which plays a good role in signal shielding, making the displayed data more stable and improving the display effect.

[0249] Figure 9A A schematic diagram of the fourth conductive layer 304 is shown. Figure 9B A fourth conductive layer 304 is shown based on the third conductive layer 303. Figure 9B The diagram also shows vias in the fifth insulating layer 205, which connect the patterns in the third conductive layer 303 and the patterns in the fourth conductive layer 304. For clarity, only four rows and six columns of sub-pixels are shown, with dashed lines indicating the boundaries between the two rows of sub-pixels; furthermore... Figure 9B The text also shows corresponding examples. Figure 3A The location of the mid-section line I-I'.

[0250] For example, the fourth conductive layer 304 includes power lines 350 and 360 extending along the second direction D2. Power line 350 is used to transmit a first power supply voltage VDD, and power line 360 ​​is used to transmit a second power supply voltage VSS. Figure 9A As shown, power lines 350 and 360 are arranged alternately in the first direction D1.

[0251] For example, multiple power lines 350 are arranged in a one-to-one correspondence with multiple power lines 330, and multiple power lines 360 are arranged in a one-to-one correspondence with multiple power lines 340; in the direction perpendicular to the substrate 101, each power line 350 overlaps with and is electrically connected (e.g., in parallel) to its corresponding power line 330, and each power line 360 ​​overlaps with and is electrically connected (e.g., in parallel) to its corresponding power line 340. This reduces the resistance on the power lines and improves display uniformity.

[0252] refer to Figure 9B Power line 350 is electrically connected to the corresponding power line 330 through via 251 in the fifth insulating layer 205, and power line 360 ​​is electrically connected to the corresponding power line 340 through via 252 in the fifth insulating layer. For example, there are at least two vias 251 and 252.

[0253] Combination Figure 9A and Figure 9BThe fourth conductive layer 304 also includes a connection electrode 342, which is electrically connected to a connection electrode 333 in the third conductive layer 303 through a via 253 in the fifth insulating layer. For example, there are at least two vias 253, so that the connection electrode 342 can make sufficient contact with the connection electrode 333 to reduce contact resistance. By providing the connection electrode 342, it helps to further reduce the resistance on the power line 270b, thereby reducing the voltage rise on the power line and helping to uniformly deliver the second power supply voltage VSS to each sub-pixel of the display substrate.

[0254] Combination Figure 3B , Figure 9A and Figure 9B The fourth conductive layer 304 further includes a connection electrode 343, which is electrically connected to a connection electrode 334 in the third conductive layer 303 through a via 254 in the fifth insulating layer, thereby connecting to the second terminal 132 of the resistor 130. The connection electrode 343 is used for electrical connection to the first electrode 121 of the light-emitting element 120. For example, the number of vias 254 is at least two.

[0255] Combination Figure 9A and Figure 9B The fourth conductive layer 304 also includes a connecting electrode 344, which is electrically connected to the shielding electrode 341 in the third conductive layer 303 through a via 255 in the fifth insulating layer. Figure 9A As shown, the fourth conductive layer 304 also includes a connection portion 345, which connects the connection electrode 344 to the power line 360 ​​directly adjacent to the connection electrode 344.

[0256] For example, such as Figure 9A As shown, the connecting electrodes 344 located on both sides of the power line 360 ​​are symmetrically arranged about the power line 360. The power line 360, the connecting electrodes 344 located on both sides of it, and the corresponding connecting portions 345 of the connecting electrodes are connected to each other as a single unit. In this way, the power line 360 ​​can provide a second power supply voltage VSS to the shielding electrode 341 to improve the shielding capability of the shielding electrode.

[0257] For example, each via can be made conductive by filling it with an additional conductive material (such as tungsten).

[0258] Figure 9B The image also shows a contact hole area 256 of the connecting electrode 343, which is used for electrical connection with the first electrode 121 of the light-emitting element 120.

[0259] It should be noted that, along the cross-sectional line I-I', the portion of the connecting electrode 343 located in the contact hole area 256 is not continuous with the portion of the connecting electrode 343 corresponding to the via 254 (e.g., Figure 9B(as shown in area F), but for ease of explanation, here... Figure 3B The cross-sectional view shown depicts the contact hole area 256 and the via 254 on a continuous connecting electrode 343, consistent with the actual situation. For example, as Figure 3B As shown, the display substrate 10 also includes a sixth insulating layer 206, in which a via 257 is formed corresponding to the contact hole area 256 of the electrode 343. The via 257 is filled with a conductive material (such as tungsten) and then a smooth surface is formed by a polishing process (such as chemical mechanical polishing) for forming the light-emitting element 120.

[0260] For example, the number of vias 257 is at least two.

[0261] For example, such as Figure 3B As shown, the number of contact hole areas for electrical connection on the connecting electrodes 314, 323, 334, and 343 connected to the first electrode 121 of the light-emitting element 120 is at least two, which reduces the contact resistance between the connecting electrodes and thus reduces the connection resistance between the resistor 130 and the first electrode 121 of the light-emitting element 120. This reduces the voltage drop on the transmission path of the data signal from the resistor 130 to the first electrode 121, alleviates the problems of color deviation and uneven display caused by the anode potential loss (grayscale loss) due to the voltage drop, and improves the display effect.

[0262] For example, such as Figure 3B As shown, in the direction perpendicular to the substrate 101, the vias 257, 254, and 414 corresponding to the first electrode 121 of the light-emitting element 120 do not overlap with each other. In the direction perpendicular to the substrate, the stacking of vias can easily lead to poor connection, broken lines, or unevenness at the via locations. This arrangement improves the electrical connection quality of the first electrode 121 of the light-emitting element 120 and enhances the display effect.

[0263] like Figure 3B As shown, the light-emitting element 120 includes a first electrode 121, a light-emitting layer 123, and a second electrode 122 sequentially disposed on the sixth insulating layer 206. For example, the first electrode 121 and the second electrode 122 are respectively the anode and cathode of the OLED. For example, multiple first electrodes 121 are disposed at intervals in the same layer, corresponding one-to-one with multiple sub-pixels. For example, the second electrode 122 is a common electrode, arranged across the entire surface of the display substrate 10.

[0264] For example, such as Figure 3B As shown, the display substrate also includes a first encapsulation layer 124, a color filter layer 125, and a cover plate 126 located on the side of the light-emitting element 120 away from the substrate 101.

[0265] For example, the first encapsulation layer 124 is configured to seal the light-emitting element to prevent external moisture and oxygen from penetrating into the light-emitting element and pixel circuitry, thereby damaging the device. For example, the encapsulation layer 124 includes an organic thin film or a structure comprising alternating layers of organic and inorganic thin films. For example, a water-absorbing layer may also be provided between the encapsulation layer 124 and the light-emitting element, configured to absorb residual moisture or sol from the early manufacturing processes of the light-emitting element. The cover plate 126 is, for example, a glass cover plate.

[0266] For example, such as Figure 3B As shown, the display substrate may also include a second encapsulation layer 127 located between the color filter layer 125 and the cover plate 126, which can protect the color filter layer 125.

[0267] For example, the light-emitting element 120 is configured to emit white light, and combined with the color filter layer 124, it achieves full-color display.

[0268] In other examples, the light-emitting element 120 is configured to emit light in the three primary colors, in which case the color filter layer 124 is not necessary. This disclosure does not limit the manner in which the display substrate 10 achieves full-color display.

[0269] Table A below exemplarily shows the thickness range and example values ​​of the first to sixth insulating layers; Table B exemplarily shows the thickness range and example values ​​of the first to fourth conductive layers; Table C exemplarily shows the dimensions and example values ​​of vias VIA2 in the second insulating layer, VIA3 in the third insulating layer, VIA4 in the fourth insulating layer, VIA5 in the fifth insulating layer, and VIA6 in the sixth insulating layer; Table D exemplarily shows example values ​​of the channel width, length, and aspect ratio of each transistor (N1-N4, P1); however, this is not intended to limit the present disclosure.

[0270]

[0271] Table A

[0272]

[0273] Table B

[0274]

[0275]

[0276] Table C

[0277] transistor W(um) / L(um) P1 0.6 / 0.6 N1 0.6 / 0.6 N2 1.5 / 0.6 N3 1.02 / 0.76

[0278] Table D

[0279] For example, as shown in Table A, among the first to sixth insulating layers, the first insulating layer 201 has the smallest thickness, and the second insulating layer 202 has the largest thickness. This is because the first insulating layer 201 includes the gate insulating layer of each transistor and also includes the dielectric layer 104 of the storage capacitor Cst. Setting the thickness of the first insulating layer 201 to be smaller helps to improve the gate control capability of the transistors and helps to obtain a larger storage capacitance. In addition, the second insulating layer 202 acts as a field oxide layer, and setting it to be thicker helps to provide electrical isolation between the transistors. For example, the thicknesses of the third insulating layer 203, the fourth insulating layer 204, the fifth insulating layer 205, and the sixth insulating layer 206 are the same or similar; for example, the thickness of the second insulating layer 202 is 1.5 to 2 times the thickness of the third insulating layer 203 / fourth insulating layer 204 / fifth insulating layer 205 / sixth insulating layer 206.

[0280] For example, the planar shape of a via can be rectangular (e.g., square) or circular, and the dimensions in Table C represent the average side length of the rectangle or the aperture. For example, as shown in Table C, multiple vias in each insulating layer have the same size. For example, among the second to sixth insulating layers, the via size in the sixth insulating layer 206 is the largest. This is because the sixth insulating layer 206 is closest to the light-emitting element. During the driving process of the light-emitting element, current flows upward from the bottom transistor to the light-emitting element; therefore, the via size in the sixth insulating layer 206 is the largest to transmit a larger converged current.

[0281] For example, the spacing between the first data write transistor P1 and the second data write transistor N1 ranges from 0.4 to 0.45 micrometers, such as 0.42 micrometers, which helps to increase pixel density. Figure 4B As shown, the spacing D0 is the distance between the closest edges of the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1.

[0282] For example, such as Figure 4B As shown, resistor 130 has an equivalent length of 4.4 micrometers and an average width of 0.42 micrometers.

[0283] For example, such as Figure 4B As shown, the effective capacitance area of ​​the storage capacitor Cst is 20 square micrometers, meaning the effective area of ​​the polysilicon layer 102 used to form the storage capacitor Cst is 20 square micrometers. For example, the area ratio of the storage capacitor Cst in each sub-pixel is 20%-35%, such as 27%. The display substrate provided in this embodiment can effectively increase the area ratio of the storage capacitor through reasonable layout, thereby increasing the capacitance value.

[0284] For example, the thickness of the polycrystalline silicon layer 102 is 200 nanometers.

[0285] At least one embodiment of this disclosure also provides a pixel structure, which includes a substrate, a pixel row on the substrate, a first scan line, and a second scan line. The pixel row includes a plurality of sub-pixels located on the substrate and arranged along a first direction; the first scan line and the second scan line extend along the first direction, and each sub-pixel includes a pixel circuit, which includes a data writing sub-circuit, a storage sub-circuit, and a driving sub-circuit. The data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal, and a second electrode. The first and second control electrodes of the data writing sub-circuit are respectively configured to receive a first control signal and a second control signal. The first terminal of the data writing sub-circuit is configured to receive a data signal. The second terminal of the data writing sub-circuit is electrically connected to the first terminal of the storage sub-circuit and configured to transmit the data signal to the first terminal of the storage sub-circuit in response to the first and second control signals. The driving sub-circuit includes a control terminal, a first terminal, and a second terminal. The control terminal of the driving sub-circuit is electrically connected to the first terminal of the storage sub-circuit. The first terminal of the driving sub-circuit is configured to receive a first power supply voltage. The second terminal of the driving sub-circuit is used to connect to a light-emitting element. The driving sub-circuit is configured to drive the light-emitting element to emit light in response to the voltage of the first terminal of the storage sub-circuit. The first scan line is electrically connected to the first control electrode of the data writing circuit of the plurality of sub-pixels to provide the first control signal. The second scan line is electrically connected to the second control electrode of the data writing circuit of the plurality of sub-pixels to provide the second control signal. The resistance of the first scan line and the second scan line are the same, and their orthogonal projection areas on the substrate are the same.

[0286] In some examples, for instance, the first scan line and the second scan line refer to the portion of the trace that transmits the corresponding control signals from the scan drive circuit to each sub-pixel located in the display area. Therefore, when comparing resistance and area, the portion of the trace located outside the display area is not considered.

[0287] In other examples, for instance, the first and second scan lines may also represent all portions of the trace that transmits the corresponding control signals from the scan drive circuit to each sub-pixel, including the portions of the trace located in the display area and the non-display area, for example... Figure 1A The S section is shown in the diagram. For example, the first control signal SEL and the second control signal SEL_B can be output by the same gate drive circuit unit (such as the GOA unit).

[0288] This configuration ensures that the RC loads on the first and second scan lines are identical. (Reference) Figure 1ADuring the transmission of control signals from the scan drive circuit 14 to each sub-pixel, the portion of the scan line 11 (e.g., the first scan line and the second scan line) located outside the display area (shown by the dashed box) accounts for a relatively small proportion. Therefore, setting the resistive and capacitive loads of the portion of the scan line 11 located in the display area to be the same can improve the synchronization of the first control signal SEL and the second control signal SEL_B; in conjunction with reference to the reference... Figure 2C For example, when transitioning from data writing 1 to the light emission stage 2, this setup allows the rising edge of the first control signal SEL and the falling edge of the second control signal SEL_B to occur at the same time. Therefore, the anti-interference performance of the pixel circuit is improved.

[0289] This disclosure also provides a display substrate including a plurality of pixel structures, wherein a plurality of pixel rows in the plurality of pixel structures are arranged in a second direction, the first direction intersecting the second direction, thereby the plurality of sub-pixels of the plurality of pixel rows are arranged into a plurality of pixel columns.

[0290] It should be noted that the pixel structure provided in this disclosure can be applied to the display substrate 10 provided in any of the foregoing embodiments. However, the pixel structure provided in this disclosure is not limited to silicon-based display substrates, and can also be applied to glass substrates or flexible substrates. In this case, the light-emitting element can be, for example, a bottom-emitting or double-sided-emitting structure.

[0291] Figure 10A A schematic diagram of a display substrate provided in at least one embodiment of this disclosure is shown. For clarity, the figure shows two rows and six columns of sub-pixels, that is, only two of the above-described pixel structures. Compared to Figure 3A The display substrate omits the third and fourth conductive layers. (The following is in conjunction with...) Figure 10A The arrangement of the first scan line and the second scan line in the display substrate and pixel structure provided in the embodiments of this disclosure is illustrated by way of example; however, the embodiments of this disclosure are not limited thereto.

[0292] For example, such as Figure 10A As shown, each sub-pixel row is connected to a first scan line 210 and a second scan line 220 respectively; however, this is not intended to limit the scope of this disclosure.

[0293] For example, the display substrate 10 also includes a plurality of first scan line connection portions 311 electrically connected to the first scan line 210 and a plurality of second scan line connection portions 312 electrically connected to the second scan line 220. The first scan line 210 is electrically connected to the first control electrode (i.e., the gate of the first data writing transistor) of the data writing circuit of a row of sub-pixels through the plurality of first scan line connection portions 311, and the second scan line 220 is electrically connected to the second control electrode (i.e., the gate of the second data writing transistor) of the data writing circuit of the row of sub-pixels through the plurality of second scan line connection portions 312.

[0294] For example, the first scan line 210 and the second scan line 220 are insulated in the same layer and made of the same material.

[0295] For example, the plurality of first scan line connection portions 311 and the plurality of second scan line connection portions 312 are arranged at intervals in the same layer and are made of the same material, and are located in different conductive layers from the first scan line 210 and the second scan line 220.

[0296] Figure 10B It shows Figure 10A An enlarged schematic diagram of region E within the dashed box. For clarity, only the gates of the first data writing transistor P1 and the second data writing transistor N1, the first scan line 210, the second scan line 220, and the first scan line connection portion 311 and the second scan line connection portion 312 are shown in the diagram. For easy comparison, in... Figure 7B The location of area E is also shown in the image. Figure 10C It shows Figure 10B A sectional view along section line V-V'.

[0297] For example, the length and line width of the first scan line 210 and the second scan line 220 are the same.

[0298] For example, the first scan line connection portion 311 and the second scan line connection portion 312 are alternately arranged in the first direction D1, and their extension directions are different from the first direction D1; the first scan line connection portion 311 intersects with the orthographic projections of the first scan line 210 and the second scan line 220 on the substrate, and the second scan line connection portion 312 intersects with the orthographic projections of the first scan line 210 and the second scan line 220 on the substrate. For example, both the first scan line connection portion 311 and the second scan line connection portion 312 are linear structures that extend along the second direction D2.

[0299] For example, the total area of ​​the orthographic projection of the plurality of first scan line connection portions 311 onto the substrate is the same as the total area of ​​the orthographic projection of the plurality of second scan line connection portions 312 onto the substrate. Therefore, the parasitic capacitance on the plurality of first scan line connection portions 311 is the same as that on the plurality of second scan line connection portions 312.

[0300] This configuration ensures that the parasitic capacitance of the traces (including the corresponding scan lines and connections) when the first control signal and the second control signal are transmitted from the first scan line and the second scan line to the data writing sub-circuit is the same, further improving the synchronization between the first control signal and the second control signal.

[0301] For example, the first data writing transistor P1 and the second data writing circuit N1, which are electrically connected to the first scan line and the second scan line respectively, are of the same size. Therefore, the load generated for each connected scan line is also the same, which further improves the synchronization between the first control signal and the second control signal, thereby improving the anti-interference performance of the circuit.

[0302] For example, each of the plurality of first scan line connection portions 311 has the same length along the second direction D2, and each of the plurality of first scan line connection portions 311 has the same line width. Each of the plurality of second scan line connection portions 312 has the same length along the second direction D2, and each of the plurality of second scan line connection portions 312 has the same line width.

[0303] For example, the first scan line 210 is electrically connected to the first scan line connection portion 311 through via 231, and the second scan line 220 is connected to the second scan line connection portion 312 through via 232. Both via 231 and via 232 are located in the third insulating layer 203.

[0304] For example, such as Figure 10B As shown, the first control electrode group 191, which is composed of the first control electrodes of two adjacent sub-pixels in the first direction D1, and the second control electrode group 192, which is composed of two adjacent sub-pixels, are arranged alternately in the first direction D1.

[0305] For example, such as Figure 10B As shown, the first scan line connection portion 311 is electrically connected to the first control electrode group 191 or the first control electrode through via 221, and the second scan line connection portion 312 is electrically connected to the second control electrode group 192 or the second control electrode through via 222. For example, multiple first scan line connection portions 311 are electrically connected to multiple first control electrode groups 191 in a one-to-one correspondence, and multiple second scan line connection portions 312 are electrically connected to multiple second control electrode groups 192 in a one-to-one correspondence.

[0306] For example, the first scan line 210313 and the second scan line 220 are located on the same side of the plurality of first control electrode groups 191 and the plurality of second control electrode groups 192, and the first scan line 210 is closer to the plurality of first control electrode groups 191 and the plurality of second control electrode groups 192.

[0307] For example, such as Figure 10BAs shown, in a direction perpendicular to the substrate, the first scan line 210 intersects both the first scan line connection portion 311 and the second scan line connection portion 312, and the second scan line 220 intersects both the first scan line connection portion 311 and the second scan line connection portion 312. The via 231 is located at the intersection of the first scan line 210 and the first scan line connection portion 311, and the via 232 is located at the intersection of the second scan line 220 and the second scan line connection portion 312.

[0308] For example, such as Figure 10B As shown, vias 231 and 232 are arranged alternately in the first direction D1 and staggered in the second direction. The via 231 is closer to the plurality of first control electrode groups 191 and second control electrode groups 192 than the via 232.

[0309] like Figure 10B As shown, one end of the second scan line connection portion 312 is electrically connected to the second scan line 220 through via 232, and the other end is electrically connected to the second control electrode or second control electrode group to be connected through via 222. The first scan line 210 passes between via 232 and via 222.

[0310] For example, such as Figure 10B As shown, the first scan line connection portion 311 includes a main body portion 321 and an extension portion 322. The extension portion 322 is the portion of the main body portion 321 that extends away from the first scan line 20 along a second direction D2. The main body portion 321 is used to electrically connect the first scan line connection portion 311 and the first control electrode or the first control electrode group, and is located between the first scan line 210 and the connected first control electrode or the first control electrode group in the second direction D2. The extension portion 322 is located on the side of the first scan line 210 away from the connected first control electrode or the first control electrode group in the second direction D2.

[0311] Here, the extension 322 is a virtual structure and does not actually serve as an electrical connection. The extension 322 is provided so that the first scan line connection 311 and the second scan line connection 312 have the same length, the same area, and form the same capacitive load.

[0312] For example, such as Figure 10B As shown, via 221 is located in the middle of the first control electrode group 191, and via 222 is located in the middle of the second control electrode group 192. The two first control electrodes in the first control electrode group 191 are symmetrical about the first scan line connection portion 311 and its extension axis to which the first control electrode group is connected; the two second control electrodes in the second control electrode group 192 are symmetrical about the second scan line connection portion 312 and its extension axis to which the second control electrode group is connected.

[0313] refer to Figure 10A The first scan line 210 connecting two adjacent pixel rows is symmetrical about the axis of symmetry along the first direction D1, and the second scan line 220 corresponding to two adjacent pixel rows is symmetrical about the axis of symmetry along the first direction D1.

[0314] The display substrate 10 includes multiple data lines extending along a second direction D2, which are used to connect to the first end of the data writing sub-circuit in the sub-pixel to provide a data signal Vd.

[0315] Figure 11A The figures show schematic diagrams of display substrates provided in other embodiments of the present disclosure, including schematic diagrams of data lines of display substrates provided in at least one embodiment of the present disclosure; however, the embodiments of the present disclosure are not limited thereto.

[0316] Reference Figure 8A The data line is divided into multiple data line groups, each data line group including a first data line 241 and a second data line 242. The multiple data line groups are electrically connected to multiple pixel columns one-to-one to provide the data signal Vd. Each sub-pixel column is electrically connected to a first data line 241 and a second data line 242 respectively; that is, a column of sub-pixels is driven by two data lines.

[0317] For example, such as Figure 11A As shown, each sub-pixel column is connected to two data lines, namely the first data line 241 and the second data line 242. For each column of sub-pixels, two sub-pixels located in the adjacent nth and (n+1)th pixel rows form a pixel group 240, sharing a data line; where n is an odd or even number greater than 0. For each column of sub-pixels, in the second direction D2, the Nth pixel group 240 is connected to the first data line 241, and the (N+1)th pixel group 240 is connected to the second data line 242, where N is a natural number; that is, in the second direction D2, pixel groups 240 are alternately connected to the first data line 241 and the second data line 242, with odd-numbered pixel groups sharing one data line and even-numbered pixel groups sharing another data line.

[0318] By setting two data lines to drive a sub-pixel column, the load on each data line can be reduced, thereby improving the driving capability of the data lines, reducing signal latency, and improving display quality.

[0319] Since the display substrate provided in this embodiment has structural symmetry, the layout of the signal lines can be coordinated with the driving method of the data lines to achieve the effect of optimized design.

[0320] For example, in conjunction with reference Figure 4AIn a pixel group 240, the first electrodes of two first data write transistors P1 are connected to each other in a single structure (see area A1), and the first electrodes of two second data write transistors N1 are connected to each other in a single structure (see area A2). Therefore, in conjunction with the aforementioned data line driving method, a connection via can be provided to the first electrode of this single structure within a limited contact area to connect to the data line. This allows for electrical connection between the data line and either the two first data write transistors P1 or the two second data write transistors N2 in the pixel group 240, without needing to provide separate connection vias for each transistor. This not only saves on manufacturing processes but also allows for a more compact layout design within design constraints, thereby improving the resolution of the display substrate.

[0321] Figure 11B The connection structure of data lines in two adjacent pixel groups 240 is shown. For clarity, only partial views of the first and second data lines connecting to the sub-pixels in each pixel group are shown selectively, and the partial views of the two pixel groups are stitched together to show the continuity of the signal lines; the dashed lines show the boundary between the two pixel groups.

[0322] like Figure 11B As shown, on a substrate perpendicular to the substrate, the first data line 241 overlaps with the first data writing transistor P1 and is electrically connected to the first pole of two adjacent first data writing transistors P1 in a pixel row 240; the second data line 242 overlaps with the second data writing transistor N1 and is electrically connected to the first pole of two adjacent second data writing transistors N1 in a pixel group 240.

[0323] For example, such as Figure 11B As shown, in the direction perpendicular to the substrate, the first data line 241 overlaps with the gate 160 of the first data writing transistor P1, and the second data line 242 overlaps with the gate 170 of the second data writing transistor N1; that is, both the first data line 241 and the second data line 242 pass through the pixel area without occupying additional pixel space, thus improving space utilization.

[0324] Figure 11C and Figure 11D They are shown respectively Figure 11B The cross-sectional views are taken along sections II-II' and III-III', for example, along the first direction D1. For clarity, only structures electrically connected to the data lines are shown in the figures, while other structures are omitted. Figure 11C and 11DAs shown, the first data line 241 and the second data line 242 are located in the third conductive layer 303 and are electrically connected to the corresponding first data line connection portion 244 in the second conductive layer 302 through vias 403 and 404 in the fourth insulating layer 204, respectively. In the direction perpendicular to the substrate, the first data line connection portion 244 overlaps with the corresponding first data line 241 or second data line 242, respectively. The first data line connection portion 244 is electrically connected to the second data line connection portion 245 in the first conductive layer 301 through vias 233 and 234 in the third insulating layer 203. The second data line connection portion 245 is then electrically connected to the first terminal 161 of the first data writing transistor P1 and the first terminal 171 of the second data writing transistor N1 through vias 223 and 224 in the second insulating layer 202, respectively, thereby transmitting data signals to the transistors.

[0325] Because the first electrodes of two adjacent first data write transistors P1 and two second data write transistors N1 in a pixel row are connected as a single unit, and the second data line connection portion 245 electrically connects the first electrodes of the first data write transistors P1 and the first electrodes of the second data write transistors N1 in a sub-pixel, the second data line connection portion 245 electrically connects the first electrodes 161 of the two first data write transistors P1 and the first electrodes 171 of the two second data write transistors N1 of two adjacent sub-pixels in the second direction D2 in a sub-pixel group to each other, and connects to the corresponding first data line 241 or second data line 242 through the corresponding first data line connection portion 244. Therefore, it can be seen that only one via is needed in the third and fourth insulating layers respectively to achieve electrical connection with the data lines, greatly saving layout space and improving space utilization.

[0326] like Figure 11B-11D As shown, for example, the first data line 241 and the second data line 242 are symmetrically arranged on both sides of the second data line connector 245.

[0327] For example, such as Figure 11C and 11D As shown, the third conductive layer also includes a shielding electrode 341, which is located between the first data line 241 and the second data line 242. For example, the first data line 241 and the second data line 242 are symmetrically arranged on both sides of the second data line shielding electrode 341. The shielding electrode 341 is disposed between the two data lines to provide shielding and prevent crosstalk between the signals in the two data lines. For example, the shielding electrode 341 is configured to receive a constant voltage to improve shielding capability; for example, the shielding electrode 341 is configured to receive a second power supply voltage.

[0328] For example, such as Figure 4AAs shown, the first pole 161 of the first data writing transistor P1 of two adjacent sub-pixels 100 in the second direction D2 is connected to each other as a whole, and the first pole 171 of the second data writing transistor N1 of two adjacent sub-pixels 100 in the second direction D2 is connected to each other as a whole.

[0329] For example, the materials of the first to fourth conductive layers are metallic materials, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys composed of the above metals. Alternatively, the materials of the first to fourth conductive layers can also be conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0330] For example, the materials of the first to sixth insulating layers are inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide, or insulating materials including metal oxides such as aluminum oxide and titanium nitride.

[0331] For example, the light-emitting element 120 is a top-emitting structure, with the first electrode 121 being reflective and the second electrode 122 being transmissive or semi-transmissive. For example, the first electrode 121 is made of a high work function material to act as the anode, such as an ITO / Ag / ITO stacked structure; the second electrode 122 is made of a low work function material to act as the cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0332] At least one embodiment of this disclosure also provides a display panel, including any of the above-described display substrates 10. It should be noted that the display substrate 10 provided in at least one embodiment of this disclosure may or may not include a light-emitting element 120; that is, the light-emitting element 120 may be formed in a panel factory after the display substrate 10 is completed. In the case where the display substrate 10 itself does not include a light-emitting element 120, the display panel provided in this disclosure, in addition to including the display substrate 10, further includes a light-emitting element 120.

[0333] At least one embodiment of this disclosure also provides a display device 40, such as Figure 12 As shown, the display device 40 includes any of the above-mentioned display substrate 10 or display panel. In this embodiment, the display device can be any product or component with display function, such as a monitor, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator.

[0334] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising a substrate and a plurality of sub-pixels on the substrate, wherein, The plurality of sub-pixels are distributed in an array along a first direction and a second direction, the first direction intersecting the second direction; each sub-pixel includes a pixel circuit, the pixel circuit including a data writing sub-circuit, a storage sub-circuit, a driving sub-circuit, and a resistor. The data writing sub-circuit is electrically connected to the first terminal of the storage sub-circuit and is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal. The driving sub-circuit includes a control electrode, a first electrode, and a second electrode. The control electrode of the driving sub-circuit is electrically connected to the first terminal of the storage sub-circuit. The first electrode of the driving sub-circuit is configured to receive a first power supply voltage. The second electrode of the driving sub-circuit is electrically connected to the first terminal of the resistor. The second end of the resistor is used to be electrically connected to the first electrode of the light-emitting element, and the driving sub-circuit is configured to drive the light-emitting element to emit light in response to the voltage at the first end of the storage sub-circuit. The resistor is insulated from the control electrode of the driving sub-circuit in the same layer, and the resistivity of the resistor is higher than that of the control electrode of the driving sub-circuit. The storage sub-circuit includes a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode and the second capacitor electrode serve as the first terminal and the second terminal of the storage sub-circuit, respectively. The data writing sub-circuit includes a first data writing transistor, and the driving sub-circuit includes a driving transistor. The first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor, and the driving transistor is an N-type metal-oxide-semiconductor field-effect transistor. The substrate is a silicon substrate, which includes a P-type doped region as the channel region of the driving transistor and an N-type doped region as the channel region of the first data writing transistor. In the second direction, the P-type first data write transistor and the N-type drive transistor are located on opposite sides of the storage capacitor.

2. The display substrate as claimed in claim 1, wherein, The resistor and the control electrode of the driving sub-circuit are both made of polycrystalline silicon.

3. The display substrate as described in claim 1, wherein, The control signal includes a first control signal. The gate of the first data writing transistor is configured to receive the first control signal, the first electrode of the first data writing transistor is configured to receive the data signal, and the second electrode of the first data writing transistor is electrically connected to the first terminal of the storage sub-circuit and the control electrode of the driving sub-circuit. The gate, first electrode, and second electrode of the driving transistor serve as the control electrode, first electrode, and second electrode of the driving sub-circuit, respectively.

4. The display substrate as described in claim 3, wherein, A PN junction is formed between the second electrode of the driving sub-circuit and the substrate, and the resistance value of the resistor is configured such that the PN junction is turned off when the driving transistor is operating in the saturation region.

5. The display substrate as claimed in claim 4, wherein, The resistance value of the resistor Wherein, Vs is the bias voltage of the substrate, Vcom1 is the common voltage provided to the second electrode of the light-emitting element, Von is the on-state voltage of the PN junction, and Is is the saturation current of the driving transistor.

6. The display substrate as claimed in claim 3, wherein, The first capacitor electrode is insulated from the resistor in the same layer.

7. The display substrate as claimed in claim 1, wherein, In the second direction, the resistor and the first data writing transistor are located on the same side of the first capacitor electrode.

8. The display substrate as claimed in claim 1, wherein the resistor has a U-shaped structure, and the opening of the U-shaped structure faces the first capacitor electrode; The first and second ends of the resistor are located at the two ends of the U-shaped structure, respectively.

9. The display substrate as claimed in claim 8, wherein, In the second direction, the second end of the resistor is closer to the driving transistor.

10. The display substrate as claimed in claim 1, wherein, The sub-pixel further includes a first connection electrode, which electrically connects a first end of the resistor to a second terminal of the driving transistor.

11. The display substrate as claimed in claim 10, wherein, The first connection electrode is electrically connected to the first end of the resistor through a first via, and electrically connected to the second electrode of the driving transistor through a second via; In a direction parallel to the surface of the substrate, the first via and the second via are located on opposite sides of the first capacitor electrode.

12. The display substrate as claimed in claim 10, wherein, The storage capacitor also includes a third capacitor electrode; In a direction perpendicular to the substrate, the third capacitor electrode is located on the side of the first capacitor electrode away from the second capacitor electrode and is configured to be electrically connected to the second capacitor electrode.

13. The display substrate as claimed in claim 12, wherein, The third capacitor electrode is insulated from the first connecting electrode in the same layer and is made of the same material.

14. The display substrate as claimed in claim 12, wherein, The third capacitor electrode includes a first portion and a second portion spaced apart. The first part and the second part are located on both sides of the first connecting electrode, and are respectively configured to be electrically connected to the second capacitor electrode.

15. The display substrate as claimed in claim 1, wherein, The second capacitor electrode of the storage capacitor is the first region of the substrate and overlaps with the first capacitor electrode in a direction perpendicular to the substrate.

16. The display substrate as claimed in claim 1, wherein, The first capacitor electrode of the storage capacitor is disposed on the same layer as the gate of the driving transistor and is an integral structure.

17. The display substrate according to any one of claims 3-16, wherein, The control signal further includes a second control signal, and the data writing sub-circuit further includes a second data writing transistor, which is an N-type metal-oxide-semiconductor field-effect transistor. The gate of the second data write transistor is configured to receive a second control signal, and the first terminal of the second data write transistor is electrically connected to the first terminal of the first data write transistor; the second terminal of the second data write transistor is electrically connected to the second terminal of the first data write transistor.

18. The display substrate as claimed in claim 17, wherein, The gates of the first data write transistor and the second data write transistor are arranged side by side along the first direction and are symmetrical about the axis of symmetry along the second direction; the first direction intersects the second direction.

19. The display substrate as claimed in claim 17, wherein, The sub-pixel further includes a second connection electrode, which includes a first end, a second end, and a third end. The first end of the second connection electrode is electrically connected to the second electrode of the first data writing transistor, the second end of the second connection electrode is electrically connected to the second electrode of the second data writing transistor, and the third end of the second connection electrode is electrically connected to the first end of the storage sub-circuit.

20. The display substrate as claimed in claim 1, wherein, Four sub-pixels constitute a pixel unit group, and the four sub-pixels are arranged in an array along the first direction and the second direction. The resistors of the four sub-pixels are projected onto the substrate in the same N-type well region of the substrate.

21. The display substrate as claimed in claim 20, wherein, The resistors of adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction, and the resistors of adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

22. The display substrate as claimed in claim 20, wherein, The first capacitor electrodes of two adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction, and the first capacitor electrodes of two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

23. The display substrate as claimed in claim 22, wherein, The first capacitor electrode of the four sub-pixels is projected onto the substrate outside the N-type well region and surrounds the N-type well region.

24. The display substrate as claimed in claim 22, wherein, The storage capacitor also includes a third capacitor electrode. In a direction perpendicular to the substrate, the third capacitor electrode is located on the side of the first capacitor electrode away from the second capacitor electrode and is configured to be electrically connected to the second capacitor electrode. The third capacitor electrodes of two adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction. The third capacitor electrodes of two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

25. The display substrate as claimed in claim 24, wherein, The third capacitor electrode includes a first portion and a second portion spaced apart from each other in the first direction, and the first portion and the second portion are respectively configured to be electrically connected to the second capacitor electrode. The first portion of the third capacitor electrode of two adjacent sub-pixels in the first direction is connected to each other as a single unit.

26. The display substrate of claim 25, comprising a plurality of said pixel unit groups arranged along the first direction. in, The second part of the third capacitor electrode of the sub-pixel in each pixel unit group and the second part of the third capacitor electrode of the sub-pixel adjacent to the sub-pixel in the pixel unit group adjacent to the pixel unit group are connected to each other as a whole.

27. The display substrate as described in any one of claims 20-26, wherein, The control signal includes a first control signal and a second control signal. The data writing sub-circuit includes a first data writing transistor and a second data writing transistor. The gate of the first data writing transistor is configured to receive the first control signal, and the gate of the second data writing transistor is configured to receive the second control signal. The first terminal of the first data writing transistor is electrically connected to the first terminal of the second data writing transistor and configured to receive the data signal; the second terminal of the first data writing transistor is electrically connected to the second terminal of the second data writing transistor and is electrically connected to the first terminal of the storage sub-circuit and the control electrode of the driving sub-circuit. The second data write transistors of the four sub-pixels are all located in the same N-type well region.

28. The display substrate as claimed in claim 27, wherein, The gates of the second data write transistors of adjacent sub-pixels in the first direction are symmetrical about the axis of symmetry along the second direction and connected as a whole. The gates of the second data write transistors in two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

29. The display substrate as claimed in claim 27, wherein, The first poles of the second data writing transistors of two adjacent sub-pixels in the second direction are symmetrically connected along the first direction and form a single structure. The first pole of the second data writing transistor of two adjacent sub-pixels in the first direction is symmetrical about the axis of symmetry along the second direction.

30. The display substrate as claimed in claim 1, wherein, The pixel circuit also includes a bias sub-circuit. The bias sub-circuit includes a control terminal, a first terminal, and a second terminal. The control terminal of the bias sub-circuit is configured to receive a bias signal. The first terminal of the bias sub-circuit and the second terminal of the storage sub-circuit are both configured to receive a second power supply voltage. The second terminal of the bias sub-circuit is electrically connected to the second electrode of the driving sub-circuit and the first terminal of the resistor.

31. A display device comprising a display substrate as described in any one of claims 1-30 and the light-emitting element on the display substrate, wherein, The first electrode of the light-emitting element is electrically connected to the second end of the resistor.

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