Sense amplifier, storage device and reading and writing method

Abstract

The present application relates to a sense amplifier, a storage device and a read-write method, wherein the sense amplifier comprises: a first switch unit, a second switch unit and an amplifying latch module, wherein the first port of the amplifying latch module is electrically connected to a bit line connected to a storage unit via the first switch unit, and the second port of the amplifying latch module is electrically connected to a reference voltage signal via the second switch unit; the amplifying latch module is used to amplify a signal in a sensing amplification stage, wherein the first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification stage, and the second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification stage, and disconnect the electrical connection between the reference voltage signal and the second port in the sensing amplification stage. The present application reduces energy consumption and improves the utilization rate of a storage array while ensuring that the sense amplifier has a high reading and writing speed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a sensitive amplifier, a storage device, and a reading and writing method. Background Art

[0002] Semiconductor memory devices are usually arranged in a large two-dimensional array of memory cells. The memory cells in each row can be selected by a row line (also commonly referred to as a word line), and the memory cells in each column can be selected by a column line (usually referred to as a bit line). The memory cells located at the intersection of the word line and the bit line are used to store the corresponding information.

[0003] Sense amplifiers can accurately determine the information stored in a storage unit and are widely used in various storage devices to read the information stored in the storage unit.

[0004] However, the sense amplifiers in conventional memory devices need to be further improved in terms of power consumption, speed, and utilization efficiency of the memory array. Summary of the invention

[0005] Based on this, it is necessary to provide a sensitive amplifier, a storage device and a reading and writing method that have higher reading and writing speeds, consume less energy and can improve the utilization efficiency of a storage cell array.

[0006] In order to achieve the above-mentioned purpose, the first aspect of the present application provides a sense amplifier, comprising a first switch unit, a second switch unit and an amplifying latch module, wherein the first port of the amplifying latch module is electrically connected to a bit line connected to a storage unit via the first switch unit, and the second port of the amplifying latch module is electrically connected to a reference voltage signal via the second switch unit; wherein the amplifying latch module is used to amplify the signal in a sensing amplification stage, the first switch unit is configured to transmit the voltage on the bit line to the first port before the sensing amplification stage, the second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification stage, and disconnect the electrical connection between the reference voltage signal and the second port in the sensing amplification stage.

[0007] In the sense amplifier in the above embodiment, it is realized that the amplifying latch module can perform information reading and writing operations on the storage unit connected to the bit line via a bit line. Compared with the amplifying latch module in the traditional sense amplifier that requires a bit line as a reference, it avoids the situation where the chip area is wasted due to the fact that some storage cells in the storage cell array are not read and written normally, and can significantly improve the storage capacity of the unit area storage chip and improve the utilization efficiency of the storage cell array. In addition, since the sense amplifier in the present application can perform information reading and writing operations on the storage unit through the bit line connected thereto without the reference bit line consuming power, the energy consumption of the sense amplifier is reduced while ensuring that the sense amplifier has a high reading and writing speed.

[0008] In one embodiment, the first switch unit is further configured to disconnect the electrical connection between the bit line and the first port in the sensing and amplification phase, and to be turned on in the write-back phase to write back the data amplified by the amplifying latch module into the storage unit, and the second switch unit is further configured to disconnect the electrical connection between the second port and the reference voltage signal in the write-back phase. Since the first switch unit disconnects the connection between the amplifying latch module and the bit line in the sensing and amplification phase, the load is prevented from having an adverse effect on the amplifying latch module in the sensing and amplification process; since the second switch unit disconnects the electrical connection between the amplifying latch module and the reference voltage signal in the write-back phase, the energy consumption of the amplifying latch module can be reduced.

[0009] In one of the embodiments, the second port of the amplifying latch module is electrically connected to a reference voltage source via the second switch unit, and the reference voltage source is used to provide a reference voltage signal to the amplifying latch module.

[0010] In one embodiment, the second port of the amplifying latch module is electrically connected to a complementary bit line connected to a complementary storage unit via the second switch unit, and the complementary bit line is used to provide a reference voltage signal to the amplifying latch module, so that the sensitive amplifier can read information and / or write information to the storage unit connected to the bit line via the unit line.

[0011] In one embodiment, the amplification latch module includes a first transistor, a second transistor, a third transistor and a fourth transistor; the source of the first transistor and the source of the third transistor are electrically connected to a first voltage node, the source of the second transistor and the source of the fourth transistor are electrically connected to a second voltage node, the drain of the first transistor and the drain of the second transistor are electrically connected and serve as a first port of the amplification latch module, the drain of the third transistor and the drain of the fourth transistor are electrically connected and serve as a second port of the amplification latch module, the gate of the first transistor and the gate of the second transistor are electrically connected to the second port, and the gate of the third transistor and the gate of the fourth transistor are electrically connected to the first port.

[0012] In the sense amplifier in the above embodiment, a first inverter is formed by setting a first transistor and a second transistor connected in series, and a second inverter is formed by setting a third transistor and a fourth transistor connected in series, so that the first inverter and the second inverter work together to form a latch. The latch can amplify and latch information read via a bit line, and can write the amplified and latched information into a storage unit via the bit line.

[0013] In one embodiment, the sensitive amplifier further includes a third switch unit and a fourth switch unit, the first voltage node is connected to the power supply signal via the third switch unit, the third switch unit is in an on state in the sensing amplification stage and the write-back stage, and is in an off state in the pre-charging stage and the charge sharing stage; the second voltage node is grounded via the fourth switch unit, the fourth switch unit is in an on state in the sensing amplification stage and the write-back stage, and is in an off state in the pre-charging stage and the charge sharing stage.

[0014] In the sense amplifier in the above embodiment, the power supply of the amplifying latch module is controlled by controlling the actions of the third switch unit and the fourth switch unit, and in accordance with the power requirements of the sense amplifier in the four working stages, the amplifying latch module cooperates with the first transistor, the second transistor, the third transistor and the fourth transistor, so that the amplifying latch module can amplify and latch the information read via the unit line, and can write the amplified and latched information back into the storage unit via the bit line.

[0015] In one embodiment, the first transistor and the third transistor are both PMOS transistors; the second transistor and the fourth transistor are both NMOS transistors.

[0016] In one of the embodiments, the sensitive amplifier also includes a pre-charge module, which is connected between the first port of the amplifying latch module and the second port of the amplifying latch module, and the pre-charge module is configured to pre-charge the first port and the second port of the amplifying latch module during the pre-charge stage.

[0017] In one embodiment, the sense amplifier further comprises:

[0018] a fifth switch unit, wherein a first port of the fifth switch unit is connected to a second port of the amplification latch module, and the second port of the fifth switch unit is used to output first information during the sensing amplification stage or after the sensing amplification stage; and / or

[0019] A sixth switch unit, wherein a first port of the sixth switch unit is connected to the first port of the amplification latch module, and a second port of the sixth switch unit is used to output second information during the sensing amplification stage or after the sensing amplification stage.

[0020] In one embodiment, the fifth switch unit includes a first sub-switch unit and a second sub-switch unit connected in series; wherein the first sub-switch unit is connected to the second port of the amplification latch module, and the second sub-switch unit outputs the information read by the amplification latch module from the storage unit during the sensing amplification stage or after the sensing amplification stage.

[0021] In one embodiment, the first sub-switch unit is an NMOS tube; the second sub-switch unit is an NMOS tube.

[0022] In one embodiment, the storage unit includes a storage capacitor and a selection transistor; the selection transistor is connected in series between the storage capacitor and the bit line; wherein the selection transistor is in an off state during the pre-charging stage, and is in an on state during the charge sharing stage, the sensing amplification stage, and the write-back stage.

[0023] In one embodiment, the selection transistor is an NMOS transistor.

[0024] A second aspect of the present application provides a storage device, which includes a storage array, a plurality of bit lines and a plurality of sensitive amplifiers as described in any one of the embodiments of the present application, wherein the storage array includes a plurality of storage cells arranged in multiple rows and columns; the bit lines are electrically connected to the storage cells located in the same column respectively; and each of the sensitive amplifiers is connected one-to-one to each of the bit lines.

[0025] In the storage device in the above embodiment, each column of storage cells can be read and written by the corresponding sensitive amplifier without consuming power of the reference bit line, thereby avoiding the situation where a part of the storage cell array located at the edge of the storage array is not read and written normally, resulting in a waste of chip area; the utilization efficiency of the storage cell array is improved, and the energy consumption is reduced while ensuring the read and write speed.

[0026] A third aspect of the present application provides a reading and writing method, comprising:

[0027] Controlling the first switch unit to transmit the voltage on the bit line to the first port of the amplification latch module before the sensing and amplification phase, wherein the first port is electrically connected to the bit line connected to the storage unit via the first switch unit;

[0028] The second switch unit is controlled to transmit the reference voltage signal to the second port of the amplification latch module before the sensing and amplification stage, and the electrical connection between the reference voltage signal and the second port is disconnected during the sensing and amplification stage, and the second port is electrically connected to the reference voltage signal via the second switch unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 This is a structural block diagram of a sensitive amplifier provided in the first embodiment of the present application.

[0031] Figure 2 This is a structural block diagram of a sensitive amplifier provided in the second embodiment of the present application.

[0032] Figure 3 This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the third embodiment of the present application.

[0033] Figure 4 This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the fourth embodiment of the present application.

[0034] Figure 5 for Figure 4 Schematic diagram of the working timing diagram of the sense amplifier shown in FIG.

[0035] Figure 6 This is a structural block diagram of a sensitive amplifier provided in the fifth embodiment of the present application.

[0036] Figure 7 This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the sixth embodiment of the present application.

[0037] Figure 8a This is a structural block diagram of a sensitive amplifier provided in the seventh embodiment of the present application.

[0038] Figure 8b This is a structural block diagram of a sensitive amplifier provided in the eighth embodiment of the present application.

[0039] Figure 8c This is a structural block diagram of a sensitive amplifier provided in the ninth embodiment of the present application.

[0040] Fig. 9 This is a structural block diagram of a sensitive amplifier provided in the tenth embodiment of the present application.

[0041] Fig.10 This is a structural block diagram of a sensitive amplifier provided in the eleventh embodiment of the present application.

[0042] Fig.11a This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the twelfth embodiment of the present application.

[0043] Fig.11b This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the thirteenth embodiment of the present application.

[0044] Fig.11c This is a schematic diagram of the circuit principle of a sensitive amplifier provided in the fourteenth embodiment of the present application.

[0045] Fig.12a This is a schematic diagram of the structure of a storage device provided in the fifteenth embodiment of the present application.

[0046] Figure 12b A schematic diagram of the structure of a traditional storage device.

[0047] Fig.13 This is a flowchart of a reading and writing method provided in the sixteenth embodiment of the present application.

[0048] Description of reference numerals:

[0049] 10. First switch unit; 20. Amplification latch module; 21. First transistor; 22. Second transistor; 23. Third transistor; 24. Fourth transistor; 25. Third switch unit; 26: Fourth switch unit; 27. Precharge module; 30. Second switch unit; 40. Storage unit; 50. Fifth switch unit; 51. First sub-switch unit; 52. Second sub-switch tube unit; 60. Sixth switch unit; 61. Third sub-switch unit; 62. Fourth sub-switch tube unit; 41. Complementary storage unit; 42. Floating storage unit; 100. Sensitive amplifier. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. In addition, certain terms used throughout the specification and the claims that follow refer to specific elements. It will be understood by those skilled in the art that manufacturers may refer to elements by different names. This document does not intend to distinguish between elements with different names but the same functions. In the following description and embodiments, the terms "include" and "include" are open-ended and should therefore be interpreted as "include, but not limited to...". Similarly, the term "connection" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be completed by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0052] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0053] like Figure 1As shown, in one embodiment of the present application, a sense amplifier 100 is provided, which includes a first switch unit 10, an amplifying latch module 20 and a second switch unit 30. The first port of the amplifying latch module 20 is electrically connected to a bit line (Bit Line, BL) connected to a storage unit 40 via the first switch unit 10, and the second port of the amplifying latch module 20 is electrically connected to a reference voltage signal Vref via the second switch unit 30. The amplifying latch module 20 is used to amplify the signal in the sensing amplification stage. The first switch unit 10 is configured to transmit the voltage on the bit line BL to the first port of the amplifying latch module 20 before the sensing amplification stage. The second switch unit 30 is configured to transmit the reference voltage signal Vref to the second port of the amplifying latch module 20 before the sensing amplification stage, and disconnect the electrical connection between the reference voltage signal Vref and the second port of the amplifying latch module 20 in the sensing amplification stage.

[0054] In the sense amplifier in the above embodiment, it is realized that the amplifying latch module 20 can perform information reading and writing operations on the storage unit 40 connected to the bit line via a bit line. Compared with the amplifying latch module in the traditional sense amplifier that needs a bit line as a reference, it avoids the situation that a part of the storage cells in the storage cell array cannot be read and written normally, resulting in a waste of chip area, and can significantly improve the storage capacity of the unit area memory chip. In addition, since the sense amplifier in this embodiment can perform information reading and writing operations on the storage unit through the bit line connected thereto without the reference bit line consuming power, the energy consumption of the sense amplifier is reduced while ensuring that the sense amplifier has a high reading and writing speed.

[0055] Further, in a sensitive amplifier provided in one embodiment of the present application, please continue to refer to Figure 1 , the first switch unit 10 is also configured to disconnect the electrical connection between the bit line BL and the first port of the amplifying latch module 20 in the sensing and amplifying stage, and to be turned on in the write-back stage to write back the data amplified by the amplifying latch module 20 into the storage unit 40, and the second switch unit 30 is also configured to disconnect the electrical connection between the second port of the amplifying latch module 20 and the reference voltage signal Vref in the write-back stage. Since the first switch unit 10 disconnects the connection between the amplifying latch module 20 and the bit line BL in the sensing and amplifying stage, the parasitic capacitance of the bit line is prevented from affecting the speed of the amplifying latch module 20 sensing and amplifying the signal in the sensing and amplifying stage; since the second switch unit 30 disconnects the electrical connection between the amplifying latch module 20 and the reference voltage signal Vref in the write-back stage, the energy consumption of the amplifying latch module can be reduced, and the amplifying latch module 20 is not affected by the reference voltage signal Vref.

[0056] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 2As shown, the second port of the amplifying latch module 20 is electrically connected to the reference voltage source U_Vref via the second switching unit 30. The reference voltage source U_Vref is used to provide a reference voltage signal to the amplifying latch module 20, so that the sensitive amplifier 100 can perform information read and write operations on the storage unit 40 through the bit line BL connected thereto without consuming power of the reference bit line, which is more energy-efficient and significantly improves the storage capacity of the memory chip per unit area.

[0057] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 3 As shown, the amplifying latch module 20 includes a first transistor 21, a second transistor 22, a third transistor 23 and a fourth transistor 24; the source of the first transistor 21 and the source of the third transistor 23 are electrically connected to the first voltage node PCS, the source of the second transistor 22 and the source of the fourth transistor 24 are electrically connected to the second voltage node NCS, the drain of the first transistor 21 and the drain of the second transistor 22 are electrically connected and serve as the first port of the amplifying latch module 20, the drain of the third transistor 23 and the drain of the fourth transistor 24 are electrically connected and serve as the second port of the amplifying latch module 20, the gate of the first transistor 21 and the gate of the second transistor 22 are electrically connected to the second port of the amplifying latch module 20, and the gate of the third transistor 23 and the gate of the fourth transistor 24 are electrically connected to the first port of the amplifying latch module 20. In this embodiment, the first voltage node PCS can be set to input a high level signal, and the second voltage node NCS can be set to input a low level signal.

[0058] In the sense amplifier in the above embodiment, a first inverter is formed by setting a first transistor and a second transistor connected in series, and a second inverter is formed by setting a third transistor and a fourth transistor connected in series, so that the first inverter and the second inverter work together to form a latch. The latch can amplify and latch information read via a bit line, and can write the amplified and latched information into a storage unit via the bit line.

[0059] For further information, please refer to Figure 3 The first transistor 21 may be a PMOS transistor M1, the second transistor 22 may be an NMOS transistor M2, the third transistor 23 may be a PMOS transistor M3, and the fourth transistor 24 may be an NMOS transistor M4.

[0060] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 4As shown, it also includes a third switch unit 25 and a fourth switch unit 26. The first voltage node PCS is connected to the power supply Vblh via the third switch unit 25. The third switch unit 25 is in the on state in the sensing amplification stage and the write-back stage, and is in the off state in the pre-charging stage and the charge sharing stage; the second voltage node NCS is grounded via the fourth switch unit 26. The fourth switch unit 26 is in the on state in the sensing amplification stage and the write-back stage, and is in the off state in the pre-charging stage and the charge sharing stage.

[0061] In the sense amplifier in the above embodiment, the power supply of the amplifying latch module is controlled by controlling the actions of the third switch unit and the fourth switch unit, and the sense amplifier cooperates with the first transistor, the second transistor, the third transistor and the fourth transistor to amplify and latch the information read through the unit line, and write the amplified and latched information back into the storage unit through the bit line in accordance with the power demand of the sense amplifier in the four working stages.

[0062] For further information, please refer to Figure 4 The sensitive amplifier also includes a pre-charging module 27, which is connected between the first port of the amplifying latch module 20 and the second port of the amplifying latch module 20. The pre-charging module 27 is configured to pre-charge the first port of the amplifying latch module 20 and the second port of the amplifying latch module 20 during the pre-charging stage.

[0063] Specifically, please refer to Figure 4 and Figure 5 The working state of the sense amplifier mainly includes four stages: pre-charging stage PCG, charge sharing stage CS, sensing amplification stage Sensing and write recovery stage of writing information to the storage unit, wherein IDEL is a transition stage. The following is a description of the working state of each component in the four stages to illustrate the working principle of the sense amplifier in this embodiment:

[0064] In the pre-charging stage PCG, the first switch unit 10 and the second switch unit 30 are both in a closed conducting state, the pre-charging module PCG starts charging, the word line WL of the storage unit 40 is low, and PCS and NCS are U_Vref.

[0065] In the charge sharing stage CS, the first switch unit 10 and the second switch unit 30 are both in a closed conduction state, the word line WL of the storage unit 40 is high, the pre-charging module PCG stops charging, and PCS and NCS are U_Vref.

[0066] In the sensing and amplification stage, the first switch unit 10 and the second switch unit 30 are both in the disconnected state, the word line WL of the storage unit 40 is high, the third switch unit 25 and the fourth switch unit 26 are both in the closed conduction state, PCS is Vblh, NCS is at a low level, the pre-charge module PCG stops charging, and the amplification latch module 20 reads information from the storage unit 40 via the first switch unit 10.

[0067] In the write-back phase Write Recovery, the first switch unit 10 is in a closed and conductive state, the second switch unit 30 is in an open state, the word line WL of the storage unit 40 is high, the third switch unit 25 and the fourth switch unit 26 are both in a closed and conductive state, PCS is at a high level, NCS is at a low level, the pre-charge module PCG stops charging, and the amplification latch module 20 writes the read information into the storage unit 40 via the first switch unit 10.

[0068] The sensitive amplifier works in the above four stages in sequence and in a cycle, realizing information reading and writing operations on the storage unit via a single bit line, which is more energy-efficient and significantly improves the storage capacity of the memory chip per unit area.

[0069] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 6 As shown, the first port of the second switch unit 30 is connected to the second port of the amplifying latch module 20, and the second port of the second switch unit 30 is connected to the complementary bit line (Bit Line Bar, BLB) connected to the complementary storage unit 41, and the complementary bit line BLB is used to provide a reference voltage signal to the amplifying latch module 20. The structure of the complementary storage unit 41 can be the same as or different from that of the storage unit 40. In this embodiment, it is preferred that the complementary storage unit 41 has the same structure as that of the storage unit 40.

[0070] Please refer to Figure 7 In a sense amplifier provided in one embodiment of the present application, the amplifying latch module 20 is connected to the complementary bit line BLB via the second switch unit 30, and the complementary bit line BLB is connected to the complementary storage unit 41. Figure 3 The difference between the sense amplifier shown in the figure is that Figure 3 The power supply U_Vref shown in the figure is replaced by the complementary bit line BLB. In this embodiment, the complementary bit line BLB provides a reference voltage signal to the amplifying latch module 20. The working principle of the sense amplifier is the same as that of the sense amplifier. Figure 3The working principle of the sense amplifier shown in FIG is the same. Since the amplifying latch module is isolated from the complementary bit line BLB by the second switch unit 30 in the disconnected state during the sensing amplification stage and the write-back stage, power consumption is saved. When the information in the complementary storage unit 41 connected to the complementary bit line BLB is read, the amplifying latch module 20 is isolated from the bit line BL by the first switch unit 10 in the disconnected state during the sensing amplification stage and the write-back stage. Whether the information of the storage unit 40 connected to the bit line BL is read or the information of the complementary storage unit 41 connected to the complementary bit line BLB is read can be identified by identifying the word line (row) address signal, such as by whether the lowest bit of the word line (row) address is "1" or "0".

[0071] Furthermore, in a sense amplifier provided in one embodiment of the present application, the sense amplifier further includes:

[0072] a fifth switch unit, wherein a first port of the fifth switch unit is connected to a second port of the amplification latch module, and the second port of the fifth switch unit is used to output first information during the sensing amplification stage or after the sensing amplification stage; and / or

[0073] A sixth switch unit, wherein a first port of the sixth switch unit is connected to the first port of the amplification latch module, and a second port of the sixth switch unit is used to output second information during the sensing amplification stage or after the sensing amplification stage.

[0074] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 8a As shown, the sense amplifier 100 further includes a fifth switch unit 50, a first port of the fifth switch unit 50 is connected to a second port of the amplifying latch module 20, and the second port of the fifth switch unit 50 is used to output the first information during the sensing amplification stage or after the sensing amplification stage. The influence of the load on the amplifying latch module 20 in the process of the amplifying latch module 20 reading information from the storage unit 40 is reduced.

[0075] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 8b As shown, the sense amplifier 100 further includes a sixth switch unit 60, a first port of the sixth switch unit 60 is connected to the first port of the amplification latch module 20, and a second port of the sixth switch unit 60 is used to output second information during or after the sensing amplification stage.

[0076] Further, in a sense amplifier provided in one embodiment of the present application, as Figure 8cAs shown, the sense amplifier 100 further includes a fifth switch unit 50 and a sixth switch unit 60, wherein the first port of the fifth switch unit 50 is connected to the second port of the amplifying latch module 20, and the second port of the fifth switch unit 50 is used to output the first information during the sensing amplification stage or after the sensing amplification stage; the first port of the sixth switch unit 60 is connected to the first port of the amplifying latch module 20, and the second port of the sixth switch unit 60 is used to output the second information during the sensing amplification stage or after the sensing amplification stage.

[0077] Furthermore, if Fig. 9 As shown, in a sensitive amplifier provided in one embodiment of the present application, the fifth switch unit 50 includes a first sub-switch unit 51 and a second sub-switch unit 52 connected in series; wherein the first sub-switch unit 51 is connected to the second port of the amplification latch module 20, and the second sub-switch unit 52 outputs the first information read by the amplification latch module 20 from the storage unit 40 during the sensing amplification stage or after the sensing amplification stage.

[0078] Further, in a sense amplifier provided in one embodiment of the present application, as Fig.10 As shown, Fig. 9 The difference between the illustrated embodiment is that it further includes a sixth switch unit 60, the first port of the sixth switch unit 60 is connected to the first port of the amplifying latch module 20, and the second port of the sixth switch unit 60 is used to output the second information in the sensing amplification stage or after the sensing amplification stage. In this embodiment, the sixth switch unit 60 can be configured to include a third sub-switch unit 61 and a fourth sub-switch tube unit 62 connected in series, the third sub-switch unit 61 is connected to the first port of the amplifying latch module 20, and the fourth sub-switch tube unit 62 outputs the second information read by the amplifying latch module 20 from the storage unit 40 in the sensing amplification stage or after the sensing amplification stage.

[0079] For further information, please refer to Fig.11a , the first sub-switch unit 51 includes an NMOS transistor M8, and the second sub-switch unit 52 includes an NMOS transistor M9, wherein the source terminal of the NMOS transistor M8 is grounded, the gate terminal of the NMOS transistor M8 is connected to the second port of the amplifying latch module 20, the source terminal of the NMOS transistor M9 is connected to the drain terminal of the NMOS transistor M8, and the drain terminal of the NMOS transistor M9 is used to output the first information Data1 read by the amplifying latch module from the storage unit 40. The NMOS transistor M8 and the NMOS transistor M9 are in a closed conduction state during the sensing amplification stage or after the sensing amplification stage, so as to output the first information Data1 read by the amplifying latch module 20 from the storage unit 40 via the drain terminal of the NMOS transistor M9.

[0080] For further information, please refer to Fig.11b ,and Figure 8b The difference between the illustrated embodiments is that the sixth switch unit 60 includes a third sub-switch unit 61 and a fourth sub-switch unit 62 connected in series, the third sub-switch unit 61 is connected to the first port of the amplifying latch module 20, and the fourth sub-switch unit 62 outputs the second information read by the amplifying latch module 20 from the storage unit 40 during the sensing amplification stage or after the sensing amplification stage. The third sub-switch unit 61 includes an NMOS transistor M10, and the fourth sub-switch unit 62 includes an NMOS transistor M11, wherein the source terminal of the NMOS transistor M10 is grounded, the gate terminal of the NMOS transistor M10 is connected to the first port of the amplifying latch module 20, the source terminal of the NMOS transistor M11 is connected to the drain terminal of the NMOS transistor M10, and the drain terminal of the NMOS transistor M11 is used to output the second information Data2 read by the amplifying latch module 20 from the storage unit 40.

[0081] For further information, please refer to Fig.11c The first sub-switch unit 51 includes an NMOS transistor M8, and the second sub-switch unit 52 includes an NMOS transistor M9, wherein the source terminal of the NMOS transistor M8 is grounded, the gate terminal of the NMOS transistor M8 is connected to the second port of the amplifying latch module 20, the source terminal of the NMOS transistor M9 is connected to the drain terminal of the NMOS transistor M8, and the drain terminal of the NMOS transistor M9 is used to output the first information Data1 read by the amplifying latch module 20 from the storage unit 40. The third sub-switch unit 61 includes an NMOS transistor M10, and the fourth sub-switch unit 62 includes an NMOS transistor M11, wherein the source terminal of the NMOS transistor M10 is grounded, the gate terminal of the NMOS transistor M10 is connected to the first port of the amplifying latch module 20, the source terminal of the NMOS transistor M11 is connected to the drain terminal of the NMOS transistor M10, and the drain terminal of the NMOS transistor M11 is used to output the second information Data2 read by the amplifying latch module 20 from the storage unit 40.

[0082] For details, please continue to refer to Fig.11c, the data output port of the second sub-switch unit and the data output port of the fourth sub-switch unit can be precharged to a high level. If the data stored in the read storage unit 40 is "0", the first port of the amplifying latch module 20 is low and the second port is high during the sensing amplification stage or after the sensing amplification stage. Then the high level of the second port of the amplifying latch module 20 is turned on, and the NMOS transistor M8 is turned on and outputs a low level signal through the NMOS transistor M9; at the same time, the low level signal of the first port of the amplifying latch module 20 is turned off, so that the NMOS transistor M10 is in a cut-off state, so that the data output port of the NMOS transistor M11 is kept in a high level state during precharging. Thereby, differential complementary transmission of signals is realized, and the accuracy of signal transmission is ensured.

[0083] Although Fig.11a , Fig.11b and Fig.11c A single transistor is shown in the figure, but the first sub-switch unit 51 or the second sub-switch unit 52 can be a plurality of NMOS transistors arranged in parallel, and the third sub-switch unit 61 or the fourth sub-switch unit 62 can be a plurality of NMOS transistors arranged in parallel. Generally, the use of multiple transistors in parallel can help increase the current handling capacity of the transistor. Since the signal of the first port and / or the second port of the amplifying latch module 20 is connected to the gate of the NMOS transistor M8 or the NMOS transistor M10, when the result is output, the load will not affect the state of the amplifying latch module 20, thereby not affecting the accuracy of the stored data. Fig.11a , Fig.11b and Fig.11c The purpose is to illustrate the working principle of this application, not to limit this application, and can be modified according to actual needs. Fig.11a , Fig.11b and Fig.11c Any equivalent deformation of the circuit shown falls within the scope of protection of this application.

[0084] Further, in a sense amplifier provided in one embodiment of the present application, as Fig.11a , Fig.11b and Fig.11c As shown, the storage cell 40 includes a storage capacitor Bit cell and a selection transistor M7, the selection transistor M7 controls the terminal word line WL; the selection transistor M7 is connected in series between the storage capacitor Bit cell and the bit line BL; the selection transistor M7 is configured to be in a disconnected state in the pre-charging stage, and in a conductive state in the charge sharing stage, the sensing amplification stage and the write-back stage. The selection transistor M7 can be an NMOS tube.

[0085] In a storage device provided in one embodiment of the present application, as Fig.12aAs shown, it includes a storage array and a plurality of bit lines, wherein the storage array includes a plurality of storage cells 40 arranged in multiple rows and columns; the bit lines are respectively connected to the storage cells 40 located in the same column; and a plurality of sensitive amplifiers SA as described in any embodiment of the present application are connected one-to-one with each of the bit lines. Figure 12b A storage device formed by a conventional sense amplifier. Figure 12b It can be seen that half of the memory cells at the edge of the memory array of the memory device are floating memory cells 42 in an idle state, resulting in a waste of memory chip area. However, by using the sensitive amplifier in the embodiment of the present application, when there is no connection to the complementary bit line for providing the reference voltage signal, it is possible to implement information reading and writing operations on the memory cells connected to the unit line via the unit line, thereby avoiding the waste of chip area due to the existence of floating memory cells in the memory device. The structure of the floating memory cell 42 may be the same as or different from that of the memory cell 40. In the present embodiment, it is preferred to set the structure of the floating memory cell 42 to be the same as that of the memory cell 40.

[0086] In a reading and writing method provided in one embodiment of the present application, as Fig.13 As shown, the following steps are included:

[0087] Step 202: Control the first switch unit to transmit the voltage on the bit line to the first port of the amplification latch module before the sensing and amplification phase, wherein the first port is electrically connected to the bit line connected to the storage unit via the first switch unit;

[0088] Step 204: Control the second switch unit to transmit the reference voltage signal to the second port of the amplification latch module before the sensing and amplification stage, and disconnect the electrical connection between the reference voltage signal and the second port during the sensing and amplification stage, and the second port is electrically connected to the reference voltage signal via the second switch unit.

[0089] In the read-write method in the above embodiment, it is realized that the amplifying latch module can perform information read and write operations on the storage unit connected to the bit line via a bit line. Compared with the amplifying latch module in the traditional read-write method that requires a bit line as a reference, it avoids the situation where the chip area is wasted due to a part of the storage cells in the storage cell array not being read and written normally, and can significantly improve the storage capacity of the unit area storage chip and improve the utilization efficiency of the storage cell array. In addition, since the read-write method in this embodiment can perform information read and write operations on the storage unit through the bit line connected thereto without the reference bit line consuming power, it reduces energy consumption while ensuring the read-write speed.

[0090] For the specific definition of the reading and writing method in the above embodiment, reference may be made to the definition of the sense amplifier in the above text, which will not be repeated here.

[0091] It should be understood that although Fig.13 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig.13 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0092] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Including but not limited to DRAM, SDRAM, SRAM, DDR SDRAM, DDR2SDRAM, DDR3 SDRAM, DDR4 SDRAM, LPDDR4 SDRAM, DDR5 SDRAM, LPDDR5SDRM, GDDR5 SDRAM, GDDR6 SDRAM, PRAM, MRAM, RRAM.

[0093] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0094] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0095] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. For a person of ordinary skill in the art, several modifications and improvements may be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present patent application shall be subject to the attached claims.

Claims

1. A sensitive amplifier, characterized in that: include: a first switch unit; a second switch unit; an amplifying latch module, wherein a first port of the amplifying latch module is electrically connected to a bit line connected to a storage unit via the first switch unit, and a second port of the amplifying latch module is electrically connected to a reference voltage signal via the second switch unit; The amplification latch module is used to amplify the signal in the sensing amplification stage, the first switch unit is configured to transmit the voltage on the bit line to the first port before the sensing amplification stage, and the second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification stage, and disconnect the electrical connection between the reference voltage signal and the second port in the sensing amplification stage; Among them, the first switch unit is also configured to disconnect the electrical connection between the bit line and the first port in the sensing and amplification phase, and to be turned on in the write-back phase to write back the data amplified by the amplification latch module into the storage unit, and the second switch unit is also configured to disconnect the electrical connection between the second port and the reference voltage signal in the write-back phase.

2. The sense amplifier according to claim 1, characterized in that: The second port of the amplifying latch module is electrically connected to a reference voltage source via the second switch unit, and the reference voltage source is used to provide a reference voltage signal to the amplifying latch module.

3. The sense amplifier according to claim 1, characterized in that: The second port of the amplifying latch module is electrically connected to a complementary bit line connected to a complementary storage unit via the second switch unit, and the complementary bit line is used to provide a reference voltage signal to the amplifying latch module.

4. The sensitive amplifier according to any one of claims 1 to 3, characterized in that: The amplifying latch module comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The source of the first transistor and the source of the third transistor are electrically connected to a first voltage node, the source of the second transistor and the source of the fourth transistor are electrically connected to a second voltage node, the drain of the first transistor and the drain of the second transistor are electrically connected and serve as a first port of the amplification latch module, the drain of the third transistor and the drain of the fourth transistor are electrically connected and serve as a second port of the amplification latch module, the gate of the first transistor and the gate of the second transistor are electrically connected to the second port, and the gate of the third transistor and the gate of the fourth transistor are electrically connected to the first port.

5. The sense amplifier according to claim 4, characterized in that: Also includes: A third switch unit, wherein the first voltage node is connected to a power supply signal via the third switch unit, and the third switch unit is in an on state in the sensing amplification stage and the write-back stage, and is in an off state in the pre-charging stage and the charge sharing stage; A fourth switch unit, wherein the second voltage node is grounded via the fourth switch unit, the fourth switch unit is in an on state in the sensing amplification stage and the write-back stage, and is in an off state in the pre-charging stage and the charge sharing stage.

6. The sense amplifier according to claim 5, characterized in that: The first transistor and the third transistor are both PMOS transistors; The second transistor and the fourth transistor are both NMOS transistors.

7. The sensitive amplifier according to any one of claims 1 to 3, characterized in that: Also includes: A pre-charging module is connected between the first port of the amplifying latch module and the second port of the amplifying latch module, and is configured to pre-charge the first port and the second port of the amplifying latch module in a pre-charging stage.

8. The sensitive amplifier according to any one of claims 1 to 3, characterized in that: Also includes: a fifth switch unit, wherein a first port of the fifth switch unit is connected to a second port of the amplification latch module, and the second port of the fifth switch unit is used to output first information during the sensing amplification stage or after the sensing amplification stage; and / or A sixth switch unit, wherein a first port of the sixth switch unit is connected to the first port of the amplification latch module, and a second port of the sixth switch unit is used to output second information during the sensing amplification stage or after the sensing amplification stage.

9. The sense amplifier according to claim 8, characterized in that: The fifth switch unit includes a first sub-switch unit and a second sub-switch unit connected in series; The first sub-switch unit is connected to the second port of the amplifying latch module, and the second sub-switch unit outputs the information read by the amplifying latch module from the storage unit in the sensing amplification stage or after the sensing amplification stage.

10. The sense amplifier according to claim 9, characterized in that: The first sub-switch unit is an NMOS tube; The second sub-switch unit is an NMOS tube.

11. The sensitive amplifier according to any one of claims 1 to 3, characterized in that: The storage unit comprises: Storage capacitor; A selection transistor connected in series between the storage capacitor and the bit line; The selection transistor is configured to be in an off state in the pre-charging stage, and in an on state in the charge sharing stage, the sensing amplification stage and the write-back stage.

12. The sense amplifier according to claim 11, characterized in that: The selection transistor is an NMOS transistor.

13. A storage device, characterized in that: include: A storage array includes a plurality of storage cells arranged in multiple rows and columns; a plurality of bit lines, each of which is electrically connected to the memory cells in the same column; and A plurality of sense amplifiers as claimed in any one of claims 1 to 12 are connected one-to-one with each of the bit lines.

14. A reading and writing method, characterized in that: include: Controlling the first switch unit to transmit the voltage on the bit line to the first port of the amplification latch module before the sensing and amplification phase, wherein the first port is electrically connected to the bit line connected to the storage unit via the first switch unit; Controlling the second switch unit to transmit the reference voltage signal to the second port of the amplification latch module before the sensing and amplification stage, and disconnecting the electrical connection between the reference voltage signal and the second port during the sensing and amplification stage, wherein the second port is electrically connected to the reference voltage signal via the second switch unit; Controlling the first switch unit to disconnect the electrical connection between the bit line and the first port during the sensing and amplifying phase, and to turn on during the writing-back phase to write back the data amplified by the amplifying latch module into the storage unit; The second switch unit is controlled to disconnect the electrical connection between the second port and the reference voltage signal during the write-back phase.

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