Ball grid array and associated devices and systems

Abstract

This application relates to ball grid arrays and associated devices and systems. A device can include a device substrate including a microelectronic device and bond pads proximate an active surface of the device substrate. A package substrate can be secured to the device substrate. A ball grid array can be supported on and electrically connected to the package substrate. Each ball positioned and configured to carry a high bandwidth data signal or a high frequency clock signal can be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high bandwidth data signal or a high frequency clock signal. Each ball positioned and configured to carry a high bandwidth data signal can be located only diagonally adjacent to any other ball configured to carry a high bandwidth data signal or a high frequency clock signal.

Description

[0001] CLAIM

[0002] This application claims the priority date benefit of U.S. Provisional Patent Application No. 63 / 033,380 for “Ball Grid Arrays and Associated Semiconductor Device Packages,” filed June 2, 2020. TECHNICAL FIELD

[0003] The present disclosure relates generally to techniques for configuring ball grid arrays of microelectronic device packages. More specifically, the disclosed embodiments relate to ball grid arrays and associated signal routing between ball grid arrays and associated microelectronic devices, embodiments of which can reduce crosstalk and improve signal quality, particularly at high bandwidths and clock speeds. BACKGROUND

[0004] One important purpose of microelectronic device (e.g., semiconductor die) packages is to connect the devices to higher level packaging of electronic systems. One aspect of packaging is to convert signals from the relatively small features of a die (e.g., bond pads or re-routed bond pads) to the larger and more widely spaced connection sites of the next higher level of packaging, such as a circuit board. One advantageous packaging configuration is the so-called ball grid array (BGA) package, in which conductive traces extend from sites on one side of a packaging substrate that is arranged and spaced to connect to the closely spaced rows of bond pads of a die to an array of discrete conductive elements, typically in the form of soldered sites or balls, arranged in rows and columns and at a larger pitch (i.e., center-to-center spacing) on the opposite side of the packaging substrate. Robust coupling between the devices and the higher level packaging of a system is critical, particularly at high signal speeds.

[0005] Internal die-level signal optimization to support various performance aspects such as power, latency, and internal jitter reduction can depend on die bond pad order to minimize data path and clock tree length, deliver sufficient power to the circuitry through an appropriate number of interpenetrating power and ground connections, and / or minimize overall die size to reduce cost. However, the pattern and pitch of the balls of a BGA, or the "ball" definition, is generally dictated by industry-wide (i.e., JEDEC) standards and takes into account the applications in which the microelectronic device package is intended to operate. Thus, the opportunity for performance optimization in the signal paths of the package substrate is limited. As signal speeds increase with increased bandwidth, increased clock speeds, and decreased ball pitch, signal crosstalk issues due to signal coupling between adjacent balls are exacerbated. In particular instances, increasing the memory capacity and operating speed of double data rate (DDR) dynamic random access memory (DRAM) in the form of synchronous DRAM (SDRAM) and graphics double data rate (GDDR) DRAM presents challenges in this regard. SUMMARY

[0006] In some embodiments, an apparatus can include a device substrate including a microelectronic device and bond pads coupled to an active surface of the device substrate. A package substrate can be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array can be supported on and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal can be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal.

[0007] In other embodiments, an apparatus can include a device substrate including a microelectronic device and bond pads proximate an active surface of the device substrate. A package substrate can be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array can be supported on and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry a high-bandwidth data signal can be located only diagonally adjacent to any other directly adjacent ball configured to carry the other of the high-bandwidth data signal or a high-frequency clock signal.

[0008] In other embodiments, a system can include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device can be connected to the CPU, the GPU, or the FPGA. The at least one memory device can include a device substrate including a microelectronic device and a bond pad proximate an active surface of the device substrate. A package substrate can be affixed to the device substrate, the package substrate configured to route signals to and from the bond pad. A ball grid array can be supported on and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal can be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high bandwidth data signal or the high frequency clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] While the disclosure is summarized with the claims of particular embodiments specifically pointed out and distinctly claimed, various features and advantages of embodiments within the scope of the disclosure can be determined with more ease from the descriptions below when read together with the drawings, in which:

[0010] Figure 1 is a quadrant bottom perspective partial transparent view of a microelectronic device package including a ball grid array and a package substrate utilizing signal routing techniques according to the present disclosure;

[0011] Figure 2 is a cross-sectional side view of the microelectronic device package of Figure 1

[0012] Figure 3 is a bottom surface view of the microelectronic device package of Figure 1

[0013] Figure 4 is a schematic view of one quadrant of a ball grid array according to the present disclosure, including labels of signals to be carried by the ball grid array;

[0014] Figure 5 is a schematic view of one quadrant of another ball grid array, including labels of signals to be carried by the ball grid array;

[0015] Figure 6 is a schematic view of one quadrant of another ball grid array, including labels of signals to be carried by the ball grid array;

[0016] Figure 7 is a schematic view of one quadrant of a conventional ball grid array known to the inventors, including labels of signals to be carried by the ball grid array;

[0017] ​​Figure 8 is a schematic diagram of another conventional ball grid array half known to the inventors, including labels of signals to be carried by the ball grid array;

[0018] Figure 9 is a plot of magnetic field strength generated by a ball grid array according to the present disclosure;

[0019] Figure 10 is another plot of magnetic field strength generated by a ball grid array according to the present disclosure;

[0020] Figure 11 is another plot of magnetic field strength generated by a conventional ball grid array known to the inventors;

[0021] Figure 12 is a plot of cross-talk between various components of a microelectronic device package according to the present disclosure;

[0022] Figure 13 is a plot of eye height of data signals carried by balls of various ball grid arrays discussed herein;

[0023] Figure 14 is a plot of simulated performance of a ball grid array according to the present disclosure and a conventional ball grid array known to the inventors; and

[0024] Figure 15 is a block diagram of an electronic system incorporating a memory configured as a BGA package according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] The disclosed embodiments generally relate to ball grid arrays (and other arrayed electrical interconnections) and associated signal routing between ball grid arrays and associated microelectronic devices, embodiments of which can reduce cross-talk and improve signal quality, particularly at high bandwidths and clock speeds. More particularly, embodiments of ball grid arrays and associated signal routing between ball grid arrays and associated microelectronic devices are disclosed that can distribute balls of a ball grid array configured to carry high bandwidth data signals, high frequency clock signals, error detection codes, or data bus inversion among other balls of the ball grid array optionally configured to carry low bandwidth data signals to reduce adjacency between such balls. For example, those balls positioned and configured to carry high bandwidth data signals or high frequency clock signals can be located no more than one other ball of the ball grid array laterally and longitudinally adjacent to a ball configured to carry the other of high bandwidth data signals or high frequency clock signals. As another example, those balls of a ball grid array positioned and configured to carry high bandwidth data signals or high frequency clock signals can be located only diagonally adjacent to any other directly adjacent ball configured to carry the other of high bandwidth data signals or high frequency clock signals.

[0026] As used herein, the terms "substantially" and "about" in reference to a given parameter, property, or condition means and includes at least some degree of deviation from an exact quantity, state, or position, due to potential manufacturing tolerances and / or measurement inaccuracies, within an acceptable range of values, and / or such that the end result is not adversely affected or changed in a material way. For example, a parameter that is substantially or about a specified value can be at least about 90% of the specified value, at least about 95% of the specified value, at least about 99% of the specified value, or even at least about 99.9% of the specified value.

[0027] As used herein, the terms "memory" and "memory device" include, without limitation, microelectronic devices exhibiting memory functionality, but excluding embodiments encompassing transitory signals. For example, a system on a chip (SoC) is encompassed in the sense of a memory device. By way of non-limiting example, as described herein, a memory device can generally include a packaged microelectronic device having a ball grid array and signal routing configuration, unless otherwise specified.

[0028] As used herein in connection with a ball grid array (or other arrayed electrical interconnect), the term "ball" means and includes a discrete mass and structure of electrically conductive material positioned and configured to connect a microelectronic device package to other devices, components, and structures of an electrical system (e.g., an interposer, a printed circuit board, etc.). For example, the term "ball" includes a solder ball or solder joint as well as other discrete electrically conductive elements, including but not limited to (e.g., metal) posts, studs, pillars, studs, or other shapes for the above-mentioned purposes.

[0029] As used herein in connection with balls of a ball grid array, the terms "laterally adjacent" and "vertically adjacent" mean and include, respectively, balls that are directly left, right, above, or below a given ball when the BGA is parallel to the plane of the drawing sheet, located when the geometric centers of the balls in the ball grid array are at least substantially aligned on a common horizontal or vertical plane. For example, balls in a ball grid array having laterally and vertically adjacent balls can form at least a substantially square-shaped diamond in a combined manner with lines connecting the geometric centers of the balls forming at least a substantially cross or plus sign. Laterally or vertically adjacent balls, pads, or elements can also be referred to as being next to, contiguous with, side-by-side with, or abutting one another, in that they can each have a side, edge, or point that is next to, contiguous with, side-by-side with, or abutting another ball, pad, or element, without any other such elements between the two.

[0030] The term "diagonally adjacent" as used herein in connection with ball grid arrays means and includes balls that are located directly above, directly below, directly to the right, and directly to the left of a given ball when the BGA is parallel to the plane of the drawing sheet when the geometric centers of the balls in the ball grid array are at least substantially aligned in a common diagonal (i.e., diagonal) plane. For example, a ball in a ball grid array that has balls diagonally adjacent to it in all directions can collectively form at least a substantially "X" shape within at least a substantially square using lines connecting the geometric centers of the balls. Diagonally adjacent balls, pads, or elements can also be referred to as being next to, contiguous with, side-by-side with, or abutting one another, as they can each have a point that is next to, contiguous with, side-by-side with, or abutting another ball, pad, or element, without any other such elements between the two.

[0031] The term "surrounding" as used herein in connection with ball grid arrays means and includes balls that are located laterally, longitudinally, and diagonally adjacent to a given ball when the BGA is parallel to the plane of the drawing sheet when the geometric centers of the balls in the ball grid array are at least substantially aligned in a common vertical, horizontal, and diagonal plane. For example, balls in a ball grid array that are surrounded by other balls can collectively form a three-by-three square matrix using lines connecting the geometric centers of the balls.

[0032] The term "high bandwidth" as used herein in connection with data signals means and includes data signals that are capable of transmitting data at a baud rate of about 10 gigasymbols per second or more. For example, a high bandwidth data signal can be capable of transmitting data at a baud rate of between about 15 gigasymbols per second and about 20 gigasymbols per second or possibly more.

[0033] The term "high frequency" as used herein in connection with clock signals means and includes clock signals that operate at a frequency of about 8 GHz or more. For example, a high frequency clock signal can operate at a frequency of between about 10 GHz and about 45 GHz or possibly more.

[0034] The illustrations presented in this disclosure are not meant to be actual views of any particular microelectronic device package, ball grid array, or component thereof, but are idealized representations that are employed to describe the illustrative embodiments. As such, the illustrations are not necessarily to scale.

[0035] Figure 1 is a bottom perspective partial transparent view of the northwest quadrant of a package substrate 102 of a microelectronic device package 100 that includes a ball grid array 400 (or other arrayed electrical interconnect) utilizing signal routing techniques in accordance with this disclosure.

[0036] Figure 2 is a bottom perspective partial transparent view of the northwest quadrant of a package substrate 102 of a microelectronic device package 100 that includes a ball grid array 400 (or other arrayed electrical interconnect) utilizing signal routing techniques in accordance with this disclosure. Figure 1 is a cross-sectional side view of a microelectronic device package 100 of Figure 3 is a cross-sectional side view of a microelectronic device package 100 of Figure 1FIG. 1 illustrates a bottom surface view of a microelectronic device package 100 with certain components removed to more clearly illustrate certain features highlighted in the following description.

[0037] Overall Reference Figures 1 to 3 The microelectronic device package 100 can include a device substrate 108 (e.g., a silicon semiconductor die, other microelectronic device structure), for example. The device substrate 108 can include a semiconductor material or other microelectronic device structure capable of forming and / or supporting integrated circuitry, for example. More specifically, the device substrate 108 can include an active surface 202 having integrated circuitry embedded therein and / or supported thereon, bond pads 106 on and coupled to the active surface 202 operatively connected to the integrated circuitry and configured to provide input and output connections for the integrated circuitry, and a passive surface 204 on an opposite side of the device substrate 108 from the active surface 202. As a specific, non-limiting example, the device substrate 108 can include an active surface 202 having integrated circuitry configured as memory (e.g., a graphics double data rate (GDDR) type 6 or higher synchronous dynamic random access memory (SDRAM)), bond pads 106 forming at least two rows located at least substantially in a center of the active surface 202 and away from a lateral perimeter of the active surface, and a passive surface 204 having no integrated circuitry on an opposite side of the device substrate 108 from the active surface 202.

[0038] The package substrate 102 can generally be configured to route signals to and from the device substrate 108, and to provide a more convenient connection configuration when compared to the size of the bond pads 106 of the device substrate 108 itself. For example, the package substrate 102 can be configured as a printed circuit board (PCB) or interposer, or other structure for routing electrical signals to and from the bond pads 106 of the device substrate 108. More specifically, the package substrate 102 can include selectively positioned regions of conductive and dielectric material, and the conductive material can be operatively connected and mechanically secured to the bond pads 106 of the device substrate 108 by the conductive elements 104 (e.g., copper pillars) interposed between the package substrate 102 and the device substrate 108. As a specific, non-limiting example, the package substrate 102 can include: a conductive material input pad 210 in contact with the conductive elements 104, which in turn are in contact with the bond pads 106; a layer 206 of dielectric material; conductive material vias 208 positioned and configured to carry signals received at the input pad 210 from the device substrate 108 at least partially longitudinally (i.e., in a direction at least substantially perpendicular to the active surface 202 of the device substrate 108) through the thickness of the package substrate 102; conductive material traces 112 positioned and configured to carry signals received at the input pad 210 from the device substrate 108 laterally (i.e., in a direction at least substantially parallel to the active surface 202 of the device substrate 108) along the surface of the layer 206 of dielectric material; and a conductive material output pad 212 on the side of the package substrate 102 opposite the device substrate 108, the output pad 212 configured to output signals routed from the input pad 210 through the traces 112 and vias 208 to the output pad 212. Although the traces 112 are depicted in Figure 1 as extending along the surface of the package substrate 102 supporting the BGA 400, the traces can also or instead extend along the surface facing the device substrate and / or within other materials of the package substrate 102, such as between layers 206 of dielectric material, as depicted in Figure 3 Suitable conductive materials for the traces 112, conductive elements 104, and any other conductive structures of the package substrate 102 can include, for example, aluminum, gold, copper, and alloys thereof, and combinations thereof. Suitable dielectric materials for the remainder of the package substrate 102 (e.g., the layers 206) can include, for example, dielectric polymer resins.

[0039] Ball grid array 400 (or other electrical interconnects comprising discrete conductive elements) can be supported on and electrically connected to an opposite side of package substrate 102 from device substrate 108. For example, ball grid array 400 can include conductive material balls 110 supported on and secured to output pads 212 of package substrate 102, and balls 110 can be distributed in an array of repeating geometric patterns. More specifically, balls 110 of ball grid array 400 can be positioned to form a rectangular (e.g., square) grid of lines interconnecting geometric centers of adjacent balls 110, with geometric centers of adjacent balls 110 forming vertices of the rectangle. As a specific non-limiting example, in a ball on chip (BOC) configuration, balls 110 of ball grid array 400 can be distributed in a frame or band near a perimeter of package substrate 102, with open areas under bond pads 106 of device substrate 108, with multiple columns and rows of balls 110 within each band or ring. A total number of columns of balls 110 within ball grid array 400 can be, for example, between about 6 and about 20 (e.g., about 10, about 15). A total number of rows of balls 110 within ball grid array 400 can be, for example, between about 10 and about 40 (e.g., about 18, about 20, about 36). A material of balls 110 can include, for example, solder (e.g., tin / silver solder). In some ball on chip (BOC) or direct chip attach (DCA) BGA packages, an array of balls 110 can be located on an underside of package substrate 102 and can bridge a space between package substrate 102 and a connected device or structure (e.g., PCB, chip, another package substrate).

[0040] Figure 4 is a schematic view of one (i.e., the northwest) quadrant of ball grid array 400 (or other arrayed electrical interconnect) according to the present disclosure, including labels of signals carried by balls 110 of ball grid array 400, respectively. Each region in the schematic view can represent a location of a single ball 110 in ball grid array 400, and an associated signal input and / or output via ball 110. In embodiments, quadrants of ball grid array 400 can be vertically stacked (i.e., northwest and southwest quadrants) with the same layout along columns and substantially laterally mirrored (i.e., northeast and southeast quadrants), with a center gap 402 inserted between adjacent bands of balls 110. Gap 402 can be located under bond pads 106 (see Figure 2 、 Figure 3 ).

[0041] To reduce crosstalk between the balls 110 of the ball grid array 400 and further improve signal quality, signals and balls 110 can be distributed such that the adjacency between balls 110 positioned and configured to carry high-bandwidth data signals and high-frequency clock signals can be reduced and / or limited, particularly lateral and longitudinal adjacency. More specifically, the layout of the ball grid array 400 and the associated signals carried by the balls 110 of the ball grid array 400 can reduce or completely eliminate the occurrence of multiple balls 110 positioned and configured to carry high-bandwidth data signals and high-frequency clock signals that are sequentially adjacent laterally across a row or longitudinally along a column.

[0042] For example, it is positioned and configured to carry high-bandwidth data input / output signals (such as...) Figure 4 (marked as "DQ") or high-frequency (write) clock signal (such as Figure 4 Each ball 110 of a ball grid array 400 (labeled "WCK") may be located laterally or longitudinally adjacent to no more than one other ball 110 of a ball grid array 400 configured to carry either a high-bandwidth data signal DQ or a high-frequency clock signal WCK. More specifically, the ball 110 is positioned and configured to carry the high-bandwidth data signal DQ, the high-frequency clock signal WCK, and error detection codes (such as...). Figure 4 (marked as "EDC") or data bus transponder (e.g.) Figure 4 Each ball 110 of one of the ball grid arrays 400 (labeled "DBI") is located laterally or longitudinally adjacent to no more than two other balls 110 of another ball grid array 400 configured to carry a high-bandwidth data signal DQ, a high-frequency clock signal WCK, an error detection code EDC, or a data bus transpose DBI.

[0043] For example, by positioning highly important signals by placing those balls 110, configured to carry high-bandwidth data signals DQ, high-frequency clock signals WCK, error detection codes EDC, or data bus transposes DBI, close to the gap 402 and thus close to the device substrate 108 and its bonding pads 106, the distance those signals travel can be shortened, thereby improving their quality and speed. For example, Figure 4 The ball grid array 400 shown is configured to place at least three highly important signals, specifically one of the balls 110 configured to carry high-bandwidth data signals, the ball 110 configured to carry error detection codes (EDC), and the ball 110 configured to carry data bus transpose (DBI) adjacent to the gap 402, while other highly important signals are distributed near the gap 402 and those signals are spaced apart to reduce crosstalk.

[0044] In some embodiments, by distributing the signals and balls 110 such that diagonal adjacency between balls 110 positioned and configured to carry high bandwidth data signals DQ and high frequency clock signals WCK, and optionally between balls 110 positioned and configured to carry error detection codes EDC and data bus inversion DBI, can be reduced and / or limited, crosstalk between balls 110 of the ball grid array 400 can be further reduced, and signal quality can be additionally improved. For example, each ball 110 of the ball grid array 400 positioned and configured to carry one of high bandwidth data signals DQ or high frequency clock signals WCK, and optionally each ball 110 positioned and configured to carry one of error detection codes EDC or data bus inversion WCK, can have no more than three other balls 110 of the ball grid array 400 configured to carry the other of high bandwidth data signals DQ or high frequency clock signals WCK, and optionally those other balls 110 configured to carry the other of error detection codes EDC or data bus inversion DBI, in positions around each respective ball 110. More particularly, each ball 110 of the ball grid array 400 positioned and configured to carry one of high bandwidth data signals DQ or high frequency clock signals WCK, and optionally each ball 110 positioned and configured to carry one of error detection codes EDC or data bus inversion DBI, can have no more than two other balls of the ball grid array configured to carry the other of high bandwidth data signals DQ or high frequency clock signals WCK, and optionally those other balls 110 configured to carry the other of error detection codes EDC or data bus inversion DBI, in positions around each respective ball 110, for example.

[0045] In Figure 4In the particular embodiment shown, the balls 110 positioned and configured to carry high frequency clock signals WCK are located in one column on one lateral side of a quadrant of the ball grid array 400, and the balls 110 positioned and configured to carry error detection codes EDC and data bus inversion DBI are located in another column on the opposite lateral side of the quadrant of the ball grid array 400. The balls 110 positioned and configured to carry high bandwidth data signals DQ are distributed diagonally relative to one another, and diagonally relative to the balls 110 configured to carry high frequency clock signals WCK, error detection codes EDC and data bus inversion DBI, generally forming a "checkerboard" pattern, but for one ball 110 positioned and configured to carry a high bandwidth data signal DQ, which is located laterally adjacent to one of the balls 110 positioned and configured to carry a high frequency clock signal WCK. The balls 110 positioned and configured to carry high bandwidth data signals DQ are also distributed in columns laterally between those columns in which the balls 110 positioned and configured to carry high frequency clock signals WCK, error detection codes EDC and data bus inversion DBI are located, for one ball 110 positioned and configured to carry a high bandwidth data signal DQ, which is located in the same column as the balls 110 positioned and configured to carry error detection codes EDC and data bus inversion DBI.

[0046] In some embodiments, by distributing the signals and the balls 110 such that adjacency between balls 110 positioned and configured to carry data signals of any bandwidth, and optionally between balls 110 positioned and configured to carry clock signals of any frequency, can be reduced and / or limited, crosstalk between the balls 110 of the ball grid array 400 can be further reduced, and signal quality can be additionally improved. For example, given a quadrant, each ball 110 of the ball grid array 400 positioned and configured to carry a data signal of any bandwidth (as denoted by the label "DQ" or "CA" (i.e., command address) according to the numbering in Figure 4 In some embodiments, each ball 110 of the ball grid array 400 positioned and configured to carry a data signal of any bandwidth (as denoted by the label "DQ" or "CA" (i.e., command address) according to the numbering in

[0047] In some embodiments, by selectively distributing the balls 110 positioned and configured to carry reference voltages, to be connected to electrical ground, and to carry special signals other than error detection codes and data bus inversion (e.g., as denoted by the label "VREF" or "GND" according to the numbering in Figure 4Balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ or the high frequency clock signals WCK can be positioned and configured to carry, for example, a voltage or ground (as indicated by the balls 110 labeled "VDD" (i.e., power supply), "VSS" (i.e., ground), "VPP" (i.e., program supply or "pump"))). More specifically, most of the balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ, the high frequency clock signals WCK, the error detection code EDC, or the data bus inversion DBI can be positioned and configured to carry, for example, a voltage (VSS, VPP) or ground (VDD), to carry a test mode select signal TMS, or to carry a reset signal RES. Figure 4 Balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ or the high frequency clock signals WCK can be positioned and configured to carry, for example, a voltage or ground (as indicated by the balls 110 labeled "VDD" (i.e., power supply), "VSS" (i.e., ground), "VPP" (i.e., program supply or "pump"))). More specifically, most of the balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ, the high frequency clock signals WCK, the error detection code EDC, or the data bus inversion DBI can be positioned and configured to carry, for example, a voltage (VSS, VPP) or ground (VDD), to carry a test mode select signal TMS, or to carry a reset signal RES.

[0048] In some embodiments, by keeping the lateral and longitudinal spacing between those balls 110 that are positioned and configured to carry the high bandwidth data signals DQ and the high frequency clock signals WCK below a predetermined maximum value, lateral and longitudinal sprawl of the ball grid array 400 can be reduced and the functional density of the ball grid array 400 can be increased. For example, at most two other balls 110 of the ball grid array 400 can be inserted laterally or longitudinally between balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ or the high frequency clock signals WCK. More specifically, at most one other ball 110 of the ball grid array 400 can be inserted laterally or longitudinally between balls 110 of the ball grid array 400 that are positioned and configured to carry one of the high bandwidth data signals DQ or the high frequency clock signals WCK that are proximate to one another.

[0049] As a specific, non-limiting example, a microelectronic device package can include a device substrate including a microelectronic device and a bond pad proximate an active surface of the device substrate. A package substrate can be secured to the device substrate, the package substrate configured to route signals to and from the bond pad. A ball grid array can be supported on the package substrate and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry one of the high bandwidth data signals DQ or the high frequency clock signals WCK can be positioned laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high bandwidth data signals DQ or the high frequency clock signals WCK.

[0050] Figure 5is a schematic diagram of another northwestern quadrant of a ball grid array 500 (or other arrayed electrical interconnect) including labels of signals to be carried by the ball grid array 500. As Figure 4 shown, Figure 5 each region in the schematic diagram can represent a single ball 110 in the ball grid array 500 and an associated signal inputted and / or outputted via the ball 110. In embodiments, the quadrants of the ball grid array 500 can be vertically stacked in the same layout along a column and substantially laterally mirrored with a center gap 402 interposed between adjacent bands of balls 110. The gap 402 can be located beneath the bond pads 106 (see Figure 2 , Figure 3 ).

[0051] In the specific embodiment shown, Figure 5 the balls 110 positioned and configured to carry high frequency clock signals WCK are in the same column on a lateral side of the quadrants of the ball grid array 400 as the balls 110 positioned and configured to carry error detection codes EDC, which are depicted in Figure 5 as being adjacent to the gap 402. The balls 110 positioned and configured to carry high bandwidth data signals DQ are distributed diagonally relative to one another and diagonally relative to the balls 110 configured to carry high frequency clock signals WCK, but for one ball 110 positioned and configured to carry a high bandwidth data signal DQ, which is laterally adjacent to one of the balls 110 positioned and configured to carry high frequency clock signals WCK. The balls 110 positioned and configured to carry error detection codes EDC can be isolated from the balls 110 positioned and configured to carry high frequency clock signals WCK and high bandwidth data signals DQ, such that the balls 110 positioned and configured to carry error detection codes EDC can not be adjacent to any of the balls 110 positioned and configured to carry high frequency clock signals WCK and high bandwidth data signals DQ. The balls 110 positioned and configured to carry high bandwidth data signals DQ are also distributed in columns laterally closer to the perimeter of the package substrate 102 than the columns in which the balls 110 positioned and configured to carry high frequency clock signals WCK and error detection codes EDC are located.

[0052] Figure 6 is a schematic diagram of another northwestern quadrant of a ball grid array 600 (or other electrical interconnect including discrete conductive elements) including labels of signals to be carried by the ball grid array 600. As Figure 4 and Figure 5 shown, Figure 6Each region in the schematic diagram can represent a single ball 110 in the ball grid array 600 and the associated signals inputted and / or outputted via the ball 110. In embodiments, the quadrants of the ball grid array 600 can be vertically stacked in the same layout along the columns (i.e., the northwest and southwest quadrants) and substantially laterally mirrored (i.e., the northeast and southeast quadrants) with a center gap 402 interposed between adjacent bands of balls 110. The gap 402 can be located above the bond pads 106 (see Figure 2 , Figure 3 ).

[0053] As another example to reduce cross-talk between the balls 110 of the ball grid array 600 and otherwise improve signal quality, each ball 110 of the ball grid array 600 positioned and configured to carry a high-bandwidth data signal (e.g., labeled as “DQ,” “LBDQ” in Figure 6 may not be laterally or longitudinally adjacent to any other ball 110 of the ball grid array 600 configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal (e.g., labeled as “DQS” in Figure 6 . More specifically, each ball 110 of the ball grid array 600 positioned and configured to carry a high-bandwidth data signal can be located diagonally adjacent to no more than two other directly-adjacent balls 110 of the ball grid array 600 positioned and configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal. In other words, as shown in the upper left portion of Figure 6 , there can be no more than two diagonally-adjacent high-bandwidth data signal aggressors (DQs, etc.). Similarly, as shown in the lower left portion of Figure 6 , there can be no more than three or four diagonally-adjacent command address CA aggressors.

[0054] In some embodiments, each ball 110 of the ball grid array 600 positioned and configured to carry one of the high-bandwidth data signal or the high-frequency clock signal can be located diagonally adjacent to no more than two other directly-adjacent balls 110 of the ball grid array 600 positioned and configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal. For example, a majority of the balls 110 of the ball grid array 600 positioned and configured to carry one of the high-bandwidth data signal or the high-frequency clock signal can be located diagonally adjacent to exactly two other balls 110 of the ball grid array 600 positioned and configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal.

[0055] In some embodiments, each ball 110 of the ball grid array 600 positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal can have no more than two other balls 110 of the ball grid array 600 positioned and configured to carry the other of the high bandwidth data signal or the high frequency clock signal in a location around each respective ball 110. For example, each ball 110 of the ball grid array 600 positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal can have one or two other balls 110 of the ball grid array 600 positioned and configured to carry the other of the high bandwidth data signal or the high frequency clock signal in a location around each respective ball 110.

[0056] In some embodiments, each ball 110 of the ball grid array 600 positioned and configured to carry a data signal of any bandwidth (e.g., labeled as “DQ,” “LBDQ,” “LBDQS,” “CA” in Figure 6 In some embodiments, each ball 110 of the ball grid array 600 positioned and configured to carry a data signal of any bandwidth (e.g., labeled as “DQ,” “LBDQ,” “LBDQS,” “CA” in

[0057] In Figure 6 In the particular embodiment shown, the balls 110 positioned and configured to carry the high frequency clock signal DQS are located in the same column on one lateral side of the quadrant of the ball grid array 400, which is depicted in Figure 6 In the particular embodiment shown, the balls 110 positioned and configured to carry the high frequency clock signal DQS are located in the same column on one lateral side of the quadrant of the ball grid array 400, which is depicted in Figure 6 In the particular embodiment shown, the balls 110 positioned and configured to carry the high frequency clock signal DQS are located in the same column on one lateral side of the quadrant of the ball grid array 400, which is depicted in

[0058] In some embodiments, each ball 110 of the ball grid array 600 located laterally and longitudinally adjacent to each ball 110 of the ball grid array 600 configured to carry a high bandwidth data signal can be configured to carry a voltage, be connected to an electrical ground, or carry a low bandwidth data signal. For example, each ball 110 of the ball grid array 600 located laterally and longitudinally adjacent to each ball 110 of the ball grid array configured to carry a high bandwidth data signal can be configured to carry a voltage, be connected to an electrical ground, or carry a low bandwidth data signal.

[0059] In some embodiments, at most two other balls 110 of the ball grid array 600 can be inserted laterally or longitudinally between adjacent balls 110 of the ball grid array 600 positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal. For example, only one other ball 110 of the ball grid array 600 can be inserted laterally or longitudinally between balls 110 of the ball grid array 600 positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal proximate to each other.

[0060] As a specific, non-limiting embodiment, a microelectronic device package can include a device substrate including a microelectronic device and a bond pad proximate an active surface of the device substrate. A package substrate can be secured to the device substrate, the package substrate configured to route signals to and from the bond pad. A ball grid array can be supported on the package substrate and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry a high bandwidth data signal can be located only diagonally adjacent to any other directly adjacent ball configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

[0061] Figure 7 is a schematic diagram of one northwest quadrant of an example ball grid array 700 known to the inventors, including labels of signals to be carried by the ball grid array 700. As shown, balls 702 positioned and configured to carry a high bandwidth data signal (as labeled "DQ" in Figure 7 Figure 7 Figure 7 are positioned proximate to each other and concentrated in two columns of the ball grid array 700. More specifically, balls 702 positioned and configured to carry a high bandwidth data signal DQ, a high frequency clock signal WCK, an error detection code EDC, and a data bus inversion DBI are positioned sequentially longitudinally adjacent to each other along two columns of the ball grid array 700. One of the balls 702 positioned and configured to carry one of a high frequency clock signal WCK can be located adjacent to a gap 704.

[0062] Figure 8 is a schematic diagram of one half (e.g., the north half, the upper half) of another example ball grid array 800 known to the inventors, including labels of signals to be carried by the ball grid array 800. As shown, balls 802 positioned and configured to carry a high bandwidth data signal (as labeled "DQ," "LBDQ," "LBDQS" in Figure 8 Figure 8 Figure 8 ​​​​At least some of the balls 802 labeled "DQS," "TDQS," "DM / TDQS") are positioned adjacent to each other and in a column of the ball grid array 800. More specifically, the balls 802 positioned and configured to carry some of the high-bandwidth data signals and some of the high-frequency clock signals are positioned sequentially longitudinally adjacent to each other along the column of the ball grid array 800 proximate the gap 804. As a result, as indicated in the upper left portion of Figure 8 there is strong coupling between the strobe (clock) and data balls. Similarly, as indicated in the lower left portion of Figure 8 there is strong coupling between the command address balls.

[0063] Figure 9 is a plot 900 of magnetic field strength generated by a 3D electromagnetic field solver for a portion of a ball grid array 400 (or other arrayed electrical interconnect) having high-strength balls 110 in a generally checkerboard pattern according to the present disclosure, other balls 110 (e.g., reference voltage or ground) interleaved between and separating the respective magnetic fields of the laterally and longitudinally adjacent high-strength balls 110.

[0064] Figure 10 is another plot 1000 of magnetic field strength generated by another portion of a ball grid array 500 (or other arrayed electrical interconnect) having high-strength balls 110 in a generally diagonal pattern according to the present disclosure, the diagonal spacing of directly adjacent high-strength balls 110 being greater than the diagonal spacing where the high-strength balls 110 are directly laterally or longitudinally adjacent to each other, separating and isolating the respective magnetic fields. Figure 9 and Figure 10 the difference between the strength regions shown is plotted on a logarithmic scale such that the lines between each region divide the order of magnitude of the strength change. By spacing apart the balls 110 positioned and configured to carry the high-bandwidth data signals and the high-frequency clock signals, the maximum strength of the magnetic field generated by the electrical signals flowing through and carried by the respective balls 110 can be reduced at locations between the balls 110 themselves, such that crosstalk between the balls 110 is reduced. As Figure 9 and Figure 10As shown in each of FIGS. 1 1 A and 1 1 B, the strength of the magnetic field is strongest near the balls 1 10 themselves, and thus the spaced balls 1 10 as disclosed herein can ensure that the magnetic field has substantially room to dissipate in the region between the balls 1 10. For example, in use, the magnetic field strength between adjacent balls 1 10 of the ball grid array 400, 500 can reach a minimum that is less than about 100 times or less the maximum strength of the magnetic field. More particularly, in use, the magnetic field strength between adjacent balls 1 10 of the ball grid array 400, 500 can reach a minimum that is between about 10 times and about 100 times (e.g., 25 times, 50 times, 75 times) less than the maximum strength of the magnetic field. Balls 1 10 positioned between balls 1 10 that generate strong magnetic fields, such as those positioned and configured to carry a reference voltage and / or connected to electrical ground, can absorb the magnetic fields generated by the other balls 1 10, thereby further reducing cross-talk between balls 1 10 positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal.

[0065] Figure 11 is a map 1 100 of the magnetic field strength generated by the example ball grid array 800 depicted in Figure 8 FIG. 1 1 A, which is known to the inventors and has high strength balls 802 in a generally sequential linear pattern. When balls 802 positioned and configured to carry a high bandwidth data signal and / or a high frequency clock signal are positioned laterally and / or longitudinally adjacent to one another, particularly in sequences of more than two balls 802, the resulting magnetic fields can overlap in a manner that causes cross-talk between the balls 802. For example, the resulting magnetic fields can not have enough room to dissipate and can overlap and combine in the region between adjacent balls 802. The presence of overlapping strong magnetic fields can induce current flow within the balls 802 other than the intended flow, thereby generating cross-talk and reducing signal quality. By comparison, the signal ball coupling shown in Figure 11 is reduced by a factor of four, and the signal ball coupling shown in Figure 9 is reduced to near zero. Figure 10

[0066] Figure 12 is a plot 1200 of cross-talk between various components of a microelectronic device package according to the present disclosure. The Y-axis represents power, and the X-axis represents signal frequency in GHz. These lines are generated by identifying the balls in a ball grid array that exhibit the most severe cross-talk, and the highest power cross-talk of the balls is plotted on the Y-axis at different frequencies. Lower power for maximum cross-talk means that the respective components experience less cross-talk and maintain higher signal quality. Lines 1202 and 1214 depict cross-talk between balls of two designs of a ball grid array (or other arrayed electrical interconnect) according to the present disclosure. In particular, line 1202 depicts cross-talk between balls in which the balls positioned and configured to carry a high bandwidth data signal and / or a high frequency clock signal are generally in a pattern corresponding to Figure 9 ​The chessboard pattern arrangement. The line marked 1214 depicts crosstalk between the balls, wherein the balls positioned and configured to carry high-bandwidth data signals and / or high-frequency clock signals generally correspond to... Figure 10 The lines are arranged in parallel diagonal configurations. Line 1204 depicts crosstalk between conductive structures of the PCB branch to which the ball grid array of line 1202 is connected, and line 1206 depicts crosstalk between traces of the microelectronic device package. Line 1208 depicts crosstalk between balls in a conventional design of a ball grid array known to the inventors. Line 1210 depicts crosstalk between conductive structures of the PCB branch to which the ball grid array of line 1208 is connected, and line 1212 depicts crosstalk between traces of the microelectronic device package.

[0067] like Figure 12 As shown, compared to known examples by the inventors, the ball grid array (or other array-type electrical interconnect) design according to this disclosure exhibits lower crosstalk in the form of signal return. Furthermore, the ball grid array design according to this disclosure provides minimal total crosstalk for its corresponding microelectronic device package. In other words, the ball grid array according to this disclosure has the lowest power crosstalk among all components of the analyzed microelectronic device package. In contrast, conventional designs of ball grid arrays known to the inventors exhibit the highest or second-highest crosstalk in the form of signal return and provide the highest total crosstalk in their package at the vast majority of clock frequencies. In other words, the ball grid array design disclosed herein reduces crosstalk attributable to the ball grid array itself from the highest crosstalk component in the package to the lowest crosstalk component. More specifically, the ball grid array design disclosed herein exhibits a crosstalk reduction of approximately 15 dB to approximately 20 dB when operating at high-frequency clock speeds.

[0068] Figure 13 Figure 1300 shows the eye height of the data signal carried by the balls of the various ball grid arrays (or other array-type electrical interconnects) discussed herein. The Y-axis represents the eye height in mV, and the X-axis represents the bandwidth of the data signal measured in gigabits per second. Generally, a larger eye makes it easier to detect changes in the signal and is a sign of high-quality signal transmission, while noisy, low-quality signals will produce a smaller eye. Lines 1302 and 1304 describe the eye height of the data signal carried by two different designs of the ball grid arrays according to this disclosure. Specifically, line 1302 depicts the eye height of the data signal carried by the ball grid array, wherein the balls positioned and configured to carry high-bandwidth data signals and / or high-frequency clock signals are substantially aligned with the eye height of the data signal carried by the ball grid array. Figure 9 The chessboard pattern arrangement. The line marked 1304 depicts the eye height of the data signal carried by the ball grid array, wherein the balls positioned and configured to carry high-bandwidth data signals and / or high-frequency clock signals generally correspond to... Figure 10parallel diagonal arrangement. Lines 1306 and 1308 depict the eye height of data signals carried by two example designs of ball grid arrays known to the inventors. Line 1310 depicts the difference in eye height between line 1304 and line 1308.

[0069] As Figure 13 reflected, the design of ball grid arrays (or other arrayed electrical interconnections) according to the present disclosure maintain greater eye height in oscillating signals across all bandwidths compared to conventional designs known to the inventors. The difference in eye height is most apparent at high bandwidths, as shown by line 1310. For example, the eye height of a high bandwidth data signal of up to about 20 gigasymbols / second carried by each ball of a ball grid array positioned and configured to carry high bandwidth data signals can be at least 100 mV. More particularly, the eye height of a high bandwidth data signal of between about 10 gigasymbols / second and about 20 gigasymbols / second carried by each ball of a ball grid array positioned and configured to carry high bandwidth data signals can be between about 100 mv and about 500 mV. As a specific, non-limiting example, the eye height of a high bandwidth data signal of between about 15 gigasymbols / second and about 20 gigasymbols / second carried by each ball of a ball grid array positioned and configured to carry high bandwidth data signals can be between about 100 mv and about 400 mV (e.g., about 250 mV, about 300 mV, about 350 mV).

[0070] Figure 14 is a plot 1400 of simulated performance of a ball grid array (or other arrayed electrical interconnection) according to the present disclosure and an example ball grid array known to the inventors. The Y-axis depicts voltage of an oscillating data signal, and the X-axis depicts time in picoseconds. The right side shows simulated performance of a ball grid array according to the present disclosure at a 16 gigasymbols / second bandwidth, and the left side shows simulated performance of an example ball grid array known to the inventors at a 16 gigasymbols / second bandwidth. As Figure 14 shown, the ball grid array according to the present disclosure produces an effective eye (i.e., a break) that indicates high signal quality and fidelity. In contrast, the conventional ball grid array known to the inventors produces a closed eye when operated at this high bandwidth. This preservation of an effective eye can be particularly important when using a multi-level signal modulation format, and crosstalk can be particularly difficult to mitigate. For example, when used in conjunction with a pulse amplitude modulation level 4 (PAM4) signal formatting, the ball grid array according to the present disclosure can mitigate crosstalk and preserve signal quality.

[0071] Embodiments of the ball grid arrays disclosed herein, as well as the relevant signal routing between the ball grid arrays and associated microelectronic devices, can reduce crosstalk and improve signal quality, particularly at high bandwidths and clock speeds.

[0072] Figure 15is a block diagram of an electronic system 1500 incorporating memory 1516, 1518 configured as BGA packages according to embodiments of the present disclosure. Electronic system 1500 can include various microelectronic devices fabricated according to embodiments of the present disclosure. For example, electronic system 1500 can be any of various types of computer, tablet, cellular phone, smartphone, control circuit, or other electronic devices. Electronic system 1500 can include one or more processors 1502, such as microprocessors, to control processing and requests of system functions in electronic system 1500.

[0073] Electronic system 1500 can include a power source 1504 in operable communication with processor 1502. For example, if electronic system 1500 is a portable system, power source 1504 can include one or more of a fuel cell, a power scavenging device, a primary cell, a replaceable cell, and / or a rechargeable cell. For example, power source 1504 can also include an AC adapter; thus, electronic system 1500 can be plugged into a wall outlet. For example, power source 1504 can also include a DC adapter, such that electronic system 1500 can be plugged into a vehicle cigarette lighter or vehicle power port.

[0074] Depending on the functions performed by electronic system 1500, various other devices can be coupled to processor 1502. For example, a user interface 1506 can be coupled to processor 1502. User interface 1506 can include input devices such as buttons, switches, a keyboard, a light pen, a mouse, a digitizer, and a stylus, a touch screen, a voice recognition system, a microphone, or combinations thereof. A display 1508 can also be coupled to processor 1502. Display 1508 can include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or combinations thereof. In addition, an RF subsystem / baseband processor 1510 can also be coupled to processor 1502. RF subsystem / baseband processor 1510 can include an antenna coupled to an RF receiver and coupled to an RF transmitter (not shown). A communication port 1512 or more than one communication port 1512 can also be coupled to processor 1502. Communication port 1512 can be adapted to be coupled to one or more peripheral devices 1514, such as a modem, a printer, a computer, a scanner, or a camera, or to a network, such as a local area network, a remote area network, an intranet, or the Internet, among others.

[0075] The processor 1502 can control the electronic system 1500 by implementing software programs stored in the memory 1516, 1518. The software programs can include, for example, an operating system, database software, drawing software, word processing software, media editing software, or media playing software. The memory 1516, 1518 can be operatively coupled to the processor 1502 to store and facilitate the execution of various programs. For example, the processor 1502 can be coupled to a system memory 1516, which can include spin-torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) conforming to Double Data Rate (DDR) and / or Graphics DDR (GDDR) standards (GDDR5, GDDR6, GDDR7)), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 1516 can include volatile memory, non-volatile memory, or a combination thereof. The system memory 1516 is typically larger in size than the system memory 1516, such that it can dynamically store loaded applications and data. In some embodiments, the system memory 1516 can include one or more ball grid arrays (or other arrayed electrical interconnections) and associated signal configurations in accordance with the present disclosure, such as the ball grid arrays and associated signal configurations described above.

[0076] The processor 1502 can also be coupled to a non-volatile memory 1518, which does not mean that the system memory 1516 must be volatile. The non-volatile memory 1518 can include one or more of STT-MRAM, MRAM, read only memory (ROM) such as EPROM, resistive read only memory (RROM), and flash memory to be used in conjunction with the system memory 1516. The size of the non-volatile memory 1518 is typically selected to be just large enough to store any necessary operating system, applications, and fixed data. In addition, the non-volatile memory 1518 can include mass storage such as disk drive memory, for example, hybrid drives including resistive memory, or other types of non-volatile solid state memory, for example. In some embodiments, the non-volatile memory 1518 can include one or more ball grid arrays (or other arrayed electrical interconnections) and associated signal routing configurations in accordance with the present disclosure, such as the ball grid arrays and associated signal routing configurations described above.

[0077] In some embodiments, electronic system 1500 can include a graphics subsystem, such as graphics card 1520, connected to processor 1502. For example, graphics card 1520 and each of processor 1502 can be connected to a motherboard in their respective sockets (e.g., a Peripheral Component Interconnect Express (PCIe) socket for graphics card 1520, a CPU socket for processor 1502) and supported on the motherboard. Graphics card 1520 can include its own processing devices, such as a graphics processing unit (GPU) or field programmable gate array (FPGA) 1522. GPU or FPGA 1522 can be configured as and can be a specialized device for processing graphics-related tasks to accelerate image creation in a frame buffer for output to display 1508. Graphics card 1520 can also include a memory bank, such as graphics memory block 1524, which can include one or more high-speed memory devices connected to GPU or FPGA 1522 and configured to store and facilitate acceleration of graphics-related data. More specifically, graphics memory block 1524 can include one or more groups of devices configured as dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) conforming to double data rate (DDR) and / or graphics DDR (GDDR) standards (GDDR5, GDDR6, GDDR7)). In some embodiments, one or more of graphics subsystem, graphics card 1520, GPU or FPGA 1522, and / or graphics memory block 1524 can include one or more ball grid arrays (or other arrayed electrical interconnections) and associated signal routing configurations in accordance with the present disclosure, such as the ball grid arrays and associated signal routing configurations described above. For example, one or more balls of graphics memory block 1524 can be configured to communicate data, command / address information, or both from GPU or FPGA 1522 with processor 1502.

[0078] In other words, an electronic system according to the present disclosure can include an input device, an output device, at least one processor, and at least one memory device each operatively interconnected with one another. The at least one memory device can include a microelectronic device package that can include a device substrate including a microelectronic device and a bond pad proximate an active surface of the device substrate. A package substrate can be affixed to the device substrate, the package substrate configured to route signals to and from the bond pad. A ball grid array can be supported on and electrically connected to the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal can be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal. In some such embodiments, each ball of the ball grid array positioned and configured to carry a high-bandwidth data signal can be located only diagonally adjacent to any other directly adjacent ball configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal.

[0079] Embodiments of a ball grid array according to the present disclosure can reduce crosstalk and improve signal quality, particularly where bandwidth and clock speed are high. For example, embodiments of a ball grid array and associated signal routing between the ball grid array and connected microelectronic devices can distribute balls of the ball grid array configured to carry a high-bandwidth data signal, a high-frequency clock signal, an error detection code, or a data bus inversion and, optionally, other balls of the ball grid array configured to carry a low-bandwidth data signal to reduce adjacency between such balls. This configuration can increase the likelihood that signals carried by the ball grid array form an effective eye, particularly when using a multi-level signal modulation format. For example, when used in conjunction with PAM4 signal formatting, a ball grid array according to the present disclosure can mitigate crosstalk and maintain signal quality.

[0080] Additional non-limiting embodiments within the scope of the present disclosure include:

[0081] Embodiment 1 : An apparatus comprising: a device substrate comprising a microelectronic device and a bond pad coupled with an active surface of the device substrate; a package substrate affixed to the device substrate, the package substrate configured to route signals to and from the bond pad; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high-bandwidth data signal or the high-frequency clock signal.

[0082] Embodiment 2: The apparatus of embodiment 1, wherein each ball of the ball grid array positioned and configured to carry one of an error detection code or a data bus inversion is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry the other of an error detection code or a data bus inversion.

[0083] Embodiment 3: The apparatus of embodiment 1 or embodiment 2, wherein each ball of the ball grid array positioned and configured to carry a high bandwidth data signal or a high frequency clock signal has no more than three other balls of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal in a position around each respective ball.

[0084] Embodiment 4: The apparatus of embodiment 3, wherein each ball of the ball grid array positioned and configured to carry a high bandwidth data signal or a high frequency clock signal has no more than two other balls of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal in a position around each respective ball.

[0085] Embodiment 5: The apparatus of any one of embodiments 1-4, wherein each ball of the ball grid array positioned and configured to carry a data signal of any bandwidth within a given quadrant of the ball grid array is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry another data signal of any bandwidth within the same quadrant of the ball grid array.

[0086] Embodiment 6: The apparatus of any one of embodiments 1-5, wherein a majority of balls of the ball grid array located laterally and longitudinally adjacent to each ball of the ball grid array configured to carry a high bandwidth data signal or a high frequency clock signal are configured to carry a voltage or ground.

[0087] Embodiment 7: The apparatus of embodiment 6, wherein at most two other balls of the ball grid array are interposed laterally or longitudinally between adjacent balls of the ball grid array positioned and configured to carry a high bandwidth data signal or a high frequency clock signal.

[0088] Embodiment 8: The apparatus of any one of embodiments 1-7, wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located laterally or longitudinally non-adjacent to any other ball of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

[0089] Embodiment 9: The apparatus of any of embodiments 1-8, wherein an eye height of the high-bandwidth data signal carried by each ball of the ball grid array positioned and configured to carry a high-bandwidth data signal up to about 20 gigasymbols / second is at least 100 mV.

[0090] Embodiment 10: The apparatus of any of embodiments 1-9, wherein a strength of a magnetic field proximate balls of the ball grid array reaches a minimum value that is less than about 100 times or less of a maximum strength of the magnetic field proximate the balls when in use.

[0091] Embodiment 11: The apparatus of any of embodiments 1-10, wherein the bond pads comprise two rows of bond pads located at least substantially at a center of the active surface of the device substrate and away from a lateral perimeter of the active surface.

[0092] Embodiment 12: An apparatus comprising: a device substrate comprising a microelectronic device and bond pads proximate an active surface of the device substrate; a package substrate secured to the device substrate, the package substrate configured to route signals to and from the bond pads; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry a high-bandwidth data signal is located diagonally adjacent to only one other directly adjacent ball configured to carry the other one of a high-bandwidth data signal or a high-frequency clock signal.

[0093] Embodiment 13: The apparatus of embodiment 12, wherein each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal is located diagonally adjacent to no more than two other directly adjacent balls of the ball grid array configured to carry the other one of a high-bandwidth data signal or a high-frequency clock signal.

[0094] Embodiment 14: The apparatus of embodiment 12 or embodiment 13, wherein each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal has no more than two other balls of the ball grid array configured to carry the other one of a high-bandwidth data signal or a high-frequency clock signal in a location around each respective ball.

[0095] Embodiment 15: The apparatus of any of embodiments 12-14, wherein each ball of the ball grid array positioned and configured to carry a high-frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other one of a high-bandwidth data signal or a high-frequency clock signal.

[0096] Embodiment 16: The apparatus of any one of embodiments 12-15, wherein each ball of the ball grid array positioned and configured to carry any bandwidth of data signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry another data signal of any bandwidth.

[0097] Embodiment 17: The apparatus of any one of embodiments 12-16, wherein each ball of the ball grid array located laterally and longitudinally adjacent to each ball of the ball grid array configured to carry a high bandwidth data signal is configured to carry a voltage, be connected to ground, or carry a low bandwidth data signal.

[0098] Embodiment 18: The apparatus of embodiment 17, wherein at most two other balls of the ball grid array are interposed laterally or longitudinally between the proximate balls of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal.

[0099] Embodiment 19: The apparatus of any one of embodiments 12-18, wherein an eye height of the high bandwidth data signal carried by each ball of the ball grid array positioned and configured to carry a high bandwidth data signal of up to about 20 gigasymbols / second is at least 100 mV.

[0100] Embodiment 20: The apparatus of any one of embodiments 12-19, wherein, in use, a strength of a magnetic field between adjacent balls of the ball grid array reaches a minimum value that is less than about 100 times or less of a maximum strength of the magnetic field of the adjacent balls.

[0101] Embodiment 21: A system comprising: a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof; and at least one memory device connected to the CPU, the GPU, or the FPGA, the at least one memory device comprising: a device substrate comprising a microelectronic device and a bond pad proximate an active surface of the device substrate; a package substrate affixed to the device substrate, the package substrate configured to route signals to and from the bond pad; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

[0102] Embodiment 22: The system of embodiment 21, wherein each ball of the ball grid array positioned and configured to carry high-bandwidth data signals is located only diagonally adjacent to any other directly adjacent ball configured to carry the other of high-bandwidth data signals or high-frequency clock signals.

[0103] Embodiment 23: The system of embodiment 21 or embodiment 22, wherein the at least one memory device comprises a graphics double data rate synchronous dynamic random access memory.

[0104] Embodiment 24: The system of any one of embodiments 21-23, wherein the system comprises the CPU and the GPU or the FPGA, wherein the GPU or the FPGA is configured as a controller for the at least one memory device, and wherein one or more balls of the at least one memory device are configured for transfer of data, command / address information, or both, with the CPU.

[0105] While certain illustrative embodiments have been described in connection with the present disclosure, those in the art will recognize and appreciate the applicability of the scope of the present disclosure is not limited to those embodiments explicitly shown and described herein. Indeed, there can be many additions, deletions, and modifications to the embodiments described in the present disclosure that fall within the scope of the present disclosure, such as those expressly stated, including legal equivalents. Further, features of one disclosed embodiment can be combined with features of another disclosed embodiment while still falling within the scope of the present disclosure.

Claims

1. An apparatus comprising: a device substrate comprising a microelectronic device and a bond pad coupled with an active surface of the device substrate; a package substrate affixed to the device substrate, the package substrate configured to route signals to and from the bond pad; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of the high bandwidth data signal or the high frequency clock signal.

2. The apparatus of claim 1, wherein each ball of the ball grid array positioned and configured to carry one of an error detection code or a data bus inversion is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry another of the high bandwidth data signal, the high frequency clock signal, the error detection code, or the data bus inversion.

3. The apparatus of claim 1, wherein each ball of the ball grid array positioned and configured to carry the high bandwidth data signal or the high frequency clock signal has no more than three other balls of the ball grid array configured to carry the other of the high bandwidth data signal or the high frequency clock signal in a position around each respective ball.

4. The apparatus of claim 3, wherein each ball of the ball grid array positioned and configured to carry the high bandwidth data signal or the high frequency clock signal has no more than two other balls of the ball grid array configured to carry the other of the high bandwidth data signal or the high frequency clock signal in a position around each respective ball.

5. The apparatus of claim 1, wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a command address within a given quadrant of the ball grid array is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry the other of the high bandwidth data signal or the command address within the same quadrant of the ball grid array.

6. The apparatus of claim 1, wherein a majority of balls of the ball grid array located laterally and longitudinally adjacent to each ball of the ball grid array configured to carry the high bandwidth data signal or the high frequency clock signal are configured to carry a voltage or ground.

7. The apparatus of claim 6, wherein at most two other balls of the ball grid array are interposed laterally or longitudinally between adjacent balls of the ball grid array positioned and configured to carry one of the high bandwidth data signal or the high frequency clock signal.

8. The apparatus of any one of claims 1-7, wherein each ball of the ball grid array positioned and configured to carry one of the high bandwidth data signal or the high frequency clock signal is located laterally or longitudinally non-adjacent to any other ball of the ball grid array configured to carry the other of the high bandwidth data signal or the high frequency clock signal.

9. The apparatus of any one of claims 1-7, wherein an eye height of the high bandwidth data signal carried by each ball of the ball grid array positioned and configured to carry a high bandwidth data signal up to about 20 gigasymbols / second is at least 100 mV.

10. The apparatus of any one of claims 1-7, wherein a strength of a magnetic field between proximate balls of the ball grid array reaches a minimum that is about 100 times or less less than a maximum strength of a magnetic field of a proximate ball, in use.

11. The apparatus of any one of claims 1-7, wherein the bond pads include at least two rows of bond pads located substantially at a center of the active surface of the device substrate and away from a lateral periphery of the active surface.

12. An apparatus comprising: a device substrate including a microelectronic device and bond pads proximate an active surface of the device substrate; a package substrate secured to the device substrate, the package substrate configured to route signals to and from the bond pads; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located diagonally adjacent to no more than two directly adjacent balls of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

13. The apparatus of claim 12, wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located diagonally adjacent to no more than two directly adjacent balls of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

14. The apparatus of claim 12, wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal has no more than two other balls of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal in a location around each respective ball.

15. The apparatus of claim 12, wherein each ball of the ball grid array positioned and configured to carry a high frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

16. The apparatus of claim 12, wherein each ball of the ball grid array positioned and configured to carry a data signal of any bandwidth is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry another data signal of any bandwidth.

17. The apparatus of any one of claims 12-16, wherein each ball of the ball grid array located laterally and longitudinally adjacent to each ball of the ball grid array configured to carry a high bandwidth data signal is configured to carry a voltage, be connected to ground, or carry a low bandwidth data signal.

18. The apparatus of claim 17, wherein at most two other balls of the ball grid array are positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal between the proximate balls of the ball grid array.

19. The apparatus of any one of claims 12-16, wherein an eye height of the high bandwidth data signal carried by each ball of the ball grid array positioned and configured to carry a high bandwidth data signal of up to about 20 gigasymbols / second is at least 100 mV.

20. The apparatus of any one of claims 12-16, wherein a strength of a magnetic field between adjacent balls of the ball grid array reaches a minimum that is about 100 times or less less than a maximum strength of a magnetic field of an adjacent ball, in use.

21. A system comprising: a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof; and at least one memory device connected to the CPU, the GPU, or the FPGA, the at least one memory device comprising: a device substrate comprising a microelectronic device and a bond pad proximate an active surface of the device substrate; a package substrate affixed to the device substrate, the package substrate configured to route signals to and from the bond pad; and a ball grid array supported on and electrically connected to the package substrate; wherein each ball of the ball grid array positioned and configured to carry one of a high bandwidth data signal or a high frequency clock signal is located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

22. The system of claim 21, wherein each ball of the ball grid array positioned and configured to carry a high bandwidth data signal is located only diagonally adjacent to any directly adjacent ball configured to carry the other of a high bandwidth data signal or a high frequency clock signal.

23. The system of claim 21 or claim 22, wherein the at least one memory device comprises a graphics double data rate synchronous dynamic random access memory.

24. The system of claim 21 or claim 22, wherein the system comprises the CPU and the GPU or the FPGA, wherein the GPU or the FPGA is configured as a controller for the at least one memory device, and wherein one or more balls of the at least one memory device are configured to communicate data, command / address information, or both, with the CPU.

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