Three-dimensional memory and method of manufacturing the same

Abstract

The present invention relates to a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory includes: a substrate; a gate stack structure located on the substrate, which is divided into a core region and a step region arranged in sequence along a first transverse direction parallel to the substrate; a virtual separation structure perpendicular to the substrate and penetrating the step region in the first transverse direction to divide the step region into a plurality of block step regions; a gate separation structure perpendicular to the substrate and penetrating the core region in the first transverse direction along an imaginary extension line of the virtual separation structure to divide the core region into a plurality of block core regions. The gate separation structure has a first side end portion in contact with the virtual separation structure in the first transverse direction, and the virtual separation structure has a second side end portion in contact with the gate separation structure in the first transverse direction. The first side end portion is surrounded by the second side end portion, or the second side end portion is surrounded by the first side end portion, thereby avoiding the problem that the gate separation structure is prone to deformation or even fracture in the step region when using the gate separation structure to separate the step region.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a three-dimensional memory and a manufacturing method thereof.

Background Art

[0002] With the development of technology, the semiconductor industry has been constantly seeking new production methods to enable each memory die in a memory device to have a larger number of memory cells. Among them, 3D NAND (three-dimensional NAND) memory has become a relatively advanced and highly potential three-dimensional memory technology at present due to its advantages such as high storage density and low cost.

[0003] A 3D NAND memory usually includes one or more sheet storage areas. A step area for leading out gates is usually provided on at least one side of the sheet storage area. The step area has a stepped shape. The sheet storage area and the step area are usually divided into multiple blocks to obtain multiple block storage areas.

[0004] However, in the existing 3D NAND memory, the block areas are separated by gate line slots (or gate separation structures). Due to the stress effect of the step area, the gate line slots located in the step area are prone to deformation and even fracture, thereby affecting the performance of the 3D NAND memory.

Summary of the Invention

[0005] The purpose of the present invention is to provide a three-dimensional memory and a manufacturing method thereof to avoid the deformation of the gate line slots in the step area, thereby improving the performance of the three-dimensional memory.

[0006] To solve the above problems, the present invention provides a three-dimensional memory, which includes: a gate stack structure, the gate stack structure includes a core area and a step area that are arranged side by side in a first direction and are in direct contact; a virtual separation structure that penetrates the step area in the first direction; a gate separation structure that penetrates the core area in the first direction, the gate separation structure has a first end that contacts the virtual separation structure in the first direction, the virtual separation structure has a second end that contacts the gate separation structure in the first direction, and the first end is located within the second end.

[0007] Wherein, the second end includes two clamping sub-parts, the first end is located between the two clamping sub-parts in a second direction perpendicular to the first direction and is in direct contact with the two clamping sub-parts.

[0008] Wherein, the width of the clamping sub-parts in the second direction perpendicular to the first direction gradually increases in the first direction from the step area to the core area.

[0009] Wherein, the second end further includes a connecting sub-part, and the connecting sub-part is connected to the two clamping sub-parts.

[0010] Among them, the connecting sub - part is in direct contact with the first end.

[0011] Among them, the virtual separation structure further includes a second extension portion that is arranged in parallel with and in direct contact with the second end.

[0012] Among them, the second extension portion extends along the first direction.

[0013] Among them, the width of the second end in the second direction perpendicular to the first direction is greater than the width of the second extension portion in the second direction.

[0014] Among them, the width of the second end in the second direction gradually increases along the first direction from the step region towards the core region.

[0015] Among them, the width of the second end in the second direction first gradually increases and then gradually decreases along the first direction from the step region towards the core region.

[0016] Among them, the material of the virtual separation structure is an insulating material.

[0017] Among them, the gate separation structure further includes a first extension portion that is arranged in parallel with and in direct contact with the first end, and the periphery of the first end is jointly surrounded by the first extension portion and the second end.

[0018] Among them, the first extension portion extends along the first direction.

[0019] Among them, at least a part of the first end has a width in the second direction perpendicular to the first direction that is greater than the width of the first extension portion in the second direction.

[0020] Among them, the width of the first end in the second direction gradually increases along the first direction from the core region towards the step region.

[0021] Among them, the width of the first end in the second direction first gradually increases and then gradually decreases along the first direction from the core region towards the step region.

[0022] Among them, the first end extends along the first direction into the step region.

[0023] Among them, the maximum width of the first end in the second direction perpendicular to the first direction is not greater than the minimum width of the second end in the second direction.

[0024] Among them, the gate separation structure includes a conductive structure and an electrically insulating layer located between the conductive structure and the gate stack structure in the second direction perpendicular to the first direction.

[0025] Among them, the second end portion includes two clamping sub-portions. The first end portion is located between the two clamping sub-portions in a second direction perpendicular to the first direction and is in direct contact with the two clamping sub-portions. The three-dimensional memory further includes: a plurality of channel structures located in the core region, and the plurality of channel structures penetrate the core region in a third direction intersecting the first direction and the second direction;

[0026] a plurality of virtual channel structures located in the step region, and the plurality of virtual channel structures penetrate the step region in the third direction.

[0027] Among them, the virtual separation structure and the gate separation structure penetrate the gate stack structure in the third direction.

[0028] Among them, the three-dimensional memory further includes a substrate, the gate stack structure is located on the substrate, and the third direction is perpendicular to the first direction and the second direction.

[0029] Among them, the virtual separation structure is used to divide the step region into a plurality of block step regions in a second direction perpendicular to the first direction, and the gate separation structure is used to divide the core region into a plurality of block core regions in the second direction.

[0030] To solve the above problems, the present invention also provides a manufacturing method of a three-dimensional memory. The manufacturing method of the three-dimensional memory includes: forming a gate stack structure, the gate stack structure includes a core region and a step region arranged in parallel and in direct contact with each other in the first direction; forming a virtual separation structure and a gate separation structure, the virtual separation structure penetrates the step region in the first direction, the gate separation structure penetrates the core region in the first direction, the gate separation structure has a first end portion in contact with the virtual separation structure in the first direction, the virtual separation structure has a second end portion in contact with the gate separation structure in the first direction, and the first end portion is located within the second end portion.

[0031] Among them, forming the virtual separation structure and the gate separation structure specifically includes: forming a virtual gate isolation groove in the step region, the virtual gate isolation groove penetrates the step region in the first direction; filling an insulating material in the virtual gate isolation groove to form a virtual separation structure; forming a gate isolation groove in the core region and the second end portion of the virtual separation structure, the gate isolation groove penetrates the core region and a part of the second end portion in the first direction; and forming a gate separation structure in the gate isolation groove.

[0032] The beneficial effects of the present invention are as follows: Different from the prior art, the three-dimensional memory and its manufacturing method provided by the present invention use a virtual separation structure and a gate separation structure to separately separate the step region and the core region of the gate stack structure, and the gate separation structure has a first end in contact with the virtual separation structure in a first direction, and the virtual separation structure has a second end in contact with the gate separation structure in the first direction, and the first end is located within the second end. Thus, the problem that the gate separation structure is prone to deformation or even fracture in the step region due to the stress effect of the step region when using the gate separation structure to separate the step region is avoided, and the performance of the three-dimensional memory is improved.

Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 is a top view structural schematic diagram of the three-dimensional memory provided by the embodiment of the present invention;

[0035] Figure 2 is along Figure 1 the cross-sectional structural schematic diagram taken along the line O-O' in

[0036] Figure 3 is along Figure 1 the cross-sectional structural schematic diagram taken along the line P-P' in

[0037] Figure 4 is along Figure 1 the cross-sectional structural schematic diagram taken along the line Q-Q' in

[0038] Figure 5 is a structural schematic diagram of the connection between the gate separation structure and the virtual separation structure provided by the embodiment of the present invention;

[0039] Figure 6 is a structural schematic diagram of four virtual separation structures provided by the embodiment of the present invention;

[0040] Figure 7 is a flow schematic diagram of the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention.

Detailed Embodiments

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be specifically noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0042] In addition, the directional terms mentioned in the present invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention. In each of the drawings, units with similar structures are denoted by the same reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0043] Please refer to Figures 1 to 4 , Figure 1 which is a top view structural schematic diagram of a three-dimensional memory provided by an embodiment of the present invention, Figure 2 is a cross-sectional structural schematic diagram taken along the line O - O' in Figure 1 , Figure 3 is a cross-sectional structural schematic diagram taken along the line P - P' in Figure 1 , Figure 4 is a cross-sectional structural schematic diagram taken along the line Q - Q' in Figure 1 . The three-dimensional memory includes a gate stack structure 12, a virtual separation structure 13, and a gate separation structure 14. Among them, the gate stack structure 12 includes a core region 12A and a step region 12B that are arranged side by side in the first direction X and are in direct contact. The above-mentioned virtual separation structure 13 penetrates the step region 12B in the first direction X. The above-mentioned gate separation structure 14 penetrates the core region 12A in the first direction X.

[0044] In this embodiment, as shown in Figure 5As shown, the above-mentioned gate separation structure 14 has a first end portion 14A that contacts the virtual separation structure 13 in the first direction X. The virtual separation structure 13 has a second end portion 13A that contacts the gate separation structure 14 in the first direction X, and the first end portion 14A is located within the second end portion 13A to ensure that the virtual separation structure 13 and the gate separation structure 14 can play a good partitioning role after being connected together. Moreover, compared with the prior art solution of using a gate separation structure to partition the stepped area, in this embodiment, the virtual separation structure 13 is used to partition the stepped area 12B. The virtual separation structure 13 can not only support the stepped area 12B of the gate stack structure 12, making the stepped area 12B not easily collapse, but also separate the first end portion 14A of the gate separation structure 14 extending into the stepped area 12B from the gate separation structure 12, so that the first end portion 14A can be surrounded by the same film layer (i.e., the virtual separation structure 13) from bottom to top, avoiding the leakage problem caused by the deformation of the gate separation structure 14 due to different film stresses from bottom to top.

[0045] Among them, as Figure 2 shown, the gate stack structure 12 may include gate layers 121 and gate insulating layers 122 that are alternately stacked in multiple layers in the longitudinal direction Z perpendicular to the first direction X. As Figure 1 shown, the above-mentioned virtual separation structure 13 can be used to divide the stepped area 12B of the gate stack structure 12 into multiple block stepped areas K1 / K2 in the second direction Y perpendicular to the first direction X, and the gate separation structure 14 can be used to divide the core area 12A of the gate stack structure 12 into multiple block core areas K3 / K4 in the second direction Y.

[0046] Specifically, as Figure 2 shown, in the above-mentioned gate stack structure 12, the gate layer 121 is located between two adjacent gate insulating layers 122. The material of the gate layer 121 can be a conductive material such as tungsten, cobalt, copper, or aluminum, and the material of the gate insulating layer 122 can be any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. Moreover, the number of layers of the above-mentioned gate layer 121 can be determined according to the number of memory cells to be formed in the longitudinal direction Z. The above-mentioned virtual separation structure 13 can specifically be an insulating layer, and its material can be any one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. As Figure 4As shown, the above-mentioned gate separation structure 14 may specifically include a conductive structure 142 and an electrically insulating layer 141 located between the conductive structure 142 and the gate stack structure 12 in a second direction Y perpendicular to the first direction X. Among them, the conductive structure 142 may include conductive materials such as titanium or titanium nitride, polysilicon, and / or tungsten metal. The above-mentioned electrically insulating layer 141 is used to electrically isolate the conductive structure 142 and the gate stack structure 12, and may specifically be an oxide layer. Moreover, the above-mentioned conductive structure 142 can serve as a common source electrode to provide a conductive channel for source connection in the three-dimensional memory.

[0047] In a specific embodiment, as Figure 1 and Figure 5 shown, the above-mentioned second end portion 13A may include two clamping sub-portions 13A-1 / 13A-2 (that is, the first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2). The above-mentioned first end portion 14A may be located between the two clamping sub-portions 13A-1 / 13A-2 in a second direction Y perpendicular to the first direction X and be in direct contact with the two clamping sub-portions 13A-1 / 13A-2 to ensure that the second end portion 13A of the virtual separation structure 13 can isolate the first end portion 14A of the gate separation structure 14 from the gate stack structures 12 on both sides of the first end portion 14A in the second direction Y.

[0048] Specifically, as Figure 1 and Figure 5 shown, the widths of the above-mentioned first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2 in a direction perpendicular to the second direction Y may gradually increase along the first direction X from the step region 12B to the core region 12A to increase the process window when forming the gate separation structure 14, thereby reducing the manufacturing process difficulty of the three-dimensional memory.

[0049] In some embodiments, as Figure 5 shown, the above-mentioned second end portion 13A may further include a connecting sub-portion 13A-3, and the connecting sub-portion 13A-3 is connected to the above-mentioned first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2. Specifically, the connecting sub-portion 13A-3 may be in direct contact with the above-mentioned first end portion 14A.

[0050] In a specific embodiment, as Figure 5As shown, the above-mentioned virtual separation structure 13 may further include a second extension portion 13B arranged in parallel with and in direct contact with the second end portion 13A. The second extension portion 13B may extend along the first direction X. Moreover, the width W1 of the above-mentioned second end portion 13A in the second direction Y perpendicular to the first direction X is greater than the width W2 of the above-mentioned second extension portion 13B in the second direction Y. In this way, only by widening the width of a part of the above-mentioned virtual separation structure 13, the manufacturing deviation tolerance of forming the virtual separation structure 13 and the gate separation structure 14 can be improved, which is beneficial to reducing the process difficulty.

[0051] Moreover, in specific implementation, as Figure 1 and Figure 5 shown, the width W2 of the above-mentioned second extension portion 13B in the second direction Y may be a fixed value V1, while the width W1 of the above-mentioned second end portion 13A in the second direction Y may gradually increase along the first direction X from the above-mentioned step region 12B to the above-mentioned core region 12A. Specifically, as Figure 6 shown in (a) and (b) of Figure 6 , the width W1 of the above-mentioned second end portion 13A in the second direction Y may increase from the middle to both sides according to a non-linear increasing rule (for example, a broken line or an arc), or, as Figure 1 , Figure 5 and Figure 6 shown in (c) of

[0052] shown in (c), it may also increase from the middle to both sides according to a linear increasing rule (for example, a straight line). In some alternative embodiments, as Figure 6 shown in (d) of Figure 6 ,

[0053] the width W1 of the above-mentioned second end portion 13A in the second direction Y may also first gradually increase and then gradually decrease along the first direction X from the above-mentioned step region 12B to the above-mentioned core region 12A, and the minimum width of the second end portion 13A in the second direction Y is not less than the fixed value V1. In this way, by designing the second end portion 13A of the virtual separation structure 13 as a large-head structure, it can be ensured that the virtual separation structure 13 and the gate separation structure 14 can play a good partition role after being connected together, so as to avoid the problem of leakage between adjacent two block memory areas. Figure 5As shown, the above-mentioned gate separation structure 14 may further include a first extension portion 14B arranged side by side with and in direct contact with the first end portion 14A, and the periphery of the first end portion 14A is jointly surrounded by the first extension portion 14B and the second end portion 13A of the above-mentioned virtual separation structure 13. Specifically, the second extension portion 13B may extend along the first direction X. And, at least a part of the first end portion 14A has a width W3 in the second direction Y perpendicular to the first direction X that is greater than the width W4 of the above-mentioned first extension portion 14B in the second direction Y. In this way, only by widening the width of a part of the above-mentioned gate separation structure 14, the manufacturing deviation tolerance for forming the virtual separation structure 13 and the gate separation structure 14 can be further improved, which is conducive to further reducing the process difficulty.

[0054] During specific implementation, as Figure 1 and Figure 5 shown, the width W4 of the above-mentioned first extension portion 14B in the second direction Y may also be a fixed value V2, and this fixed value V2 may be less than the above-mentioned fixed value V1, that is, the width W4 of the above-mentioned first extension portion 14B in the second direction Y is less than the width W2 of the above-mentioned second extension portion 13B in the second direction Y. Further, the width W3 of the above-mentioned first end portion 14A in the second direction Y may gradually increase along the first direction X from the core area 12A to the step area 12B. And, similar to the specific implementation manner in which the width W3 of the above-mentioned second end portion 13A gradually increases in the second direction Y, the width W3 of the above-mentioned first end portion 14A in the second direction Y may also increase from the middle to both sides according to a non-linear increasing rule (such as a broken line or an arc), or may increase from the middle to both sides according to a linear increasing rule (a straight line), or may first gradually increase and then gradually decrease along the first direction X from the core area 12A to the step area 12B. At the same time, it is also possible to make the minimum width of the above-mentioned first end portion 14A in the second direction Y not less than the above-mentioned fixed value V2.

[0055] In this way, by designing the first end portion 14A of the gate separation structure 14 as a large-head structure, it can be further ensured that the above-mentioned virtual separation structure 13 and the gate separation structure 14 can play a good partitioning role after being connected together, thereby better avoiding the leakage problem between adjacent two block memory areas.

[0056] Moreover, to enable the first end portion 14A to be better wrapped by the second end portion 13A, the variation law of the width of the second end portion 13A in the second direction Y can match the variation law of the width of the first end portion 14A in the second direction Y. For example, the widths W1 / W3 of the second end portion 13A and the first end portion 14A in the second direction Y can both increase non-linearly (e.g., in a broken line pattern) from the middle to both sides. In some specific embodiments, the maximum width of the first end portion 14A along the second direction Y can be designed to be not greater than the minimum width of the second end portion 13A along the second direction Y, so that the first end portion 14A can be more easily wrapped by the second end portion 13A.

[0057] It should be noted that in this embodiment, only the side widths of the virtual separation structure 13 and / or the gate separation structure 14 are increased, so that the main widths of the virtual separation structure 13 and the gate separation structure 14 can still be maintained at a relatively small value. Compared with the solution of increasing the overall width of the separation structure, the process requirements of the etching step and the filling step can be reduced.

[0058] Moreover, only one core area 12A and one step area 12B are given as examples in this embodiment. In some embodiments, there can be two step areas 12B, and the core area 12A is located between the two step areas 12B. In other embodiments, there can be two core areas 12A, and the step area 12B is located between the two core areas 12A. Correspondingly, the internal structure on one side of the three-dimensional memory in the first direction X can refer to the internal structure on the other side. It can be understood that only the internal structure on one side of the three-dimensional memory in the first direction X is specifically described in this embodiment.

[0059] In the above embodiment, as Figure 1 and Figure 5 shown, the first end portion 14A of the gate separation structure 14 can extend along the first direction X into the step area 12B of the gate stack structure 12. Thus, without the virtual separation structure 13 extending into the core area 12A of the gate stack structure 12, the virtual separation structure 13 can surround the first end portion 14A of the gate separation structure 14 from three directions, avoiding the influence on the performance of the three-dimensional memory caused by the virtual separation structure 13 extending into the core area 12A of the gate stack structure 12.

[0060] In the above embodiment, as Figures 1 to 4As shown, the above three-dimensional memory may further include a plurality of channel structures 16 and a plurality of virtual channel structures 17. Among them, the plurality of channel structures 16 are located in the core area 12A and may penetrate the core area 12A in a third direction (for example, the above-mentioned longitudinal Z) intersecting with the above-mentioned first direction X and second direction Y. The plurality of virtual channel structures 17 are located in the step area 12B and may penetrate the step area 12B in the above-mentioned third direction. Specifically, the above-mentioned channel structure 16 may specifically include a dielectric pillar, a channel layer surrounding the dielectric pillar, and a charge storage layer surrounding the channel layer. The charge storage layer may include a tunneling oxide layer surrounding the channel layer, a charge trapping layer surrounding the tunneling oxide layer, and a blocking oxide layer surrounding the charge trapping layer. Among them, the material of the charge trapping layer may be silicon nitride, and the material of the channel layer may be polysilicon. The above-mentioned virtual separation structure 13 and the gate separation structure 14 may penetrate the gate stack structure 12 in the above-mentioned third direction.

[0061] Moreover, it can be understood that for the above three-dimensional memory, one channel structure 16 in the core area 12A is shared by multiple memory cells in a memory string. The multiple virtual channel structures in the step area 12B do not provide a storage function but are used to provide mechanical support to prevent the storage device from collapsing. And, in specific implementation, the above-mentioned virtual channel structure and the above-mentioned channel structure may have the same structure, so it will not be elaborated here.

[0062] Specifically, as Figures 1 to 4 shown, the above three-dimensional memory may further include a substrate 11. The gate stack structure 12 is located on the substrate 11, and the material of the substrate 11 may be single crystal silicon, single crystal germanium, silicon on insulator (SOI), etc. The above-mentioned third direction may be perpendicular to the above-mentioned first direction X and second direction Y, that is, the above-mentioned third direction may be the longitudinal Z perpendicular to the substrate 11. Correspondingly, the above-mentioned virtual separation structure 13 and the gate separation structure 14 may be perpendicular to the above-mentioned substrate 11.

[0063] In some specific embodiments, as Figures 1 to 4 shown, the above three-dimensional memory may further include a dielectric layer 15 covering the step area 12B, and the above-mentioned virtual separation structure 13 sequentially penetrates the dielectric layer 15 and the step area 12B in the longitudinal Z. Among them, the material of the dielectric layer 15 may be an insulating material such as silicon oxide. And, in specific implementation, the material of the above-mentioned virtual separation structure 13 may be the same as the material of the dielectric layer 15. For example, both are silicon oxide, so that the virtual separation structure 13 can be free from the stress influence of the dielectric layer 15, thereby preventing the virtual separation structure 13 from having lateral bending or torsional deformation.

[0064] In a specific embodiment, as Figure 1As shown, the above three-dimensional memory may further include at least one first sub-gate separation structure 18 and at least one second sub-gate separation structure 19. The at least one first sub-gate separation structure 18 is located in the block core regions K3 / K4, extends in the first direction X, and is not connected to the second sub-gate separation structure 19. The at least one second sub-gate separation structure 19 is located in the block step regions K1 / K2, extends in the first direction X, and is not connected to the first sub-gate separation structure 18. In the above three-dimensional memory, the block core region K3 and the block step region K1 connected in the first direction X form a block storage region, and the block core region K4 and the block step region K2 connected in the first direction X form another block storage region. Moreover, the purpose of arranging the first sub-gate separation structure 18 and the second sub-gate separation structure 19 in the above block storage region is to reduce the process difficulty. Because the more the number of steps, the greater the process difficulty. To reduce the process difficulty, when the number of gate layers is large, the block storage region can be divided into several parts by arranging the first sub-gate separation structure 18 and the second sub-gate separation structure 19, and each part exposes each layer of steps. For example, when the number of the gate layers 121 is 32 layers, if the block storage region is divided into four parts, the first part can expose the 1st, 5th, 9th, 13th, 17th, 21st, 25th, and 29th gate layers respectively, the second part can expose the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, and 30th gate layers respectively, the third part can expose the 3rd, 7th, 11th, 15th, 19th, 23rd, 27th, and 31st steps respectively, and the fourth part can expose the 4th, 8th, 12th, 16th, 20th, 24th, 28th, and 32nd steps respectively. In this way, each part has only eight steps, and at least one step includes four gate layers 121. Compared with the scheme of directly forming 32 continuous steps, the process is simpler. Moreover, the first sub-gate line separation structure 18 and the second sub-gate line separation structure 19 are staggered and not connected to each other, so that the gate layers 121 on the same layer are electrically connected to each other. And the specific structures of the first sub-gate line separation structure 18 and the second sub-gate line separation structure 19 are substantially the same as those of the gate separation structure 14, so they will not be elaborated here.

[0065] Different from the prior art, in the three-dimensional memory of this embodiment, by using the virtual separation structure and the gate separation structure to separately separate the step region and the core region of the gate stack structure, and making the gate separation structure have a first end in contact with the virtual separation structure in the first direction, the virtual separation structure have a second end in contact with the gate separation structure in the first direction, and the first end is located within the second end. Thus, the problem that the gate separation structure is prone to deformation or even fracture in the step region due to the stress action of the step region when using the gate separation structure to separate the step region is avoided, and the performance of the three-dimensional memory is improved.

[0066] Please refer to Figure 7 and Figures 1 to 6 , Figure 7 which is a schematic flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention, Figures 1 to 6 and is a schematic structural diagram of a three-dimensional memory or a partial structure in the three-dimensional memory provided by an embodiment of the present application. The specific process of the method for manufacturing the three-dimensional memory can be as follows:

[0067] Step S11: Form a gate stack structure 12, where the gate stack structure 12 includes a core region 12A and a step region 12B that are arranged side by side in the first direction X and are in direct contact.

[0068] Specifically, the above-mentioned gate stack structure 12 includes a gate sacrificial layer and a gate insulating layer 122 that are alternately stacked in multiple layers in the longitudinal direction Z perpendicular to the first direction X. The material of the gate sacrificial layer can be silicon nitride, the material of the gate insulating layer 122 can be silicon oxide, and the number of layers of the gate sacrificial layer can be determined according to the number of memory cells to be formed in the longitudinal direction. In specific implementation, the gate stack structure 12 can be formed on the substrate 11, and then the gate stack structure 12 is etched so that one end of the gate stack structure 12 in the first direction X is stepped. Among them, the material of the substrate 11 can be single crystal silicon, single crystal germanium, silicon on insulator (SOI), etc.

[0069] Step S12: Form a virtual separation structure 13 and a gate separation structure 14. The virtual separation structure 13 penetrates the step region 12B in the first direction X, the gate separation structure 14 penetrates the core region 12A in the first direction X, the gate separation structure 14 has a first end 14A that is in contact with the virtual separation structure 13 in the first direction X, the virtual separation structure 13 has a second end 13A that is in contact with the gate separation structure 14 in the first direction X, and the first end 14A is located within the second end 13A.

[0070] Among them, the virtual separation structure 13 can be used to divide the step region 12B of the gate stack structure 12 into multiple block step regions K1 / K2 in the second direction Y perpendicular to the first direction X. The gate separation structure 14 can be used to divide the core region 12A of the gate stack structure 12 into multiple block core regions K3 / K4 in the second direction Y.

[0071] Specifically, the above step S12 can include:

[0072] Step S121: Form a virtual gate isolation groove 13 in the step region 12B, and the virtual gate isolation groove 13 penetrates the step region 12B in the first direction X.

[0073] Wherein, before the above-mentioned step S121, it may further include: forming a dielectric layer 15 covering the step region 12B, and the above-mentioned dummy gate isolation trench sequentially penetrates the dielectric layer 15 and the step region 12B in the longitudinal direction Z. Among them, the material of the dielectric layer 15 may be an insulating material such as silicon oxide.

[0074] Step S122: Fill the dummy gate isolation trench with an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride) to obtain a dummy separation structure 13.

[0075] Step S123: Form a gate isolation trench in the core region 12A and the second end portion 13A of the dummy separation structure 13. The gate isolation trench penetrates the core region 12A and a part of the second end portion 13A in the first direction X.

[0076] Step S124: Form a gate separation structure 14 in the gate isolation trench.

[0077] Specifically, an electrically insulating layer 141 (such as an oxide layer) and a conductive structure 142 serving as a common source electrode may be sequentially formed on the sidewall of the above-mentioned gate isolation trench to obtain the above-mentioned gate separation structure 14. Among them, the conductive structure 142 may include conductive materials such as titanium or titanium nitride, polysilicon, and / or tungsten.

[0078] In one embodiment, as Figure 5 shown, the above-mentioned second end portion 13A may include two clamping sub-portions 13A-1 / 13A-2 (that is, a first clamping sub-portion 13A-1 and a second clamping sub-portion 13A-2). The above-mentioned first end portion 14A may be located between the first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2 in a second direction Y perpendicular to the first direction X, and be in direct contact with the first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2.

[0079] Specifically, as Figure 1 and Figure 5 shown, the widths of the above-mentioned first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2 in a direction perpendicular to the second direction Y may gradually increase in the direction from the step region 12B to the core region 12A along the first direction X.

[0080] In a specific embodiment, as Figure 5 shown, the above-mentioned second end portion 13A may further include a connecting sub-portion 13A-3, and the connecting sub-portion 13A-3 is connected to the above-mentioned first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2. Specifically, the connecting sub-portion 13A-3 may be in direct contact with the above-mentioned first end portion 14A.

[0081] In one embodiment, as Figure 5As shown, the above-mentioned virtual separation structure 13 may further include a second extension portion 13B arranged in parallel with and in direct contact with the second end portion 13A. The second extension portion 13B may extend along the first direction X. Moreover, the width W1 of the second end portion 13A in the second direction Y perpendicular to the first direction X is greater than the width W2 of the second extension portion 13B in the second direction Y.

[0082] Specifically, the width W1 of the second end portion 13A in the second direction Y may gradually increase along the first direction X from the step region 12B towards the core region 12A. In some alternative embodiments, the width W1 of the second end portion 13A in the second direction Y may first gradually increase and then gradually decrease along the first direction X from the step region 12B towards the core region 12A.

[0083] In the above embodiment, the gate separation structure 14 may further include a first extension portion 14B arranged in parallel with and in direct contact with the first end portion 14A, and the periphery of the first end portion 14A is jointly surrounded by the first extension portion 14B and the second end portion 13A of the virtual separation structure 13. Specifically, the second extension portion 13B may extend along the first direction X. Moreover, at least a part of the width W3 of the first end portion 14A in the second direction Y perpendicular to the first direction X is greater than the width W4 of the first extension portion 14B in the second direction Y.

[0084] Specifically, the width W3 of the first end portion 14A in the second direction Y may gradually increase along the first direction X from the core region 12A towards the step region 12B. In some alternative embodiments, the width W3 of the first end portion 14A in the second direction Y may first gradually increase and then gradually decrease along the first direction X from the core region 12A towards the step region 12B.

[0085] In some embodiments, the first end portion 14A may extend into the step region 12B along the first direction X.

[0086] In some embodiments, the maximum width of the first end portion 14A in the second direction Y perpendicular to the first direction X is not greater than the minimum width of the second end portion 13A in the second direction Y.

[0087] In some embodiments, the above three-dimensional memory may further include a plurality of channel structures 16 located in the core region 12A and a plurality of virtual channel structures 17 located in the step region 12B. Among them, the plurality of channel structures 16 may penetrate the core region 12A in a third direction (for example, the above-mentioned longitudinal Z) intersecting with the first direction X and the second direction Y. The plurality of virtual channel structures 17 may penetrate the step region 12B in the third direction.

[0088] Specifically, the above-mentioned virtual separation structure 13 and gate separation structure 14 can penetrate the above-mentioned gate stack structure 12 in the above-mentioned third direction.

[0089] In some specific embodiments, the above-mentioned 3D memory may further include a substrate 11, and the above-mentioned gate stack structure 12 is located on the substrate 11. Specifically, the above-mentioned third direction may be perpendicular to the above-mentioned first direction X and second direction Y, that is, the above-mentioned third direction may be the longitudinal Z perpendicular to the substrate 11.

[0090] In some embodiments, before the above-mentioned step S124, the following may further be included:

[0091] Step S125: Form a gate line slit in the core area 12A, the gate line slit being perpendicular to the substrate 11 and penetrating the core area 12B in the first direction X.

[0092] Specifically, the above-mentioned gate line slit and the above-mentioned gate isolation groove may be formed by the same etching process, and the gate line slit is not connected to the above-mentioned virtual separation structure.

[0093] Step S126: Replace the gate sacrificial layer in the gate stack structure 12 with a gate layer 121 through the gate line slit and the gate isolation groove.

[0094] Specifically, a replacement process may be used to replace the gate sacrificial layer in the above-mentioned gate stack structure 12, and a conductive material (such as tungsten) may be filled at the same position to form the corresponding gate layer 121.

[0095] Step S127: Form a common source structure in the gate line slit.

[0096] In specific embodiments, the above-mentioned step S127 and the above-mentioned step S124 may be executed simultaneously, that is, an electrically insulating layer 141 and a conductive structure 142 serving as a common source may be sequentially formed on the side walls of the above-mentioned gate line slit and the above-mentioned gate isolation groove at the same time, so as to correspondingly obtain the above-mentioned common source structure and gate separation structure 14.

[0097] It should be noted that the specific structure of the 3D memory in this embodiment may refer to the specific implementation manners in the embodiments of the above-mentioned 3D memory, so details are not described herein again.

[0098] Different from the prior art, the manufacturing method of the three-dimensional memory in this embodiment forms a gate stack structure, which includes a core region and a step region arranged side by side and in direct contact along a first direction; a virtual separation structure and a gate separation structure are formed. The virtual separation structure penetrates the step region in the first direction, and the gate separation structure penetrates the core region in the first direction. The gate separation structure has a first end in contact with the virtual separation structure in the first direction, and the virtual separation structure has a second end in contact with the gate separation structure in the first direction, and the first end is located within the second end. Thus, the problem that the gate separation structure is prone to deformation or even fracture in the step region due to the stress effect of the step region when using the gate separation structure to separate the step region is avoided, thereby improving the performance of the three-dimensional memory.

[0099] The foregoing are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A three-dimensional memory, which comprises: a gate stack structure including a core region and a step region arranged side by side and in direct contact along a first direction; a virtual separation structure penetrating the step region in the first direction; a gate separation structure penetrating the core region in the first direction, the gate separation structure having a first end in contact with the virtual separation structure in the first direction, the virtual separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end; the second end includes two clamping sub-parts, the first end being located between the two clamping sub-parts in a second direction perpendicular to the first direction and in direct contact with the two clamping sub-parts; a plurality of channel structures located in the core region, the plurality of channel structures penetrating the core region in a third direction intersecting the first direction and the second direction; a plurality of virtual channel structures located in the step region, the plurality of virtual channel structures penetrating the step region in the third direction.

2. The three-dimensional memory according to claim 1, wherein, the width of the clamping sub-part in the second direction perpendicular to the first direction gradually increases in the direction from the step region to the core region along the first direction.

3. The three-dimensional memory according to claim 1, wherein, the second end further includes a connecting sub-part connecting the two clamping sub-parts.

4. The three-dimensional memory according to claim 3, wherein, the connecting sub-part is in direct contact with the first end.

5. The three-dimensional memory according to claim 1, wherein, the virtual separation structure further includes a second extension portion arranged side by side and in direct contact with the second end.

6. The three-dimensional memory according to claim 5, wherein, the second extension portion extends along the first direction.

7. The three-dimensional memory according to claim 5, wherein, the width of the second end in the second direction perpendicular to the first direction is greater than the width of the second extension portion in the second direction.

8. The three-dimensional memory according to claim 7, wherein, the width of the second end in the second direction gradually increases in the direction from the step region to the core region along the first direction.

9. The three-dimensional memory according to claim 7, wherein, the width of the second end in the second direction first gradually increases and then gradually decreases in the direction from the step region to the core region along the first direction.

10. The three-dimensional memory according to claim 1, wherein, the material of the virtual separation structure is an insulating material.

11. The three-dimensional memory according to any one of claims 1-10, wherein, the gate separation structure further includes a first extension portion arranged side by side and in direct contact with the first end, and the periphery of the first end is jointly surrounded by the first extension portion and the second end.

12. The three-dimensional memory according to claim 11, wherein, the first extension portion extends along the first direction.

13. The three-dimensional memory according to claim 11, wherein, at least a part of the first end portion has a width in a second direction perpendicular to the first direction that is greater than the width of the first extension portion in the second direction.

14. The three-dimensional memory according to claim 13, wherein, the width of the first end portion in the second direction gradually increases in the direction from the core region to the step region along the first direction.

15. The three-dimensional memory according to claim 13, wherein, the width of the first end portion in the second direction first gradually increases and then gradually decreases in the direction from the core region to the step region along the first direction.

16. The three-dimensional memory according to any one of claims 1-10, wherein, the first end portion extends into the step region along the first direction.

17. The three-dimensional memory according to any one of claims 1-10, wherein, the maximum width of the first end portion in a second direction perpendicular to the first direction is not greater than the minimum width of the second end portion in the second direction.

18. The three-dimensional memory according to any one of claims 1-10, wherein, the gate separation structure includes a conductive structure and an electrically insulating layer located between the conductive structure and the gate stack structure in a second direction perpendicular to the first direction.

19. The three-dimensional memory according to claim 1, wherein, the virtual separation structure and the gate separation structure penetrate through the gate stack structure in the third direction.

20. The three-dimensional memory according to claim 19, wherein, the three-dimensional memory further includes a substrate, the gate stack structure is located on the substrate, and the third direction is perpendicular to the first direction and the second direction.

21. The three-dimensional memory according to any one of claims 1-10, wherein, the virtual separation structure is used to divide the step region into a plurality of block step regions in a second direction perpendicular to the first direction, and the gate separation structure is used to divide the core region into a plurality of block core regions in the second direction.

22. A method for manufacturing a three-dimensional memory, which comprises: forming a gate stack structure, the gate stack structure including a core region and a step region arranged side by side and in direct contact along a first direction; forming a virtual separation structure and a gate separation structure, the virtual separation structure penetrating through the step region in the first direction, the gate separation structure penetrating through the core region in the first direction, the gate separation structure having a first end portion in contact with the virtual separation structure in the first direction, the virtual separation structure having a second end portion in contact with the gate separation structure in the first direction, and the first end portion being located within the second end portion; the second end portion includes two clamping sub-portions, the first end portion is located between the two clamping sub-portions in a second direction perpendicular to the first direction and is in direct contact with the two clamping sub-portions; forming a plurality of channel structures located in the core region, the plurality of channel structures penetrating through the core region in a third direction intersecting with the first direction and the second direction; Form a plurality of virtual channel structures located in the step region, and the plurality of virtual channel structures penetrate the step region in the third direction.

23. The method for manufacturing a three-dimensional memory according to claim 22, wherein, the forming of the virtual separation structure and the gate separation structure specifically includes: forming a virtual gate trench in the step region, and the virtual gate trench penetrates the step region in the first direction; filling an insulating material in the virtual gate trench to form a virtual separation structure; forming a gate trench in the core region and the second end of the virtual separation structure, and the gate trench penetrates the core region and part of the second end in the first direction; forming a gate separation structure in the gate trench.

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