Array substrate and display module

Abstract

The application provides an array substrate and a display module, and relates to the technical field of display. The array substrate comprises a substrate, a plurality of array-arranged thin film transistor units, each thin film transistor unit comprising a gate electrode, an active layer, a source electrode and a drain electrode arranged on a first side of the substrate; a plurality of first structural members arranged on the first side of the substrate; a first structural member does not overlap with the source electrode in the orthographic projection of the substrate, and the first structural member does not overlap with the drain electrode in the orthographic projection of the substrate. The first structural member is arranged to at least partially shield the light emitted by the backlight in the display module, thereby avoiding the problem of element characteristic drift of the thin film transistor unit under high brightness and high temperature. Furthermore, the first structural member does not overlap with the drain electrode in the orthographic projection of the substrate, thereby avoiding the generation of overlapping capacitance between the first structural member and the drain electrode, and thereby avoiding the increase of the load of the drain electrode in the working process.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an array substrate and a display module. Background Technology

[0002] In flat panel display technology, the main structure of a liquid crystal display (LCD) consists of an array substrate and a color filter substrate assembled together, with liquid crystal injected between them. The side of the array substrate away from the color filter substrate also includes a backlight module. The array substrate contains gate lines, data lines, arrayed thin-film transistor (TFT) units, and pixel electrodes. When IGZO (indium gallium zinc oxide) is used as the TFT unit in the LCD, and the backlight emitted by the backlight module illuminates the active layer of the IGZO transistor when the LCD is in display mode, it causes poor negative bias stability of the IGZO at high brightness and high temperature. The TFT unit experiences component characteristic drift due to prolonged continuous bias, resulting in degraded display performance. Therefore, there is an urgent need to provide a new type of display module that can solve the component characteristic drift problem of TFT units at high brightness and high temperature. Summary of the Invention

[0003] In view of this, the present invention provides an array substrate and a display module to solve the problem of component characteristic drift of thin film transistor units under high brightness and high temperature.

[0004] In a first aspect, this application provides an array substrate, comprising:

[0005] Substrate

[0006] Multiple thin-film transistor units arranged in an array, each thin-film transistor unit including a gate, an active layer, a source, and a drain disposed on a first side of a substrate;

[0007] Multiple first structural components are disposed on the first side of the substrate.

[0008] The orthographic projection of the first structural component onto the substrate does not overlap with the orthographic projection of the source onto the substrate, and the orthographic projection of the first structural component onto the substrate does not overlap with the orthographic projection of the drain onto the substrate.

[0009] Secondly, this application provides a display module, including a display panel and a backlight module, wherein the display panel includes an array substrate;

[0010] The backlight module is located on the side of the substrate away from the gate.

[0011] Compared with the prior art, the array substrate and display module provided by the present invention achieve at least the following beneficial effects:

[0012] This application provides an array substrate and a display module. The array substrate includes a plurality of thin-film transistor units disposed on a first side of a substrate, and a plurality of first structural members disposed on the first side of the substrate. By setting the first structural members, the illumination emitted by the backlight in the display module is at least partially blocked, thereby avoiding the problem of component characteristic drift of the thin-film transistor units under high brightness and high temperature. Furthermore, the orthographic projection of the first structural member on the substrate and the orthographic projection of the drain on the substrate do not overlap, thereby avoiding the generation of overlapping capacitance between the first structural member and the drain, thereby avoiding the increase of load on the drain during operation, and thus avoiding the problem of poor display effect of the display panel using the array substrate.

[0013] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0014] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0016] Figure 1 The image shown is a partial perspective view of an array substrate provided in an embodiment of this application;

[0017] Figure 2 The image shown is provided in an embodiment of this application. Figure 1 A schematic diagram of a cross-section of AA';

[0018] Figure 3 The image shown is provided in an embodiment of this application. Figure 1 A schematic diagram of a cross-section of BB';

[0019] Figure 4 The image shown is another partial perspective view of the array substrate provided in an embodiment of this application;

[0020] Figure 5 The image shown is provided in an embodiment of this application. Figure 4 A schematic diagram of a cross-section of CC';

[0021] Figure 6 The image shown is another partial perspective view of the array substrate provided in an embodiment of this application;

[0022] Figure 7 The image shown is another partial perspective view of the array substrate provided in an embodiment of this application;

[0023] Figure 8 The image shown is provided in an embodiment of this application. Figure 1 Another cross-sectional schematic diagram of BB';

[0024] Figure 9 The image shown is a partial perspective view of a display module provided in an embodiment of this application;

[0025] Figure 10 The image shown is provided in an embodiment of this application. Figure 9 A schematic diagram of a cross-section of EE'. Detailed Implementation

[0026] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0027] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0028] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0029] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] In existing technologies, when IGZO (indium gallium zinc oxide) is used as the thin-film transistor (TFT) unit in an LCD, and the backlight emitted by the LCD is in display mode, the light illuminating the active layer of the IGZO transistor causes poor negative bias stability of the IGZO under high brightness and high temperature. The TFT unit experiences component characteristic drift due to prolonged continuous bias, resulting in degraded display performance. Therefore, there is an urgent need to provide a new type of display module that can solve the component characteristic drift problem of TFT units under high brightness and high temperature.

[0032] In view of this, the present invention provides an array substrate and a display module to solve the problem of component characteristic drift of thin film transistor units under high brightness and high temperature.

[0033] Figure 1 The image shown is a partial perspective view of an array substrate provided in an embodiment of this application. Figure 2 The image shown is provided in an embodiment of this application. Figure 1 A schematic diagram of a cross-section of AA'. Figure 3 The image shown is provided in an embodiment of this application. Figure 1 Please refer to a cross-sectional schematic diagram of BB'. Figures 1-3 This application provides an array substrate 100, comprising:

[0034] Substrate 01,

[0035] Multiple thin-film transistor units 10 are arranged in an array. Each thin-film transistor unit 10 includes a gate 11, an active layer 12, a source 13 and a drain 14 disposed on the first side of the substrate 01.

[0036] Multiple first structural members 20 are disposed on the first side of the substrate 01;

[0037] The orthographic projection of the first structural member 20 on the substrate 01 does not overlap with the orthographic projection of the source electrode 13 on the substrate 01, and the orthographic projection of the first structural member 20 on the substrate 01 does not overlap with the orthographic projection of the drain electrode 14 on the substrate 01.

[0038] Specifically, this application provides an array substrate 100, which includes a substrate 01, and a plurality of thin-film transistor units 10 and a plurality of first structural members 20 disposed on the same side (first side) of the substrate 01. The array substrate 100 also includes a plurality of gate lines 110 extending along a first direction and arranged along a second direction, and a plurality of data lines 130 extending along the second direction and arranged along the first direction. The plurality of thin-film transistor units 10 are arrayed and arranged along the first and second directions on the first side of the substrate 01. Each thin-film transistor unit 10 includes a gate 11, an active layer 12, a source 13, and a drain 14.

[0039] It should be noted that, Figure 1 Only four thin-film transistor units 10 are shown in the image to clearly illustrate the partial arrangement of the array substrate 100 provided in this application, and are not intended to limit the number of thin-film transistor units 10 disposed on an array substrate 100.

[0040] Since backlighting not only emits light toward the thin-film transistor unit in a direction perpendicular to the substrate, but also scatters light toward the thin-film transistor unit in different directions, even when the gate in the thin-film transistor unit is located directly below the active layer, and the orthogonal projection of the gate onto the substrate covers the orthogonal projection of the active layer onto the substrate, some light will still scatter and illuminate the active layer.

[0041] Based on the above reasons, this application provides an alternative embodiment in which a first structural member 20 is added to the array substrate 100, and the added first structural member 20 is configured in a one-to-one correspondence with the thin film transistor unit 10. Since the added first structural member 20 and the thin film transistor unit 10 are both located on the same side of the substrate 01, the film layer of the first structural member 20 can be adjusted as needed so that the first structural member 20 can be used to partially block the light emitted from the side of the substrate 01 away from the thin film transistor unit 10 toward the active layer 12 of the thin film transistor unit 10, so as to avoid the continuous irradiation of the thin film transistor unit 10 by high brightness and high temperature light as much as possible, thereby avoiding the problem of device characteristic drift of the thin film transistor unit 10 due to the irradiation of high brightness and high temperature light, which is beneficial to improving the working performance of the array substrate 100 and increasing the working life of the array substrate 100.

[0042] Meanwhile, the first structural member 20 added in this application is configured such that its orthographic projection on the substrate 01 does not overlap with the orthographic projections of the source 13 and drain 14 on the substrate 01. This avoids the generation of parasitic capacitance between the added first structural member 20 and the source 13, and between the first structural member 20 and the drain 14. This also avoids the influence of the added first structural member 20 on the source 13 and drain 14 of the thin-film transistor unit 10 during the operation of the array substrate 100. This avoids the risk of increased load on the source 13 and drain 14 during the operation of the array substrate 100, which is beneficial to ensuring the normal operation of the array substrate 100. This also helps to make the display panel including the array substrate 100 have a better display effect.

[0043] Figure 4 The image shown is another partial perspective view of the array substrate provided in an embodiment of this application. Figure 5 The image shown is provided in an embodiment of this application. Figure 4 Please refer to a cross-sectional schematic diagram of CC'. Figure 4 and Figure 5 Optionally, the first structural member 20 is located near the first edge of the gate 11 in the orthographic projection of the substrate 01, and there is a first spacing D between the gate 11 and the second edge of the gate 11 near the first structural member 20 in the orthographic projection of the substrate 01.

[0044] Specifically, the addition of the first structural member 20 in the array substrate 100 is mainly used to block light emitted from the side of the substrate 01 away from the thin-film transistor unit 10 toward the active layer 12 of the thin-film transistor unit 10. Therefore, this application provides an optional embodiment in which the first structural member 20 is positioned such that the first edge of the first structural member 20 near the gate 11 in the orthographic projection of the substrate 01 has a certain distance (first spacing D) between it and the second edge of the gate 11 near the first structural member 20 in the orthographic projection of the substrate 01. During the fabrication of the array substrate 100, this application provides an optional embodiment in which the first spacing D is made as small as possible, thereby preventing excessive light from passing through the first spacing D to irradiate the active layer 12 of the thin-film transistor unit 10, thereby reducing the amount of light irradiating the active layer 12 of the thin-film transistor unit 10 to a certain extent, and thus reducing the possibility of device characteristic drift of the thin-film transistor unit 10 caused by high-brightness and high-temperature light.

[0045] It should be noted that the added first structural member 20 prevents light from illuminating the thin-film transistor unit 10, mainly by preventing light from illuminating the active layer 12 of the thin-film transistor unit 10. Therefore, this application may choose to place the first structural member 20 on the side of the active layer 12 facing the substrate 01, so that the first structural member 20 can block light from illuminating the active layer 12. However, this application does not limit the specific film layer position of the first structural member 20, as long as it can block at least part of the light illuminating the active layer 12.

[0046] Please refer to Figures 1-3 Optionally, the orthographic projection of the first structural member 20 onto the substrate 01 takes at least one edge of the gate 11 extending along the first direction as the starting point, and extends along the second direction.

[0047] The first direction is the row direction in which the thin-film transistor units 10 are arranged, and the second direction is the column direction in which the thin-film transistor units 10 are arranged.

[0048] Specifically, all the thin-film transistor units 10 included in the array substrate 100 can be uniformly arrayed along the row and column directions on one side of the substrate 01. The row direction of the thin-film transistor units 10 arranged on the first side of the substrate 01 can be a first direction, and the column direction of the thin-film transistor units 10 arranged on the first side of the substrate 01 can be a second direction. The relationship between the first direction and the second direction is specifically a perpendicular relationship.

[0049] This application also provides an optional embodiment for adding a first structural member 20, wherein the side of the gate 11 in the thin-film transistor unit 10 extending along the first direction in the orthographic projection of the gate 11 on the substrate 01 includes two sides (31 and 32) arranged opposite to each other in the second direction. This application can select either side (31 / 32) as the starting point for setting the first structural member 20. Specifically, the orthographic projection of the first structural member 20 on the substrate 01 is set with at least one edge of the orthographic projection of the gate 11 on the substrate 01 extending along the first direction as the starting point, and the first structural member 20 extends along the second direction, with the extension direction being the side of the starting edge away from the gate 11, thereby completing the setting of the first structural member 20.

[0050] It should be noted that this application does not limit all the first structural members 20 in the array substrate 100 to start from the edge on the same side of the gate 11. It is possible to set some of the first structural members 20 to start from the first side edge 31 extending from the gate 11 along the first direction, and set some of the first structural members 20 to start from the second side edge 32 extending from the gate 11 along the first direction. As long as the set first structural members 20 can block at least part of the light irradiated to the active layer 12 of the thin film transistor unit 10, it is acceptable.

[0051] Please continue to refer to Figures 1-3 Optionally, along the second direction, the gate 11 includes a first side edge 31 and a second side edge 32 disposed opposite to each other, and at least a portion of the first structure 20 is projected onto the substrate 01 with the first side edge 31 of the gate 11 as the starting point.

[0052] Specifically, the edge of the gate 11 extending along the first direction in the orthogonal projection of the gate onto the substrate 01 includes a first side edge 31 and a second side edge 32, wherein the first side edge 31 and the second side edge 32 are disposed opposite to each other along the second direction. This application provides a first structural member 20 in a selectable configuration such as... Figure 1 As shown, the orthographic projection of all the first structural members 20 on the substrate 01 extends toward the second direction, starting from the first side edge 31 of the gate 11 in each thin film transistor unit 10; specifically, starting from the first side edge 31 of the gate 11, it extends along the second direction and along the first side edge 31 of the gate 11 toward the side away from the second side edge 32.

[0053] Thus, all thin-film transistor units 10 on the array substrate 100 provided in this application are arranged in an array uniformly, and the first structural members 20 are all disposed on the same side (first side edge 31) and at the same position of each thin-film transistor unit 10. All the first structural members 20 on the array substrate 100 are also arranged in an array uniformly. With this arrangement, the combination of all thin-film transistor units 10 and first structural members 20 on the array substrate 100 is the same and uniform, which is conducive to the simplified fabrication of the array substrate 100 and avoids the increase in complexity of the array substrate 100 process caused by adding the first structural members 20.

[0054] Figure 6 The image shown is another partial perspective view of the array substrate provided in an embodiment of this application. Please refer to... Figure 1 and Figure 6 Optionally, along the second direction, the gate 11 includes a first side edge 31 and a second side edge 32 disposed opposite to each other, and at least a portion of the first structure 20 is projected onto the substrate 01 with the second side edge 32 of the gate 11 as the starting point.

[0055] Specifically, the edge of the gate 11 extending along the first direction in the orthogonal projection of the gate 11 onto the substrate 01 includes a first side edge 31 and a second side edge 32, wherein the first side edge 31 and the second side edge 32 are disposed opposite each other along the second direction. In addition to the above-mentioned provision that the first structural member 20 is disposed with the first side edge 31 of the gate 11 as the starting point, extending along the second direction and along the side of the first side edge 31 of the gate 11 away from the second side edge 32, this application also provides an optional disposal method for the first structural member 20, wherein the orthogonal projection of all the first structural members 20 onto the substrate 01 is extended toward the second direction with the second side edge 32 of the gate 11 in each thin film transistor unit 10 as the starting point; specifically, it is disposed with the second side edge 32 of the gate 11 as the starting point, extending along the second direction and along the second side edge 32 of the gate 11 away from the first side edge 31.

[0056] Thus, all the thin-film transistor units 10 on the array substrate 100 provided in this application are also arranged in an array uniformly, and the first structural members 20 are all disposed on the same side (second side edge 32) and at the same position of each thin-film transistor unit 10. All the first structural members 20 on the array substrate 100 are also arranged in an array uniformly. With this arrangement, the combination of all the thin-film transistor units 10 and the first structural members 20 on the array substrate 100 is the same and uniform, which is conducive to the simplified manufacturing of the array substrate 100 and avoids the addition of the first structural members 20 from increasing the complexity of the array substrate 100 manufacturing process.

[0057] Figure 7The image shown is another partial perspective view of the array substrate provided in an embodiment of this application. Please refer to... Figure 1 , Figure 6 and Figure 7 Optionally, along the second direction, the gate 11 includes a first side edge 31 and a second side edge 32 disposed opposite to each other, and the orthographic projection of the plurality of first structural members 20 on the substrate 01 starts from the first side edge 31 of the gate 11 and at the same time from the second side edge 32 of the gate 11.

[0058] Specifically, taking an embodiment where each thin-film transistor unit 10 is provided with two opposing first structural members 20, this application also provides a selectable arrangement of the first structural members 20, such as... Figure 7 The semi-circular first structural members 20 shown, i.e., half of the first structural members 20, are projected onto the substrate 01 with their orthogonal projections extending in the second direction from the first side edge 31 of the gate 11 in each thin-film transistor unit 10. Specifically, they extend in the second direction from the first side edge 31 of the gate 11, along the first side edge 31 of the gate 11, towards the side away from the second side edge 32. Figure 7 The triangular first structural member 20 shown in the figure, that is, the other half of the first structural members 20, are all extended in the second direction from the second side edge 32 of the gate 11 in each thin film transistor unit 10. Specifically, they are extended in the second direction from the second side edge 32 of the gate 11 to the side away from the first side edge 31.

[0059] Thus, all thin-film transistor units 10 on the array substrate 100 provided in this application are still uniformly arranged in an array, and the first structural members 20 are all disposed on the same side (first side edge 31 and second side edge 32) of each thin-film transistor unit 10 at the same position. That is, all the first structural members 20 on the array substrate 100 are also uniformly arranged in an array. With this arrangement, the combination of all thin-film transistor units 10 and first structural members 20 on the array substrate 100 is the same and uniform, which is also conducive to the simplified fabrication of the array substrate 100 and avoids the addition of first structural members 20 from increasing the complexity of the array substrate 100 process.

[0060] Furthermore, this application provides that each thin-film transistor unit 10 is provided with two corresponding first structural members 20, with the first side edge 31 and the second side edge 32 of the gate 11 in each thin-film transistor unit 10 as the starting points and extending towards the second direction. At this time, for each thin-film transistor unit, there are two first structural members 20 to prevent light from irradiating the active layer 12 of the thin-film transistor unit 10. This is beneficial to further reduce the amount of light irradiating the active layer 12 of the thin-film transistor unit 10, thereby further preventing the problem of device characteristic drift of the thin-film transistor unit 10 caused by continuous irradiation of the thin-film transistor unit 10 by high-brightness and high-temperature light.

[0061] It should also be added that, such as Figure 4 As shown, the number of first structural members 20 corresponding to each thin-film transistor unit 10 in the array substrate 100 can be different. For example, some thin-film transistor units 10 may be provided with one first structural member 20 on the first side edge 31, some thin-film transistor units 10 may be provided with one first structural member 20 on the second side edge 32, and some thin-film transistor units 10 may be provided with two first structural members 20 on the first side edge 31 and the second side edge 32. This application does not make specific limitations on this.

[0062] Furthermore, although this application only shows that one first structural member 20 is provided on one side edge of a thin film transistor unit 10, this application does not make specific limitations on this. Multiple first structural members 20 may also be provided on one side edge of the thin film transistor unit 10, as long as the provided first structural members 20 can block at least part of the light irradiated to the active layer 12 of the thin film transistor unit 10.

[0063] Please refer to Figure 1 , Figure 4 , Figure 6 and Figure 7 Optionally, it also includes: multiple data lines 130 extending along the second direction and arranged along the first direction, wherein the orthographic projection of the first structural member 20 on the substrate 01 does not overlap with the orthographic projection of the data lines 130 on the substrate 01.

[0064] Specifically, the array substrate 100 provided in this application also includes a plurality of data lines 130 extending along the second direction and arranged along the first direction, and a plurality of gate lines 110 extending along the first direction and arranged along the second direction. Each thin film transistor unit 10 is disposed in the area enclosed by the data lines 130 and the gate lines 110.

[0065] This application provides an alternative embodiment in which the orthographic projection of the first structural member 20 added on the array substrate 100 onto the substrate 01 does not overlap with the orthographic projection of the data line 130 onto the substrate 01, thereby avoiding the generation of overlapping capacitance between the first structural member 20 and the data line 130, avoiding the increase of load on the data line 130 during operation, and avoiding the problem of poor display effect in the display panel using the array substrate 100.

[0066] It should be noted that this application does not specifically limit the shape of the gate line 110, and the edge of the gate line 110 can be... Figure 1 The straight line shown can also be Figure 4 The serrated shape shown can also be wavy or other shapes, and this application does not make any specific limitation on this.

[0067] Please refer to Figures 1-7 Optionally, the first structural member 20 is made of a light-shielding material.

[0068] Specifically, the main purpose of adding the first structural member 20 to the array substrate 100 is to partially block the light emitted from the side of the substrate 01 away from the thin-film transistor unit 10 toward the active layer 12 of the thin-film transistor unit 10, thereby preventing the continuous irradiation of the thin-film transistor unit 10 by high-brightness and high-temperature light and avoiding the problem of device characteristic drift of the thin-film transistor unit 10. Therefore, this application can use a light-shielding material to fabricate the first structural member 20. The higher the light-shielding efficiency of the first structural member 20, the higher the amount of light blocked from irradiating to the active layer 12 of the thin-film transistor unit 10, and the better the guarantee effect on the working performance of the thin-film transistor unit 10.

[0069] Please continue to refer to Figures 1-7 Optionally, the first structural member 20 and the gate 11 are manufactured in the same process.

[0070] Specifically, when the thin-film transistor unit 10 is configured as a bottom-gate structure, the gate 11 is located on the side of the active layer 12 facing the substrate 01. In this case, the first structural member 20 and the gate 11 can be located in the same film layer structure and fabricated in the same process. This helps to avoid increasing the complexity of the fabrication process when adding the first structural member 20 to the array substrate 100. That is, the material of the first structural member 20 can be a light-shielding material or a metal material. It should also be noted that the first structural member 20 can be made of the same metal as the gate 11, or it can be made of a different metal; this application does not impose specific limitations on this.

[0071] It should be noted that when the first structural member 20 is disposed on the same layer as the gate 11, the first structural member 20 and the gate 11 can be electrically connected, or a first gap D can be provided between the first structural member 20 and the gate 11. This application does not make specific limitations on this, as long as the added first structural member 20 can reduce the amount of light irradiating the active layer 12 of the thin film transistor unit 10.

[0072] It should also be noted that when the added first structural member 20 is electrically connected to the gate 11, it can receive the same electrical signal as the gate 11; when the added first structural member 20 is not connected to the gate 11, it is possible to choose whether to apply an electrical signal to the first structural member 20 as needed, and this application does not make any specific limitations on this.

[0073] Figure 8 The image shown is provided in an embodiment of this application. Figure 1 Another cross-sectional diagram of BB' is shown. It should also be noted that... Figure 2 , Figure 3 , Figure 5 All shown are bottom-gate thin-film transistor units 10, and only one insulating film layer is included between the gate 11 and the active layer 12. Therefore, the first structural member 20 shown is disposed on the same layer as the gate 11; however, as Figure 8 As shown, if there is one or more insulating film layers between the substrate 01 and the gate 11, the first structural member 20 and the gate 11 can be disposed in different layers. In this case, the orthographic projection of the first structural member 20 onto the substrate 01 and the orthographic projection of the gate 11 onto the substrate 01 can be partially overlapped to ensure good light blocking by the first structural member 20. Alternatively, when there are multiple insulating film layers between the gate 11 and the active layer 12, the first structural member 20 can be located between the gate 11 and the active layer 12, so that the gate 11 and the first structural member 20 together block light from emanating into the active layer 12.

[0074] Please refer to Figures 1-8 Optionally, the active layer 12 is made of indium gallium zinc oxide.

[0075] Specifically, the thin-film transistor unit 10 provided in the array substrate 100 provided in this application can be an IGZO (indium gallium zinc oxide) transistor. In this case, the active layer 12 in the thin-film transistor unit 10 can be made of indium gallium zinc oxide.

[0076] It should also be noted that, generally, the orthographic projection of the active layer 12 in the thin-film transistor unit 10 onto the substrate 01 is located within the orthographic projection of the gate 11 onto the substrate 01. Therefore, when the first structural member 20 is constructed in this application, the first side edge 31 and the second side edge 32 of the orthographic projection of the gate 11 onto the substrate 01 are used as the starting point. If the orthographic projection of the gate 11 in the thin-film transistor unit 10 onto the substrate 01 is located within the orthographic projection of the active layer 12 onto the substrate 01, then the first structural member 20 can be constructed starting from at least a portion of the edges of the orthographic projection of the active layer 12 onto the substrate 01, thereby reducing the amount of light irradiated onto the active layer 12 of the thin-film transistor unit 10.

[0077] Please refer to Figure 1 , Figure 4 , Figure 6 and Figure 7 Optionally, the orthographic projection of the first structural member 20 onto the substrate 01 is rectangular, semi-circular, or polygonal.

[0078] Specifically, this application does not impose specific limitations on the shape of the first structural member 20 added to the array substrate 100. For example, the orthographic projection of the first structural member 20 onto the substrate 01 can be selected as a rectangle, a semicircle, a triangle, or other polygons.

[0079] It should be noted that, within the same area where the first structural member 20 can be set, this application preferably sets the orthographic projection of the first structural member 20 on the substrate 01 to be a rectangle, or a polygon that is nearly equal to the area where the first structural member 20 can be set, so that the setting area of ​​the first structural member 20 is as large as possible, so that the first structural member 20 can exert a better shielding effect on the high brightness and high temperature light irradiating the active layer 12 of the thin film transistor unit 10.

[0080] Figure 9 The image shown is a partial perspective view of a display module provided in an embodiment of this application. Please refer to the image for details. Figures 1-8 Reference Figure 9 Based on the same inventive concept, this application also provides a display module 200, including a display panel and a backlight module 40. The display panel includes an array substrate 100, which can be any type of array substrate 100 provided in this application. The backlight module 40 is located on the side of the substrate 01 away from the gate 11. Specifically, the light-emitting surface of the backlight module 40 faces the array substrate 100 and is used to provide illumination for the display panel, serving as a light source for the display panel during the display process.

[0081] Figure 10 The image shown is provided in an embodiment of this application. Figure 9 A cross-sectional schematic diagram of EE', please refer to... Figures 1-8 ReferenceFigure 9 and Figure 10 Optionally, the array substrate 100 includes a first structural member 20, and a first surface 21 of the first structural member 20 near the backlight module 40 is used to reflect the light emitted by the backlight module 40.

[0082] Specifically, the first structural member 20 added to the array substrate 100 in this application is mainly used to prevent the light emitted from the backlight module 40 from irradiating the active layer 12 in the thin film transistor unit 10. Specifically, the first surface 21 of the first structural member 20 on the side close to the backlight module 40 reflects the light emitted from the backlight module 40 back to the backlight module 40, thereby reducing the amount of light irradiating the active layer 12 in the thin film transistor unit 10, avoiding excessive high-brightness and high-temperature light from continuously irradiating the active layer 12 of the thin film transistor unit 10, thereby avoiding the problem of device characteristic drift in the thin film transistor unit 10, which is conducive to improving the working performance of the array substrate 100 and increasing the working life of the array substrate 100.

[0083] As can be seen from the above embodiments, the array substrate and display module provided by the present invention achieve at least the following beneficial effects:

[0084] This application provides an array substrate and a display module. The array substrate includes a plurality of thin-film transistor units disposed on a first side of a substrate, and a plurality of first structural members disposed on the first side of the substrate. By setting the first structural members, the illumination emitted by the backlight in the display module is at least partially blocked, thereby avoiding the problem of component characteristic drift of the thin-film transistor units under high brightness and high temperature. Furthermore, the orthographic projection of the first structural member on the substrate and the orthographic projection of the drain on the substrate do not overlap, thereby avoiding the generation of overlapping capacitance between the first structural member and the drain, thereby avoiding the increase of load on the drain during operation, and thus avoiding the problem of poor display effect of the display panel using the array substrate.

[0085] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate substrate, a plurality of array-arranged thin film transistor units, each of the thin film transistor units comprising a gate electrode, an active layer, a source electrode and a drain electrode arranged on a first side of the substrate substrate; a plurality of first structural members arranged on the first side of the substrate substrate, the first structural members being arranged in the same layer as the gate electrode; a projection of the first structural member on the substrate substrate does not overlap with a projection of the source electrode on the substrate substrate, and a projection of the first structural member on the substrate substrate does not overlap with a projection of the drain electrode on the substrate substrate; a projection of the first structural member on the substrate substrate starts from at least one side edge of a projection of the gate electrode on the substrate substrate extending in a first direction, and extends in a second direction; wherein the first direction is a row direction of the arrangement of the thin film transistor units, and the second direction is a column direction of the arrangement of the thin film transistor units.

2. The array substrate of claim 1, wherein, The first edge of the gate electrode in the projection on the substrate substrate is close to the first edge of the first structural member in the projection on the substrate substrate, and a first spacing is included between the second edge of the gate electrode in the projection on the substrate substrate close to the first structural member.

3. The array substrate of claim 1, wherein, In the second direction, the gate electrode comprises oppositely arranged first and second side edges, and at least part of the projection of the first structural member on the substrate substrate starts from the first side edge of the gate electrode.

4. The array substrate of claim 1, wherein, In the second direction, the gate electrode comprises oppositely arranged first and second side edges, and at least part of the projection of the first structural member on the substrate substrate starts from the second side edge of the gate electrode.

5. The array substrate of claim 1, wherein, In the second direction, the gate electrode comprises oppositely arranged first and second side edges, and a plurality of the first structural members in the projection on the substrate substrate start from the first side edge of the gate electrode and simultaneously start from the second side edge of the gate electrode.

6. The array substrate of claim 1, wherein, Further comprising: a plurality of data lines extending in the second direction and arranged in the first direction, and a projection of the first structural member on the substrate substrate does not overlap with a projection of the data line on the substrate substrate.

7. The array substrate of claim 1, wherein, The first structural member is made of light-shielding material.

8. The array substrate of claim 1, wherein, The first structural member and the gate electrode are made in the same process.

9. The array substrate of claim 1, wherein, The active layer is made of indium gallium zinc oxide.

10. The array substrate of claim 1, wherein, The projection of the first structural member on the substrate substrate is rectangular, semicircular or polygonal.

11. A display module, characterized by The display panel comprises an array substrate as claimed in any one of claims 1-10. The backlight module is located on the side of the substrate substrate away from the gate electrode.

12. The display module of claim 11, wherein, The array substrate comprises a first structural member close to the first surface of the side of the backlight module for reflecting light emitted by the backlight module.

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