A variable-gain amplifier

Abstract

The present invention discloses a variable-gain amplifier, comprising: a bandgap reference which generates a reference current and a reference voltage and outputs them to a variable bias voltage circuit; the variable bias voltage circuit which, under the control of an n-bit gain control signal, converts the reference current and the reference voltage into a first variable bias voltage required by a current-voltage bias circuit; the current-voltage bias circuit which converts the first variable bias voltage into an output-stage variable bias voltage required by an output stage and converts it into a variable bias current required by an input-stage bias mirror module; the input-stage bias mirror module which generates a second variable bias voltage under the control of the variable bias current and outputs it to the input stage; the input stage which preliminarily amplifies a radio frequency signal under the control of the second variable bias voltage; the output stage which, under the control of the output-stage variable bias voltage, amplifies the radio frequency signal amplified by the input stage to obtain a radio frequency output signal; and a low-dropout voltage regulator circuit which generates a stable voltage to supply the input stage and the output stage.

Description

Technical Field

[0001] The present invention relates to an amplifier, and particularly to an amplifier with variable gain. Background Art

[0002] As a key module for signal reception, the high gain of an amplifier system determines the sensitivity to the minimum received signal, and the low gain affects the maximum received signal and linearity. Therefore, the programmable design of gain and power consumption is crucial for the sensitivity and dynamic range of the reception system. Therefore, the programmable optimization design of the amplifier can improve the system dynamic range, simplify the system design, and reduce the system cost. At the same time, the programmable design of gain can optimize the gain-power consumption energy efficiency ratio, reduce the system power consumption, and extend the battery life.

[0003] As Figure 1 shown, the traditional radio frequency amplifier is composed of a band-gap reference (BGR) 10, a bias mirror module 20, an input stage 30, an output stage 40, and a bias circuit 50. Among them, the band-gap reference is used to generate a reference current Iref and output it to the bias mirror module 20; the bias mirror module 20 is composed of an input bias NMOS transistor N inb and a first gate isolation resistor Rg, and is used to generate a stable bias voltage Vg Nin under the control of the reference current Iref and output it to the gate of the input stage 30; the input stage 30 is an inductive-degenerated common-source structure, which is composed of an input matching inductor L g , an input matching capacitor C g , an input NMOS amplification transistor N in and an emitter negative feedback inductor L s , and is used to complete the preliminary amplification of the radio frequency signal RF in ; the output stage 40 is a common-gate structure, which is composed of an output load inductor L d , an output coupling capacitor C o , an output NMOS amplification transistor M o , a gate decoupling capacitor C b and a second gate isolation resistor Rb, and is used to further amplify the radio frequency signal RF in amplified by the input stage 30 to obtain a radio frequency output signal RF out ; the bias circuit 50 is used to provide the required bias voltage Vg Mo for the output stage 40.

[0004] However, as Figure 1 can be seen, the traditional radio frequency amplifier adopts a fixed bias current and voltage circuit, with fixed power consumption and fixed gain, does not have variable gain, and the power consumption energy efficiency ratio is not adjustable. Summary of the Invention

[0005] To overcome the deficiencies of the above-mentioned existing technologies, the object of the present invention is to provide a variable-gain amplifier, which realizes the optimized and efficient gain-power efficiency ratio under the programmable bias of the input and output stages of the amplifier, programmable gain adjustment control, and digital programming control of power consumption.

[0006] To achieve the above and other objects, the present invention proposes a variable-gain amplifier, comprising:

[0007] A bandgap reference for generating a reference current (Iref) and a reference voltage (Vref) and outputting them to a variable bias voltage circuit;

[0008] A variable bias voltage circuit for converting the reference current (Iref) and the reference voltage (Vref) into a first variable bias voltage (Vpc) required by a current-voltage bias circuit under the control of an n-bit gain control signal (CT[1:n]);

[0009] A current-voltage bias circuit for converting the first variable bias voltage (Vpc) output by the variable bias voltage circuit into an output-stage variable bias voltage (Vpcb) required by the output stage, and at the same time converting the first variable bias voltage (Vpc) into a variable bias current (Ipcb) required by an input-stage bias mirror module;

[0010] An input-stage bias mirror module for generating a second variable bias voltage (Vg Nin ) and outputting it to the input stage under the control of the variable bias current (Ipcb) output by the current-voltage bias circuit;

[0011] An input stage for completing the preliminary amplification of a radio frequency signal (RF Nin ) under the control of the second variable bias voltage (Vg in );

[0012] An output stage for further amplifying the radio frequency signal (RF in ) amplified by the input stage to obtain a radio frequency output signal (RF out ) under the control of the output-stage variable bias voltage (Vpcb);

[0013] A low-dropout regulator for generating a stable voltage (Va) to supply the input stage and the output stage to obtain a more stable gain control effect.

[0014] Preferably, the variable bias voltage circuit makes the first variable bias voltage (Vpc) variable by digitally controlling and adjusting the resistance feedback ratio of the n-bit digital control signal (CT[1:n]).

[0015] Preferably, the variable bias voltage circuit includes an error amplifier (Amp1), a third variable voltage dividing resistor (R3), a fourth variable voltage dividing resistor (R4), and a fifth NMOS bias transistor (MN5). The output reference current (Iref) of the bandgap reference is connected to the control input terminal of the error amplifier (Amp1), the reference voltage (Vref) is connected to the inverting input terminal of the error amplifier (Amp1), and the output of the error amplifier (Amp1), the first variable bias voltage (Vpc), is connected to one end of the third variable voltage dividing resistor (R3) and the current-voltage bias circuit. The other end of the third variable voltage dividing resistor (R3) is connected to one end of the fourth variable voltage dividing resistor (R4) to form a voltage dividing output node connected to the non-inverting input terminal of the error amplifier (Amp1). The other end of the fourth variable voltage dividing resistor (R4) is connected to the drain and gate of the fifth NMOS bias transistor (MN5). The source and substrate of the fifth NMOS bias transistor (MN5) are grounded, and the n-bit gain control signal (CT[1:n]) is connected to the control terminals of the third variable voltage dividing resistor (R3) and the fourth variable voltage dividing resistor (R4).

[0016] Preferably, the error amplifier (Amp1) includes a first NMOS bias transistor (MN1), a second NMOS bias transistor (MN2), a third NMOS amplification transistor (MN3), a fourth NMOS amplification transistor (MN4), a first PMOS bias transistor (MP1), a second PMOS bias transistor (MP2), and a third PMOS amplification output transistor (MP3). The gate of the third NMOS amplification transistor (MN3) is the inverting input terminal of the error amplifier (Amp1), the gate of the fourth NMOS amplification transistor (MN4) is the non-inverting input terminal of the error amplifier (Amp1), the drain and gate of the first NMOS bias transistor (MN1) are the control input terminal of the error amplifier (Amp1), and the drain of the third PMOS amplification output transistor (MP3) is the output terminal of the error amplifier (Amp1), that is, the first variable bias voltage (Vpc) is output; the output reference current (Iref) of the bandgap reference is connected to the drain and gate of the first NMOS bias transistor (MN1) and the gate of the second NMOS bias transistor (MN2), the reference voltage (Vref) is connected to the gate of the third NMOS amplification transistor (MN3), the drain of the second NMOS bias transistor (MN2) is connected to the source and substrate of the third NMOS amplification transistor (MN3) and the source and substrate of the fourth NMOS amplification transistor (MN4), the drain of the third NMOS amplification transistor (MN3) is connected to the drain of the first PMOS bias transistor (MP1) and connected to the gate of the third PMOS amplification output transistor (MP3), the drain of the fourth NMOS amplification transistor (MN4) is connected to the drain and gate of the second PMOS bias transistor (MP2) and the gate of the first PMOS bias transistor (MP1), the drain of the third PMOS amplification output transistor (MP3) is connected to one end of the third variable voltage dividing resistor (R3) to form the first variable bias voltage node (Vpc), the other end of the third variable voltage dividing resistor (R3) is connected to one end of the fourth variable voltage dividing resistor (R4) and connected to the gate of the fourth NMOS amplification transistor (MN4); the source and substrate of the first NMOS bias transistor (MN1), the source and substrate of the second NMOS bias transistor (MN2) are grounded, and the source and substrate of the first PMOS bias transistor (MP1), the source and substrate of the second PMOS bias transistor (MP2), and the source and substrate of the third PMOS amplification output transistor (MP3) are connected to the input power supply (Vdd).

[0017] Preferably, the current-voltage bias circuit includes a fourth PMOS bias transistor (MP4), a fifth PMOS bias transistor (MP5), a first voltage-dividing resistor (R1), and a second voltage-dividing resistor (R2). The gates of the fourth PMOS bias transistor (MP4) and the fifth PMOS bias transistor (MP5) are connected to the output of the error amplifier (Amp1). The drain of the fourth PMOS bias transistor (MP4), i.e., the variable bias current node (Ipcb), is connected to the input-stage bias mirror module. The drain of the fifth PMOS bias transistor (MP5) is connected to one end of the first voltage-dividing resistor (R1). The other end of the first voltage-dividing resistor (R1) is connected to one end of the second voltage-dividing resistor (R2) to form an output-stage variable bias voltage node (Vpcb). The output-stage variable bias voltage node (Vpcb) is connected to the output stage, and the other end of the second voltage-dividing resistor (R2) is grounded.

[0018] Preferably, the input-stage bias mirror module includes a third NMOS bias transistor (N inb ) and a first gate isolation resistor (Rg). The variable bias current node (Ipcb) is connected to the drain and gate of the third NMOS bias transistor (N inb ) and one end of the first isolation resistor (Rg). The source of the third NMOS bias transistor (N inb ) is grounded, and the other end of the first isolation resistor (Rg) is connected to the input stage.

[0019] Preferably, the input stage adopts an inductive negative feedback common-source structure.

[0020] Preferably, the input stage includes an input matching inductor (L g ), an input matching capacitor (C g ), an input NMOS amplifying transistor (N in ), and an emitter negative feedback inductor (L s ). The source of the input NMOS amplifying transistor (N in ) and one end of the input matching capacitor (C g ) are connected to the first isolation resistor (Rg). The other end of the input matching capacitor (C g ) is connected to the input radio frequency signal (RF g ) through the input matching inductor (L in ). The source of the input NMOS amplifying transistor (N in ) is grounded through the emitter negative feedback inductor (L s ). The drain of the input NMOS amplifying transistor (N in ) is connected to the output stage.

[0021] Preferably, the output stage adopts a common-gate structure.

[0022] Preferably, the output stage includes an output load inductor (L d ), an output coupling capacitor (C o ), an output NMOS amplifier transistor (M o ), a gate decoupling capacitor (C b ), and a second gate isolation resistor (Rb). The source and substrate of the output NMOS amplifier transistor (M o ) are connected to the drain of the input NMOS amplifier transistor (N in ). One end of the second gate isolation resistor (Rb) is connected to the output stage variable bias voltage node (Vpcb), and the other end is connected to the gate of the output NMOS amplifier transistor (M o ) and one end of the gate decoupling capacitor (C b ). The drain of the output NMOS amplifier transistor (M o ) is connected to one end of the output load inductor (L d ) and one end of the output coupling capacitor (C o ). The other end of the output coupling capacitor (C o ) is the RF output signal (RF out ).

[0023] Compared with the prior art, a variable-gain amplifier according to the present invention uses a reference voltage Vref and a current Iref through its variable bias voltage circuit, and is digitally controlled and adjusted by an input digital control signal CT[1:n] to achieve a variable bias voltage Vpc. The current-voltage bias circuit uses the variable bias voltage Vpc to generate an amplifier input stage bias mirror current Ipcb and an output stage variable bias voltage Vpcb, thereby realizing the variable adjustment of the amplifier input and output stage biases, the variable adjustment control of the gain, and the optimized and efficient gain-power energy efficiency ratio under digital variable control of the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit structure diagram of a conventional RF amplifier;

[0025] Figure 2 is a circuit structure diagram of a variable-gain amplifier according to the present invention;

[0026] Figure 3 is a circuit structure diagram of a variable-gain amplifier (n-bit) in a specific embodiment of the present invention;

[0027] Figure 4 is a detailed structure diagram of an error amplifier Amp1 in a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The embodiments of the present invention will be described below through specific examples in conjunction with the accompanying drawings. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] Figure 2 This is the circuit structure diagram of a gain variable amplifier of the present invention. As Figure 2 shown, a gain variable amplifier of the present invention realizes the power consumption control of an n - bits variable gain amplifier, and includes a band - gap reference (BGR) 10, a variable bias voltage circuit 20, a current - voltage bias circuit 30, a bias mirror module 40, an input stage 50, an output stage 60, and a low - dropout regulator (LDO) 70.

[0030] Among them, the band - gap reference (BGR, Band - Gap Reference) 10 is used to generate a reference current Iref and a reference voltage Vref and output them to the variable bias voltage circuit 20. Specifically, the reference current Iref is used to provide bias for the error amplifier, and the reference voltage Vref is used to provide a reference for error amplification comparison; the variable bias voltage circuit 20 is composed of an error amplifier Amp1, a third variable voltage - dividing resistor R3, a fourth variable voltage - dividing resistor R4, and a fifth NMOS bias transistor MN5, and is used to convert the reference current Iref and the reference voltage Vref into a variable bias voltage Vpc required by the current - voltage bias circuit 30 under the control of the gain control signal CT[1:n]. In a specific embodiment of the present invention, the variable bias voltage circuit 20 uses the reference voltage Vref and the current Iref, and realizes the variability of the bias voltage Vpc through digital control adjustment by the input digital control signal CT[1:n]. The digital control signal CT[1:n] realizes the variability of the bias voltage Vpc by digitally controlling and adjusting the variable resistor feedback ratio; the current - voltage bias circuit 30 is composed of a fourth PMOS bias transistor MP4, a fifth PMOS bias transistor MP5, a first voltage - dividing resistor R1, and a second voltage - dividing resistor R2, and is used to convert the variable bias voltage Vpc output by the variable bias voltage circuit 20 into an output - stage variable bias voltage Vpcb required by the output stage 60, and at the same time convert the variable bias voltage Vpc into a variable bias current Ipc required by the input - stage bias mirror module 40; the input - stage bias mirror module 40 is composed of an input - bias NMOS transistor N inb and a first gate isolation resistor Rg, and is used to generate a variable bias voltage Vg under the control of the variable current Ipcb output by the current - voltage bias circuit 30 Ninand output it to the gate of the input stage 50; the input stage 50 is an inductive-degenerated common-source structure, consisting of an input matching inductor L g , an input matching capacitor C g , an input NMOS amplifier transistor N in and an emitter-degenerated inductor L s to complete the preliminary amplification of the radio frequency signal RF in ; the output stage 60 is a common-gate structure, consisting of an output load inductor L d , an output coupling capacitor C o , an output NMOS amplifier transistor M o , a gate decoupling capacitor C b and a second gate isolation resistor Rb, to further amplify the radio frequency signal RF in amplified by the input stage 50 under the control of the variable bias voltage Vpcb of the output stage to obtain a radio frequency output signal RF out ; the low dropout regulator (LDO) 70 is used to generate a stable voltage Va to supply the radio frequency input stage 50 and the radio frequency output stage 60 to obtain a more stable gain control effect.

[0031] Figure 3 is the circuit structure diagram of the variable gain amplifier (n-bit) in the specific embodiment of the present invention. In the specific embodiment of the present invention, the digital control signal CT[1:n] realizes the variable bias voltage Vpc by digitally controlling and adjusting the variable resistor feedback ratio. Specifically, the variable bias voltage circuit 20 includes an error amplifier Amp1, a third variable voltage dividing resistor R3, a fourth variable voltage dividing resistor R4, and a fifth NMOS bias transistor MN5, which are used to convert the reference current Iref and the reference voltage Vref into the variable bias voltage Vpc required by the current-voltage bias circuit 30 under the control of the gain control signal CT[1:n]. The variable bias voltage Vpc is generated by the output variable resistor string of the error amplifier and the self-biased NMOS adjustment load. Specifically, the output reference current Iref of the bandgap reference (BGR) 10 is connected to the control input terminal of the error amplifier Amp1, the reference voltage Vref is connected to the inverting input terminal of the error amplifier Amp1, and the output of the error amplifier Amp1, that is, the variable bias voltage Vpc, is connected to one end of the third variable voltage dividing resistor R3, the gate of the fourth PMOS bias transistor MP4, and the gate of the fifth PMOS bias transistor MP5. The other end of the third variable voltage dividing resistor R3 is connected to one end of the fourth variable voltage dividing resistor R4 to form a voltage dividing output node and is connected to the non-inverting input terminal of the error amplifier Amp1. The other end of the fourth variable voltage dividing resistor R4 is connected to the drain and gate of the fifth NMOS bias transistor MN5. The source and substrate of the fifth NMOS bias transistor MN5 are grounded, and the gain control signal CT[1:n] is connected to the control terminals of the third variable voltage dividing resistor R3 and the fourth variable voltage dividing resistor R4;

[0032] The drain of the fourth PMOS bias transistor MP4, i.e., the variable bias current Ipc node, is connected to the drain and gate of the input bias NMOS transistor Ninb and one end of the first isolation resistor Rg, and the source of the input bias NMOS transistor Ninb is grounded; inb The drain of the fourth PMOS bias transistor MP4, i.e., the variable bias current Ipc node, is connected to the drain and gate of the input bias NMOS transistor Ninb and one end of the first isolation resistor Rg, and the source of the input bias NMOS transistor Ninb is grounded;

[0033] The drain of the fifth PMOS bias transistor MP5 is connected to one end of the first voltage dividing resistor R1, the other end of the first voltage dividing resistor R1 and one end of the second voltage dividing resistor R2 form the output stage variable bias voltage Vpcb node, and this output stage variable bias voltage Vpcb node is connected to one end of the second isolation resistor Rb, and the other end of the second voltage dividing resistor R2 is grounded;

[0034] The other end of the first isolation resistor Rg is connected to the gate of the input NMOS amplifier transistor N in and one end of the input matching capacitor C g The other end of the input matching capacitor C g is connected to the input radio frequency signal RF g through the input matching inductor L in , and the source of the NMOS amplifier transistor N in is grounded through the emitter negative feedback inductor L s , and the drain of the NMOS amplifier transistor N in is connected to the source and substrate of the output NMOS amplifier transistor M o ;

[0035] The other end of the second isolation resistor Rb is connected to the gate of the output NMOS amplifier transistor M o and one end of the gate decoupling capacitor C b , the drain of the output NMOS amplifier transistor M o is connected to one end of the output load inductor L d and one end of the output coupling capacitor C o , and the other end of the output coupling capacitor C o is the radio frequency output signal RF out .

[0036] The input power supply Vdd is connected to the power supply terminal of the bandgap reference (BGR) 10, the power supply terminal of the error amplifier Amp1, the source and substrate of the fourth PMOS bias transistor MP4, the source and substrate of the fifth PMOS bias transistor MP5, and the input terminal of the low dropout regulator (LDO) 70. The other end of the gate decoupling capacitor C b and the other end of the output load inductor L d are connected to the output terminal of the low dropout regulator (LDO) 70, i.e., the power supply Va.

[0037] Figure 4This is the detailed structural diagram of the error amplifier Amp1 in a specific embodiment of the present invention. As Figure 4 shown, the error amplifier Amp1 is composed of a first NMOS bias transistor MN1, a second NMOS bias transistor MN2, a third NMOS amplification transistor MN3, a fourth NMOS amplification transistor MN4, a first PMOS bias transistor MP1, a second PMOS bias transistor MP2, and a third PMOS amplification output transistor MP3. The gate of the third NMOS amplification transistor MN3 is the inverting input terminal of the error amplifier Amp1, and the gate of the fourth NMOS amplification transistor MN4 is the non-inverting input terminal of the error amplifier Amp1. The drain and gate of the first NMOS bias transistor MN1 are the control input terminals of the error amplifier Amp1. The drain of the third PMOS amplification output transistor MP3 is the output terminal of the error amplifier Amp1, namely the variable bias voltage Vpc. The output reference current Iref of the bandgap reference (BGR) 10 is connected to the drain and gate of the first NMOS bias transistor MN1 and the gate of the second NMOS bias transistor MN2. The reference voltage Vref is connected to the gate of the third NMOS amplification transistor MN3. The drain of the second NMOS bias transistor MN2 is connected to the source and substrate of the third NMOS amplification transistor MN3 and the source and substrate of the fourth NMOS amplification transistor MN4. The drain of the third NMOS amplification transistor MN3 is connected to the drain of the first PMOS bias transistor MP1 and is connected to the gate of the third PMOS amplification output transistor MP3. The drain of the fourth NMOS amplification transistor MN4 is connected to the drain and gate of the second PMOS bias transistor MP2 and the gate of the first PMOS bias transistor MP1. The drain of the third PMOS amplification output transistor MP3 is connected to one end of the third variable voltage dividing resistor R3 to form a variable bias voltage Vpc node. The other end of the third variable voltage dividing resistor R3 is connected to one end of the fourth variable voltage dividing resistor R4 and is connected to the gate of the fourth NMOS amplification transistor MN4. The source and substrate of the first NMOS bias transistor MN1 and the source and substrate of the second NMOS bias transistor MN2 are grounded. The source and substrate of the first PMOS bias transistor MP1, the source and substrate of the second PMOS bias transistor MP2, and the source and substrate of the third PMOS amplification output transistor MP3 are connected to the input power supply Vdd.

[0038] It can be seen that the present invention utilizes the reference voltage Vref and the current Iref through its variable bias voltage circuit, and realizes the variable bias voltage Vpc through digital control and adjustment by the input digital control signal CT[1:n]. And through the current-voltage bias circuit, the variable bias voltage Vpc is used to generate the bias mirror current Ipcb of the amplifier input stage and the variable bias voltage Vpcb of the output stage, thereby realizing the variable adjustment of the amplifier input and output stage biases, the variable adjustment control of the gain, and the optimized and efficient gain-power energy efficiency ratio under the digital variable control of the power consumption.

[0039] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the present invention shall be as set forth in the claims.

Claims

1. A variable gain amplifier, comprising: A bandgap reference for generating a reference current (Iref) and a reference voltage (Vref) and outputting them to a variable bias voltage circuit; A variable bias voltage circuit for converting the reference current (Iref) and the reference voltage (Vref) into a first variable bias voltage (Vpc) required by a current-voltage bias circuit under the control of an n-bit gain control signal (CT[1:n]); A current-voltage bias circuit for converting the first variable bias voltage (Vpc) output by the variable bias voltage circuit into an output-stage variable bias voltage (Vpcb) required by an output stage, and at the same time converting the first variable bias voltage (Vpc) into a variable bias current (Ipcb) required by an input-stage bias mirror module; Input stage bias mirror module, which is used to generate a second variable bias voltage (Vg Nin ) under the control of the variable bias current (Ipcb) output by the current-voltage bias circuit and output it to the input stage; An input stage for performing preliminary amplification of a radio frequency signal (RF Nin ) under the control of the second variable bias voltage (Vg in ); An output stage, configured to further amplify the radio frequency signal (RF in ) amplified by the input stage to obtain a radio frequency output signal (RF out ) under the control of a variable bias voltage (Vpcb) at the output stage; A low-dropout regulator circuit for generating a stable voltage (Va) to supply the input stage and the output stage to obtain a more stable gain control effect.

2. The gain variable amplifier according to claim 1, wherein The variable bias voltage circuit makes the first variable bias voltage (Vpc) variable by digitally controlling and adjusting the resistance feedback ratio through an n-bit digital control signal (CT[1:n]).

3. A gain variable amplifier according to claim 2, characterized in that, The variable bias voltage circuit includes an error amplifier (Amp1), a third variable voltage-dividing resistor (R3), a fourth variable voltage-dividing resistor (R4), and a fifth NMOS bias transistor (MN5). The output reference current (Iref) of the bandgap reference is connected to the control input terminal of the error amplifier (Amp1), the reference voltage (Vref) is connected to the inverting input terminal of the error amplifier (Amp1), the output terminal of the error amplifier (Amp1) outputs the first variable bias voltage (Vpc) and is connected to one end of the third variable voltage-dividing resistor (R3) and the current-voltage bias circuit. The other end of the third variable voltage-dividing resistor (R3) is connected to one end of the fourth variable voltage-dividing resistor (R4) to form a voltage-dividing output node connected to the non-inverting input terminal of the error amplifier (Amp1). The other end of the fourth variable voltage-dividing resistor (R4) is connected to the drain and gate of the fifth NMOS bias transistor (MN5). The source and substrate of the fifth NMOS bias transistor (MN5) are grounded, and the n-bit gain control signal (CT[1:n]) is connected to the control terminals of the third variable voltage-dividing resistor (R3) and the fourth variable voltage-dividing resistor (R4).

4. The gain variable amplifier according to claim 3, wherein: The error amplifier (Amp1) includes a first NMOS bias transistor (MN1), a second NMOS bias transistor (MN2), a third NMOS amplification transistor (MN3), a fourth NMOS amplification transistor (MN4), a first PMOS bias transistor (MP1), a second PMOS bias transistor (MP2), and a third PMOS amplification output transistor (MP3). The gate of the third NMOS amplification transistor (MN3) is the inverting input terminal of the error amplifier (Amp1), the gate of the fourth NMOS amplification transistor (MN4) is the non-inverting input terminal of the error amplifier (Amp1), the drain and gate of the first NMOS bias transistor (MN1) are the control input terminal of the error amplifier (Amp1), and the drain of the third PMOS amplification output transistor (MP3) is the output terminal of the error amplifier (Amp1) for outputting the first variable bias voltage (Vpc). The output reference current (Iref) of the bandgap reference is connected to the drain and gate of the first NMOS bias transistor (MN1) and the gate of the second NMOS bias transistor (MN2), the reference voltage (Vref) is connected to the gate of the third NMOS amplification transistor (MN3), the drain of the second NMOS bias transistor (MN2) is connected to the source and substrate of the third NMOS amplification transistor (MN3) and the source and substrate of the fourth NMOS amplification transistor (MN4), the drain of the third NMOS amplification transistor (MN3) is connected to the drain of the first PMOS bias transistor (MP1) and is connected to the gate of the third PMOS amplification output transistor (MP3), the drain of the fourth NMOS amplification transistor (MN4) is connected to the drain and gate of the second PMOS bias transistor (MP2) and the gate of the first PMOS bias transistor (MP1), the drain of the third PMOS amplification output transistor (MP3) is connected to one end of a third variable voltage-dividing resistor (R3) to form a first variable bias voltage node (Vpc), the other end of the third variable voltage-dividing resistor (R3) is connected to one end of a fourth variable voltage-dividing resistor (R4) and is connected to the gate of the fourth NMOS amplification transistor (MN4). The source and substrate of the first NMOS bias transistor (MN1) and the source and substrate of the second NMOS bias transistor (MN2) are grounded, and the source and substrate of the first PMOS bias transistor (MP1), the source and substrate of the second PMOS bias transistor (MP2), and the source and substrate of the third PMOS amplification output transistor (MP3) are connected to the input power supply (Vdd).

5. The gain variable amplifier according to claim 4, wherein: The current-voltage bias circuit includes a fourth PMOS bias transistor (MP4), a fifth PMOS bias transistor (MP5), a first voltage-dividing resistor (R1), and a second voltage-dividing resistor (R2). The gates of the fourth PMOS bias transistor (MP4) and the fifth PMOS bias transistor (MP5) are connected to the output of the error amplifier (Amp1). The drain of the fourth PMOS bias transistor (MP4), i.e., the variable bias current node (Ipcb), is connected to the input-stage bias mirror module. The drain of the fifth PMOS bias transistor (MP5) is connected to one end of the first voltage-dividing resistor (R1). The other end of the first voltage-dividing resistor (R1) is connected to one end of the second voltage-dividing resistor (R2) to form an output-stage variable bias voltage node (Vpcb). The output-stage variable bias voltage node (Vpcb) is connected to the output stage, and the other end of the second voltage-dividing resistor (R2) is grounded.

6. The gain variable amplifier according to claim 5, characterized in that: The input stage bias mirror module includes a third NMOS bias transistor (N inb ), and a first gate isolation resistor (Rg). The variable bias current node (Ipcb) is connected to the drain and gate of the third NMOS bias transistor (N inb ), and one end of the first isolation resistor (Rg). The source of the third NMOS bias transistor (N inb ) is grounded, and the other end of the first isolation resistor (Rg) is connected to the input stage.

7. The gain variable amplifier according to claim 6, wherein: The input stage adopts an inductor negative feedback common-source structure.

8. The gain variable amplifier according to claim 7, characterized in that: The input stage includes an input matching inductor (L g ), an input matching capacitor (C g ), an input NMOS amplifier transistor (N in ), and an emitter negative feedback inductor (L s ). The source of the input NMOS amplifier transistor (N in ) and one end of the input matching capacitor (C g ) are connected to a first isolation resistor (Rg). The other end of the input matching capacitor (C g ) is connected to an input radio frequency signal (RF g ) through the input matching inductor (L in ). The source of the input NMOS amplifier transistor (N in ) is grounded through the emitter negative feedback inductor (L s ). The drain of the input NMOS amplifier transistor (N in ) is connected to the output stage.

9. The gain variable amplifier according to claim 8, wherein: The output stage adopts a common-gate structure.

10. A gain variable amplifier according to claim 9, characterized in that: The output stage includes an output load inductor (L d ), an output coupling capacitor (C o ), an output NMOS amplifier transistor (M o ), a gate decoupling capacitor (C b ), and a second gate isolation resistor (Rb). The source and substrate of the output NMOS amplifier transistor (M o ) are connected to the drain of the input NMOS amplifier transistor (N in ). One end of the second gate isolation resistor (Rb) is connected to the output stage variable bias voltage node (Vpcb), and the other end is connected to the gate of the output NMOS amplifier transistor (M o ) and one end of the gate decoupling capacitor (C b ). The drain of the output NMOS amplifier transistor (M o ) is connected to one end of the output load inductor (L d ) and one end of the output coupling capacitor (C o ). The other end of the output load inductor (L d ) and the other end of the gate decoupling capacitor (C b ) are both connected to the low dropout regulator circuit. The other end of the output coupling capacitor (C o ) is the radio frequency output signal (RF out ).

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