Data and power isolation barrier

Abstract

A semiconductor package includes a transformer (T1) having a primary winding (L1) and a secondary winding (L2). The primary winding (L1) has first and second terminals and a pair of taps. The secondary winding (L2) has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits (110, 140), a bridge (120), and a rectifier (130). The first data transfer circuit (110) is coupled to the pair of taps of the primary winding (L1). The second data transfer circuit (140) is coupled to the pair of taps of the secondary winding (L2). The bridge (120) is coupled to the first and second terminals of the primary winding (L1). The rectifier (130) is coupled to the first and second terminals of the secondary winding (L2).

Description

BACKGROUND

[0001] Some circuits benefit from isolation of the power and data nodes of the circuit from other circuits and power nodes. For example, sensitive circuits in power tools or other types of high voltage machines benefit from isolation of such circuits from AC (alternating current) power lines. SUMMARY

[0002] In one example, a semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

[0003] In yet another example, an apparatus includes a transformer, first and second data transfer circuits, a transformer driver, and a rectifier. The transformer has a primary and a secondary winding. The primary winding has first and second terminals and a center tap. The secondary winding has first and second terminals and a center tap. The center tap of the primary winding is coupled to a supply voltage node. The center tap of the secondary winding provides an isolated ground. The first data transfer circuit is coupled to the first and second terminals of the primary winding. The second data transfer circuit is coupled to the first and second terminals of the secondary winding. The transformer driver is coupled to the first and second terminals of the primary winding. The rectifier has first and second rectifier inputs and a rectifier output. The first rectifier input is coupled to the first terminal of the secondary winding. The second rectifier input is coupled to the second terminal of the secondary winding.

[0004] In yet another example, a circuit includes a modulator, an oscillator, a transmitter, a transformer driver, and first and second capacitors. The modulator has an input and an output. The oscillator is coupled to the input of the modulator. The transmitter has an input and first and second outputs. The input of the transmitter is coupled to the output of the modulator. The transformer driver has first and second terminals configured to be coupled to terminals of a transformer. The first capacitor is coupled between the first output of the transmitter and the first terminal of the transformer driver. The second capacitor is coupled between the second output of the transmitter and the second terminal of the transformer driver.

[0005] In another example, a circuit includes a modulator, an oscillator, a transmitter, a transformer driver, first and second capacitors, and a rectifier. The modulator has an input and an output. The oscillator is coupled to the input of the modulator. The transmitter has an input and first and second outputs. The input of the transmitter is coupled to the output of the modulator. The first capacitor has first and second terminals, where the first terminal of the first capacitor is coupled to the first output of the transmitter and the second terminal of the first capacitor is configured to be coupled to a first terminal of a transformer. The second capacitor has first and second terminals, where the first terminal of the second capacitor is coupled to the second output of the transmitter and the second terminal of the second capacitor is configured to be coupled to a second terminal of the transformer. The rectifier has first and second rectifier inputs and an output. The first rectifier input is coupled to the second terminal of the first capacitor and the second rectifier input is coupled to the second terminal of the second capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0007] Figure 1 Examples of isolation circuits are described.

[0008] Figure 2 Three-die devices implementing Figure 1 isolation circuits are described.

[0009] Figure 3 Another example of an isolation circuit is described.

[0010] Figure 4 Examples of transformer drivers usable in Figure 3 isolation circuits are shown.

[0011] Figure 5 Multi-die implementations of Figure 3 isolation circuits are described.

[0012] Figure 6 Another multi-die implementation of Figure 3 isolation circuits is described. DETAILED DESCRIPTION

[0013] Some isolation barrier implementations include separate isolation barriers for data and power. Thus, one isolation barrier is used to isolate the data inputs and outputs of a circuit from external data connections and another isolation barrier is used to isolate power. When separate isolation barriers are used for data and power, size and cost increase. In an example, one isolation barrier is used for both data and power. In this example, data is modulated onto the same isolation channel used for power isolation.

[0014] Figure 1 An example of an isolation circuit 100 is shown. In this example, the isolation circuit 100 includes data transfer circuits 110 and 140, a bridge 120, a transformer Tl, and a rectifier 130. The data path through the illustrated isolation circuit 100 is bidirectional. Thus, the data transfer circuit 110 includes a data input 95 that can receive incoming data (DATA IN 91) to be transferred through the isolation circuit 100 and output as output data (DATA OUT 94) via a data output 98 of the data transfer circuit 140. Similarly, the data transfer circuit 140 includes a data input 97 that can receive incoming data (DATA IN 93) to be transferred through the isolation circuit 100 and output as output data (DATA OUT 91) via a data output 96 of the data transfer circuit 110. The bridge 120, which is coupled to a primary winding LI of the transformer Tl, receives an input voltage (VCC1), and the rectifier 130, which is coupled to a secondary winding L2 of the transformer Tl, provides an isolated output voltage VISO. VISO is galvanically isolated from VCC1 and GND1. The transformer Tl is used to isolate both data and power.

[0015] The data transfer circuit 110 includes a data serializer 111, a modulator 112, an oscillator 113, a transmitter (TX) 114, a receiver (RX) 115, a bandpass filter 116, a demodulator 117, a data deserializer 118, and capacitors CI and C2. The data input 95 of the data transfer circuit 110 is an input to the data serializer 111. An output of the data serializer 111 is coupled to one input of the modulator 112. In one example, the modulator 112 is a mixer. The oscillator 113 is coupled to another input of the modulator 112. An output of the modulator 112 is coupled to an input of the transmitter 114. The transmitter 114 has a positive output 150 and a negative output 151. The positive output 150 of the transmitter 114 is coupled to one terminal of the capacitor CI and a positive input 152 of the receiver 115. The negative output 151 of the transmitter 114 is coupled to one terminal of the capacitor C2 and a negative input 153 of the receiver 115. An output of the receiver 115 is coupled to an input of the bandpass filter 116, and an output of the bandpass filter 116 is coupled to an input of the demodulator 117. An output of the demodulator 117 is coupled to an input of the data deserializer 118, and an output of the data deserializer provides DATA OUT 91.

[0016] The bridge 120 includes transistors PP0, PP1, PN0, and PN1. In the shown configuration, the bridge 120 includes a full bridge. In other configurations, the bridge 120 can include a half bridge, a bridge rectifier, or other configurations. The bridge 120 receives an input voltage (VCC1) at its input terminals and provides an output voltage (VCC2) at its output terminals. The output voltage (VCC2) is galvanically isolated from the input voltage (VCC1). The output voltage (VCC2) is provided to the primary winding LI of the transformer Tl. Figure 1In the example of FIG. 1, PP0 and PP1 comprise p-type metal oxide semiconductor field effect transistors (PMOS), and PN0 and PN1 comprise n-type metal oxide semiconductor field effect transistors (NMOS). Different types of transistors can be used in other implementations. The sources of PP0 and PP1 are coupled together at node N1. Node N1 is also coupled to an input voltage node to receive an input voltage VCC1. The drains of PP1 and PN1 are coupled together at node N2. The drains of PP0 and PN0 are coupled together at node N3. The sources of PN1 and PN0 are coupled together at a ground node (GND1). Controller 122 generates control signals 123, 124, 125, and 126 for the gates of respective PP1, PP0, PN1, and PN0, as shown. Primary winding LI has terminals 160 and 161. Terminal 160 is coupled to node N2, and terminal 161 is coupled to node N3.

[0017] In operation, controller 122 causes PP1 and PN0 to turn on at the same time (while PN0 and PN1 turn off) and vice versa causes PP0 and PN1 to turn on at the same time (while PP1 and PN0 turn off). When both PP1 and PN0 are on, the VCC1 voltage is applied to terminal 160 of primary winding LI, and ground GND1 is applied to terminal 161 of the primary winding. Conversely, when both PP0 and PN1 are on, the VCC1 voltage is applied to terminal 161 of primary winding LI, and ground GND1 is applied to terminal 160 of the primary winding. Thus, a switching waveform is applied to the terminals of primary winding LI at a switching frequency (Fs) set by controller 122.

[0018] Secondary winding L2 includes terminals 162 and 163 coupled to rectifier 130. Rectifier 130 comprises a full-wave bridge rectifier including diodes D1-D4. The cathodes of D1 and D2 are coupled together at node N4. The voltage on node N4 is the isolated output voltage VISO. The anode of D1 is coupled to the cathode of D3 at node N5, and the anode of D2 is coupled to the cathode of D4 at node N6. The anodes of D3 and D4 are coupled together and provide an isolated ground node (GISO). GISO is galvanically isolated from GND1 and VCCI. Terminal 162 of secondary winding L2 is coupled to node N6, and terminal 163 of the secondary winding is coupled to node N5. Capacitor C3 is coupled across secondary winding L2 between terminals 162 and 163.

[0019] Data transfer circuit 140 has a similar architecture to data transfer circuit 140. Data transfer circuit 140 includes a data serializer 141, a modulator 142, an oscillator 143, a transmitter 144, a receiver 145, a bandpass filter 146, a demodulator 147, a data deserializer 148, and capacitors C4 and C5. Data input 93 of data transfer circuit 140 is an input to data serializer 141. An output of data serializer 141 is coupled to one input of modulator 142. In one example, modulator 142 is a mixer. Oscillator 143 is coupled to another input of modulator 142. An output of modulator 142 is coupled to an input of transmitter 144. Transmitter 144 has a positive output 170 and a negative output 171. Positive output 170 of transmitter 144 is coupled to one terminal of capacitor C4 and a positive input 172 of receiver 145. Negative output 171 of transmitter 144 is coupled to one terminal of capacitor C5 and a negative input 173 of receiver 145. An output of receiver 145 is coupled to an input of bandpass filter 146, and an output of bandpass filter 146 is coupled to an input of demodulator 147. An output of demodulator 147 is coupled to an input of data deserializer 148, and an output of data deserializer provides DATA OUT 94.

[0020] Controller 122 turns on and off transistors PP0, PP1, MN0, and PN1 as described above to produce a switching waveform across primary winding LI of transformer Tl. Capacitor C3 across secondary winding L2 of the transformer helps set the resonant frequency of the secondary side of the transformer to be approximately the same as the switching frequency Fs of the switching waveform applied to primary winding LI. By setting the resonant frequency to be equal to Fs, a large amount of power is transferred across the transformer to produce the isolated output voltage VISO. In one example, Fs is in the range of 20 MHz to 100 MHz (e.g., 25 MHz). The switching frequency can also be significantly less than 25 MHz (e.g., 200 KHz), but the size of the transformer would need to increase (compared to Fs of 25 MHz). In one implementation, transformer Tl is fabricated on a semiconductor die (as illustrated in the example of FIG. 1 and described below). If transformer Tl is forced to be significantly larger due to the use of a small Fs (e.g., 200 KHz), it can become infeasible to fabricate the transformer on a semiconductor die. If Tl is too large to be fabricated on a semiconductor die, Tl can be provided as an external device (i.e., off-die of the die containing the other components shown in FIG. 1). Figure 3 Figure 1

[0021] Data is also transferred magnetically through the same isolation transformer Tl as the power. Data serializer 111 converts DATA IN 90 from a parallel format to a serial format, in Figure 1 ​​The data is represented as serial data (SD). In one example, the data serializer 111 can comprise a multiplexer. The frequency of the SD is increased by the modulator 112. The oscillator 113 produces a clock with a frequency significantly greater than the switching frequency Fs of the bridge 120. In one example, the frequency of the oscillator 113 is 10 times, 20 times, etc. the frequency of Fs. For example, if Fs is 25 MHz, then the frequency of the oscillator 113 can be 250 MHz or 500 MHz. Thus, the output signal from the modulator 113 is a modulated version of the SD, and is shown as SDMOD.

[0022] The primary winding LI of the transformer Tl has a pair of taps 180 and 181 between the external terminals 160 and 161. The taps can be positioned so as to divide the primary winding into three portions. For example, the taps can be positioned to divide the primary winding into three equal portions. The capacitor CI is coupled to the tap 180, and the capacitor C2 is coupled to the tap 181. By coupling the data transfer circuit 110 to the center taps 180, 181 of LI instead of the terminals 160, 162 of LI, it is ensured that the data transfer circuit 110 is not coupled to a low impedance load - if terminals 160 and 161 are used, then when opposite pairs of transistors are flipped between VCCl and GNDl, the data transfer circuit 110 would experience a low impedance load through the transistors of the bridge 120. Similarly, the secondary winding L2 of the transformer Tl also has a pair of center taps 190 and 191. The capacitor C4 is coupled to the tap 190, and the capacitor C5 is coupled to the tap 191.

[0023] SDMOD is provided by the transmitter 150 to the taps 180, 181 of the primary winding LI. A corresponding signal (of the same frequency as SDMOD) is produced on the taps 190, 192 of the secondary winding L2 and provided to the receiver 145. The receiver provides the received signal to the bandpass filter 146, which is centered at approximately the carrier frequency of the received data signal to attenuate noise at higher and lower frequencies. Then, the demodulator 147 demodulates the data signal back to its original data rate, and the data deserializer 148 converts the serial signal back to a parallel format as DATA OUT 94.

[0024] Data transmitted in the opposite direction through isolation circuit 100 is processed in much the same way as described. Data serializer 141 converts DATA IN 93 to serial format, and modulator 142 modulates the serial data signal to a higher frequency (significantly higher than Fs) using oscillator 143. The higher frequency modulated data signal is provided to taps 190 and 191 of the secondary winding, and a corresponding data signal is generated on taps 180 and 181 of the primary winding. Receiver 115 receives the higher frequency data signal. Bandpass filter 116 filters it, and demodulator 117 converts the higher frequency data signal back to its original data rate. Data deserializer 118 converts the recovered data signal back to parallel format as DATA OUT 91.

[0025] Figure 2 An example of a semiconductor package (also referred to as a "chip") 200 that includes isolation circuit 100 is illustrated. Semiconductor package 200 in this example includes three dies 220, 230, and 240. All three dies 220, 230, and 240 are encapsulated by molding compound 210 to form a single semiconductor package. Each die has Figure 1 different portions of isolation circuit 100. Die 220 includes data transmission circuit 110 and bridge 120. Die 230 includes transformer Tl. Die 240 includes rectifier 130 and data transmission circuit 140.

[0026] Figure 3 Another example of an isolation circuit 300 is shown. In this example, isolation circuit 300 includes data transmission circuits 310 and 350, transformer driver 320, transformer T2, rectifier 330, and voltage regulator 340 (e.g., a low-dropout voltage regulator). As in the case of isolation circuit 100, the data path through isolation circuit 300 is bidirectional. Thus, data transmission circuit 310 includes data input 395, which can receive incoming data (DATA IN 301) to be transmitted through isolation circuit 300 and output as output data (DATA OUT 304) via data output 396 of data transmission circuit 350. Similarly, data transmission circuit 350 includes data input 397, which can receive incoming data (DATA IN 303) to be transmitted through isolation circuit 300 and output as output data (DATA OUT 302) via data output 396 of data transmission circuit 310.

[0027] Transformer T2 includes a primary winding L3 and a secondary winding L4. Primary winding L3 has opposing terminals 380 and 381, and secondary winding L4 has opposing terminals 383 and 384. Each winding of transformer T2 is center tapped. Primary winding L3 includes a center tap 382, and secondary winding L4 includes a center tap 385. Center tap 382 of primary winding L3 receives input voltage VIN. The output of voltage regulator 340 provides an isolated voltage (VISO) that is galvanically isolated from VIN. Center tap 385 of secondary winding L4 is connected to an isolated ground (GISO) that is galvanically isolated from the ground reference on the primary side of transformer T2.

[0028] Data transfer circuit 310 includes a data serializer 311, a modulator 312, an oscillator 313, a transmitter 314, a receiver 315, a bandpass filter 316, a demodulator 317, a data deserializer 318, and capacitors C31 and C32. Data input 395 of data transfer circuit 310 is an input to data serializer 311. The output of data serializer 311 is coupled to one input of modulator 312. In one example, modulator 312 is a mixer. Oscillator 313 is coupled to the other input of modulator 312. The output of modulator 312 is coupled to an input of transmitter 314. Transmitter 314 has a positive output 370 and a negative output 371. Positive output 370 of transmitter 314 is coupled to one terminal of capacitor C31 and to a positive input 372 of receiver 315. Negative output 371 of transmitter 314 is coupled to one terminal of capacitor C32 and to a negative input 373 of receiver 315. The output of receiver 315 is coupled to an input of bandpass filter 316, and the output of bandpass filter 316 is coupled to an input of demodulator 317. The output of demodulator 317 is coupled to an input of data deserializer 318, and the output of data deserializer provides DATA OUT 302.

[0029] Transformer driver 320 is coupled across primary winding L3 of transformer T2 (e.g., to terminals 380 and 381). In one example (as will be explained in Figure 4 Transformer driver 320 is configured to operate as a "push-pull" converter, in one example (as will be explained in

[0030] Rectifier 330 is coupled across secondary winding L4 of transformer T2 (i.e., connected to terminals 383 and 384). In Figure 3In the example shown, the rectifier 330 includes Zener diodes Zl and Z2. The anode of Zl is coupled to terminal 383 of the secondary winding L4, and the anode of Z2 is coupled to terminal 384 of the secondary winding. The cathodes of Zl and Z2 are coupled together at node N31, and to an input of the voltage regulator 340. The voltage on node N31 is isolated from VIN and the ground reference of VIN, and is further converted by the voltage regulator 340 to an isolated output voltage VISO.

[0031] The data transfer circuit 350 has a similar architecture to the data transfer circuit 310. The data transfer circuit 350 includes a data serializer 351, a modulator 352, an oscillator 353, a transmitter 354, a receiver 355, a bandpass filter 356, a demodulator 357, a data deserializer 358, and capacitors C33 and C34. The data input 303 of the data transfer circuit 350 is an input to the data serializer 351. The output of the data serializer 351 is coupled to one input of the modulator 352. In one example, the modulator 352 is a mixer. The oscillator 353 is coupled to another input of the modulator 352. The output of the modulator 352 is coupled to an input of the transmitter 354. The transmitter 354 has a positive output 374 and a negative output 375. The positive output 374 of the transmitter 354 is coupled to one terminal of the capacitor C33 and a positive input 376 of the receiver 355. The negative output 375 of the transmitter 354 is coupled to one terminal of the capacitor C34 and a negative input 377 of the receiver 355. The output of the receiver 355 is coupled to an input of the bandpass filter 356, and the output of the bandpass filter 356 is coupled to an input of the demodulator 357. The output of the demodulator 357 is coupled to an input of the data deserializer 358, and the output of the data deserializer provides the DATA OUT 304.

[0032] Figure 4An example implementation of a transformer driver 320 is shown. In this example, the transformer driver 320 includes transistors M1 and M2 and a controller 409. M1 and M2 include NMOS transistors, but may include other types of transistors. The controller 409 is coupled to the gates of M1 and M2 and provides control signals to the respective gates. The controller 409 conversely turns on M1 and M2 such that M1 and M2 are not turned on simultaneously. Thus, M1 turns on when M2 is off, and then M2 turns on when M1 is off. Each cycle includes a period in which neither transistor is turned on. When one of M1 and M2 is turned on, VIN is applied between center tap 382 and ground, wherein current flows from center tap 381 to the drain of the turned-on transistor. The voltage is reversed across the non-conducting half of the primary winding L3 to maintain volt-second balance, thereby generating 2*VIN across the primary winding L3 between terminals 380 and 381. The same voltage is generated across each corresponding half of the secondary winding L4, but scaled by a factor N (the turns ratio of transformer T2).

[0033] return Figure 3 Data transmission circuit 310 is coupled to terminals 380 and 381 of the primary winding L3 of transformer T2, and data transmission circuit 350 is coupled to terminals 383 and 384 of the secondary winding. More specifically, C31, C32, C33, and C34 are coupled to the corresponding terminals 380, 381, 383, and 384. The data to be transmitted across transformer T2 is synchronized with the operation of transformer driver 320, such that when the corresponding transistors M1 / M2 (M1 / M2) coupled to the corresponding transformer terminals are activated... Figure 4 When M1 (coupled to terminal 380) is off, the transmitter output 370 (also coupled to terminal 380 via capacitor C31) provides its data signal to terminal 380. The transformer driver 320 has power transistors M1 and M2 that turn on and off at relatively low frequencies (e.g., 300 kHz). Figure 4 When the gate of M1 is 0V, Figure 4 The controller 409 can send a signal to the transmitter (via control signal 411). At this time, the transmitter can drive a high-frequency RF signal to terminal 380.

[0034] The transformer secondary terminals 383 and 384 swing between +ve and -ve voltages (e.g., +6V and -6V) around GISO, while node N31 is at a constant output voltage (e.g., 6V minus a diode drop, or the voltage at N31 is approximately 5.5V). When terminal 383 is at the -ve potential diode, Zl is reverse biased, and terminal 383 is at a relatively high impedance. At this time, RF signal 413 can be coupled between terminal 383 (and 384) and transmitter 354. This can be illustrated in the figure by showing the connection between 383, 384, and the transmitter. While coordination between the transmitter and transformer driver 320 can improve the efficiency of the communication, in some implementations there is no coordination between the transmitter and transformer driver - the transmitter can keep transmitting the high frequency signal, and it will naturally couple to the transformer when the transformer is at high impedance (e.g., every alternating cycle).

[0035] Figure 5 An example is described in which the isolation circuit 300 is fabricated as three separate packages - die 410, die 420, and transformer T2. Each die 410, 420 has Figure 3 different parts of the isolation circuit 300. Die 410 includes data transfer circuit 310 and transformer driver 320. Die 420 includes rectifier 330, voltage regulator 340, and data transfer circuit 350. Alternatively, the components of die 410 and 420 can be fabricated on a single die, with transformer T2 separately packaged.

[0036] Figure 6 An example is described in which the isolation circuit 300 is fabricated as four separate packages - die 410, die 510, die 520, and transformer T2. Each die 410, 510, and 520 has Figure 3 different parts of the isolation circuit 300. Die 410 includes data transfer circuit 310 and transformer driver 320. Die 510 includes rectifier 330. Die 520 includes voltage regulator 340 and data transfer circuit 350.

[0037] Throughout this specification the term "coupled" is used. The term can cover a connection, communication or signal path enabling a functional relationship consistent with the description described. For example, in a first instance, device A is coupled to device B if device A generates a signal to control device B to perform an action, or in a second instance, device A is coupled to device B through intermediate component C if the intermediate component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0038] Within the scope of the claims modifications in the described embodiments can be made, and other embodiments can be possible.

Claims

1. A semiconductor package comprising: a transformer having a primary winding and a secondary winding, the primary winding having first and second terminals and a pair of taps therebetween, and the secondary winding having first and second terminals and a pair of taps therebetween; a first data transfer circuit coupled to the pair of taps of the primary winding; a second data transfer circuit coupled to the pair of taps of the secondary winding; a bridge coupled to the first and second terminals of the primary winding and configured to receive an input voltage; and a rectifier coupled to the first and second terminals of the secondary winding and configured to provide an isolated output voltage.

2. The semiconductor package of claim 1, further comprising: a first die including the first data transfer circuit and the bridge; and a second die including the rectifier and the second data transfer circuit.

3. The semiconductor package of claim 2, further comprising a third die including the transformer.

4. The semiconductor package of claim 1, further comprising: a first die including the first data transfer circuit and the bridge; and a second die including the transformer.

5. The semiconductor package of claim 1, wherein: the first data transfer circuit includes a first modulator and a first oscillator, the first modulator configured to modulate a first data input signal using a first clock signal from the first oscillator; and the bridge includes first, second, third, and fourth transistors and a first controller coupled to the first, second, third, and fourth transistors.

6. The semiconductor package of claim 5, wherein the first controller is configured to operate the first, second, third, and fourth transistors at a first frequency, and the first clock signal from the first oscillator has a second frequency different from the first frequency.

7. The semiconductor package of claim 6, wherein the second frequency is at least ten times the first frequency.

8. The semiconductor package of claim 5, wherein: the second data transfer circuit includes a second modulator and a second oscillator, the second modulator configured to modulate a second data input signal using a second clock signal from the second oscillator.

9. The semiconductor package of claim 8, wherein: the first data transfer circuit includes a first demodulator configured to demodulate a data signal produced on the primary winding; and the second data transfer circuit includes a second demodulator configured to demodulate a data signal produced on the secondary winding. ​ ​ ​ ​

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