Optical detector sensor array

Abstract

A photodetector sensor array device that can be used in a camera chip includes upper and lower contact layers of n+ and p+ semiconductor material on either side of a light absorption region made of either one or two oppositely doped layers in a semiconductor material. Insulating trenches of dielectric material extend through these layers to form individual pixels. Respective contacts are connected to the upper and lower contact layers so that each pixel can be reverse biased or forward biased. In operation, the device is reset using a reverse bias and then switched to a forward bias for sensing. After switching, carriers generated in response to photon absorption accumulate in the potential well of the light absorption region, thereby lowering the potential barrier to the contact layers, causing current to begin flowing between the contacts after a time delay that is inversely proportional to the intensity of the incident light.

Description

Technical Field

[0001] The present disclosure relates to photodetector sensor arrays. Background Art

[0002] Current commercial photodetector sensor arrays used in smartphone cameras and high-quality digital still cameras are mostly, if not entirely, based on pinned photodiodes (PPDs), a photodiode design primarily invented in 1980 by Shiraki, Teranishi, and Ishihara of NEC Corporation and described in US Pat. No. 4,484,210. PPDs largely solved the shutter lag problem in early sensor arrays. While the NEC invention was originally conceived for CCD sensor arrays, PPDs were later developed in the 1990s and early 2000s for use in CMOS sensor arrays, which are now the standard sensor array type used in commercial cameras. Current CMOS sensor arrays primarily use so-called active pixel sensors (APSs) based on intra-pixel charge transfer.

[0003] Figure 1A The figure shows a schematic cross-section of a PPD used in a CMOS APS pixel. The PPD is based on a shallow p+ region above a thicker n-region, which in turn is above a thicker p-region. This creates a pn junction between the n- and p-regions. When the PPD is held at a constant reverse bias voltage, the pn junction functions in principle like a conventional pn (or pin) photodetector. That is, incident photons are absorbed in the light-absorbing n- and p-regions to generate electron-hole pairs. The n-region also serves to accumulate photogenerated charge and is therefore referred to as a storage well (SW). The PPD has a transfer gate TG for charge transfer, which is laterally interposed in the p-type region between the n-region (i.e., SW) and the floating n+ diffusion region FD.

[0004] Figure 1B Schematically shows Figure 1A Energy diagram of a PPD. As shown, the voltage applied to the TG is used to control the transfer of accumulated charge for readout. In operation, the n-type SW region of the PPD is first fully depleted, while the TG is maintained at a voltage that prevents charge flow between the PPD and the FD. Charge is then generated from electron-hole pairs in the n- and p-regions and accumulated in the SW. When needed, the voltage at the TG is lowered to remove the barrier between the PPD and the FD, and the accumulated charge is then swept out to the FD.

[0005] Figure 1C Including Figure 1A and Figure 1BEquivalent circuit of a CMOS APS pixel used in current commercial cameras with a PPD shown. The equivalent circuit shown is for a so-called 4T cell design, which contains four CMOS transistors. Other CMOS APS pixel designs with three, five and six transistors (called 3T, 5T and 6T designs) are also known. All of these designs are based on the PPD and contain a transistor amplifier structure. The PPD, together with its transfer gate TG and floating diffusion region FD, forms a transistor whose potential is monitored and amplified by a source follower transistor SF. In the 4T design, the third and fourth transistors are: a row select transistor SEL for readout and a reset transistor RST for resetting FD between detection cycles.

[0006] As in conventional pn photodiodes, the magnitude of the photocurrent in a CMOS APS sensor pixel is proportional to the number of electron-hole pairs generated by photon absorption in the p- and n-regions. However, in a CMOS APS pixel, instead of electron-hole pairs being swept to the contacts as they are generated, as in a simple pn junction photodetector, the output photocurrent is a current output to the column bus via the SF, which in turn is proportional to the amount of charge transferred from the PPD to the FD.

[0007] More generally, it is naturally desirable for sensor arrays to have smaller pixels, allowing for higher resolution without making the sensor chip area larger, which also increases power consumption. For example, current sensor chips used in high-end still cameras from Canon, Sony, Nikon, and others may have an area of up to 20 mm × 30 mm, which is too large to fit in a typical smartphone and would also consume too much power to be suitable for a smartphone. Between approximately 2000 and 2010, the pixel pitch decreased from approximately 10 microns to approximately 1 micron. However, over the past decade, further reductions in pixel pitch have proven difficult. The reason lies in the pixel aspect ratio. For a 10-micron pixel size, the pixel is essentially a planar structure with a width several times greater than its depth. Edge effects caused by the trenches separating the pixels are not too problematic. However, for a 1-micron pixel size, the pixels are arranged in columns, with a width less than their depth, meaning the aspect ratio is significantly less than 1. The trenches separating adjacent pixels thus become noticeable.

[0008] The trenches are associated with a high defect density and form depletion regions that begin to encroach on the pixel's carrier drift and accumulation regions. In terms of electrical performance, the edges begin to constitute significant sources of dark current.

[0009] Actlight SA of Lausanne, Switzerland, discloses an unconventional type of photodetector in US 2012 / 313155 A1 and subsequent patent applications. The Actlight photodetector operates using a pulsed voltage that switches from reverse bias to forward bias. This switch to forward bias causes a photocurrent to flow through the device structure. However, the onset of photocurrent flow is not instantaneous, but occurs after a time delay from light incidence. This time delay is known as the trigger time. The trigger time is proportional to the inverse of the light intensity and is therefore used as a measure of the incident light intensity.

[0010] Figure 2A and Figure 2B Schematic representations of a cross-sectional view and a plan view, respectively, of an Actlight photodetector 1 as disclosed in US 2012 / 313155 A1. The growth direction (i.e., perpendicular to the plane of the wafer) is labeled the z-direction. The first and second gates G1 and G2, held at voltages VG1 and VG2, extend in the y-direction. The direction orthogonal to the gates in which electrons and holes are swept out is the x-direction. Figure 2A The section AA is at Figure 2B In the xz plane shown. Gates G1 and G2 are arranged on either side of the light absorbing layer 15, and the central part of the light absorbing layer 15 is open for receiving incident photons. The light absorbing layer 15 can be an intrinsic or doped semiconductor suitable for absorbing incident photons in the wavelength range to be detected, such as silicon or germanium. Highly doped n+ and p+ regions are arranged on either side of the body region 15 outside the gate and serve as outputs for reading out the optical signal. The layers of the photodetector 1 are epitaxially fabricated on a semiconductor-on-insulator (SOI) substrate 3, which includes a silicon wafer and a buffer layer 7, with an insulator layer 8 deposited on the buffer layer 7. Gates G1 and G2 are made of a conductive material (such as a metal, silicide or semiconductor). Gates G1 and G2 are separated from the light absorbing layer 15 by an insulator or dielectric material 4 (such as silicon oxide or silicon nitride). The photodetector 1 is operated with the following bias voltage. A negative voltage VG1 is applied to the gate G1 (e.g., -2V), a negative or zero voltage V1 is applied to the n+ region, a positive voltage VG2 is applied to the gate G2 (e.g., 2V), and a positive voltage V2 (e.g., 1V) is applied to the p+ region. The triggering time of the photodetector is a function of the electric field in the light absorbing layer 15, and thus it can be adjusted by adjusting the gate voltage. Under these bias conditions, photons incident on the light absorbing region 15 between the gates, for example from the optical fiber device 30, are absorbed, thereby generating electron-hole pairs, which are then swept out by the electric field caused by the bias voltage and are thus detected as current flowing between the n+ and p+ regions. Actlight photodetectors can be integrated to form a CMOS sensor array as disclosed in the above-mentioned US2012 / 313155A1 (see Figure 13 ). Summary of the Invention

[0011] According to one aspect of the present disclosure, a sensor array device having an array of sensing pixels in one or two dimensions is provided, the device comprising: an upper contact layer composed of a highly doped p-type or n-type semiconductor material; a lower contact layer composed of a highly doped n-type or p-type semiconductor material of the opposite type to the upper contact layer; a light absorbing layer of doped semiconductor material, the light absorbing layer being sandwiched between the upper and lower contact layers, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; and a grid of insulating trenches of dielectric material, the insulating trenches of dielectric material being vertically spaced apart. extending directly through the upper contact layer and at least a portion of the doped light absorbing layer to subdivide the layer into an array of laterally adjacent, independently contactable columns of semiconductor material forming pixels; and upper and lower contacts connected to corresponding pixels of the upper contact layer and the lower contact layer, such that after a voltage applied between the upper contact and the lower contact of the pixel is switched from a reverse bias to a forward bias, carriers generated in the light absorbing layer in response to absorption of photons accumulate in the light absorbing layer, which causes current to begin to flow between the upper contact and the lower contact after a time delay that is inversely proportional to the intensity of the incident light.

[0012] Certain embodiments of the present disclosure can provide a very simple pixel design based on a planar layer sequence and vertical carrier transport. As a result of the carrier transport being vertical rather than in-plane, the design has essentially no in-plane structural complexity. Furthermore, depending on the embodiment, each pixel requires only one or two contacts at the top and only one contact at the bottom. The simplicity of this pixel design not only makes the operation of the sensor array simple, but also provides excellent scalability and manufacturability in terms of reducing the pixel pitch and increasing the total number of pixels in the array. Furthermore, compared to CMOS APS designs using PPDs, our design does not require any transistor integration because the signal is essentially a digital signal based on measuring time delays, and because the intensity of the signal can be made high enough that amplification is not required. The requirement in CMOS APS designs to have to integrate a photodiode and a transistor into each pixel does not exist in our design.

[0013] In some embodiments, the columns forming the pixels have an aspect ratio less than 1. We define the aspect ratio as the ratio of the lateral spacing between adjacent pixels divided by the depth of the light absorbing layer. Due to the lack of lateral structure and vertical carrier transport, our design is particularly suitable for small aspect ratios.

[0014] In one set of embodiments the doped light absorbing layer is subdivided into oppositely doped upper and lower layers of semiconductor material arranged in a vertical doping sequence of n+pnp+ together with oppositely doped upper and lower contact layers.

[0015] In another set of embodiments, a doped light absorbing layer extends between an upper contact layer and a lower contact layer with a single type of doping and is configured such that in each pixel, when a reverse bias voltage is applied between the upper and lower contacts, a charge sink is created in the doped light absorbing layer adjacent to one of the contacts, and when the voltage is switched from reverse bias to forward bias, carriers generated in the light absorbing layer in response to photon absorption initially accumulate at the charge sink, and then, after the charge sink approaches saturation, current begins to flow between the contacts, the start of current flow occurring after a time delay from the switching, the time delay being inversely proportional to the intensity of the incident light. In this set of embodiments, the pixels within their upper contact layer can each have a portion connected to the upper contact, partially separated from a surrounding portion of the upper contact layer by a closed loop of doped semiconductor material of the light absorbing layer, such that when a reverse bias voltage is applied between the upper and lower contacts, the charge sink is provided by a depletion region formed around the portion of the upper contact layer connected to the upper contact. Alternatively, each pixel may further include one or more islands of doped semiconductor material, preferably highly doped (e.g., n+ or p+), wherein the islands are doped oppositely to the semiconductor material of the doped light absorbing layer in which the islands are contained, such that when a reverse bias voltage is applied between the upper contact and the lower contact, a charge sink is provided by forming a depletion region at the islands. Furthermore, the pixels within their upper contact layer may each have a portion connected to the upper contact, the portion being separated from a surrounding portion of the upper contact layer by a closed loop of highly doped semiconductor material of the opposite dopant type, the closed loop having its own contact, and the island being adjacent to the portion of the upper contact layer connected to the upper contact.

[0016] The columns forming the pixels have sidewalls adjacent to the dielectric material of the trench, and these sidewalls can be advantageously doped to passivate surface defects. That is, the sidewalls have a highly doped cladding over at least a portion of their vertical extent. In some embodiments, at least the lower portion of the sidewall has a highly doped cladding of the same dopant type as the lower contact layer, such that the highly doped cladding forms an electrical extension of the lower contact layer around the column. In some embodiments, at least the upper portion of the sidewall has a highly doped cladding of the same dopant type as the upper contact layer, such that the highly doped cladding forms an electrical extension of the upper contact layer around the column. In addition, the lower contact layer and the upper contact layer can be electrically separated from each other by a first highly doped sidewall cladding portion and a second highly doped sidewall cladding portion, such that the lower contact layer and the upper contact layer and the intervening highly doped sidewall cladding portion are in a vertical doping order of p+n+p+n+.

[0017] The dielectric trench need not extend directly through the epitaxial structure. For example, in some embodiments, the dielectric trench terminates vertically above the lower contact layer, and the lower contact is a blanket contact for the array. This is an alternative to extending the dielectric trench vertically completely through the doped light absorbing layer and through the lower contact layer, in which case the lower contact includes an array of contacts connected to the corresponding pixels of the lower contact layer.

[0018] In some cases, a sub-pixel structure may also be advantageous. In such a design, some of the dielectric trenches terminate vertically above the lower contact layer, while others extend vertically completely through the doped light-absorbing layer and the lower contact layer. This forms an array of pixel groups, each with its own lower contact common to all pixels in the group. We refer to pixels in the same group as sub-pixels.

[0019] The proposed sensor chip can be incorporated into a module where other chips are manufactured in a different wafer using a different process. The module can be based on front- or rear-illumination, i.e., the additional chip can be attached to the front (top) side of the sensor array chip for rear-illumination, or to the rear (bottom) side of the sensor array chip for front-illumination.

[0020] An integrated sensor array module can be provided, comprising a first chip having a sensor array device as described above, mounted together with a processor device formed as a second chip. The respective chips can then be independently manufactured on separate wafers using corresponding materials and manufacturing processes optimized for each. The processor chip includes an array of pixel-specific processing elements for the pixels of the sensor chip. The processor chip is mounted on the sensor chip. Vias between the two chips form an electrical connection between each of the pixel-specific processing elements of the processor chip and the pixel contacts of the corresponding pixels in the sensor array device. Thus, the integration is vertical, with a one-to-one correspondence between the pixels of the sensor array and the processing elements in the processor chip. Further integration can be achieved by attaching a memory chip to the module. The memory device is formed as a third chip from a third wafer and includes pixel-specific memory elements for the pixels of the sensor chip. The memory chip is mounted on the processor chip such that additional vias form an electrical connection between each of the pixel-specific processing elements of the processor chip and the pixel-specific memory elements in the memory chip. The memory can be a random access memory, such as DRAM.

[0021] According to another aspect of the present disclosure, a method for fabricating a photodetector device is provided, the method comprising: fabricating a semiconductor epitaxial structure, the semiconductor epitaxial structure comprising: an upper contact layer composed of a highly doped p-type or n-type semiconductor material; a lower contact layer composed of a highly doped n-type or p-type semiconductor material of an opposite type to the upper contact layer; and a light absorbing layer of doped semiconductor material, the light absorbing layer being sandwiched between the upper contact layer and the lower contact layer, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; etching a grid of trenches, the trenches extending vertically through the upper contact layer. a photodetector device comprising: a first layer and a second layer of semiconductor material doped with a dielectric material to subdivide the layer into an array of laterally adjacent, independently contactable columns of semiconductor material that will form pixels; filling the trenches with a dielectric material to insulate them; and providing upper and lower contacts for the pixels of the upper and lower contact layers, such that in the photodetector device, after a voltage applied between the upper and lower contacts of the pixel is switched from a reverse bias to a forward bias, carriers generated in the light absorbing layer in response to absorption of photons accumulate in the light absorbing layer, which causes current to begin to flow between the upper and lower contacts after a time delay that is inversely proportional to the intensity of the incident light.

[0022] According to another aspect of the present disclosure, a method of operating a photodetector device is provided, the method comprising: an upper contact layer composed of a highly doped p-type or n-type semiconductor material; a lower contact layer composed of a highly doped n-type or p-type semiconductor material of the opposite type to the upper contact layer; a light absorbing layer of doped semiconductor material, the light absorbing layer being sandwiched between the upper contact layer and the lower contact layer, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; and a grid of insulating trenches of dielectric material, the insulating trenches of dielectric material extending vertically through at least a portion of the upper contact layer and the doped light absorbing layer. The invention relates to a method for manufacturing a photodetector device for detecting a light absorbing layer comprising: applying a reverse bias voltage between the upper contact and the lower contact; switching the reverse bias voltage to a forward bias voltage such that carriers subsequently generated in the light absorbing layer in response to absorption of photons accumulate in the light absorbing layer; and sensing the start of current flow between the upper contact and the lower contact and measuring a time delay between the switching and the start of current flow, wherein the time delay is inversely proportional to the incident light intensity.

[0023] The light absorbing layer forms a light absorbing region that can be made of a single semiconductor material. The light absorbing layer or region can be composed of one or more doped layers or regions. In some embodiments, the light absorbing layer or region is made of a single layer of semiconductor material doped with the same dopant type (e.g., all p-doped or all n-doped). In other embodiments, the light absorbing layer or region is made of a single semiconductor material, but has different n-doped layers or regions and p-doped layers or regions, such that a pn junction is formed, and the pn junction between the p-type region and the n-type region is therefore a homojunction. In further embodiments, the light absorbing layer or region is made of different semiconductor materials, such that the pn junction between the p-type and n-type regions is a heterojunction. With a heterojunction, two different materials can be in the same material system and thus can form an alloy with each other, such as a SiGeC material system or a GaAlInAsP material system. It should be understood that the semiconductor materials making up the light absorbing layer or region are selected based on their band gap so that interband absorption of photons occurs within the desired energy range, such as the visible or near-infrared, as required by the photodetector to meet specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In the following, the present invention will be further described, by way of example only, with reference to exemplary embodiments shown in the accompanying drawings.

[0025] Figure 1A is a schematic cross-section of a standard PPD used in CMOS APS pixels used in current commercial cameras.

[0026] Figure 1B yes Figure 1A Schematic cross-sectional energy band diagram of PPD.

[0027] Figure 1C It includes Figure 1A and Figure 1B The PPD equivalent circuit of the CMOS APS pixel used in current commercial cameras is shown.

[0028] Figure 2A and Figure 2B Schematic representations of a cross-sectional view and a plan view, respectively, of a prior art photodetector as disclosed in US 2012 / 313155 A1.

[0029] Figure 3A is a schematic cross-section in the xz plane of three sensing pixels of the sensor array device according to the first embodiment.

[0030] Figure 3B yes Figure 3A Schematic plan view of the sensor array device in the xy plane.

[0031] Figure 4A 、 Figure 4B and Figure 4C 1 is an energy band diagram illustrating a photodetector pixel according to the first embodiment, wherein the photodetector pixel is in a reverse biased state, a forward biased non-conductive state, and a forward biased conductive state, respectively.

[0032] Figure 5 Is for the basis Figure 3A and Figure 3B The light detector of the first embodiment is in the case of incident light and in the case of no incident light, that is, Figure 4C and Figure 4B Plot of the output current as a function of bias voltage in the forward biased conducting and non-conducting states.

[0033] Figure 6A and Figure 6B The voltage V applied in the absence and presence of light is shown. d and an oscilloscope screenshot of the output current I;

[0034] Figure 7 is a graph plotting the inverse trigger time 1 / t as a function of the absorbed optical power A.

[0035] Figure 8 is a schematic cross-section of a photodetector sensor array according to a modification of the first embodiment.

[0036] Figure 9 is a schematic cross-sectional view of an integrated sensor array module including a sensor array device embodying the present invention, such as the sensor array device of the first embodiment.

[0037] Figure 10 is a schematic cross-sectional view of another integrated sensor array module including a sensor array device embodying the present invention, such as the sensor array device of the first embodiment.

[0038] Figure 11 is a schematic cross-section in the xz plane of three sensing pixels of the sensor array device according to the second embodiment.

[0039] Figure 12 is a schematic cross-section in the xz plane of three sensing pixels of the sensor array device according to the third embodiment.

[0040] Figure 13 is a schematic cross-section in the xz plane of three sensing pixels of the sensor array device according to the fourth embodiment.

[0041] Figure 14A 、 Figure 14B and Figure 14C It shows that according to Figure 13Energy band diagram of a photodetector pixel of an embodiment of the present invention, wherein the photodetector pixel is in a reverse biased state, a forward biased non-conducting state, and a forward biased conducting state, respectively.

[0042] Figure 15 Is for the basis Figure 13 The light detector of the embodiment is in the case of incident light and no incident light, that is, respectively Figure 14C and Figure 14B Plot of the output current as a function of bias voltage in the forward biased conducting and non-conducting states.

[0043] Figure 16 is a schematic cross-section in the xz plane of three sensing pixels of the sensor array device according to the fifth embodiment.

[0044] Figure 17A 、 Figure 17B and Figure 17C It shows that according to Figure 16 Energy band diagram of a photodetector of an embodiment of the present invention, wherein the photodetector pixel is in a reverse biased state, a forward biased non-conducting state, and a forward biased conducting state, respectively.

[0045] Figure 18 Is for the basis Figure 16 The light detector of the embodiment is in the case of incident light and no incident light, that is, respectively Figure 17C and Figure 17B Plot of the output current as a function of bias voltage for the forward biased conducting and non-conducting states. DETAILED DESCRIPTION

[0046] In the following detailed description, for the purpose of explanation rather than limitation, specific details are set forth in order to provide a better understanding of the present disclosure. It will be apparent to one skilled in the art that the present disclosure can be implemented in other embodiments that depart from these specific details.

[0047] Figure 3A is a schematic cross-section in the xz plane of three sensing pixels 2 of the sensor array device 1 according to the first embodiment, each pixel 2 being an independently operable photodetector. Figure 3B is a schematic plan view of the same sensor array device 1 and shows that the sensing pixels 2 are arranged with a pixel pitch P in the x and y directions, respectively. x and P y (Other embodiments may have a one-dimensional pixel array.) The pitch P x 、P yThe pixels 2 may be formed of columns 5 of semiconductor material which are electrically isolated from their adjacent columns by dielectric (i.e. electrically insulating) material filling the trenches 16 between the columns 5. The columns 5 thus have sidewalls 18 adjacent to the dielectric material of the trenches 16. Thus, a two-dimensional array of laterally adjacent, independently contactable columns 5 of semiconductor material forming the pixels 2 is provided. The sensor array device 1 may also have areas for control or other electronic components 25 formed in the same wafer, such as Figure 3B The growth direction (ie, normal to the plane of the wafer) is labeled the z-direction, wherein the epitaxial layers are in the xy plane. For example, the layers of the photodetector are epitaxially fabricated on a semiconductor-on-insulator (SOI) substrate.

[0048] refer to Figure 3A The semiconductor portion of the structure consists of a sequence of layers, from bottom to top: p+, n, p, n+. That is, there is a lower contact layer 20 composed of a highly doped p-type semiconductor material (denoted as p+), a lower layer 14 of an n-type doped semiconductor material (denoted as n), an upper layer 12 of a p-type semiconductor material (denoted as p), which together form a light-absorbing region 15, and an upper contact layer 10 composed of a highly doped n-type semiconductor material (denoted as n+). The highly doped materials can be doped sufficiently highly to degenerate, i.e., so that the doping centers merge into minibands that allow electrons or holes to move without transferring to the adjacent conduction or valence bands, respectively, or can be doped at a level lower than the threshold for degenerate doping, but still significantly higher than the doping concentration in the light-absorbing region 15. Thus, the light-absorbing region 15 forms a pn junction 13 sandwiched between the upper contact layer 10 and the lower contact layer 20. The light absorption region 15 is configured to generate oppositely charged carrier pairs, ie, electrons 'e', in response to absorption of photons 'hv' when light is incident on the device. - 'and hole'h + The trenches 16 form a grid of dielectric material, extending vertically through at least a portion of the upper contact layer 10 and the doped light absorbing region 15 , and optionally through the entire light absorbing region 15 , and further optionally through the lower contact layer 20 .

[0049] refer to Figure 3BIn addition to the sensor array, the detector array may also include a control circuit system 25 to manage the acquisition, capture and / or sensing operations of the array's light sensors. For example, the control circuit system (which may be integrated on the same substrate as the sensors) may control or enable / disable the sensors in a manner such that data acquisition or sensing is correlated with the transmitted data rate; the detector array may be coupled to a plurality of fiber optic output devices, each of which is associated with one or a group of sensors. The sensors may be configured and / or arranged in any array architecture and in conjunction with any type of integrated circuit system. Furthermore, the array may be manufactured using any suitable manufacturing technology.

[0050] Thus, the planar layers 10, 12, 14, 20 of semiconductor material are subdivided into a two-dimensional array of laterally adjacent, individually contactable columns 5 forming pixels 2. Upper and lower contacts 22, 24 are connected to the respective pixel columns 5 of the upper and lower contact layers 10, 20. More generally, the lower contact layer 20 is doped in the opposite direction to the upper contact layer 10, and considering any embodiment described herein, there will be equivalent "mirror image" embodiments in which the doping directions of all semiconductor layers or regions are opposite.

[0051] The dielectric trench 16 is shown extending vertically completely through the light absorbing layers 12, 14 and also through the lower contact layer 20. The lower contact 24 is then implemented as an array of individual contacts connected to the corresponding pixel columns 5 through the portion of the lower contact layer 20 at the base of each column. A variation (not shown) is that the dielectric trench 16 terminates vertically above the lower contact layer 20, for example, at or near the bottom of the lower light absorbing layer 14. The lower contact 20 would then be a blanket contact, that is, one common contact for all pixels in the array.

[0052] Note that Figure 3A As schematically shown for the xz plane, the columns 5 forming the pixels may have an aspect ratio of less than 1, which is determined by a pixel pitch greater than the lateral spacing between adjacent pixels (ie, the pixel pitch P in the xz plane). x (or P in the yz plane y )) is defined by the depth of the light absorption region 15. Typically, the thickness of the light absorption region 15 will be determined by the physical property, namely the absorption length of photons of the desired wavelength range in the semiconductor material used for the light absorption region. For detection in the visible light range using silicon as the semiconductor material, the thickness of the light absorption region will likely be 2-5 microns. The present design is particularly well suited to small pitch dimensions, and therefore small aspect ratios of 0.1 to 0.3 (or 0.4) may be possible, because the carrier transport direction is vertical rather than lateral, and because, as described above with reference to Figures 1A to 1C Compared to conventional PPD-based pixel designs of the described CMOS APS, there is virtually no lateral structure in the pixel columns.

[0053] we will Figure 3A Embodiments of the invention are referred to as vertical devices. By vertical we mean that the layers are formed epitaxially in the xy plane, which is the plane of the substrate, so that the layer sequence is in the z-direction. The structure is subdivided into individual pixels in a two-dimensional array of rows and columns (or alternatively, a one-dimensional array of rows) by insulating trenches filled with a dielectric material that electrically insulates adjacent pixels from each other. For example, the dielectric material may be a material deposited after etching, or a material generated by an oxidation process after etching. Instead of filling the trenches with dielectric material, they may be left unfilled, or only partially filled, by a thin layer of oxide or other insulating material coating the sides of the trenches. Thus, the insulating trenches extend vertically through at least one of the light absorption region and the contact region so as to subdivide the photodetector into an array of individually contactable pixels.

[0054] As shown in the figure, the semiconductor layers are deposited on a suitable substrate in the order of p+np n+ or in the reverse order. The doping of each layer can be achieved at the time of deposition, or by a post-deposition process (such as ion implantation) or a combination of the two as required. The n-type and p-type layers form the light absorption region of the detector, while the n+ and p+ layers form its contact region. The n-type and p-type layers have an interface that forms a pn junction. The n-type and p-type layers have a band gap suitable for absorbing photons of a specified wavelength (energy) range and generate electron and hole pairs that drift in opposite directions according to the electric field experienced when they were generated when the device is under forward bias, and move towards their respective potential wells, as shown in FIG. Figure 4B and Figure 4C When the device is under forward bias, electron-hole pairs generated by absorption of photons in the p-layer (as schematically shown) or in the n-layer are separated by the applied electric field induced by the forward bias. If the photon absorption is close to the pn junction, the holes initially drift towards the n+ layer, while the electrons initially drift towards the p+ layer, as shown in Figure 2. Figure 3A The electrons and holes then accumulate in their respective potential wells in the conduction and valence bands, as shown in Figure 4C Schematically shown in FIG. The substrate is not shown, but a suitable substrate, such as a p+ substrate for a pixel with an ohmic contact p+ layer, may be provided. When the structure switches from reverse bias to forward bias relative to the pn junction, electron-hole pairs generated by photon absorption initiate current flow between the contacts once a sufficient number of electrons and holes have accumulated in their respective potential wells to sufficiently reduce the potential barrier of the contacts. Consequently, there is a time delay from the reverse to forward bias switching event to the start of current flow, which is inversely proportional to the incident light intensity.

[0055] The photodetector operates by repeatedly switching from reverse bias to forward bias. Specifically, operation is achieved by applying a voltage to reverse bias the n+ and p+ contacts; the reverse bias voltage is switched to a forward bias voltage. Following this switching, electrons and holes generated in the light-absorbing region in response to photon absorption drift toward and accumulate in the corresponding conduction and valence band potential wells. The device then senses the onset of current flow between the first and second contacts. The time delay between the switching and the onset is measured, and is inversely proportional to the incident light intensity. This reverse-to-forward bias sequence is then repeated. The repeated cycles of drive and readout can be periodic or aperiodic. In the periodic case, the durations of the forward and reverse bias segments are fixed. In the aperiodic case, the reverse bias segment is of fixed duration, while the forward bias duration varies within a time window set between a minimum and maximum value in response to the incident light intensity. After the onset of current flow has occurred and the time delay has been measured, the forward bias segment of the cycle can be terminated. When there is no incident light, the forward bias duration will have a maximum value because there will be no onset of current flow, and when the incident light intensity is high, the forward bias duration will have a minimum value because the time delay will be shorter than the minimum value, but when the incident light intensity is such that the time delay for the onset of current flow is within the window, the forward bias duration has an intermediate value.

[0056] Figure 4A 、 Figure 4B and Figure 4C is a band diagram along the z direction, showing how the pixel of the device operates to sense light. Figure 4A The vertical p+, n, p, n+ structure shown in the figure applies a reverse bias RB voltage to initially reset the pixel. The pixel is then switched from reverse bias RB to forward bias FB. The energy band diagram immediately after switching to FB is shown in Figure 4B As shown. After switching to FB, the electron and hole pairs generated in the light absorption region (i.e., in the p-type layer 12 or n-type layer 14 in response to photon absorption) drift toward their respective potential wells in the conduction band and valence band and accumulate therein. Over time, as photons are absorbed, more and more holes and electrons accumulate in their respective potential wells. Therefore, the potential barrier between layers 12 and 14 and the contact layers 10 and 20 is gradually reduced until the barrier is removed, or at least small enough to allow thermal transport of carriers over the remaining barrier height, as shown in FIG. Figure 4C Current will then flow between the contacts 22, 24. The current starts to flow after a time delay that is inversely proportional to the intensity of the incident light, since a certain number of electron-hole pairs will be required to sufficiently lower the potential barrier.

[0057] The reconfiguration of RB can be generated, for example, by setting the following items, namely Figure 4A Status shown:

[0058] Vp + =Vdd / 2 and Vn + =Vdd

[0059] Where Vdd is the power supply voltage. Figure 4B and Figure 4C The FB sensing mode can be generated by way of example by setting the following:

[0060] Vp + =Vdd / 2 and Vn + =0

[0061] Figure 4A 、 Figure 4B and Figure 4C is the energy band diagram along the z direction. Figure 4A The photodetector is shown in reverse bias. Figure 4B and Figure 4C are shown with a bias voltage Vp + -Vn + forward biased photodetector. Figure 4B The situation is shown after reset (eg, directly after switching from a RB) before any photons have been absorbed, where the structure is in a non-conducting state. Figure 4C The diagram shows the situation after a sufficient number of photons have been absorbed to place the structure in a conductive state. That is, in forward bias, when the sensor has not yet absorbed any light or the amount of light is insufficient, little or no current flows between the p+ region 20 and the n+ region 10 due to the potential barrier. However, when light is incident on the forward-biased structure, the incident photons are absorbed, generating electron-hole pairs, and the sensor becomes conductive after a period of time. Specifically, under the electric field generated by the bias voltage, the holes generated by the photons drift toward the valence band potential well in the p- region 12 adjacent to the n+ contact region 10 and accumulate there, causing a lowering of the potential barrier between the p- region 12 and the n+ contact region 10. Similarly, the electrons generated by the photons drift toward the conduction band potential well in the n- region 14 adjacent to the p+ contact region 20 and accumulate there, causing a lowering of the potential barrier between the n- region 14 and the p+ region 20. In its conductive state, the sensor provides a large internal current gain. Furthermore, the positive feedback mechanism accelerates the accumulation of excess positive and negative charge carriers adjacent to the respective n+ and p+ contact regions 10, 20, which in turn reduces the associated potential barriers corresponding to these regions and, when the potential barriers have been sufficiently reduced, causes current to flow between the p+ and n+ regions of the photosensor and results in an output current when detecting or responding to incident light.

[0062] Figure 5 is a graph showing the time intervals when incident light is detected (on / hv) and when incident light is not detected (off / hv) (i.e., Figure 4C and Figure 4B As the bias voltage Vp between the n+ and p+ contact regions + -Vn + Schematic diagram of the output current of the photodetector as a function of . Note that above the threshold bias voltage, Vth, the output current in the conducting state is more or less static with varying bias voltage, assuming that the incident light intensity is measured by the trigger time rather than the current amplitude, which is the preferred operating scenario.

[0063] Figure 6A and Figure 6B The voltage Vd=Vp applied in the absence of light and in the presence of light are shown respectively. + -Vn + Oscilloscope screenshot of the output current I. The trigger time t decreases with increasing light intensity. Figure 6A The triggering time in the absence of light is shown to be t0 = 5.5 μs. Figure 6B The triggering time is shown to be t1 = 1.5 μs in the presence of light at an absorbed power of 35 nW. The switch from the low-current state to the high-current state occurs very abruptly, which facilitates accurate measurement of the delay time. The output current of 0.8 mA is more than four orders of magnitude higher than that achievable with a conventional photodiode at an absorbed power of 35 nW.

[0064] Figure 7 The graph plots the inverse trigger time 1 / t (in microseconds) as a function of the absorbed optical power A (in nanowatts). It can be seen that there is a linear relationship between the inverse of the trigger time and the absorbed optical power.

[0065] Figure 8is a schematic cross-section of a vertical photodetector array 1 according to a variation of the first embodiment, which will be largely understood from the previous discussion of the first embodiment. In this variation, each pixel 2 is composed of a group of sub-pixels 2'. As in the first embodiment, each pixel 2 is defined by a dielectric material trench 16 that extends through the entire structure, i.e., through the n+pn p+ layers, to define columns 5. The sub-pixel columns 5' of a given pixel 2 are separated from each other by dielectric material trenches 26, but the dielectric material trenches 26 extend partially, but not completely, through the structure, i.e., at least through the upper contact layer 10 (here n+) and at least partially through the upper light absorbing layer (here p) in the light absorbing layer 12, and possibly also partially through the lower light absorbing layer (here n) in the light absorbing layer 14. Thus, each pixel column 5 is subdivided into a one- or two-dimensional array of sub-pixel columns 5′ by additional insulating trenches 26. For each pixel 2, the additional insulating trenches 26 extend laterally inwardly of the pixel-defining insulating trenches 16 and vertically through one of the contact areas 10 and at least one of the light-absorbing layers 12, 14, but further than the other of the contact areas 20, so that the sub-pixel columns 5′ of any one pixel 2 remain contacted together by a common lower contact 24′. The sub-pixel columns 5′ are, however, individually contacted by corresponding upper contacts 22. This sub-pixel structure can be used to reduce internal capacitance, thereby providing improved sensitivity. With this sub-pixel structure, the trenches 26 terminate vertically above the lower contact layer 20, while the trenches 16 extend vertically completely through the doped light-absorbing layers 12, 14 and, optionally, also through the lower contact layer 20, forming an array of pixel groups, wherein each pixel group has its own lower contact 24′, which is common to the sub-pixels 2′ of the group. It will be appreciated that similar variations of the other embodiments described below will also exist, ie variations in which each pixel is subdivided into a plurality of sub-pixels.

[0066] Figure 9 is a schematic cross-section of an integrated sensor array module including a sensor array device embodying the present invention, such as the sensor array device of the first embodiment or any of the embodiments described below. Figure 3AThe photodetector sensor array device 1 shown in the figure is combined as a chip with a processor chip formed by a semiconductor circuit layer wafer structure 6 arranged on the upper contact area. The circuit layer of the processor chip includes a readout sensor array for the pixel array of the photodetector, wherein the sensor-to-pixel connection is realized by means of vias 28. In particular, the circuit layer can be a CMOS circuit layer that utilizes silicon through vias (TSVs) 28 to electrically connect it to the pixels. A bias voltage can then be applied to the n+ and p+ contact regions through the TSVs. In addition, the signal current caused by the incident light can be detected on a per-pixel basis through the TSV connections. The CMOS circuit layer is shown as being arranged on the n+ contact layer, but alternatively, it can be arranged on the p+ contact layer.

[0067] Figure 10 FIG. 1 is a schematic cross-section of another integrated sensor array module, which includes a sensor array device embodying the present invention as a chip, such as the sensor array of the first embodiment or any embodiment described below. The integrated sensor array module includes a first chip 1 formed as Figure 3A The sensor array device shown and an electronic processing device formed as a second chip 6. The processor chip 6 has corresponding electronic processing elements for the pixels of the sensor array device 1, such as a digital front-end circuit system 60 and a time-to-digital converter (TDC) element 62, and optionally also has some pixel-specific digital signal processing elements, such as an integrator or a counter. The processor chip 6 is mounted on the sensor chip 1 so that vias 28 form electrical interconnections between the processing elements of the processor chip and the contacts of the corresponding pixels in the sensor chip 1. The module optionally further includes a memory device 64 formed as a third chip 9. The memory can be a random access memory, such as a DRAM. The memory chip includes memory elements for the pixels of the sensor array, such as DRAM memory elements 64. The memory chip 9 is mounted on the processor chip 6 so that further vias 28 form electrical interconnections between the processing elements of the processor chip 6 and the corresponding memory elements of the memory chip 9. The memory chip can also be added to Figure 9 Example of .

[0068] Will Figure 9 and Figure 10 For comparison, it should be noted that Figure 9 In FIG, the processor chip 6 is on top of the sensor chip 1 (implying bottom illumination of the sensor array), while in Figure 10 In Figure 1, the processor chip 6 is below the sensor chip 1 (implying top illumination of the sensor array). This difference represents the fact that either option is possible. Figure 9 and Figure 10As shown, multiple specialized chips can be integrated, each made using a manufacturing process in materials optimized for its respective design. That is, the sensor chip 1 can be manufactured on one wafer using a dedicated optimized process, the electronic circuits for signal processing can be manufactured on another wafer to produce a digital processing chip 6 based on, for example, a high-performance CMOS process, and a third wafer can be used to manufacture the memory chip 9 using, for example, a dedicated DRAM manufacturing process.

[0069] Figure 11 The figure shows a schematic cross-section of three sensing pixels 2 in the xz plane of a sensor array device 1 according to the second embodiment. The pixel column sidewalls 18 have a highly doped cladding layer 32 formed from four distinct vertical sections 34, 36, 38, and 40, doped with n+, p+, and p+, respectively. Thus, the upper contact layer 10 and the lower contact layer 20 are electrically separated from each other by the cladding sections. The uppermost cladding section 34 is doped with the same dopant type as the upper contact layer 10, thus forming an electrical extension of the upper contact layer 10 around the pixel column 5. The uppermost section 34 terminates midway within the p-type upper light absorbing layer 12. The lowermost cladding section 40 is doped with the same dopant type as the lower contact layer 20, thus forming an electrical extension of the lower contact layer 20 around the base of the pixel column 5. The lowermost section 40 terminates midway within the n-type lower light absorbing layer 14. Additional sections 36 and 38 are arranged between sections 34 and 40. The lower portion of the p-type layer 12 is clad with a p+ cladding layer 36, and the upper portion of the n-type layer 14 is clad with an n+ cladding layer 38. In a variation, the cladding portions 36 and 38 may be omitted, and the cladding portions 34 and 40 may extend to meet at the pn junction 13. The functional aspects of the device according to this embodiment are similar to those described above with respect to FIG. Figures 4A to 7 Same as described.

[0070] Figure 12FIG2 is a schematic cross-section in the xz plane of three sensing pixels 2 of a sensor array device 1 according to a third embodiment. In this embodiment, the top contact 22 is connected to an inner portion 42 of the top contact layer 10, which is electrically insulated from its outer portion 44 by a ring of dielectric material 43. A light absorption region 15 is formed by a single layer 14 of n-type semiconductor material extending vertically between the top contact layer 10 and the lower contact layer 20. Adjacent to the inner portion 42 of the top contact layer 10, a region 17 of p-type semiconductor material is provided. This region 17 of p-type semiconductor material is laterally surrounded by the p-type layer 14 in each pixel column 5, such that the lateral boundary of the region 17 (i.e., the pn junction 13) terminates at the outer portion 44 of the top contact layer 10. The p-type region 17 is thus embedded within the epitaxial layer 14 that forms the n-type portion of the light absorption region. With regard to the sidewall doped cladding 32, referenced in this embodiment as 40, it is formed of a single dopant of the same doping type as the lower contact layer 20, in the example shown being p+, so that the doped cladding 40 on the sidewall 18 forms an electrical extension of the lower contact layer 20 around the entire height of the pixel column 5. The functional aspects of the device according to this embodiment are similar to those described above with regard to Figures 4A to 7 Same as described.

[0071] Figure 13 Figure 1 is a schematic cross-section in the xz plane of three sensing pixels of a sensor array device according to a fourth embodiment. In this embodiment, the stacking is reversed compared to the previous embodiments, with the upper contact layer 10 doped p+ and the lower contact layer 20 doped n+. Furthermore, a light-absorbing region is formed by a single layer 12 of p-type semiconductor material extending between the upper and lower contact layers 10, 20. When the device is reset by applying a reverse bias (i.e., when the lower contact 24 is held at a higher voltage than the upper contact 22), a depletion region 50 with a boundary 51 is generated in the p-type light-absorbing layer 12 adjacent to the p-type contact. Subsequently, when the device is switched to a forward bias for sensing (i.e., when the lower contact 24 is held at a lower voltage than the upper contact 22), the depletion region 50 acts as a charge sink, trapping holes that have migrated toward the p+ contact. In other words, holes generated in the light-absorbing layer in response to photon absorption initially accumulate in the depletion region, gradually eroding it. As the charge sinking effect of the depletion region 50 approaches saturation, i.e., as the depletion region gradually collapses, current begins to flow between the contacts 22, 24. The effect of establishing the depletion region 50 before switching to forward bias is that the start of current flow is delayed from the RB to FB switching event by an amount of time that is inversely proportional to the incident light intensity. Thus, the same operating principle as in the previous embodiment is achieved, but with a different layer structure.

[0072] Furthermore, in this embodiment, top contact 22 is connected to an inner portion 47 of top contact layer 10, which is separated from an outer portion 46 of top contact layer 10 by a vertical extension 45 of p-type light absorbing layer 12, thereby forming a closed loop in the xy plane. Annular extension 45 carries a gate 49 of the same ring shape, connected to gate contact 48. Gate 49 can be a CMOS gate and can be used during manufacturing to create a shadow for doping top contact layer 10 with its p+ dopant. Gate contact 49 can be driven together, for example, connected together with top contact 22, or can remain connected separately as shown. This provides greater flexibility in tailoring the shape of the depletion region during operation by applying different voltages to contacts 22 and 49, allowing for adjustment of the number of carriers that need to accumulate after switching to forward bias before the device switches from its non-conducting state to its conducting state. Thus, each pixel within its upper contact layer 10 has a portion 47 connected to the upper contact 22, separated from a surrounding portion 46 of the upper contact layer 10 by a closed loop 45 of doped semiconductor material of the light absorbing layer 14. With regard to the sidewall doped cladding 32, referenced in this embodiment as 40, it is formed from a single dopant of the same doping type as the lower contact layer 20, in the example shown being p+, so that the doped cladding 40 on the sidewall 18 forms an electrical extension of the lower contact layer 20 around the entire height of the pixel column 5. The functional aspects of the device according to this embodiment are the same as those described above with respect to Figures 4A to 7 Same as described.

[0073] Figure 14A 、 Figure 14B and Figure 14C It shows that according to Figure 13 Energy band diagram of the photodetector of the embodiment, wherein the photodetector is in a reverse bias state ( Figure 14A ), forward biased non-conductive state ( Figure 14B ) and the forward biased conduction state ( Figure 14C ). The reset in RB, i.e. Figure 14A The state shown can be generated, for example, by setting the following:

[0074] Vp + =Vg=0V and Vn + =Vdd / 2

[0075] Where Vdd is the power supply voltage. Figure 14B and Figure 14C The FB sensing mode can be generated by way of example by setting the following:

[0076] Vp + =Vg=Vdd and Vn + =Vdd / 2

[0077] Figure 15 It is based on Figure 13 The light detector of the embodiment is in the case of incident light and without incident light, that is, respectively Figure 14C and Figure 14B Plot of the output current as a function of bias voltage in the forward biased conducting and non-conducting states.

[0078] Figure 16 FIG2 is a schematic cross-section in the xz plane of three sensing pixels of a sensor array device according to a fifth embodiment. An upper contact 22, having a voltage labeled Vp+, is connected to an inner portion 53 of the upper contact layer 10, which is doped p+. An outer portion 54 of the upper contact layer 10 is doped oppositely to the inner portion 53, in this case n+. Outer portion 54 is connected to a contact 55, which has a voltage labeled Vn+ applied thereto. Contacts 22 and 55 can be driven together or with different voltages, thereby providing flexibility in customizing the shape of the depletion region 50 (i.e., the location of its boundary 51) by applying different voltages to contacts 22 and 55. This allows for adjusting the number of carriers that need to accumulate after switching to forward bias before the device switches from its non-conductive state to its conductive state. In this embodiment, each pixel further includes at least one island 52 of doped semiconductor material that is doped oppositely to the semiconductor material of the doped light absorbing layer containing the doped semiconductor material (in the example shown, there are two islands per pixel, and they are doped n+). The islands provide charge sinks within the depletion region 50 which are formed when a reverse bias voltage is applied between the upper contact 10 and the lower contact 20. Thus, each pixel has within its upper contact layer 10 a portion 53 connected to the upper contact 22 which is separated from a surrounding portion 54 of the upper contact layer 10 by a closed loop 54 of highly doped semiconductor material of the opposite dopant type, wherein the closed loop 54 has its own contact 55 and wherein the island is adjacent to the portion of the upper contact layer connected to the upper contact. In a variant illustrated by the circular inset, a single island 52 placed in the same xy plane as in the main illustration may be used. Further variants may use more than two coplanar islands. Still further variants may have multiple islands which are vertically offset and therefore lie in different xy planes. With respect to the sidewall doped cladding 32 in this embodiment, this is marked 40 and is formed of a single dopant of a doping type opposite to that of the lower contact layer 20, in the example shown p+. The functional aspects of the operation of the device according to this embodiment are the same as those described above with respect to Figures 4A to 7 Same as described.

[0079] Figure 17A 、 Figure 17B and Figure 17C It shows that according to Figure 16The energy band diagram of the photodetector of the embodiment of the invention, wherein the photodetector is in a reverse bias state, a forward bias conductive state and a forward bias non-conductive state respectively. Figure 17A The state shown can be generated, for example, by setting the following:

[0080] Vp + =Vn + =0V and Vbc=Vdd / 2

[0081] Among them, by way of example, you can generate by setting the following items Figure 17B and Figure 17C FB sensing mode:

[0082] Vp + =Vn + =Vdd and Vbc = Vdd / 2

[0083] Figure 18 It is based on Figure 16 The light detector of the embodiment, in the case of incident light and without incident light, that is, respectively Figure 17C and Figure 17B Plot of the output current as a function of bias voltage in the forward biased conducting and non-conducting states.

[0084] It should be noted that the term "circuit" may particularly refer to a single component or multiple components (whether in the form of an integrated circuit or otherwise) that are active and / or passive and coupled together to provide or perform a desired function. The term "circuitry" may particularly refer to a circuit (whether integrated or otherwise), a group of such circuits, one or more processors, one or more state machines, one or more processors implementing software, one or more gate arrays, programmable gate arrays and / or field programmable gate arrays, or a combination of one or more circuits (whether integrated or otherwise), one or more state machines, one or more processors implementing software, one or more gate arrays, programmable gate arrays and / or field programmable gate arrays. The term "data" may particularly refer to (one or more) current or voltage signals, whether in analog or digital form, which may be a single bit(s) or multiple bits(s).

[0085] It should also be noted that the various circuits and circuit systems disclosed herein can be described using computer-aided design tools and, for example, expressed (or represented) in terms of their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics as data and / or instructions embodied in various computer-readable media. Files and other object formats that can implement such circuit expressions include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register-level description languages such as RTL, and formats supporting geometric description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media that can embody such formatted data and / or instructions include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media) and carrier waves that can be used to transmit such formatted data and / or instructions via wireless, optical, or wired signaling media, or any combination thereof. Examples of transmitting such formatted data and / or instructions via carrier waves include, but are not limited to, transmission (upload, download, email, etc.) over the Internet and / or other computer networks via one or more data transmission protocols (e.g., HTTP, FTP, SMTP, etc.). The present embodiments also relate to such representations of the circuitry described herein and / or techniques implemented thereby, and are therefore intended to fall within the scope of the present embodiments.

[0086] In practice, when received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the aforementioned circuitry can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs (including, but not limited to, netlist generation programs, placement and routing programs, etc.) to generate a representation or image of the physical manifestation of such circuitry. Such representation or image can then be used in device fabrication, for example, by enabling the generation of one or more masks for forming various components of the circuitry during device fabrication.

[0087] In addition, the various circuits and circuit systems and technologies disclosed herein can be represented by simulation and expressions based on simulation instructions using computer-aided design, simulation and / or testing tools. The simulation of the circuit system (including light detectors and / or the technology implemented thereby) of the present embodiment can be implemented by a computer system, wherein the characteristics and operation of such circuit system and the technology implemented thereby are simulated, imitated, copied, analyzed and / or predicted via a computer system. The present embodiment also relates to such simulation and testing of the apparatus and / or circuit system of the present invention and / or the technology implemented thereby, and is therefore intended to fall within the scope of the present embodiment. Computer-readable media and data corresponding to such simulation and / or testing tools are also intended to fall within the scope of the present embodiment.

[0088] In summary, in the detailed description above, we have described a photodetector sensor array device suitable for use as a camera chip, having a structure including upper and lower contact layers of n+ and p+ semiconductor materials on either side of a light-absorbing region. The light-absorbing region is made of a single layer of doped semiconductor material (p or n) or two layers of oppositely doped semiconductor material (forming a pn junction). The pixel array is formed by etching trenches through at least a portion of the layers, which are then filled with a dielectric material, optionally after first doping the sidewalls of the pixel columns to passivate surface defects at or near the sidewalls. The upper and lower contacts are connected to the upper and lower contact layers so that appropriate voltages can be applied to the pixels during operation. In each operating cycle, the device is first reset with reverse bias and then switched to forward bias for sensing. After switching to forward bias, carriers generated in the light-absorbing region in response to photon absorption accumulate in a potential well. The carriers do not immediately cause current to flow between the contacts because carrier accumulation is first required to reduce the potential barrier between the light-absorbing region and the contacts. The current will then begin to flow following the time delay characteristic of the potential barrier, wherein the time delay is inversely proportional to, and is therefore a measure of, the incident light intensity.

[0089] It will be apparent to those skilled in the art that many improvements and modifications can be made to the foregoing exemplary embodiments without departing from the scope of the present disclosure.

[0090] Reference numerals

[0091] Reference Digital Project

[0092] 1 Sensor array (chip / device)

[0093] 2 pixels

[0094] 2' sub-pixel

[0095] 3 Silicon-on-insulator wafer substrate

[0096] 4 Insulator for gate

[0097] 5 pixel columns / photodetector

[0098] 5' sub-pixel column

[0099] 6 CMOS electronic chips

[0100] 7 Silicon Wafer

[0101] 8 Insulator layer

[0102] 9 DRAM memory chips

[0103] 10 Highly doped contact layer (n+)

[0104] 12 Upper part of the light absorbing layer (p)

[0105] 13 pn junction

[0106] 14 Lower part of the light absorbing layer (n)

[0107] 15 Light absorption layer

[0108] 16 dielectric trenches (between pixels)

[0109] 17 Upper region of the light absorbing layer (p)

[0110] 18 side walls

[0111] 20 Lower highly doped contact layer (p+)

[0112] 22 Upper Contact

[0113] 24 Lower Contact

[0114] 24' Common lower contact for sub-pixel group

[0115] 25 Control circuit systems / electronic devices

[0116] 26 dielectric trenches (within pixel)

[0117] 28 vias

[0118] 30 Fiber Optic

[0119] 32 Sidewall doped cladding

[0120] 34 Forming the sidewall cladding of the electrical extension of the upper contact layer 10

[0121] 36 Intermediate sidewall cladding

[0122] 38 Intermediate sidewall cladding

[0123] 40 forming the sidewall cladding of the electrical extension of the lower contact layer 20

[0124] 42 Internal portion of layer 10 connected to contact 22

[0125] 43 Dielectric ring around 42 in layer 10

[0126] 44 External portion of layer 10 isolated from contact 22

[0127] 45 Closed loop at the top of the light absorbing layer

[0128] 46 Outer portion of layer 10 separated from contact 24

[0129] 47 Inner portion of layer 10 connected to contact 24

[0130] 48 Gate contact

[0131] 49 Gate (ring)

[0132] 50 Transient depletion region adjacent to layer 10

[0133] 51 Boundary of depletion region 50

[0134] 52 Islands in the light absorbing layer 12

[0135] 53 Inner portion of layer 10 connected to contact 22

[0136] 54 External portion of layer 10 connected to contact 55

[0137] Contact from 55 to 54

[0138] 60 Digital front-end circuit system

[0139] 62 Time-to-Digital Converter (TDC) and Digital Signal Processor

[0140] 64 DRAM memory

Claims

1. A sensor array device having an array of sensing pixels, the device comprising: an upper contact layer, the upper contact layer being composed of a highly doped p-type or n-type semiconductor material; a lower contact layer, the lower contact layer being composed of a highly doped n-type or p-type semiconductor material of the opposite type to that of the upper contact layer; a light absorbing layer of a doped semiconductor material, the light absorbing layer sandwiched between the upper contact layer and the lower contact layer, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; a grid of insulating trenches of dielectric material extending vertically through at least a portion of the doped light absorbing layer and the upper contact layer to subdivide the upper contact layer and at least a portion of the doped light absorbing layer into an array of laterally adjacent, independently contactable columns of semiconductor material forming the pixels; as well as an upper contact and a lower contact connected to corresponding pixels of the upper contact layer and the lower contact layer, such that after a voltage applied between the upper contact and the lower contact of a pixel is switched from a reverse bias to a forward bias, carriers generated in the light absorbing layer in response to absorption of photons accumulate in the light absorbing layer, which causes current to begin to flow between the upper contact and the lower contact after a time delay that is inversely proportional to the intensity of light incident on the device, The doped light absorbing layer is subdivided into oppositely doped upper and lower layers of semiconductor material, which are arranged together with the oppositely doped upper and lower contact layers in a vertical doping sequence of n+pnp+.

2. The device according to claim 1, wherein The columns of semiconductor material forming the pixels have an aspect ratio less than 1, the aspect ratio being defined by the depth of the light absorbing layer being greater than the lateral spacing between adjacent pixels.

3. The device according to claim 1, wherein The doped light absorbing layer extends between the upper contact layer and the lower contact layer with a single type of doping and is configured such that in each pixel, generating a charge sink in the doped light absorbing layer adjacent to one of the upper contact and the lower contact when a reverse bias voltage is applied between the upper contact and the lower contact, and When the voltage is switched from reverse bias to forward bias, carriers generated in the light absorbing layer in response to photon absorption are initially accumulated at a charge sink, and then, after the charge sink approaches saturation, current begins to flow between the upper contact and the lower contact, with the start of current flow occurring after a time delay from the switching, the time delay being inversely proportional to the intensity of the incident light.

4. The device according to claim 3, wherein Each of the pixels within its upper contact layer has a portion connected to the upper contact, which is separated from a surrounding portion of the upper contact layer by a closed loop of the doped semiconductor material of the light absorbing layer, so that when a reverse bias voltage is applied between the upper contact and the lower contact, the charge sink is provided by a depletion region formed around the portion of the upper contact layer connected to the upper contact.

5. The device of claim 3 , wherein each pixel further comprises at least one island of doped semiconductor material, the at least one island of doped semiconductor material being oppositely doped to the semiconductor material of the doped light absorbing layer in which the at least one island is contained, such that when a reverse bias voltage is applied between the upper contact and the lower contact, the charge sink is provided by forming a depletion region at the island.

6. The device according to claim 5, wherein The pixels within their upper contact layer each have a portion connected to the upper contact, the portion being separated from a surrounding portion of the upper contact layer by a closed loop of highly doped semiconductor material of opposite dopant type, wherein the closed loop has its own contact, and wherein the island is adjacent to the portion of the upper contact layer connected to the upper contact.

7. The device according to claim 1, wherein The columns of semiconductor material forming the pixels have sidewalls adjacent to the dielectric material of the trenches, the sidewalls having a highly doped cladding over at least a portion of their vertical extent.

8. The device according to claim 7, wherein At least a lower portion of the sidewall has a highly doped cladding layer such that the highly doped cladding layer forms an electrical extension of the lower contact layer around the column, wherein the highly doped cladding layer has a dopant of the same doping type as the lower contact layer.

9. The device according to claim 7, wherein At least an upper portion of the sidewall has a highly doped cladding layer such that the highly doped cladding layer forms an electrical extension of the upper contact layer around the column, wherein the highly doped cladding layer has dopants of the same doping type as the upper contact layer.

10. The device according to claim 9, wherein The lower contact layer and the upper contact layer are electrically separated from each other by a first highly doped sidewall cladding portion and a second highly doped sidewall cladding portion, so that the lower contact layer and the upper contact layer and the first highly doped sidewall cladding portion and the second highly doped sidewall cladding portion are in a vertical doping order of p+n+p+n+.

11. The device according to claim 1, wherein The trench terminates vertically above the lower contact layer, and wherein the lower contact is a blanket contact for the array.

12. The device according to claim 1, wherein The trench further extends vertically completely through the doped light absorbing layer and also through the lower contact layer, and wherein the lower contact comprises an array of contacts connected to respective pixels of the lower contact layer.

13. The device according to claim 1, wherein Some of the trenches terminate vertically above the lower contact layer, while other dielectric trenches extend vertically completely through the doped light absorbing layer and the lower contact layer, so that an array of pixel groups is formed, wherein each pixel group has its own lower contact common to the pixels of the pixel group.

14. An integrated sensor array module, comprising: The sensor array device according to claim 1; as well as a processor device comprising an array of pixel-specific processing elements for the pixels of the sensor array device, The processor device is mounted on the sensor array device such that a via forms an electrical connection between each of the pixel-specific processing elements of the processor device and a pixel contact of a corresponding pixel in the sensor array device.

15. The integrated sensor array module according to claim 14, further comprising: a memory device comprising pixel-specific memory elements for the pixels of the sensor array device, The memory device is mounted on the processor device such that further vias form an electrical connection between each of the pixel-specific processing elements of the processor device and the pixel-specific memory element in the memory device.

16. A method of manufacturing a photodetector device comprising a sensing pixel, the method comprising: Fabricating a semiconductor epitaxial structure, the semiconductor epitaxial structure comprising: an upper contact layer, the upper contact layer composed of a highly doped p-type or n-type semiconductor material; a lower contact layer, the lower contact layer composed of a highly doped n-type or p-type semiconductor material of an opposite type to the upper contact layer; and a light absorbing layer of a doped semiconductor material, the light absorbing layer sandwiched between the upper contact layer and the lower contact layer, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; etching a grid of trenches perpendicularly through at least a portion of the doped light absorbing layer and the upper contact layer to subdivide the upper contact layer and at least a portion of the doped light absorbing layer into an array of laterally adjacent, independently contactable columns of semiconductor material that will form the pixels; filling the trenches with a dielectric material to render them insulating; and providing upper and lower contacts for pixels of the upper and lower contact layers, such that in the photodetector device, after a voltage applied between the upper and lower contacts of a pixel is switched from a reverse bias to a forward bias, carriers generated in the light absorbing layer in response to absorption of photons accumulate in the light absorbing layer, causing current to begin flowing between the upper and lower contacts after a time delay that is inversely proportional to the intensity of light incident on the device, The doped light absorbing layer is subdivided into oppositely doped upper and lower layers of semiconductor material, which are arranged together with the oppositely doped upper and lower contact layers in a vertical doping sequence of n+pnp+.

17. A method of operating a photodetector device comprising a sensing pixel, the method comprising: A photodetector device is provided, the photodetector device having: an upper contact layer, the upper contact layer being composed of a highly doped p-type or n-type semiconductor material; a lower contact layer, the lower contact layer being composed of a highly doped n-type or p-type semiconductor material of the opposite type to that of the upper contact layer; a light absorbing layer of a doped semiconductor material, the light absorbing layer sandwiched between the upper contact layer and the lower contact layer, the light absorbing layer being configured to generate oppositely charged carrier pairs in response to absorption of photons when light is incident on the device; a grid of insulating trenches of dielectric material extending vertically through at least a portion of the doped light absorbing layer and the upper contact layer to subdivide the upper contact layer and at least a portion of the doped light absorbing layer into an array of laterally adjacent, independently contactable columns of semiconductor material forming the pixels; as well as upper contacts and lower contacts of corresponding pixels connected to the upper contact layer and the lower contact layer; The photodetector device is operated by repeating the following: applying a reverse bias voltage between the upper contact and the lower contact; switching the reverse bias voltage to a forward bias voltage so that carriers subsequently generated in the light absorbing layer in response to photon absorption are accumulated in the light absorbing layer; as well as sensing the onset of current flow between the upper contact and the lower contact and measuring a time delay between the switching and the onset, wherein the time delay is inversely proportional to the intensity of light incident on the device, The doped light absorbing layer is subdivided into oppositely doped upper and lower layers of semiconductor material, which are arranged together with the oppositely doped upper and lower contact layers in a vertical doping sequence of n+pnp+.

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