Driving substrate and manufacturing method thereof, display device

Abstract

The application discloses a driving substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The driving substrate comprises a substrate (1), a stress buffer layer (2) on the substrate (1), a plurality of first wirings (3) on the side, away from the substrate (1), of the stress buffer layer (2), a first insulating layer (6) on the side, away from the substrate (1), of the first wirings (3), a plurality of second wiring structures (4) on the side, away from the substrate (1), of the first insulating layer (6), wherein each first wiring (3) is connected with at least one second wiring structure (4) through a first via penetrating through a second insulating layer (12), a second insulating layer (12) on the side, away from the substrate (1), of the second wiring structure (4), and an electronic element (7) on the side, away from the substrate (1), of the second insulating layer (12), wherein the electronic element (7) is connected with the second wiring structure (4) through a second via penetrating through the second insulating layer (12). The number of patterning processes for manufacturing the driving substrate can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly refers to a driving substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] The HDR (High-Dynamic Range) technology realizes high-contrast and high-gamut display effects. In a display device with the HDR technology, a large number of signal traces are needed to transmit electrical signals. Therefore, how to manufacture a signal trace capable of bearing a large load to reduce the line resistance loss is one of the technical problems to be considered in the semiconductor field. SUMMARY

[0003] Embodiments of the present disclosure provide a driving substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the driving substrate.

[0004] Embodiments of the present disclosure provide technical solutions as follows:

[0005] In one aspect, a driving substrate is provided, comprising:

[0006] a substrate substrate;

[0007] a stress buffer layer located on the substrate substrate;

[0008] a plurality of first traces located on a side of the stress buffer layer away from the substrate substrate, the first traces having a first thickness;

[0009] a first insulating layer located on a side of the first traces away from the substrate substrate;

[0010] a plurality of second trace structures located on a side of the first insulating layer away from the substrate substrate, each of the first traces being connected to at least one of the second trace structures through a first via penetrating the first insulating layer, the second trace structures having a second thickness, the second thickness being smaller than the first thickness;

[0011] a second insulating layer located on a side of the second trace structures away from the substrate substrate;

[0012] an electronic element located on a side of the second insulating layer away from the substrate substrate, the electronic element being connected to the second trace structures through a second via penetrating the second insulating layer.

[0013] In some embodiments, the first traces include a copper layer and a first metal layer arranged in a stack, the first metal layer being located on a side of the copper layer close to the substrate substrate, and an adhesion of the first metal layer to the stress buffer layer being greater than an adhesion of the copper layer to the stress buffer layer.

[0014] In some embodiments, the thickness of the copper layer is 1-30 um.

[0015] In some embodiments, the first trace further comprises a first conductive protective layer on the side of the copper layer close to the substrate.

[0016] In some embodiments, the second trace structure comprises at least one second trace layer, each of the second trace layers comprises a plurality of second traces, when the second trace layers are multiple layers, there is an insulating layer between any two adjacent second trace layers, from the side close to the substrate to the side far from the substrate, each second trace of a previous layer is connected to at least one second trace of a subsequent layer, and each second trace of the last layer is connected to at least one electronic component.

[0017] In some embodiments,

[0018] The second trace comprises a copper layer and a second metal layer stacked together, the second metal layer is on the side of the copper layer close to the substrate, and the adhesion of the second metal layer to the first insulating layer is greater than the adhesion of the copper layer to the first insulating layer.

[0019] In some embodiments, the driving substrate comprises a display area and a fan-out area around the display area, and the driving substrate further comprises:

[0020] A second conductive protective layer covering the second trace of the fan-out area.

[0021] In some embodiments, the first insulating layer comprises:

[0022] A first inorganic insulating layer and a first organic insulating layer stacked together, the first organic insulating layer is on the side of the first inorganic insulating layer far from the substrate.

[0023] In some embodiments, the driving substrate further comprises:

[0024] A fourth inorganic insulating layer on the side of the first organic insulating layer far from the substrate, and the second trace structure is on the side of the fourth inorganic insulating layer far from the substrate.

[0025] The present disclosure also provides a display device comprising the driving substrate as described above.

[0026] The present disclosure also provides a manufacturing method of a driving substrate, comprising:

[0027] Providing a substrate;

[0028] Forming a stress buffer layer on the substrate;

[0029] forming a plurality of first traces on the stress buffer layer by a one-time patterning process, the first traces having a first thickness;

[0030] forming a first insulating layer covering the first traces, the first insulating layer including first vias exposing part of surfaces of the first traces;

[0031] forming a plurality of second trace structures on the first insulating layer, each of the first traces being connected to at least one of the second trace structures through a first via penetrating the first insulating layer, the second trace structures having a second thickness, the second thickness being less than the first thickness;

[0032] forming a second insulating layer covering the second trace structures, the second insulating layer including second vias exposing part of surfaces of the second trace structures;

[0033] disposing electronic elements on the second insulating layer, the electronic elements being connected to the second trace structures through second vias penetrating the second insulating layer.

[0034] In some embodiments, forming the first traces comprises:

[0035] depositing a first conductive layer having the first thickness on the stress buffer layer, patterning the first conductive layer to form the first traces.

[0036] In some embodiments, forming the first traces comprises:

[0037] depositing a seed layer having a thickness less than the first thickness on the stress buffer layer, forming a negative photoresist on the seed layer, exposing and developing the photoresist to form photoresist removal areas and photoresist retention areas, the photoresist removal areas corresponding to the first traces to be formed;

[0038] growing a third conductive layer on the seed layer having the pattern of the photoresist by an electroplating method;

[0039] removing the photoresist in the photoresist retention areas;

[0040] etching the seed layer after the photoresist is removed, the third conductive layer and the seed layer in the photoresist removal areas forming the first traces.

[0041] In some embodiments, forming the first traces comprises:

[0042] depositing a seed layer with a thickness less than the first thickness on the stress buffer layer, forming a photoresist on the seed layer, exposing and developing the photoresist to form a photoresist removal area and a photoresist reserved area, the photoresist reserved area corresponding to the first trace to be formed, etching the seed layer in the photoresist removal area to form a pattern of the seed layer;

[0043] growing a third conductive pattern on the pattern of the seed layer by electroplating, the third conductive pattern and the pattern of the seed layer forming the first trace.

[0044] In some embodiments, before growing the third conductive pattern on the pattern of the seed layer by electroplating, the method further comprises:

[0045] forming a third inorganic insulating layer;

[0046] forming a third organic insulating layer on the third inorganic insulating layer;

[0047] exposing and developing the third organic insulating layer to form a pattern of the third organic insulating layer, the pattern of the third organic insulating layer including a third organic insulating layer reserved area and a third organic insulating layer removal area, the third organic insulating layer removal area coinciding with an area where the pattern of the seed layer is located;

[0048] etching the third inorganic insulating layer using the pattern of the third organic insulating layer as a mask to form a pattern of the third inorganic insulating layer.

[0049] In some embodiments, the first insulating layer includes a first inorganic insulating layer and a first organic insulating layer arranged in a stack, and forming the first insulating layer includes:

[0050] forming a first inorganic insulating layer;

[0051] forming a first organic insulating layer;

[0052] exposing and developing the first organic insulating layer to form a pattern of the first organic insulating layer including a third via, etching the first inorganic insulating layer using the pattern of the first organic insulating layer as a mask to form a pattern of the first inorganic insulating layer including a fourth via, the third via and the fourth via being in communication to form the first via.

[0053] In some embodiments, the second trace structure includes at least one second trace layer, each of the second trace layers including a plurality of second traces, and forming the second traces on the first insulating layer includes:

[0054] sputtering a second conductive layer on the first insulating layer, and patterning the second conductive layer to form the second traces; or

[0055] A second conductive layer is formed on the first insulating layer by low-temperature deposition, the second conductive layer is patterned, and the second trace is formed. The temperature of the low-temperature deposition is not greater than 50 degrees Celsius. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 A schematic diagram of a display area of a substrate driven by an embodiment of the present disclosure;

[0057] Figure 2 A schematic diagram of a manufacturing process of a substrate driven by an embodiment of the present disclosure. Figure 1 An equivalent circuit diagram of the middle C part;

[0058] Figures 3-22 A schematic diagram of a manufacturing process of a substrate driven by an embodiment of the present disclosure.

[0059] REFERENCE NUMERALS

[0060] 1 substrate; 2 stress buffer layer; 3 first trace; 31 first metal layer; 32 copper layer; 4 second trace; 41 second metal layer; 42 copper layer; 6 first insulating layer; 61 first inorganic insulating layer; 62 first organic insulating layer; 8 fourth inorganic insulating layer; 12 second insulating layer; 13 second conductive protective layer; 14 light reflection pattern; 15 first metal layer; 16 copper layer; 17, 19 photoresist pattern; 18 third conductive layer; 20 third conductive pattern; 21 third inorganic insulating layer; 22 third organic insulating layer; 51 anode trace; 52 cathode trace; 53 connecting line; 7 LED; 71 N pad; 72 P pad; 73 epitaxial layer DETAILED DESCRIPTION

[0061] To make the technical problems, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be described in detail with reference to the drawings and specific embodiments.

[0062] The HDR (High-Dynamic Range) technology can significantly enhance the contrast ratio of a liquid crystal display and the viewing experience, and perfect HDR requires high contrast ratio and excellent color performance. The partition-controlled surface light source can realize the HDR technology and greatly improve the display effect. When the surface light source is composed of LED chips arranged in an array, a large current is required for driving the LED to emit light. In order to minimize the loss of the electrical signal in the signal line, thick copper process (copper with a thickness of 1-20 μm) is required to make the traces of the LED substrate. In the related art, the LED is bound to a printed circuit board, and the printed circuit board is usually small in size due to cost constraints. Therefore, if a large-size LED surface light source is required, the small-size printed circuit boards need to be spliced together. However, the splicing position of the adjacent printed circuit boards needs to be left for the FPC (Flexible Printed Circuit) binding position, which will cause the frame of the LED surface light source to be very wide (usually centimeter level), affecting the resolution and display effect of the display product.

[0063] The inventors find that the signal line for driving the LED can be made on a large-size glass substrate, thereby forming a large-size surface light source without splicing to reduce the production cost. However, the glass substrate is relatively brittle, and the stress generated when forming a copper layer with a large thickness on the glass substrate will cause the glass substrate to be fragmented.

[0064] In order to reduce the stress generated when forming a copper layer with a large thickness, a plurality of thin copper layers can be formed by a plurality of patterning processes, and the plurality of thin copper layers can be combined to form a copper layer with a large thickness. However, this will cause the number of patterning processes for manufacturing the driving substrate to be large, which will affect the production cycle of the driving substrate and cause the production cost of the driving substrate to be large.

[0065] Embodiments of the present disclosure provide a driving substrate and a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the driving substrate.

[0066] Embodiments of the present disclosure provide a driving substrate, comprising:

[0067] A substrate substrate; a stress buffer layer on the substrate substrate; a plurality of first traces on a side of the stress buffer layer away from the substrate substrate, the first traces having a first thickness; a first insulating layer on a side of the first traces away from the substrate substrate; a plurality of second trace structures on a side of the first insulating layer away from the substrate substrate, each of the first traces being connected to at least one of the second trace structures through a first via penetrating the first insulating layer, the second trace structures having a second thickness, the second thickness being less than the first thickness; a second insulating layer on a side of the second trace structures away from the substrate substrate; and an electronic element on a side of the second insulating layer away from the substrate substrate, the electronic element being connected to the second trace structures through a second via penetrating the second insulating layer.

[0068] By providing the stress buffer layer, the stress generated when forming the conductive layer on the substrate substrate can be relieved, so that the substrate substrate will not be broken, so that a conductive layer with a larger thickness can be formed on the substrate substrate, and the conductive layer with a larger thickness is used to make the first traces with the first thickness through a one-time patterning process. The thickness of the first traces is relatively large, which can meet the resistivity requirement of the driving substrate for the traces, and can drive the electronic element arranged on the substrate substrate to realize a large-size driving substrate. In this way, the first traces with the first thickness do not need to be formed through multiple patterning processes, which can reduce the number of patterning processes for manufacturing the driving substrate.

[0069] Specifically, the first thickness can be greater than 1 μm.

[0070] The greater the thickness of the conductive layer, the greater the stress generated when forming the conductive layer, and the greater the thickness of the stress buffer layer, that is, the thickness of the stress buffer layer is positively correlated with the thickness of the first traces. For example, when the first thickness is 2 um, the thickness of the stress buffer layer can be 1500 angstroms; when the first thickness is 5 um, the thickness of the stress buffer layer can be 3000 angstroms.

[0071] In order to avoid short circuit, the orthographic projection of the first via on the substrate substrate does not exceed the orthographic projection of the first trace on the substrate substrate, that is, the aperture of the orthographic projection of the first via on the substrate substrate is not greater than the line width of the orthographic projection of the first trace on the substrate substrate. The substrate substrate can be a glass substrate or a quartz substrate. The size of the substrate substrate can reach 3m*3m or more, so that the technical solution of the present disclosure can realize mass production of large-size driving substrates. The electronic element can be an LED with a size in the micron level, that is, the technical solution of the present disclosure can realize a large-size LED substrate.

[0072] To improve the density of electronic components on the driving substrate, the second trace structure can include at least one second trace layer, each second trace layer including a plurality of second traces, and an insulating layer between adjacent two second trace layers, each second trace of a previous layer being connected to at least one second trace of a next layer from the direction close to the substrate to the direction away from the substrate, and each second trace of the last layer being connected to at least one electronic component.

[0073] To avoid short circuit, the orthographic projection of the second via on the substrate is not beyond the orthographic projection of the second trace on the substrate, i.e. the aperture of the orthographic projection of the second via on the substrate is not larger than the line width of the orthographic projection of the second trace on the substrate. In a specific embodiment, the trace structure can include a first trace layer and a second trace layer, the first trace layer including a plurality of mutually insulated first traces, and the second trace layer including a plurality of mutually insulated second traces, each first trace being connected to at least one second trace through a via penetrating the first insulating layer, and each second trace being connected to at least one electronic component through a via penetrating the second insulating layer.

[0074] In the embodiment, the first trace can be connected to a plurality of second traces, the first trace transmitting large current, so the thickness of the first trace is large; the second trace is mainly used for connecting electronic components, the current on the second trace being relatively small compared to the current transmitted by the first trace, and the thickness of the second trace can also be small, specifically, the second thickness can be 0.6-0.9um.

[0075] Figure 1 A plan view of the display area of the driving substrate in the embodiment of the present disclosure, the driving substrate including a display area and a fan-out area located at the periphery of the display area as shown in Figure 1 The left half of Figure 7 The right half of Figure 1 The cross-sectional view of the display area of the driving substrate in the DD' direction as shown in Figure 7 The cross-sectional view of the fan-out area of the driving substrate, wherein the display area is provided with electronic components for emitting light; and the fan-out area is used for binding with a flexible circuit board or a printed circuit board. As shown in Figure 7As shown, in an embodiment, taking the electronic component as an example, the LED, the driving substrate comprises: a substrate 1; a stress buffer layer 2 on the substrate 1; a first trace 3 on the stress buffer layer 2, the first trace 3 is composed of a first metal layer 31 and a copper layer 32; a first insulating layer 6 covering the first trace 3, the first insulating layer 6 comprises a first inorganic insulating layer 61 and a first organic insulating layer 62; a second trace 4 on the first insulating layer 6, the second trace 4 is composed of a second metal layer 41 and a copper layer 42; a second insulating layer 12 covering the second trace 4; an LED 7 on the second insulating layer 12, the LED 7 is connected with the second trace 4 through a via hole penetrating the second insulating layer 12, the second trace 4 can be connected with multiple LEDs 7, and plays a role of connecting adjacent LEDs 7. As shown in the figure, Figure 7 As shown, each LED 7 comprises an epitaxial layer 73, an N pad 71 and a P pad 72, and the N pad 71 and the P pad 72 of the LED 7 are connected with the second trace 4 at different positions through a via hole penetrating the second insulating layer 12.

[0076] Specifically, as shown in the figure, Figure 1 The second trace 4 is divided into multiple groups arranged in an array. In some embodiments, each group of second traces 4 connects four LEDs 7, and each group of second traces 4 can be distributed in a substantially square ring shape. Of course, each group of second traces 4 is not limited to forming a ring shape, and can also be other shapes.

[0077] Figure 2 For Figure 1 As shown in the equivalent circuit diagram of the C part, Figure 2 As shown in the figure, each group of second traces 4 comprises an anode trace 51, a connecting line 53 and a cathode trace 52, each group of second traces 4 connects four LEDs, and the four LEDs are connected in a two-in-two-out manner, wherein the anode trace 51 connects the anodes of two LEDs, the cathode trace 52 connects the cathodes of the two LEDs, and the connecting line 53 connects the anode of one LED and the cathode of the adjacent LED.

[0078] Since the current load of the driving substrate can reach tens of milliamperes, the resistance performance of the trace is required to be high, and a metal with small resistance needs to be used, otherwise the heat generation of the trace will be large, which will cause the temperature to be too high. The conductive performance of copper is superior, therefore, copper is used as the main body of the first trace 3. Of course, the first trace 3 is not limited to using copper, and other metals such as silver and aluminum can also be used. As shown in the figure, Figure 7As shown, the first trace 3 includes a copper layer 32, and the thickness of the copper layer 32 can be adjusted according to the current load, and the greater the current load, the greater the thickness of the copper layer 32. The thickness of the copper layer 32 can be 1-30 μm, and in some embodiments, can be 2 μm. The copper layer 32 can be formed by sputtering, electroplating, chemical plating, etc., and the stress buffer layer 2 can be formed by using one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the stress direction of the copper layer 32 formed is opposite, so that the stress generated when the copper layer 32 is formed can be offset, and the substrate 1 can be prevented from being broken. The thickness of the stress buffer layer 2 can be 500-3000 angstroms.

[0079] The compressive stress refers to the stress resisting the compression tendency of the object, and the tensile stress is the reaction force of the object to the external force that causes the object to have a stretching tendency. The stress directions of the compressive stress and the tensile stress are opposite, and the stress increases with the increase of the thickness of the film layer. The copper layer 32 exhibits tensile stress, and the stress buffer layer 2 exhibits compressive stress. Taking the case of using silicon nitride as the stress buffer layer 2, a layer of silicon nitride exhibiting compressive stress is first deposited on the substrate, and then a layer of copper layer exhibiting tensile stress is deposited. Since the stress directions of the stress buffer layer and the copper layer are opposite, the stress is offset, and thus the warpage of the substrate can be greatly reduced. It has been verified through experiments that the copper layer with a thickness of 3 μm can be formed on the substrate by increasing the stress buffer layer, and at this time, the warpage of the substrate is only equivalent to that of the substrate on which the copper layer with a thickness of 1 μm is formed without the stress buffer layer. The copper layer with a thickness of 3 μm can be used to prepare the first trace 3 with resistance performance meeting the requirements, and thus the first trace 3 can be prepared by one patterning process using the copper layer with a thickness of 3 μm, and there is no need to form multiple thin copper layers to form the first trace 3 with a relatively large thickness by multiple patterning processes.

[0080] In some embodiments, as shown in FIG. 7, the first trace 3 further includes a first metal layer 31 located on the side of the copper layer 32 close to the substrate 1, and the adhesion of the first metal layer 31 to the stress buffer layer 2 is greater than that of the copper layer 32 to the stress buffer layer 2. In this way, the adhesion of the first trace 3 to the stress buffer layer 2 can be increased by the first metal layer 31, and the first trace 3 can be prevented from falling off the substrate 1. Specifically, the first metal layer 31 can be at least one of Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and can also be IGZO, IZO, GZO, ITO, and other metal oxides. The thickness of the first metal layer 31 does not need to be set to be large, and can be 200-500 angstroms.

[0081] Since the surface of the copper layer 32 is easy to be oxidized after contacting with air, affecting the conductive performance, in some embodiments, the first trace 3 can further include a first conductive protective layer on the side of the copper layer 32 away from the substrate 1. The first conductive protective layer can be made of a metal or a transparent conductive material which is not easy to be oxidized. Specifically, the first conductive protective layer can be made of at least one of Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi. The first conductive protective layer can avoid the surface of the copper layer 32 from being oxidized. The thickness of the first conductive protective layer can be 50-500 angstroms.

[0082] The first insulating layer 6 is arranged on the first trace 3. As shown in Figure 7 , the first insulating layer 6 includes a first inorganic insulating layer 61 which can be made of an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, etc. to protect the first trace 3 from being oxidized in subsequent high-temperature processes. The thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms. Due to the limitation of the process, the thickness of the first inorganic insulating layer 61 is smaller than the thickness of the first trace 3 and cannot meet the requirement of planarization. The first insulating layer 6 further includes a first organic insulating layer 62 which can be made of an organic insulating material with a larger thickness, such as organic resin, etc. to fill the recesses between the patterns of the first trace 3, provide a flat surface for subsequent processes, and avoid large steps in subsequent processes, so that the LED displacement problem does not occur when the LED is bonded. The total thickness of the first insulating layer 6 should be greater than or equal to the thickness of the first trace 3, and can be 1-30 μm.

[0083] The second trace 4 is arranged on the first insulating layer 6. Since the second trace 4 serves to connect the anode and / or cathode pins of the LEDs, the thickness of the second trace 4 does not need to be too large and can be 3000-9000 angstroms, specifically 6000 angstroms. Since the conductive performance of copper is superior, the second trace 4 can be made of copper. Figure 7 As shown in Figure 7 , the second trace 4 includes a copper layer 42 which can be completed by low-temperature deposition, sputtering, electroplating, chemical plating, etc. In some embodiments, as shown in Figure 7 , the second trace 4 further includes a second metal layer 41 on the side of the copper layer 42 close to the substrate 1. The adhesion of the second metal layer 41 to the first insulating layer 6 is greater than the adhesion of the copper layer 42 to the first insulating layer 6. In this way, the adhesion of the second trace 4 to the first insulating layer 6 can be increased by the second metal layer 41 to prevent the second trace 4 from falling off the substrate 1. Specifically, the second metal layer 41 can be made of at least one of Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and can also be made of metal oxides such as IGZO, IZO, GZO, ITO, etc. The thickness of the second metal layer 41 does not need to be set too large and can be 200-500 angstroms.

[0084] If the second trace 4 is formed on the first insulating layer 6 by sputtering, the plasma during sputtering can damage the first organic insulating layer 62, causing the first organic insulating layer 62 to have chipping phenomenon, and the chipping can contaminate the sputtering chamber. To avoid this situation, as shown in FIG. 1C, the driving substrate further includes a fourth inorganic insulating layer 8 on the first insulating layer 6, and the fourth inorganic insulating layer 8 can protect the first organic insulating layer 62. Figure 11 The fourth inorganic insulating layer 8 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and the thickness of the fourth inorganic insulating layer 8 can be 500-3000 angstroms.

[0085] If the second trace 4 is formed by low-temperature deposition, since the low-temperature deposition method does not damage the first organic insulating layer 62, the process of forming the fourth inorganic insulating layer 8 can be omitted.

[0086] Before the LED is transferred to the substrate, the exposed surface of the second trace 4 in the display area is covered with solder paste, and the LED to be bonded can be soldered on the substrate by a subsequent reflow soldering process. The exposed surface of the second trace 4 in the fan-out area B is not covered with solder paste, and oxidation will occur in the reflow soldering, affecting the conductivity of the second trace 4. To avoid this problem, as shown in FIG. 1C, a second conductive protective layer 13 is provided on the side of the second trace 4 in the fan-out area away from the substrate 1, and the second conductive protective layer 13 can be made of a metal or alloy that is not easy to oxidize, or can be made of a transparent conductive material such as ITO, and the second conductive protective layer 13 can protect the second trace 4 in the fan-out area. Figure 13

[0087] Since the light emitted by the LED 7 is in all directions, only a part of the light is emitted towards the light-emitting side of the driving substrate, which is the side of the LED 7 away from the substrate 1. To improve the utilization rate of light, a light reflection pattern 14 can be used to reflect the light emitted by the LED 7 onto the light reflection pattern 14 to the light-emitting side, thereby improving the light utilization rate of the driving substrate. In some embodiments, as shown in FIG. 1C, Figure 7 、 Figure 11 and Figure 13 ​As shown, the driving substrate further comprises a light-reflecting pattern 14 located on the side of the second insulating layer 12 away from the substrate 1, and the light-reflecting pattern 14 has a non-overlapping projection on the substrate 1 with the projection of the LED 7 on the substrate 1. The minimum horizontal distance between the projection of the light-reflecting pattern 14 and the edge of the projection of the LED 7 can be about 100 um. The material of the light-reflecting pattern 14 can be white ink formed by screen printing, inkjet printing, etc. The material of the light-reflecting pattern 14 can also be metal formed by a patterning process. It can be understood that the light-reflecting pattern 14 can also include a portion located on the side of the LED 7 facing the substrate 1 to further increase the reflectivity of light.

[0088] In some embodiments of the present disclosure, the second insulating layer 12 can only include an inorganic insulating layer for protecting the second trace 4, but the thickness of the inorganic insulating layer is generally below 6000 angstrom, and the protection effect on the second trace 4 is limited. In addition, before the LED is transferred, a tin paste is formed on the exposed surface of the second trace 4 by screen printing. When the protection effect is insufficient, the second trace 4 is easily damaged. Therefore, the second insulating layer 12 can further include an organic insulating layer, and the organic insulating layer is located on the side of the inorganic insulating layer away from the substrate 1. The thickness of the organic insulating layer is generally about 1-3 um, and can be 2 um. At this time, the thickness of the inorganic insulating layer can be about 1000 angstrom. Since the thickness of the organic insulating layer is relatively large, the second trace 4 can be better protected.

[0089] The present disclosure further provides a display device comprising the driving substrate as described above. The display device can be a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or any product or component having a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board, and a back plate.

[0090] When the electronic element is an LED, the driving substrate described above can be used as a surface light source of a display device.

[0091] The embodiment of the present disclosure further provides a manufacturing method of a driving substrate, comprising: providing a substrate substrate; forming a stress buffer layer on the substrate substrate; forming a first trace on the stress buffer layer by a one-time patterning process, the first trace having a first thickness; forming a first insulating layer covering the first trace, the first insulating layer comprising a first via exposing the first trace; forming a second trace structure on the first insulating layer, each first trace being connected to at least one second trace structure through the first via penetrating the first insulating layer, the second trace structure having a second thickness, the second thickness being smaller than the first thickness; forming a second insulating layer covering the second trace structure, the second insulating layer comprising a second via exposing the second trace structure; and disposing an electronic element on the second insulating layer, the electronic element being connected to the second trace structure through the second via penetrating the second insulating layer.

[0092] In the embodiment, the stress buffer layer is disposed on the substrate substrate, which can relieve the stress generated when the conductive layer is formed on the substrate substrate, so that the substrate substrate will not be broken, so that the conductive layer with a larger thickness can be formed on the substrate substrate, and the first trace with the first thickness is manufactured by the one-time patterning process using the conductive layer with the larger thickness. The thickness of the first trace is relatively large, which can meet the resistivity requirement of the driving substrate on the trace, can drive the electronic element disposed on the substrate substrate, and realize the large-size driving substrate. In this way, the first trace with the first thickness is not formed by the multiple patterning processes, and the number of patterning processes for manufacturing the driving substrate can be reduced.

[0093] The manufacturing method of the driving substrate is used to manufacture the driving substrate in the above embodiment.

[0094] In some embodiments, forming the stress buffer layer comprises:

[0095] The stress buffer layer is formed by depositing at least one of the following materials on the substrate substrate: silicon nitride, silicon oxide, silicon oxynitride.

[0096] In some embodiments, a first conductive layer with the first thickness can be deposited on the stress buffer layer, and the first conductive layer is patterned to form the first trace. In some other embodiments, a first conductive layer with the first thickness can also be formed on the stress buffer layer by electroplating, and the first conductive layer is patterned to form the first trace.

[0097] Since copper has good electrical conductivity, it can meet the requirements of the driving substrate on the trace, so copper can be used to manufacture the trace of the driving substrate. Taking the case that the trace is manufactured by copper and the electronic element is LED as an example, in an embodiment, the manufacturing method of the driving substrate specifically comprises the following steps:

[0098] Step 1, as follows Figure 3 As shown, a substrate 1 is provided, a stress buffer layer 2 is formed on the substrate 1, and a first trace 3 is formed on the stress buffer layer 2.

[0099] The substrate 1 can be a glass substrate, a quartz substrate, or a flexible substrate.

[0100] The stress buffer layer 2 can be made of one or more insulating materials selected from silicon nitride, silicon oxide, and silicon oxynitride. The stress buffer layer 2 has the opposite stress direction to the copper layer 32 to be formed. In this way, the stress buffer layer 2 can offset the stress generated during the formation of the copper layer 32 and prevent the substrate 1 from fragmenting. The thickness of the stress buffer layer 2 can be 500 to 3000 angstroms.

[0101] Since the adhesion between the copper layer 32 and the stress buffer layer 2 is not very strong, a first metal layer 31 can be formed on the stress buffer layer 2 first. The adhesion between the first metal layer 31 and the stress buffer layer 2 is greater than that between the copper layer 32 and the stress buffer layer 2. In this way, the first metal layer 31 can increase the adhesion between the first trace 3 and the stress buffer layer 2, preventing the first trace 3 from falling off the substrate 1. Specifically, the first metal layer 31 can be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, or metal oxides such as IGZO, IZO, GZO, and ITO. The thickness of the first metal layer 31 does not need to be large and can be 200–500 angstroms.

[0102] A copper layer 32 is formed on the first metal layer 31. The copper layer 32 can be formed by sputtering, and the thickness of the copper layer 32 can be 1.0 to 2 μm.

[0103] The first metal layer 31 and the copper layer 32 are patterned together to form the first trace 3, such as... Figure 3 As shown, the driving substrate includes a display area A and a fan-out area B, and a first trace 3 is formed in both the display area A and the fan-out area B.

[0104] Since the copper layer 32 is prone to oxidation upon contact with air, affecting its conductivity, a first conductive protective layer can be formed on the side of the copper layer 32 away from the substrate 1. This first conductive protective layer can be made of a metal that is not easily oxidized or a transparent conductive material. Specifically, the first conductive protective layer can be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, or MoNiTi. This first conductive protective layer protects the copper layer 32 from surface oxidation. The thickness of the first conductive protective layer does not need to be large and can be 50-500 angstroms.

[0105] Step 2, as follows Figure 4 As shown, a first insulating layer 6 is formed to cover the first trace 3;

[0106] The first insulating layer 6 can include a first inorganic insulating layer 61 and a first organic insulating layer 62. The first inorganic insulating layer 61 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. to protect the first traces 3 from oxidation in subsequent high-temperature processes. The thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms. Since the thickness of the first inorganic insulating layer 61 is smaller than the thickness of the first traces 3, it cannot meet the requirement of planarization. The first insulating layer 6 further includes the first organic insulating layer 62. The first organic insulating layer 62 can be made of organic insulating materials with a larger thickness, such as organic resin, etc. to fill the gaps between the first traces 3, provide a flat surface for subsequent processes, and avoid large steps in subsequent processes. In this way, LED displacement problems will not occur when performing LED binding. The total thickness of the first insulating layer 6 should be greater than or equal to the thickness of the first traces 3.

[0107] Step 3, as shown in Figure 5 The first insulating layer 6 is patterned to form a via that exposes the first traces 3, and the second traces 4 are formed on the first insulating layer 6.

[0108] The first organic insulating layer 62 can be exposed and developed to form a pattern of the first organic insulating layer 62 including a third via. The first inorganic insulating layer 61 is etched, such as dry etching, using the pattern of the first organic insulating layer 62 as a mask to form a pattern of the first inorganic insulating layer 61 including a fourth via. The third via and the fourth via communicate to form a first via that penetrates the first insulating layer 6. The second traces 4 formed subsequently are connected to the first traces 3 through the first via. Etching the first inorganic insulating layer 61 using the pattern of the first organic insulating layer 62 as a mask can save the number of patterning processes.

[0109] The thickness of the second traces 4 does not need to be too large and can be 3000-9000 angstroms. Since copper has excellent conductivity, copper can be used to make the second traces 4. Of course, other conductive materials can also be used to make the second traces 4.

[0110] As shown in Figure 5As shown, the second trace 4 includes a second metal layer 41 and a copper layer 42, the second metal layer 41 and the copper layer 42 can be formed by low-temperature deposition, which will not damage the first organic insulating layer 62. The adhesion of the second metal layer 41 to the first insulating layer 6 is greater than the adhesion of the copper layer 42 to the first insulating layer 6, so that the adhesion of the second trace 4 to the first insulating layer 6 can be increased by the second metal layer 41, preventing the second trace 4 from falling off the substrate 1. Specifically, the second metal layer 41 can be at least one of Mo, MoNb, MoTi, MoWu, MoNi, and MoNiTi. The thickness of the second metal layer 41 does not need to be set too large, and can be 50-500 angstroms. The thickness of the copper layer 42 can be about 6000 angstroms.

[0111] The second metal layer 41 and the copper layer 42 are patterned together to form the second trace 4.

[0112] Step 4, as shown in Figure 6 The second insulating layer 12 is formed;

[0113] The second insulating layer 12 can only include an inorganic insulating layer for protecting the second trace 4, but the thickness of the inorganic insulating layer is generally below 6000 angstroms, which is not very good for protecting the second trace 4. When the LED is fixed on the driving substrate by transfer binding, tin paste is formed by screen printing, which can easily damage the second trace 4 when the protection effect is not good. Therefore, the second insulating layer 12 can also include an inorganic insulating layer with a thickness of about 6000 angstroms, or can include an inorganic insulating layer and an organic insulating layer. The organic insulating layer is located on the side of the inorganic insulating layer away from the substrate 1, and the thickness of the organic insulating layer is generally about 2um. At this time, the thickness of the inorganic insulating layer can be about 1000 angstroms. Because the thickness of the organic insulating layer is relatively large, the second trace 4 can be better protected.

[0114] When the second insulating layer 12 includes an inorganic insulating layer and an organic insulating layer, the organic insulating layer can be exposed and developed first to form a pattern of the organic insulating layer when the second insulating layer is patterned. Then, the inorganic insulating layer is etched, such as dry etching, to form a pattern of the inorganic insulating layer. The pattern of the second insulating layer 12 is composed of the pattern of the inorganic insulating layer and the pattern of the organic insulating layer, and the pattern of the second insulating layer 12 exposes the second trace 4.

[0115] Step 5, as shown in Figure 7 A light-reflecting pattern 14 is formed on the second insulating layer, and the LED 7 is fixed on the substrate;

[0116] The light emitted by the LED 7 is in all directions. In order to improve the utilization of the light, the light emitted by the LED 7 and irradiated onto the light reflection pattern 14 can be reflected to the side away from the substrate 1 by the light reflection pattern 14, thereby improving the light utilization of the driving substrate. The light reflection pattern 14 can be formed by screen printing white ink, so that the light reflection pattern does not need to be formed by a patterning process, thereby saving the number of times of the patterning process. The light reflection pattern 14 can also be formed by inkjet printing.

[0117] Then, the LED 7 can be formed on the driving substrate by a process of printing solder, die bonding, reflow soldering, packaging, etc. The LED 7 includes an N pad 71 and a P pad 72. The N pad 71 and the P pad 72 of the LED 7 are respectively connected to the second traces 4 at different positions through vias penetrating the second insulating layer 12.

[0118] The driving substrate of the embodiment shown in Figure 7 can be obtained by the above steps. By the embodiment, the driving substrate can be formed by four times of patterning process, thereby reducing the number of times of the patterning process for manufacturing the driving substrate and reducing the production cost of the driving substrate.

[0119] In another embodiment, for example, the embodiment shown in Figure 11 differs from the embodiment shown in Figure 7 in that the first insulating layer 6 not only includes the first inorganic insulating layer 61 and the first organic insulating layer 62, but also includes a fourth inorganic insulating layer 8 located on the side of the first organic insulating layer 62 away from the substrate 1.

[0120] The manufacturing method of the driving substrate, for example, the embodiment shown in Figure 11 provides the substrate 1, forms the stress buffer layer 2, forms the first traces 3, forms the first insulating layer 6 including the first inorganic insulating layer 61 and the first organic insulating layer 62 and is patterned (as shown in Figure 8 ), forms the second traces 4 (as shown in Figure 9 ), forms the second insulating layer 12 (as shown in Figure 10 ), and the steps of forming the light reflection pattern 14 and transferring and binding the LED 7 can refer to the aforementioned manufacturing method, which will not be described here. Between the steps of forming the first insulating layer 6 including the first inorganic insulating layer 61 and the first organic insulating layer 62 and forming the second traces 4, there is also a step of:

[0121] As shown in Figure 8 , the fourth inorganic insulating layer 8 is formed, the fourth inorganic insulating layer 8 is patterned, and a via exposing the first traces 3 is formed;

[0122] In the process of forming the second trace 4 on the first insulating layer 6 by sputtering, the plasma in the sputtering process can damage the first organic insulating layer 62, causing the first organic insulating layer 62 to fall off in pieces, which can contaminate the sputtering chamber. To avoid this, the fourth inorganic insulating layer 8 is formed on the first insulating layer 6, which can protect the first organic insulating layer 62. The fourth inorganic insulating layer 8 can be made of silicon nitride, silicon oxide, silicon oxynitride, or other inorganic insulating materials. The thickness of the fourth inorganic insulating layer 8 can be 500-3000 angstroms. The fourth inorganic insulating layer 8 is patterned to form a pattern of the fourth inorganic insulating layer 8 including a fifth via, the orthogonal projection of the fifth via on the substrate 1 coincides with the orthogonal projection of the first via on the substrate 1.

[0123] After the above steps, the driving substrate of the embodiment shown in Figure 11 can be obtained through a five-time patterning process, reducing the number of patterning processes for manufacturing the driving substrate and reducing the production cost of the driving substrate.

[0124] Before the LED is transferred to the substrate, the exposed surface of the second trace 4 in the display area is covered with solder paste, and the LED to be bonded can be soldered on the substrate through a subsequent reflow soldering process. The exposed surface of the second trace 4 in the fan-out area B is not covered with solder paste and will be oxidized in the reflow soldering process, affecting the conductivity of the second trace 4. To avoid this problem, the method for manufacturing the driving substrate further includes:

[0125] As shown in Figure 12 , a second conductive protective layer 13 is formed to cover the second trace 4 in the fan-out area. The second conductive protective layer 13 can be made of a metal or alloy that is not easily oxidized, or a transparent conductive material such as ITO. If the second conductive protective layer 13 is formed on the side of the second trace 4 in the fan-out area away from the substrate 1, an additional patterning process is required.

[0126] Then, as shown in Figure 13 , a second insulating layer 12 can be formed, and a reflective pattern 14 and an LED 7 can be formed on the second insulating layer 12. The steps of forming the second insulating layer 12, the reflective pattern 14, and the LED 7 are described above and will not be repeated here.

[0127] In another embodiment, the copper layer constituting the first trace can be formed by electroplating. The method for manufacturing the driving substrate specifically includes the following steps:

[0128] As shown in Figure 14As shown, a substrate 1 is provided, a stress buffer layer 2 is formed on the substrate 1, a seed layer is formed on the stress buffer layer 2, and a negative photoresist is formed on the seed layer. After exposure and development of the photoresist, a photoresist removal area and a photoresist retention area are formed, resulting in a photoresist pattern 17. The photoresist removal area corresponds to the first trace to be formed, that is, the first trace will be formed in the photoresist removal area. The substrate 1 can be a glass substrate, a quartz substrate, or a flexible substrate.

[0129] The stress buffer layer 2 can be made of one or more insulating materials selected from silicon nitride, silicon oxide, and silicon oxynitride. The stress buffer layer 2 has the opposite stress direction to the seed layer to be formed, so that the stress generated during the formation of the seed layer can be offset by the stress buffer layer 2, thus preventing the substrate 1 from fragmenting. The thickness of the stress buffer layer 2 can be 500 to 3000 angstroms.

[0130] The seed layer can be formed by sputtering. The thickness of the seed layer is much smaller than the thickness of the first trace to be formed. The thickness of the seed layer can be 3000-6000 angstroms, so that too much stress will be generated when the seed layer is formed.

[0131] like Figure 14 As shown, the seed layer may include a first metal layer 15 and a copper layer 16. Since the adhesion between the copper layer 16 and the stress buffer layer 2 is not very strong, the first metal layer 15 can be formed on the stress buffer layer 2 first. The adhesion between the first metal layer 15 and the stress buffer layer 2 is greater than that between the copper layer 16 and the stress buffer layer 2. In this way, the first metal layer 15 can increase the adhesion between the first trace 3 and the stress buffer layer 2, preventing the first trace 3 from falling off the substrate 1. Specifically, the first metal layer 15 can be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and can also be metal oxides such as IGZO, IZO, GZO, and ITO. The thickness of the first metal layer 15 does not need to be large and can be 200-500 angstroms.

[0132] In this embodiment, a negative photoresist can be used to form the photoresist pattern 17, which can form a photoresist pattern 17 with an inverted trapezoidal structure. This is beneficial for the subsequent formation of a copper layer with a positive trapezoidal structure, and thus facilitates the deposition of the subsequent insulating layer. To facilitate the subsequent removal of the photoresist, the thickness of the photoresist pattern 17 is not less than the thickness of the third conductive layer 18, and preferably slightly greater than the thickness of the third conductive layer 18.

[0133] Of course, the technical solution disclosed herein is not limited to using negative photoresist; positive photoresist can also be used to form the photoresist pattern 17. If positive photoresist is used to form the photoresist pattern 17, the slope angle of the photoresist pattern 17 is preferably greater than 80°.

[0134] Step 2, as follows Figure 15 As shown, a third conductive layer 18 is grown on the seed layer of the pattern 17 on which photoresist is formed by electroplating.

[0135] A third conductive layer 18 is formed by electroplating. When the material of the third conductive layer 18 is copper, the stress generated by electroplating is small, and the formation speed is fast, allowing for the formation of a third conductive layer 18 with a thickness of 1.0–20 μm. Figure 15 As shown, a third conductive layer 18 will not form in the area where the photoresist is retained.

[0136] Step 3: Remove the photoresist from the photoresist-retained area, and etch the seed layer from the photoresist-removed area. The third conductive layer and the seed layer located in the photoresist-removed area form the first trace 3, as shown below. Figure 3 As shown.

[0137] Subsequently, it also includes forming and patterning a first insulating layer 6 comprising a first inorganic insulating layer 61 and a first organic insulating layer 62 (e.g., Figure 8 As shown), a fourth inorganic insulating layer 8 is formed and patterned (as shown). Figure 8 As shown), forming the second routing line 4 (as shown). Figure 9 As shown), a second insulating layer 12 is formed (as shown). Figure 10 As shown in the figure, the steps of reflective pattern 14 and transfer-bonded LED 7 can be referred to the aforementioned preparation method, and will not be repeated here.

[0138] In another embodiment, the formed seed layer is patterned, and then a third conductive pattern 20 is grown on the pattern of the seed layer by electroplating. The method for fabricating the driving substrate specifically includes the following steps:

[0139] Step 1, as follows Figure 16 As shown, a substrate 1 is provided, a stress buffer layer 2 is formed on the substrate 1, a seed layer is formed on the stress buffer layer 2, the thickness of the seed layer is much smaller than the first thickness, typically several thousand angstroms, photoresist is formed on the seed layer, and after the photoresist is exposed and developed, a photoresist removal area and a photoresist retention area are formed, resulting in a photoresist pattern 19, which defines the area of ​​the first trace to be formed subsequently.

[0140] Step 2, as follows Figure 17 As shown, the seed layer in the photoresist removal area is etched to remove the remaining photoresist and form the seed layer pattern.

[0141] Step 3, as follows Figure 18 As shown, a third conductive pattern 20 is grown on the seed layer pattern by electroplating.

[0142] Then, the first insulating layer 6 including the first inorganic insulating layer 61 and the first organic insulating layer 62 is formed and patterned (as shown in Figure 8 The fourth inorganic insulating layer 8 is formed and patterned (as shown in Figure 8 The second trace 4 is formed (as shown in Figure 9 The second insulating layer 12 is formed (as shown in Figure 10 The reflective pattern 14 and the transfer bonding LED 7 are formed. The above steps can refer to the aforementioned preparation method, and will not be described here.

[0143] The driving substrate of the embodiment shown in Figure 11 is obtained through the above steps by five times of patterning process, which reduces the number of patterning processes for manufacturing the driving substrate and reduces the production cost of the driving substrate.

[0144] In another embodiment, before the first trace 3 is formed, a partial planarization layer can be formed first. The manufacturing method of the driving substrate specifically includes the following steps:

[0145] Step 1, as shown in Figure 16 , a substrate 1 is provided, a stress buffer layer 2 is formed on the substrate 1, a seed layer is formed on the stress buffer layer 2, a photoresist is formed on the seed layer, and after the photoresist is exposed and developed, a photoresist removal area and a photoresist retention area are formed, obtaining a photoresist pattern 19, the photoresist pattern 19 corresponds to the first trace to be formed, that is, after the first trace is formed, the orthographic projection of the first trace on the substrate 1 coincides with the orthographic projection of the photoresist pattern 19 on the substrate 1.

[0146] The substrate 1 can be a glass substrate, a quartz substrate or a flexible substrate.

[0147] The stress buffer layer 2 can be made of one or more insulating materials such as silicon nitride, silicon oxide and silicon oxynitride. The stress buffer layer 2 is opposite to the stress direction of the seed layer to be formed, so that the stress generated when the seed layer is formed can be offset by the stress buffer layer 2, avoiding the fragmentation of the substrate 1. The thickness of the stress buffer layer 2 can be 500-3000 angstroms.

[0148] The seed layer can be formed by sputtering, and the thickness of the seed layer is much smaller than the thickness of the first trace to be formed. The thickness of the seed layer can be 3000-6000 angstroms, so that the seed layer will not generate too much stress when it is formed.

[0149] As shown in Figure 16As shown, the seed layer can include a first metal layer 15 and a copper layer 16. Since the adhesion of the copper layer 16 to the stress buffer layer 2 is not too strong, the first metal layer 15 can be formed on the stress buffer layer 2 first. The adhesion of the first metal layer 15 to the stress buffer layer 2 is greater than the adhesion of the copper layer 16 to the stress buffer layer 2. In this way, the adhesion of the first trace 3 to the stress buffer layer 2 can be increased through the first metal layer 15, preventing the first trace 3 from falling off the substrate 1. Specifically, the first metal layer 15 can be at least one of Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and can also be IGZO, IZO, GZO, ITO, and other metal oxides. The thickness of the first metal layer 15 does not need to be set too large and can be 200-500 angstroms.

[0150] The embodiment can form a photoresist pattern 19 using a positive photoresist. The thickness of the photoresist pattern 19 does not need to be too large and is generally 1-3 um, which can be 1.5 um.

[0151] Step 2, as shown in Figure 17 The seed layer in the photoresist removal area is etched, the remaining photoresist is removed, and a seed layer pattern is formed.

[0152] Step 3, as shown in Figure 19 A third inorganic insulating layer 21 and a third organic insulating layer 22 are formed.

[0153] Step 4, as shown in Figure 20 A third inorganic insulating layer 21 and a third organic insulating layer 22 are formed by a one-time patterning process.

[0154] The third organic insulating layer 22 is first exposed and developed to form a third organic insulating layer 22 pattern, which includes a third organic insulating layer retention area and a third organic insulating layer removal area. The third organic insulating layer removal area coincides with the area where the seed layer pattern is located. The third inorganic insulating layer 21 is etched using the third organic insulating layer 22 pattern as a mask to form a third inorganic insulating layer 21 pattern.

[0155] The third inorganic insulating layer 21 and the third organic insulating layer 22 pattern are to provide a flat surface for the subsequent formation of the second trace 4. In this embodiment, a partial planarization layer is formed before the first trace 3 is formed, making it easier to perform planarization later.

[0156] Step 5, as shown in Figure 21 A third conductive pattern 20 is grown on the seed layer pattern by electroplating.

[0157] Since the seed layer is a copper layer, the third conductive pattern 20 is also a copper layer, and the stress generated by the electroplating method is small, the copper layer is formed at a high speed, and a copper layer with a large thickness can be formed, specifically, the third conductive pattern 20 can have a thickness of 1.5-20 um. As shown in Figure 20 The area where the seed layer is not arranged will not form the third conductive pattern 20. The pattern of the seed layer and the third conductive pattern 20 form the first trace 3.

[0158] Step 6, as shown in Figure 22 a first insulating layer 6 covering the first trace 3 is formed;

[0159] The first insulating layer 6 can include a first inorganic insulating layer 61 and a first organic insulating layer 62. The first inorganic insulating layer 61 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., to protect the first trace 3 from oxidation in subsequent high-temperature processes. The thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms. Since the thickness of the first inorganic insulating layer 61 is small, it is less than the thickness of the first trace 3 and cannot meet the planarization requirement. The first insulating layer 6 further includes a first organic insulating layer 62, which can be made of an organic insulating material with a large thickness, such as organic resin, etc., to fill the gaps between the first traces 3 and provide a flat surface for subsequent processes, avoiding large steps in subsequent processes, so that LED displacement problems will not occur when the LED is bonded.

[0160] Since the third inorganic insulating layer 21 and the third organic insulating layer 22 have been formed in advance, the thickness of the first insulating layer 6 does not need to be too large and can be about 1.5 um. As long as the total thickness of the third inorganic insulating layer 21, the third organic insulating layer 22, and the first insulating layer 6 is greater than the thickness of the first trace 3.

[0161] Further, in this step, the first inorganic insulating layer 61 can be omitted, and only the first organic insulating layer 62 can be retained.

[0162] After that, the first insulating layer 6 can be patterned according to the steps of the above embodiments, the second trace 4 is formed, the pattern of the second insulating layer 12 is formed, and the reflective pattern 14 and the LED 7 are formed on the second insulating layer 12, so that the driving substrate of the present embodiment is obtained. Through the present embodiment, the driving substrate can be formed by six times of patterning process, the driving substrate can be manufactured with fewer times of patterning process, and the production cost of the driving substrate can be reduced.

[0163] In the above embodiment, in order to avoid the pollution of the metal deposition equipment in the process of directly depositing the metal to form the second trace on the organic insulating layer, the low-temperature deposition process can be used to form the second trace 4, and then the fourth inorganic insulating layer 8 can be omitted, and the one-time patterning process can be reduced. In the above embodiment, when the electroplating method is used to form the first trace 3, in order to avoid affecting the electroplating, the first trace 3 can only include the first metal layer and the copper layer, and does not need to include the first conductive protection layer.

[0164] In the method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes of the sequence of the steps without creative efforts are within the protection scope of the present disclosure.

[0165] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings of the technical terms or scientific terms understood by those skilled in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may also be changed accordingly.

[0166] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being “on” or “under” another element, the element can be “directly” on or under the other element, or there can be an intermediate element.

[0167] The above is the preferred embodiment of the present disclosure, and it should be pointed out that for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A driving substrate, characterized in that, include: Substrate; Stress buffer layer located on the substrate; A plurality of first traces are located on the side of the stress buffer layer away from the substrate, and the first traces have a first thickness; A first insulating layer located on the side of the first trace away from the substrate. A plurality of second trace structures are located on the side of the first insulating layer away from the substrate. Each of the first traces is connected to at least one second trace structure through a first via penetrating the first insulating layer. The second trace structure has a second thickness, which is less than the first thickness. A second insulating layer located on the side of the second trace structure away from the substrate. An electronic component located on the side of the second insulating layer away from the substrate, the electronic component being connected to the second wiring structure through at least two second vias penetrating the second insulating layer; The second wiring structure includes at least one second wiring layer, each second wiring layer including multiple second wirings, the driving substrate including a display area and a fan-out area located around the display area, and the driving substrate further including: A second conductive protective layer covering the second trace in the fan-out area; The plurality of second trace structures have a thickness greater than 6,000 angstroms and not greater than 9,000 angstroms; The second insulating layer includes an inorganic insulating layer and an organic insulating layer located on the surface of the inorganic insulating layer away from the substrate. The electronic component overlaps with the orthogonal projection portion of the second wiring structure on the substrate. The aperture of the first via projected onto the substrate is not greater than the line width of the first trace projected onto the substrate; the aperture of the second via projected onto the substrate is not greater than the line width of the second trace projected onto the substrate. The first insulating layer includes: A first inorganic insulating layer and a first organic insulating layer are stacked together, wherein the first organic insulating layer is located on the side of the first inorganic insulating layer away from the substrate. The driving substrate further includes: A fourth inorganic insulating layer is located on the side of the first organic insulating layer away from the substrate, and the second wiring structure is located on the side of the fourth inorganic insulating layer away from the substrate.

2. The driving substrate according to claim 1, characterized in that, The first trace includes a copper layer and a first metal layer stacked together. The first metal layer is located on the side of the copper layer closer to the substrate. The adhesion between the first metal layer and the stress buffer layer is greater than the adhesion between the copper layer and the stress buffer layer.

3. The method for manufacturing a driving substrate according to claim 2, characterized in that, The thickness of the copper layer is 1-30 μm.

4. The method for manufacturing a driving substrate according to claim 2, characterized in that, The first trace also includes a first conductive protective layer located on the side of the copper layer near the substrate.

5. The driving substrate according to claim 1, characterized in that, When the second trace layer is multilayered, an insulating layer is spaced between two adjacent second trace layers. From the direction close to the substrate to the direction away from the substrate, each second trace of the previous layer is connected to at least one second trace of the next layer, and each second trace of the last layer is connected to at least one of the electronic components.

6. The driving substrate according to claim 5, characterized in that, The second trace includes a copper layer and a second metal layer stacked together. The second metal layer is located on the side of the copper layer closer to the substrate. The adhesion between the second metal layer and the first insulating layer is greater than the adhesion between the copper layer and the first insulating layer.

7. A display device, characterized in that, Includes the driving substrate as described in any one of claims 1-6.

8. A method for manufacturing a driving substrate, applied to the driving substrate as described in any one of claims 1-6, characterized in that, include: Provide a substrate; A stress buffer layer is formed on the substrate. Multiple first traces are formed on the stress buffer layer through a single patterning process, and the first traces have a first thickness. A first insulating layer is formed to cover the first trace, the first insulating layer including a first via exposing a portion of the surface of the first trace; A plurality of second trace structures are formed on the first insulating layer. Each first trace is connected to at least one second trace structure through a first via penetrating the first insulating layer. The second trace structure has a second thickness, which is less than the first thickness. A second insulating layer is formed covering the second trace structure, the second insulating layer including a second via exposing a portion of the surface of the second trace structure; An electronic component is disposed on the second insulating layer, and the electronic component is connected to the second wiring structure through at least two second vias penetrating the second insulating layer; The second wiring structure includes at least one second wiring layer, each second wiring layer including multiple second wirings, the driving substrate including a display area and a fan-out area located around the display area, and the driving substrate further including: A second conductive protective layer covering the second trace in the fan-out area; The plurality of second trace structures have a thickness greater than 6,000 angstroms and not greater than 9,000 angstroms; The second insulating layer includes an inorganic insulating layer and an organic insulating layer located on the surface of the inorganic insulating layer away from the substrate. The electronic component overlaps with the orthogonal projection portion of the second wiring structure on the substrate. The aperture of the first via projected onto the substrate is not greater than the linewidth of the first trace projected onto the substrate; the aperture of the second via projected onto the substrate is not greater than the linewidth of the second trace projected onto the substrate.

9. The method for manufacturing a driving substrate according to claim 8, characterized in that, The formation of the first trace includes: A first conductive layer of a first thickness is deposited on the stress buffer layer, and the first conductive layer is patterned to form the first trace.

10. The method for manufacturing a driving substrate according to claim 8, characterized in that, The formation of the first trace includes: A seed layer with a thickness less than a first thickness is deposited on the stress buffer layer, and a negative photoresist is formed on the seed layer. After the photoresist is exposed and developed, a photoresist removal area and a photoresist retention area are formed. The photoresist removal area corresponds to the first trace to be formed. A third conductive layer is grown on the seed layer on which the photoresist pattern is formed by electroplating. Remove the photoresist from the photoresist-retained area; The seed layer that has been removed from the photoresist is etched, and the third conductive layer located in the photoresist removal area and the seed layer form the first trace.

11. The method for manufacturing a driving substrate according to claim 8, characterized in that, The formation of the first trace includes: A seed layer with a thickness less than a first thickness is deposited on the stress buffer layer, and photoresist is formed on the seed layer. After the photoresist is exposed and developed, a photoresist removal area and a photoresist retention area are formed. The photoresist retention area corresponds to the first trace to be formed. The seed layer in the photoresist removal area is etched to form the pattern of the seed layer. A third conductive pattern is grown on the pattern of the seed layer by electroplating, and the third conductive pattern and the pattern of the seed layer constitute the first trace.

12. The method for manufacturing a driving substrate according to claim 11, characterized in that, Before growing a third conductive pattern on the seed layer pattern by electroplating, the method further includes: Forming a third inorganic insulating layer; A third organic insulating layer is formed on the third inorganic insulating layer; The third organic insulating layer is exposed and developed to form a pattern of the third organic insulating layer. The pattern of the third organic insulating layer includes a retained area of ​​the third organic insulating layer and a removed area of ​​the third organic insulating layer. The removed area of ​​the third organic insulating layer coincides with the area where the pattern of the seed layer is located. Using the pattern of the third organic insulating layer as a mask, the third inorganic insulating layer is etched to form the pattern of the third inorganic insulating layer.

13. The method for manufacturing a driving substrate according to claim 8, 9, 10 or 11, characterized in that, The first insulating layer comprises a first inorganic insulating layer and a first organic insulating layer stacked together, and forming the first insulating layer includes: Forming the first inorganic insulating layer; Forming the first organic insulating layer; The first organic insulating layer is exposed and developed to form a pattern of the first organic insulating layer including a third via. Using the pattern of the first organic insulating layer as a mask, the first inorganic insulating layer is etched to form a pattern of the first inorganic insulating layer including a fourth via. The third via and the fourth via are connected to form the first via.

14. The method for manufacturing a driving substrate according to claim 8, characterized in that, The second routing structure includes at least one second routing layer, each second routing layer including multiple second traces, forming the second traces located on the first insulating layer including: A second conductive layer is sputtered onto the first insulating layer, and the second conductive layer is patterned to form the second trace; or A second conductive layer is formed on the first insulating layer by low-temperature deposition. The second conductive layer is then patterned to form the second trace. The temperature of the low-temperature deposition is no greater than 50 degrees Celsius.

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