Method and apparatus for cross-correlation

Abstract

The present invention relates to a multi-stream cross-correlator for a spiking neural network, wherein each stream contains significant random content. At least one event occurs with a fixed temporal relationship across at least two streams. Each stream is considered a reference frame (FOR) and is subject to an adjustable delay based on comparison with the other streams. For each spike in the FOR, a timing analysis relative to the last and current FOR spike is performed by comparing the Post accumulator with the Pre accumulator. Furthermore, a new timing analysis is started with the current FOR spike by restarting the generation of Post and Pre weighting functions, accumulating the values ​​of the Post and Pre weighting functions immediately after each additional spike until the next FOR spike. If time-neutral collision resolution is used, a single spike delay unit can be used. The average spike rate of the FOR can be determined and used in the Post and Pre weighting functions.

Description

[0001] This patent claims the benefit of the filing dates of the following U.S. patent applications, which are incorporated herein by reference in their entirety:

[0002] The inventor is David Carl Barton and the application number is 62 / 819,590, filed on March 17, 2019 (year / month / day), "Method and apparatus for cross-correlation". Technical Field

[0003] The present invention relates generally to cross-correlation, and more particularly to cross-correlation of data streams with significantly random content. Background Art

[0004] Cross-correlation is well understood in signal processing and is commonly used to find the relative delays between signal streams in a variety of applications. Established cross-correlation methods compare the similarity of signals at multiple relative delay offsets, typically finding the offset with the greatest similarity.

[0005] There are many optimizations to reduce the computational cost of the required repeated comparisons, including the use of FFTs and various sliding window methods. Besides its computational expense, established methods also suffer from the drawback of introducing high latency into the system, both due to the need to perform many comparisons and due to the memory buffers required when processing streaming data. The buffers are necessary to enable bidirectional searches for both positive and negative delay offsets on a continuous basis.

[0006] Therefore, there is a need for a method of cross-correlation that has lower latency and does not require buffering. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the present invention and, together with the description, serve to explain the principles of the invention:

[0008] Figure 1 Describes an example application scenario of multi-stream cross-correlators in the field of spiking neural networks.

[0009] Figure 2 It is aimed at Figure 1 Functional block diagram of an exemplary internal structure of each CCU.

[0010] Figure 3 Describes a functional implementation of a learning delay, the use of which exists in its FOR d Each pair of spikes at one input served as a reference frame to analyze any spikes occurring at the other input at the learned delay.

[0011] Figure 4 Depicts an example pseudo-coding implementation of learning delays based on the Python programming language.

[0012] Figures 5 to 7 Depicts an example electrical implementation of a learned delay.

[0013] Figure 8 yes Figure 2 Functional block diagram of the CCU of FIG1 , except that a conflict resolution block is added to the memory-less version which incurs delays.

[0014] Figure 9 Depicts an example of implementing delay generation by combining an exponential decay curve with threshold detection.

[0015] Figure 10 Presentation for implementation of the combination Figure 8 The circuitry for generating delay functionality discussed with respect to functional block 0220.

[0016] Figure 11 Describing and Figure 8 The same CCU shown in , except for the addition of a "Learning Rate Overall" (or LRA) function block 0223.

[0017] Figure 12 Plotted on known actual MEA ALL Example distribution of spikes in the case of .

[0018] Figure 13 Depicted on MEA ALL A guess at the value of (called MEA guess ) is too high.

[0019] Figure 14 Depicted on MEA ALL The value of the guess (called MEA guess ) is too low.

[0020] Figure 15 The equality testing method for finding the MEA is depicted instead of solving Equation 1 for a point that yields half of its total range (eg, P = 0.5).

[0021] Figure 16 A circuit implementation for learning rate ensemble based on an equal testing approach is presented.

[0022] Figure 17 and 18 Presented in Figure 6 and 7 The same circuit implementation of the learned delay shown in , but with the addition of ALL Except for the input hardware.

[0023] Figure 19 Presentation Figure 10The same circuit implementation for generating delay as shown in FIG, but with the addition of a circuit for r ALL Except for the input hardware. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0025] Please refer to Section 3 ("Selected Terms") for definitions of selected terms used below.

[0026] Catalog of implementation methods

[0027] 1 Introduction

[0028] 2 Cross-correlation unit

[0029] 2.1 Introduction

[0030] 2.2 Learning Delay

[0031] 2.2.1 Functional Description

[0032] 2.2.2 Sequential Operation and Pseudo-coding Implementation

[0033] 2.2.3 Electrical Implementation Plan

[0034] 2.3 Producing a Delayed-Lossy Version

[0035] 2.3.1 Conflict Resolution

[0036] 2.3.2 Electrical Implementation Plan

[0037] 2.4 Learning Rate All

[0038] 3 Selected Glossary

[0039] 4 Computing devices

[0040] 1 Introduction

[0041] Cross-correlation is known to have many important applications. Among these applications, cross-correlation is expected to continue to become important in the field of spiking neural networks, where relative spike timing can be critical to proper operation.

[0042] Figure 1 Depicts an example application scenario in the field of spiking neural networks. The input on the left is three spike streams: S1, S2, and S3. Each spike stream is expected to contain significant random (or stochastic) content.

[0043] Regarding the stochastic content, the temporal size of the inter-spike gap (or ISG) takes on a random distribution (usually Poisson), and each ISG i is within the range:

[0044] 0 seconds < i < ∞ seconds

[0045] For the entire time range of i, we refer to the average spike rate of the spike train as r ALL (since a rate encompassing all spikes may occur).

[0046] This content is random both with respect to the stream in which it occurs and relative to other streams. However, non-random events are also expected to occur that manifest themselves across two or more of the input streams. (In the following exposition, we will generally refer to non-random events simply as "events".)

[0047] Each of the streams S1, S2, and S3 is coupled respectively to the F.O.R. inputs: 0110, 0112, and 0114 of a cross-correlation unit (or CCU). Each CCU has an output labeled "FOR d ". As can be seen, each FOR d output is connected to an input of a "Soma" 0121. At its most basic functional level, the Soma can be designed to act as a coincidence detector that produces an output spike whenever spikes occur simultaneously at each of its inputs.

[0048] In the following discussion, three input streams are chosen for ease of exposition. It will be readily appreciated that the system (e.g., Figure 1 's system) can be applied to any large number of inputs without any change in the operating principle. A minimum of two input streams is required. Generally speaking, for example Figure 1 's system can be regarded as a biologically inspired model of a neuron. Although biologically inspired, from an engineering design (and non-biological) perspective, Figure 1 it can be understood as representing a multi-stream cross-correlator or "MCC".

[0049] When an event occurs, in two or more input streams of the MCC, it is expected that its manifestation in each input stream has a fixed temporal relationship with respect to its manifestation in other spike streams. Although the multi-stream manifestations of an event are expected to have a fixed temporal relationship with respect to each other, it is also expected that such manifestations will not occur simultaneously.

[0050] It is expected that any other spike (i.e., any non-event spike) has a random relationship with respect to all other non-event spikes both within the input stream in which the spike occurs and when considering other input streams.

[0051] We also refer to any such non-event spike as a "random spike".

[0052] The job of each of the CCUs 0110, 0112, and 0114 is to determine delays or time offsets so that as many event representations as possible across multiple streams appear simultaneously at the output of the CCU (and therefore simultaneously at the input of Soma 0121).

[0053] More specifically, it can be observed that each CCU of Figure 01 has two inputs:

[0054] FOR, and

[0055] Others

[0056] "FOR" (which may alternatively be written as "FOR") means "Frame of Reference." (Unless the context indicates otherwise, any use of the term "FOR" or "FOR" herein refers to a "Frame of Reference" rather than the preposition "for.") The spike stream presented to the FOR input of a CCU appears at the CCU's FOR input after some modification. d It is possible for a CCU to modify its FOR output by inserting a delay relative to the spike that appears at its FOR input. d Output streams. The "other" inputs of each CCU are intended to be the outputs that appear on the other CCUs (i.e., other CCUs connected to the same Soma). d The union of the spikes at the output.

[0057] As can be seen, the other inputs to each CCU are determined as follows. First, the output spikes of all CCUs are connected together through an OR gate 0120 to form a single combined spike stream. The output of this OR gate is labeled "ANY" because a spike is expected to appear at its output as long as it appears at the FOR of any CCU. d At the output.

[0058] Each of CCUs 0110, 0112, and 0114 is provided with AND gates 0111, 0113, and 0115, respectively. As can be seen, each AND gate filters out (i.e., removes) the spike stream received by the other inputs of its CCU. Specifically, any spikes contributed by the CCU of that AND gate are removed.

[0059] 2 Cross-correlation unit

[0060] 2.1 Introduction

[0061] Compared to conventional correlation and cross-correlation techniques, the MCC of the present invention relies on the presence of a large number (eg, hundreds or thousands) of random spikes.

[0062] The MCC operates by having each CCU operate essentially independently of the other CCUs. The exception to the independent operation is the fact that each CCU receives (at its other input) the FOR d The union of outputs (specifically, for example, the union of spike streams presented to the FOR inputs of other CCUs).

[0063] Figure 2 It is aimed at Figure 1 Functional block diagram of an exemplary internal structure of each CCU.

[0064] As can be seen, the CCU consists of two main units:

[0065] Generate a delay (block 0225), and

[0066] • Learn delay (block 0226).

[0067] Produces a delayed stream of incoming spikes (at its FOR input) and at its output (called FOR d ) generates a delayed version of this input stream. The delayed FOR input is coupled to the FOR input of the CCU (labeled 0211), and the delayed FOR d Output coupled to the CCU's FOR d Output (labeled 0212).

[0068] The learning delay accepts other spike flows from the CCU (other inputs from the CCU 0210), and also accepts (in the learning delay's FOR d Input) produces a delayed FOR d Output. Learning delay uses the existence of its FOR d Each pair of spikes at one input served as a reference frame to analyze any spikes occurring at the other input at the learned delay.

[0069] If the generation delay is incorporated into sufficient memory, it can be reproduced (at its FOR d The output of the FOR is a stream of spikes that is identical to the stream of spikes at its FOR input, except for the possibility of delay. We can call this a lossless version that generates delays.

[0070] Depending on the application, the memory that generates the delay can be implemented using analog or digital devices. For digital implementations, the delay generation can include, for example, a FIFO (first-in, first-out) queue or buffer implemented using semiconductor random access memory (RAM). For analog implementations, the delay generation can include any suitable signal or waveguide, such as a cable or a free-space wave propagation cavity.

[0071] However, in general, generating a lossy version of the delay may require an infinite (or unbounded) amount of memory.

[0072] Another important aspect of the present invention is to exploit the random nature of the spike stream presented to the FOR input of the CCU to generate a FOR at the output that produces the delay d In fact, only one spike (one time) of memory passing through the delay may be enough to generate the lossy version of the CCU's FOR d A useful stream of correlated spikes is generated at the output. When using storage of only one spike, the generation delay can be considered as a kind of "timer". When a spike appears at its FOR input, the timer can be started. At the end of the delay period, the timer is the value of the FOR that generated the delay. d The output generates a spike. The use of a single spike memory is discussed below in Section 2.3 ("Generating Delay").

[0073] 2.2 Learning Delay

[0074] 2.2.1 Functional Description

[0075] As mentioned above, learning to delay use exists in its FOR d Each pair of spikes at one input served as a reference frame to analyze any spikes occurring at the other input at the learned delay. Figure 3 Describe this example scenario.

[0076] As can be seen, Figure 3 Contains two axes:

[0077] Horizontal time axis, where: 0.00 seconds ≤ t ≤ 0.60 seconds.

[0078] • A vertical axis used to assign weights to each other spike (explained further below), where: 0.00 ≤ Weight ≤ 1.00.

[0079] Let's learn about delayed FOR d A continuous pair of spikes is called at the input, which serves as a framework for evaluating the other spikes n and n+1. The vertical line at time t=0.00 (in addition to representing the weight axis) depicts spike n (this spike is also labeled 0310). Conversely, spike n+1 is depicted at t=0.60 (this spike is also labeled 0311). The magnitudes of the n and n+1 spikes along the vertical axis are irrelevant and are selected only for graphical presentation purposes.

[0080] The weight axis is related to the curves 0320 and 0321. As can be seen, 0320 is of the form e -rtwhere r is the rate, t is the time, and r (for example purposes) is equal to 3. Conversely, 0321 is an exponential decay curve of the form e -r(m-t) , where r and t are the same as in the case of 0320, and m (the "maximum" time) is equal to 0.60 seconds. For reasons that will be explained below, curves 0320 and 0321 are also referred to as "Post" and "Pre", respectively.

[0081] Appear in FOR d Each other peak between peaks n and n+1 is assigned both Post and Pre values. A peak whose Post value is greater than its Pre value is characterized as "post" (or following) peak n being more intense than "pre" (or preceding) peak n+1. Conversely, a peak whose Pre value is greater than its Post value is characterized as "pre" (or preceding) peak n+1 being more intense than "post" (or following) peak n.

[0082] Figure 3 Two example other peaks are depicted with the following values:

[0083] Other spikes 1:

[0084] ○t=0.065 seconds.

[0085] ○Post value = 0.723

[0086] ○Pre value = 0.05

[0087] Other Peaks 2:

[0088] ○t=0.44 seconds.

[0089] ○Post value = 0.112

[0090] ○Pre value = 0.446

[0091] As can be seen, each other peak is given two weights, depending on where it intersects the Post and Pre weighting curves.

[0092] Span can appear in a pair of FOR d For multiple other peaks between peaks n and n+1, the net tendency to be "behind" or "ahead" can be determined and corrected as follows:

[0093] · Accumulate the sum of all Post values ​​(which we also call "postAcc"), and

[0094] · Accumulate the sum of all Pre values ​​(which we also call “preAcc”).

[0095] If postAcc>preAcc, then:

[0096] ○ Other peak flows are considered to occur in FOR d This also means that FOR d The flow is generally ahead of schedule.

[0097] ○ Learning delays (e.g., Figure 2 The learned delay block 0226) may attempt to correct the advance by issuing a command (e.g., a pulse) at its "more d" output.

[0098] o In response to a "more d" command, a generate delay (eg, see generate delay block 0225) may cause its FOR input to be compared to the FOR d Increases the delay between outputs by a specific increment.

[0099] If preAcc>postAcc, then:

[0100] ○ Other peak flows are considered to occur in FOR d This also means that FOR d The flow is generally lagging.

[0101] o A learned delay may attempt to correct the hysteresis by issuing a command (eg, a pulse) at its "less d" output.

[0102] ○ In response, a delay is generated to make its FOR input and FOR d The delay between outputs is reduced by a specific increment.

[0103] The incremental amount by which the delay of the learned delay is changed (in response to a "more d" or "less d" command) can be selected based on the specific application and its speed and accuracy requirements. Generally speaking, smaller increments (also known as slower learning rates) increase the time it takes the CCU to find the delay value that achieves optimal synchronization of its events with its other streams. However, smaller increments have the advantage of producing a more accurate determination of the necessary delay value.

[0104] Although both decreasing and increasing exponential curves have been shown, for the purposes of Post and Pre weighting, various functions may be suitable. The main criteria for a suitable function include:

[0105] The Pre function is the opposite of the Post function.

[0106] The Post and Pre functions are at their maximum at the times of spikes n and n+1, respectively.

[0107] Post and Pre functions that decrease monotonically from their maximum values.

[0108] 2.2.2 Sequential Operation and Pseudo-coding Implementation

[0109] The operations explained in the previous subsections of learning delays are discussed in a manner consistent with the following spikes being obtained at a time:

[0110] FOR d Input spikes n and n+1, and

[0111] · In n and n+1F.OR d Any spikes present at the other input during the time interval between spikes are learned delays.

[0112] During actual operation, it is expected that the CCU (and its MCC) operates on a spike-by-spike basis. For example, based on the existence of a learned delay FOR which we can call spike n d For each spike at the input, we can expect the learned delay to perform two main operations:

[0113] If there is peak n-1, then try to perform the cross-correlation analysis starting with peak n-1. In other words, perform the cross-correlation analysis with peaks n-1 and n as the reference frame.

[0114] Start a new cross-correlation analysis that will be completed in the future immediately after the arrival of spike n+1. In other words, start a new cross-correlation analysis where spikes n and n+1 will be used as a reference frame.

[0115] Depending on the particular application, it may be desirable to implement the learned delay as a computer program, as electrical hardware, or as a hybrid combination of the two approaches.

[0116] Figure 4 Depicts an example pseudo-coded implementation of a learning delay based on the Python programming language. Bold text corresponds closely to Python syntax and semantics. Comments are inserted according to Python syntax. Line numbers have been added to the left to aid interpretation. The main deviation from Python syntax and semantics is in the right-hand side of the assignment operator, on lines 5 through 17. Furthermore, passing parameters or other data into and out of the procedure is handled informally.

[0117] Figure 4 The procedure is called "Learn_Delay_PC", where the "PC" suffix indicates pseudocode. Line 1.

[0118] Whenever a spike occurs in FOR d Or other input calls Learn_Delay_PC.

[0119] Several important values ​​and variables are assigned on lines 5-17, but will be set forth on lines 22-44 as part of the discussion of the pseudocode that utilizes these variables.

[0120] Line 22 updates the Pre accumulator "preAcc" by causing its contents to undergo exponential decay with respect to the amount of time (i.e., T to TLO) since the last other spike caused a call to Learn_Delay_PC (where Figure 4 T and TLO are defined in lines 8-9 of . As will be explained further below, this exponential decay of preAcc is combined with adding a unity value to preAcc each time an additional spike occurs.

[0121] At each additional spike, a unity value is added to preAcc and preAcc is caused to undergo exponential decay (until the next FOR d Peak time) is mathematically equivalent to the above Figure 3 The preAcc accumulation method discussed: e is added immediately after each other spike. -r(m-t) The value of is added to preAcc (where m is the maximum value of t), with unattenuated preAcc.

[0122] Causing preAcc to undergo exponential decay might seem like an unnecessarily indirect way to accumulate Pre values. However, as will be discussed in the next subsection, -rt For comparison, -r(m-t) It is a relatively complex function implemented with the help of electronic hardware.

[0123] Following the update of preAcc, the execution current spike is of type FOR d Or other tests. Line 25. FOR d The spike is considered to "belong" to the currently executing learning delay unit because it originates from a generation delay unit belonging to the same CCU. Therefore, the IS_MINE variable is false indicating that another spike was received, causing execution of lines 26 to 33. Otherwise, the current spike is of type FOR d , and execute lines 35 to 45.

[0124] Assuming IS_MINE is false, perform the following steps:

[0125] To indicate that the current spike is of a different type, a unit value is added to preAcc. Line 26.

[0126] The value added to postAcc is only the value since the last FOR d Exponential decay to unity since the spike. Line 30.

[0127] Update the time of the last other spike in preparation for the next call to Learn_Delay_PC. Line 32.

[0128] Assuming IS_MINE is true, perform the following steps:

[0129] · As completed with the previous FOR d As part of the cross-correlation analysis currently being performed, a test is first performed to determine if any other spikes have occurred.

[0130] Assuming at least one other spike has occurred, compare the value of preAcc to the value of postAcc. Line 38.

[0131] ○If preAcc>postAcc, then in general, FOR d The spike is considered to be lagging relative to other spikes. The delay from the generation delay represented by the variable D is reduced. The amount of reduction in the control learning rate is represented by "-D_LR" in line 38.

[0132] ○ If postAcc>preAcc, then in general, FOR d The spike is considered to be early relative to the other spikes. The delay from the generation delay is increased, represented by the variable D. The amount of increase in the control learning rate is represented by "D_LR" in line 38.

[0133] A check can be performed to ensure that D remains within acceptable limits. Line 40.

[0134] As part of starting a new cross-correlation analysis, perform the following steps:

[0135] ○ Reset preAcc and postAcc to zero. Line 42.

[0136] ○ Change the last FOR d The time of the spike is updated to the current time. Line 44.

[0137] 2.2.3 Electrical Implementation Plan

[0138] Figures 5 to 7 Depicts an example electrical implementation of a learned delay.

[0139] Figure 5 Describes the top-level controls and interface of the learned delay module. Figure 6 Focusing on the circuit system related to accumulating postAcc value, Figure 7 Focus on the circuit system related to the accumulation of preAcc.

[0140] Figure 5The outline 0510 indicates the external interface of the learning delay, where each connection corresponds to the previously combined Figure 2 Input or output of the learning delay function block 0221 in question.

[0141] Contour 0520 indicates the learning delay and Figure 6 postAcc circuit system and Figure 7 The internal interface of the preAcc circuit system.

[0142] External interface 0510 is discussed below.

[0143] Presented to FOR d Each spike in the input triggers a "double shot" 0530. First, out1 of the double shot completes the current reference frame by causing a read of the comparator amplifier 0540. Second, out2 resets the postAcc and preAcc circuitry so that accumulation across the next reference frame can begin.

[0144] Out1 causes a read of comparator 0540 by enabling AND gates 0541 and 0542. If the output of comparator 0540 is a logic 0 when the AND gates are enabled, AND gate 0542 presents a trigger signal to single-shot 0532. Single-shot 0532, when triggered, generates a pulse at the "less d" output (of interface 0510). Conversely, if the output of comparator 0540 is a logic 1, AND gate 0541 presents a trigger signal to single-shot 0531. Single-shot 0531, when triggered, generates a pulse at the "more d" output (of interface 0510).

[0145] The comparator 0540 compares two signals: a signal representing preAcc (referred to as "preAcc") and a signal representing postAcc (referred to as "postAcc"). Figure 6 The circuit system generates the postAcc signal, and at the same time Figure 7 The circuitry accumulates the preAcc signal. Each of the preAcc and postAcc signals is analog, having a voltage level representing its accumulated value. If the preAcc signal has a higher voltage than the postAcc signal, comparator 0540 outputs a signal representing a logic 0. As discussed above, a logic 0 (when read by out1 of dual 0530) causes a pulse from the "less d" output. Conversely, if postAcc > preAcc, comparator 0540 outputs a logic 1. As discussed above, a logic 1 (when read by out1 of dual 0530) causes a pulse from the "more d" output.

[0146] The last connection to be discussed for the external interface 0510 is the other inputs.d As with the input, a spike elsewhere also triggers the double send. In this case, it is the double send 0533. As will be discussed further below, out1 of the double send 0533 causes the current voltage level of each of the postAcc accumulator and the preAcc accumulator to be sampled (among other actions). Second, out2 causes the postAcc and preAcc accumulators to be charged to their new voltage levels.

[0147] about Figure 6 , capacitor 0650 maintains the voltage of the postAcc signal (or node). Figure 3 The Post n function 0320 discussed is determined by the combination of capacitor 0640 and resistor 0641. Figure 6 The Post n function is available at the decay variable node.

[0148] As discussed above, as part of starting up a new reference frame, the dual 0530 asserts (at its out2 output) the "RESET (FOR)" signal. Figure 6 , it can be seen that the reset (FOR) signal causes the reset of the following capacitors:

[0149] • The accumulation of postAcc values ​​is reset to zero by switch 0660 coupling the postAcc node to ground.

[0150] The Post n function 0320 is reset to a new exponential decay period by switches S1 and S2 of the switching unit 0643. Specifically, during the duration of the reset (FOR) pulse:

[0151] o S1 couples capacitor 0640 to unity voltage source 0642, and

[0152] o S2 ensures that the decay variable node maintains the correct initial value to restart the exponential decay while capacitor 0640 is recharged.

[0153] At the appropriate time, capacitor 0632 is used to hold a sample of the voltage at the attenuation variable node. It is reset by switch 0662 which couples capacitor 0632 to ground.

[0154] At the appropriate time, capacitor 0622 is used to hold a sample of the voltage at the postAcc node. It is reset by switch 0661 which couples capacitor 0622 to ground.

[0155] Once the reset (FOR) signal ends, the combination of capacitor 0640 and resistor 0641 begins its exponential decay, where the Post n function can be obtained at the decay variable node.

[0156] If the postAcc node is reset (via FOR d If another peak appears after the peak, then a double 0533 is triggered. Figure 6 , it can be seen that the assertion of the "sample(other)" signal causes the following:

[0157] The current voltage is sampled at the decay variable node by closing switch 0631.

[0158] The current voltage is sampled at the postAcc node by closing switch 0621.

[0159] After the assertion of the Sample(other) signal, the following occurs:

[0160] Switch 0631 is open, and the sampled voltage of the decay variable node is held by capacitor 0632 .

[0161] Switch 0621 is open, and the sampled voltage of the postAcc node is held by capacitor 0622.

[0162] The voltages held by capacitors 0632 and 0622 are summed by summing amplifier 0610.

[0163] Next, the double 0533 asserts the "Charge Acc (Other)" signal, which closes Figure 6 0611. This causes comparator 0612 to compare the voltage at the postAcc node with the output of summing amplifier 0611. The voltage from the summing amplifier will be greater than the voltage of the postAcc node by the amount sampled at the attenuation variable node. Therefore, comparator 0612 will cause switch 0613 to close and remain closed until the postAcc node has charged to a voltage substantially equal to the output of the summing amplifier.

[0164] As can be appreciated, the following is the net effect of the sequential assertion of the "Sample(other)" and "ChargeAcc(other)" signals. At each other spike, the voltage of the postAcc node increases by an amount equal to the present voltage of the decay variable node.

[0165] about Figure 7 , capacitor 0720 maintains the voltage of the preAcc signal (or node). However, as mentioned above Figure 4 As discussed in the Learn_Delay_PC pseudocode of , the preAcc node is designed to attenuate due to its combination with resistor 0721. As discussed above, the combination of attenuating the preAcc node and adding a unit voltage for every other spike is mathematically equivalent to determining ( Figure 3The) Pre n+1 function 0321 and adds its value to the non-decayed Pre accumulator. Figure 7 The attenuation preAcc node method is relatively simple from a circuit implementation perspective.

[0166] As discussed above, as part of starting up a new reference frame, the dual 0530 asserts (at its out2 output) the "RESET (FOR)" signal. Figure 7 , it can be seen that the reset (FOR) signal causes the reset of the following capacitors:

[0167] • The accumulation of preAcc values ​​is reset to zero by switch 0741 coupling the preAcc node to ground.

[0168] At the appropriate time, capacitor 0732 is used to hold a sample of the voltage at the postAcc node. It is reset by switch 0740 which couples capacitor 0732 to ground.

[0169] If the preAcc node is reset (via FOR d If another peak occurs after the peak, then a double 0533 is triggered. Figure 7 , it can be seen that the assertion of the “sample(other)” signal causes the current voltage to be sampled at the preAcc node by closing switch 0731.

[0170] After the assertion of the Sample(other) signal, the following occurs:

[0171] Switch 0731 is open, and the sampled voltage of the preAcc node is held by capacitor 0732 .

[0172] The voltage held by capacitor 0732 is summed with the unit voltage from voltage source 0714 by summing amplifier 0710 .

[0173] Next, the double 0533 asserts the "Charge Acc (Other)" signal, which closes Figure 7 0711. This causes comparator 0712 to compare the voltage at the preAcc node to the output of summing amplifier 0710. The voltage from the summing amplifier will be greater than the voltage at the preAcc node by the amount provided by unity voltage source 0714. Therefore, comparator 0712 will cause 0713 to close and remain closed until the preAcc node has charged to a voltage substantially equal to the output of the summing amplifier.

[0174] As can be appreciated, the following is the net effect of the sequential assertion of the "Sample(Other)" and "ChargeAcc(Other)" signals. At each other spike, the voltage of the preAcc node is increased by an amount equal to the unit voltage of Voltage Source 0714. After the increase, the preAcc node will continue its exponential decay until either of the following occurs:

[0175] · When FOR appears d In case of a spike the current reference frame ends.

[0176] Another spike appears.

[0177] 2.3 Generating Delay – Lossy Version

[0178] 2.3.1 Conflict Resolution

[0179] As discussed above, in Section 2.1 ("Introduction"), another important aspect of the present invention is to exploit the random nature of the spike stream presented to the FOR input of each CCU to generate a FOR at the output that produces a delay. d Option for a lossy version of .

[0180] Only one spike (one time) of memory passes through the delay (e.g., through Figure 2 Function block 0225) can be sufficient in the CCU's FOR d A useful stream of correlated spikes is generated at the output of the FOR. In this case, the generation delay can be considered as a kind of "timer". When a spike appears at the input of the FOR that generates the delay, the timer can be started. At the end of the delay period, the timer is the value of the FOR that generates the delay. d The output generates a spike. The use of a single spike memory is discussed below.

[0181] Since the lossy version that generates the delay requires much less memory (just a spike) than the lossless version (whose memory requirements are potentially infinite), we call the lossy version "memoryless."

[0182] The key issue when implementing a memory-less approach is what we call the "conflict resolution" problem. A conflict resolution problem can arise whenever the delay of a generation delay is greater than 0 seconds. Due to the random nature of the spike stream input to each CCU, whenever a generation delay is timing out for delay period d due to a FOR spike x, the next FOR spike x+1 is always likely to arrive. There are then two options:

[0183] Ignore spike x+1 and continue the timing of spike x until its delay period d is completed. We call this the "keep oldest" selection.

[0184] Restart the timer so that the delay period d starts with spike x + 1. We call this the "keep-update" selection.

[0185] Either of these two strategies can potentially be applied an infinite number of times sequentially if applied consistently. For example:

[0186] Keep the oldest: while timing the delay d of spike x, there may be an infinite number of subsequent FOR d Spikes may arrive. All of these will be ignored.

[0187] Staying up to date: If spike x is restarted by a delay of d due to spike x+1, then spike x+2 is likely to restart the time period of spike x+1, and spike x+3 is further likely to restart the time period of spike x+2. The restart of the delay period can continue to occur a potentially unlimited number of times.

[0188] Either of these two options has the effect of introducing a temporal bias into the learning delay when applied exclusively as a conflict resolution strategy. d Problems in comparison with other peak flows. Specifically:

[0189] Keep the oldest: with FOR d The effect of a spike stream appearing earlier than it should be relative to other spike streams. As a result, the delay caused by the generation delay is too large. This effect can be understood from the fact that the keep oldest strategy causes later spikes (i.e., spikes after spike x) to drop.

[0190] · Keep up to date: Have the FOR d The effect of a spike stream appearing later than it should be relative to other spike streams. The result is that the delay introduced by the generation delay is too small. This effect can be understood from the fact that the keep-up-to-date strategy causes earlier spikes (e.g., spike x that is older than spike x+1) to be ignored.

[0191] The time skew problem may be addressed by any technique that generally results in an equal number of selections for each of the keep-oldest and keep-newest policies. Figure 8 and Figure 2 The main difference is the introduction of the conflict resolution block 0224, where the proposed implementation can be seen. Figure 8 Function block 0220 (generate delay) contains a function that does not exist in Figure 2The additional "delay complete" output in function block 225 is provided. Delay complete is a logic 0 whenever a delay is occurring to time the delay cycle, and a logic 1 otherwise. Whenever delay complete is a logic 1, AND gate 0230 will permit a spike at FOR input 0211 to initiate a delay operation. This makes sense because there is no conflict with pre-existing delay cycles under these conditions.

[0192] Conversely, we know that a conflict scenario exists when a FOR spike arrives at input 0211 and the delay is complete at a logic 0. This scenario is decoded by AND gate 0233 of the conflict resolution block 0224. AND gate 0233, which produces a logic 1, causes one of two actions depending on the pre-existing state of flip-flop 0234:

[0193] If flip-flop 0234 happens to have generated a logic 1 at its Q output, then that Q output, along with the logic 1 from AND 0233, will cause AND 0232 to generate (via OR gate 0231) a signal that causes the delayed timer to restart. As can be seen, this is an implementation of the "keep current" strategy.

[0194] Conversely, if flip-flop 0234 happens to produce a logic 0 at its Q output, then the logic 0 prevents AND 0232 from generating a signal that causes a timed restart of the generated delay. This is an implementation of the "keep oldest" strategy.

[0195] Regardless of whether flip-flop 0234 happens to have already generated a logic 1, AND 0233 triggers flip-flop 0234 to change state each time it generates a logic 1. The net result is that resolve conflict block 0224 immediately implements a policy based on the current state of flip-flop 0234 after each conflict scenario is detected, and then changes the state of flip-flop 0234 so that the opposite policy is executed next time.

[0196] 2.3.2 Electrical Implementation Plan

[0197] Figures 9 to 10 An example electrical implementation for generating the delay is presented.

[0198] Figure 9 Depict the exponential decay curve through coupling (i.e., 0910 is e -rt ) and threshold detection (horizontal line 0911) to implement the delay example. Figure 9 In the example, the decay rate r is equal to 3, and the threshold to be detected (called th d ) is equal to 0.1. As can be seen, under these conditions, the resulting delay period (referred to as "d") is 0.77 seconds. As can be appreciated, the delay can be increased or decreased by lowering or increasing the threshold, respectively.

[0199] Figure 10 Presented for implementation Figure 8 The circuit system for generating delay functionality shown for functional block 0220 in FIG.

[0200] Figure 10 The outline 1010 indicates the external interface of the delay generation function block 0220, where each connection corresponds to an input or output of the delay generation function block 0220.

[0201] The exponential decay formed by the combination of capacitor 1040 and resistor 1041 forms the basis for the timing capability of generating the delay. The decay applied to the negative input of the comparator amplifier 1030 occurs at the "decay" node. The threshold value (called th) applied to the positive input of the comparator d ) is set by adjustable voltage source 1031. The voltage output by 1031 can be incrementally adjusted lower or higher by pulses applied to the "more d" or "less d" inputs, respectively, of interface 1010. At any one time, the state of voltage source 1031 (i.e., the voltage it is currently set to output) can be maintained by a capacitor (not shown).

[0202] Each spike at the start / restart input triggers the one-shot 1020. The one-shot 1020 generates a pulse that, when asserted, prepares the capacitor 1040 to generate a new exponential decay cycle through switches S1 and S2 of the switching unit 1043. Specifically, during the duration of the one-shot's pulse:

[0203] S1 couples capacitor 1040 to a unity voltage source 1042, and

[0204] • S2 ensures that the decay node maintains the correct initial value for restarting the exponential decay when capacitor 1040 is recharged.

[0205] Once the signal of single shot 1020 ends, the combination of capacitor 1040 and resistor 1041 begins its exponential decay. When the voltage of the decay node drops below the voltage output by voltage source 1031, the output of comparator 1030 generates a logic 1.

[0206] A logical 1 causes both of the following:

[0207] Assert the "delayed completion" output at interface 1010.

[0208] Trigger single shot 1021, whose pulse constitutes the FOR of interface 1010 d Spikes are output at the output.

[0209] 2.4 Learning Rate

[0210] As presented above, the generate delay and learn delay function blocks (e.g., Figure 8 Blocks 0220 and 0226 of FIG. 2 both operate by using exponential decay curves. The decay rate r of these functions can be selected based on the expected spike frequency for a particular application.

[0211] However, in the CCU, the average spike rate (which we call r ALL ) function block may be useful. In general, for generating delay and learning delay decay function, r ALL is a good value for r.

[0212] For example, regarding Figure 3 The learning delay shown in r ALL Can be used for both Post and Pre functions. Using this value of r tends to ensure that the other peaks are located in a region where each function changes relatively rapidly and is therefore easier to measure. By measuring the decay rate of the delay for the generated delay (e.g., see Figure 9 Function 0910) uses r ALL Achieve similar advantages.

[0213] Figure 11 Describing and Figure 8 The same CCU, except for the following:

[0214] Add the "Learning Rate Overall" (or LRA) function block 0223. As can be seen, LRA 0223 accepts a FOR spike as input and outputs r ALL .

[0215] · Add r ALL An input is added to each of the generation delay and the learning delay (hence their labeling from Figure 8 0220 and 0226 are changed to Figure 11 0227 and 0228). These ALL Input by LRA 0223 r ALL Output driver.

[0216] The learning rate is all based on the following properties of the random spike stream s: if a random spike stream has r ALL If the correct value of t is given, then the following expression provides the probability that the next spike will occur at time t or any later time:

[0217]

[0218] This also means that if a random spike stream decays exponentially according to Equation 1, the time P = 0.5 is the median expected arrival (or MEA) time of the next spike of stream s. We also call MEA ALL This median expected arrival time has the following special properties:

[0219] Special property 1: Among the large number of spikes in s, we can expect to see the MEA ALL The number of preceding spikes will be equal to the number appearing at MEA ALL The number of subsequent spikes.

[0220] for Figure 12 , assuming the actual MEA ALL Targeting r ALL = 3 is 0.23 seconds. As can be seen (for the purpose of clarity of illustration), the peaks a to d have been chosen to be evenly distributed across the MEA. ALL On both sides.

[0221] Special property 1 has the following meaning:

[0222] If MEA ALL A guess at the value of (called MEA guess ) is too high (ie, in practice, MEA guess >MEA ALL ), then in the peaks of s that appear in large numbers, in MEA guess The previous peak will be larger than that in MEA guess There are many spikes appearing later. Figure 13 An extreme example of this is shown, where MEA guess is 0.345 seconds (for r=2), and peaks a to d (labeled a' to d' relative to their positions for r=2) are all in MEA guess Front.

[0223] If MEA ALL A guess at the value of (called MEA guess ) is too low (ie, in practice, MEA guess <MEA ALL ), then in the peaks of s that appear in large numbers, in MEA guess The subsequent peak will be larger than that in MEA guess There are many spikes in the front. Figure 14 An example of this is shown where the MEA guess is 0.115 seconds (for r=6), and the same spikes a to d (now labeled a" to d" relative to r=6) all appear at MEA guess later.

[0224] Special property 1 together with its meaning can be found in MEA ALL The search process can be described as consisting of the following two main steps:

[0225] 1. Select MEA guess Reasonable initial values ​​for :

[0226] ○For example, MEA guess The choice of an initial value for r can be limited to a range of possible values ​​based on the specific system design and its intended application. guess ) to determine MEA guess The value of r guess To determine the MEA guess The MEA can then be determined according to Equation 1 guess Specifically, when P = 0.5 and r = r guess In this case, Equation 1 becomes:

[0227]

[0228] 2. For each pair of peaks n and n+1 of stream s, the time between the peaks (t n+1 -t n ) and MEA guess For comparison:

[0229] ○If (t n+1 -t n ) <MEA guess , assuming (based only on this latest data point) that MEA guess The guessed value of is too high, then:

[0230] ■ Reduce MEA for the purpose of subsequent comparison between spike pairs guess value.

[0231] ■ By using r guess Increment the standard amount (referred to as Δr) and then redefine Equation 2 to determine MEA guess The reduced value of .

[0232] ○If (t n+1 -t n )>MEA guess , assuming (based only on this latest data point) that MEA guess The guessed value of is too low, then:

[0233] ■ Add MEA when comparing subsequent spike pairs guess value.

[0234] ■ By using r guess Decrement the standard amount (called Δr) and then redefine Equation 2 to determine MEA guess of economic added value.

[0235] For each of the above assumptions for MEA guessToo high or too low In the search process listed above, there are the following possibilities:

[0236] If MEA is present in a large number of spikes guess is actually too high, then this fact is indicated by the appearance of MEA guess Too high rather than too low is more determined by comparison, and MEA guess The value of guess net increase in 2018).

[0237] If MEA is present in a large number of spikes guess is actually too low, then this fact is indicated by the presence of MEA guess Too low rather than too high is more determined by comparison, and MEA guess The value of guess net decrease).

[0238] MEA guess Only if it is factually correct (i.e., in the MEA guess =MEA ALL And r guess =r ALL net dynamic stability.

[0239] Therefore, in a sufficient number of peaks, r ALL , where Δr is chosen to provide convergence to r ALL The speed (also called "learning rate") is determined by r ALL A suitable compromise between the accuracy of the values:

[0240] Larger values ​​of Δr increase the learning rate but reduce the accuracy of the results.

[0241] Smaller values ​​of Δr decrease the learning rate but increase the accuracy of the results.

[0242] Except for solving Equation 1 for a point that yields one-half of its total range (e.g., P=0.5), Figure 15 An alternative way to find the MEA is also described. The alternative method is to solve for the time at which Equation 1 is equal to the following Equation 3 (where Equation 3 defines the cumulative probability distribution):

[0243]

[0244] like Figure 15 As can be seen, by finding the equal points, we can find the previous Figures 12 to 14 Each of the MEAs discussed.

[0245] This equality test method is Figure 16Based on the hardware implementation of , the hardware implementation can be described as follows.

[0246] Figure 16 The outline 1610 indicates the external interface of the LRA, where each connection corresponds to Figure 11 Input or output of LRA function block 0223.

[0247] exist Figure 16 , the exponential decay of Equation 1 is performed by the combination of capacitor 1630 and variable resistor 1631. The decay value is available at the "decay" node 1641. Equation 3 (exponential increase) is performed by the subtractive amplifier 1621 as follows:

[0248] Apply unity voltage to the 'A' input of the amplifier.

[0249] • Apply the attenuation node 1641 (ie, Equation 1) to the "B" input.

[0250] The output of the subtracting amplifier 1621 available at node 1640 is therefore the voltage level representation of Equation 3.

[0251] The equality test between Equation 1 and Equation 3 is performed by comparator amplifier 1622, where the result is available at node 1642 (corresponding to the MEA explained above). guess ).

[0252] Whenever there is a spike n, a doublet 1620 is triggered at the FOR input of interface 1610. The first step activated by the doublet out1 is to complete the MEA measurement starting with the last FOR spike n-1. Out1 operates this step by enabling AND gates 1623 and 1624 to read the output of comparator 1622.

[0253] The output of comparator 1622 can be interpreted as follows:

[0254] If the time period between the comparison indicator peaks n-1 and n is less than the current MEA guess , then comparator 1622 outputs a logic 1. This is because the exponential decay node 1641 drives the + input of the comparator.

[0255] If the duration between the comparison indicator spikes n-1 and n is greater than the current MEA guess , then comparator 1622 outputs a logic 0. This is because the exponential increase node 1640 drives the - input of the comparator.

[0256] If the current measurement of comparator 1622 indicates that MEA guessToo high, then a logic 1 on node 1642 causes AND gate 1623 to be enabled and the out1 pulse is applied to the R- input of variable resistor 1631. As can be appreciated, decreasing the resistance results in a faster decay rate at the "decay" node 1641 and a faster decay rate for MEA. guess downward adjustment.

[0257] Conversely, if the current measurement of comparator 1622 indicates that MEA guess If the value is too low, then a logic 0 on node 1642 causes AND gate 1624 to be enabled and the out1 pulse is applied to the R+ input of variable resistor 1631. As can be seen, increasing the resistance results in a slower decay rate at the "decay" node 1641 and a slower decay rate for MEA. guess upward adjustment.

[0258] Factors such as the duration of the out1 pulse and the specific configuration of the variable resistor 1631 determine r guess The change increments are each referred to as the Δr “learning rate” in the above discussion.

[0259] The state of the variable resistor 1631 (i.e., its current resistance level) can be maintained by an internal state capacitor (not shown). For example, the voltage of this capacitor can increase with each pulse to the R- input and decrease with each pulse to R+. In addition, the external interface 1610 driving the LRA can be connected to the R- input. ALL The output voltage follower amplifier (also not shown) obtains the voltage of the internal state capacitor.

[0260] As mentioned above about Figure 11 As discussed, LRA 0223 can be used to ALL The output is provided to each of the generation delay 0227 and the learning delay 0228. ALL enter.

[0261] Figure 6 and 7 By adding r ALL Part of the circuit implementation of the learning delay 0226 that changes with the input. For the circuit implementation of the learning delay 0228, Figure 6 and 7 Replace with Figure 17 and 18 . Figure 17 and 18 and Figure 6 and 7 The differences are as follows:

[0262] · Use acceptance r ALL Input 0601 variable resistor 0644 ( Figure 17)Replace fixed resistor 0641( Figure 6 ).

[0263] · Use acceptance r ALL Input 0701 variable resistor 0722 ( Figure 18 )Replace fixed resistor 0721( Figure 7 ).

[0264] For the circuit implementation that produces a delay of 0227, Figure 10 Replace with Figure 19 . Figure 19 and Figure 10 The difference is as follows: it accepts as part of its external interface 1011 ALL Input variable resistor 1044 ( Figure 19 ) replaces the fixed resistor 1041 ( Figure 10 ).

[0265] In order to make the LRA r ALL The voltage at the output produces an exponential decay curve (for the generation delay 0227 and the learning delay 0228), where r is equal to r found by LRA 0223. ALL , you can complete the following:

[0266] · Capacitor 0640 (see Figure 17 Implementation of postAcc), 0720 (see Figure 18 Implementation of preAcc) and 1040 (see Figure 19 The embodiment of generating delay) has a capacitor 1630 with LRA (see Figure 16 ) same capacitance.

[0267] · Can make variable resistor 0644 (see Figure 17 Implementation of postAcc), 0722 (see Figure 18 Implementation of preAcc) and 1044 (see Figure 19 Implementation scheme for generating delay) and the variable resistor 1631 of the LRA (see Figure 16 ) with the following exceptions: Each of 0644, 0722, and 1044 uses the external interface r ALL The input drives the voltage follower instead of holding internal state.

[0268] 3 Selected Glossary

[0269] Summing amplifier: A voltage whose output at any instant is the sum of the voltages present at its inputs.

[0270] Single-shot: It has an input trigger and one output. It generates a pulse at its output immediately after receiving a trigger signal.

[0271] Spike: As used herein, a spike may refer to any point in a signal between two different levels that can be considered to have substantially (or approximately) zero transition time.

[0272] Subtracting amplifier: At any instant in time, the output is the voltage resulting from subtracting the voltage present at the second input from the voltage present at the first input.

[0273] Dual-shot: has one input flip-flop and two outputs. Upon receiving a trigger signal, it generates a pulse sequentially at each of its two outputs.

[0274] 4 Computing devices

[0275] As is generally known to those skilled in the art, the inventive methods, processes, or techniques described herein may be implemented using any suitable computing hardware. Suitable hardware may include the use of one or more general-purpose computers or processors. Hardware implementation techniques may include the use of various types of integrated circuits, programmable memory (volatile and non-volatile), or both.

[0276] Computing hardware (whether in the form of integrated circuits or otherwise) is typically based on the use of transistors (field-effect, bipolar, or both), although other types of components (e.g., optical, microelectromechanical, or magnetic) may be included. Any computing hardware has the property that it consumes energy as a necessary part of being able to perform its functions. Furthermore, no matter how fast it can operate, computing hardware will require a certain amount of time to change state. Because it is based on physical devices (electronic or otherwise), computing hardware, no matter how small, will occupy a certain amount of physical space.

[0277] Programmable memory is also typically implemented in the form of integrated circuits and is subject to the same physical limitations described above for computing hardware. Programmable memory is intended to include devices that use any type of physics-based effect or property to store information, at least in a non-transitory manner and for an amount of time commensurate with the application. The types of physical effects used to implement such storage include, but are not limited to: maintaining a specific state through a feedback signal, charge storage, changes in the optical properties of a material, magnetic changes, or chemical changes (reversible or irreversible).

[0278] Unless specifically indicated otherwise, the terms computing hardware, programmable memory, computer-readable media, systems, and subsystems do not include a person or mental steps that a person might take.

[0279] Any of the methods, processes, or techniques described above, when implemented by programming a computer or other data processing system, may also be described as a computer program product. The computer program product may be embodied on any suitable computer-readable medium or programmable memory.

[0280] The types of information described herein (e.g., data and / or instructions) (on a computer-readable medium and / or programmable memory) may be stored on a computer-readable code device embodied herein. The computer-readable code device may represent that portion of a memory in which defined information units (e.g., bits) may be stored, from which defined information units may be retrieved, or both.

[0281] Although the present invention has been described in conjunction with specific embodiments, it is apparent that many alternatives, modifications and variations will be apparent in light of the foregoing description. Therefore, the present invention is intended to encompass all such alternatives, modifications and variations that fall within the spirit and scope of the appended claims and equivalents.

Claims

1. A method for cross-correlation, comprising: receiving a first spike stream comprising a first plurality of random spikes and a first non-random spike, the receiving being performed at least in part by an electronic hardware configuration; receiving a second spike stream comprising a second plurality of random spikes and a second non-random spike, the receiving being performed at least in part by an electronic hardware configuration, wherein the first non-random spike and the second non-random spike have a fixed temporal relationship; inputting the first spike stream into a first delay unit, the inputting being performed at least in part by means of an electronic hardware configuration; outputting a first delayed spike stream from the first delay unit by inserting a first delay into the first spike stream, the outputting being performed at least in part by means of an electronic hardware configuration, wherein the first delay is generated by the first delay unit and has a lower bound of zero seconds; comparing a first accumulated value to a second accumulated value upon receiving a first delayed spike from the first delayed spike stream to produce a first comparison result, the comparison being performed at least in part by means of an electronic hardware configuration; if the first comparison result indicates that the first accumulated value is greater than the second accumulated value, increasing the first delay; if the first comparison result indicates that the first accumulated value is less than the second accumulated value, reducing the first delay; resetting the first accumulated value and the second accumulated value after generating the first comparison result; restarting a first process for generating a first weighting function and a second weighting function after generating the first comparison result, wherein the first weighting function is monotonically decreasing and the second weighting function is both monotonically increasing and symmetrically opposite to the first weighting function; accumulating a first weighted value in a first accumulator according to the first weighting function immediately after receiving a second spike from the second spike stream; and A second weighted value is accumulated in a second accumulator according to the second weighting function upon receipt of the same second spike from the second spike stream.

2. The method according to claim 1, further comprising: increasing the first delay by increasing the length of a first queue including the first delay unit; and The first delay is reduced by reducing the length of the first queue.

3. The method according to claim 1, further comprising: timing a duration equal to the first delay immediately after inputting a first undelayed spike from the first spike stream into the first delay cell if timing of the first delay cell has not yet been initiated; outputting a spike immediately after completion of any timing of said first delay; deciding, based on a first state of a first decision variable and based on receiving a second undelayed spike during the duration of a previous undelayed spike, to continue the duration of the previous undelayed spike; determining a timing to restart the first delay of the first delay cell based on a second state of the first decision variable and based on receipt of the second undelayed spike during the duration of the previous undelayed spike; Substantially equal occurrences of the first and second states are ensured for the first decision variable in a plurality of instances in which the second undelayed spike is received during the duration of the previous undelayed spike.

4. The method according to claim 1, further comprising: increasing a first average spike rate for use in generating both the first exponentially decreasing function and the first exponentially increasing function if the first exponentially decreasing function is greater than the first exponentially increasing function upon receiving a first undelayed spike from the first spike stream; If a first exponentially decreasing function is less than a first exponentially increasing function when the first undelayed spike from the first spike stream is received, reducing the first average spike rate for use in generating both the first exponentially decreasing function and the first exponentially increasing function; and The first average spike rate is used to generate the first and second weighting functions.

5. The method according to claim 3, further comprising: increasing a first average spike rate for use in generating both the first exponentially decreasing function and the first exponentially increasing function if the first exponentially decreasing function is greater than the first exponentially increasing function upon receiving a first undelayed spike from the first spike stream; If a first exponentially decreasing function is less than a first exponentially increasing function when the first undelayed spike from the first spike stream is received, reducing the first average spike rate for use in generating both the first exponentially decreasing function and the first exponentially increasing function; and The first delay is timed using the first average spike rate.

6. A system for cross-correlation, comprising: a first subsystem configured, at least in part, by electronic hardware, to receive a first spike stream comprising a first plurality of random spikes and a first non-random spike; a second subsystem configured, at least in part by electronic hardware, to receive a second spike stream comprising a second plurality of random spikes and a second non-random spike, wherein the first non-random spikes and the second non-random spikes have a fixed temporal relationship; a first delay unit that receives the first spike stream at least in part by means of an electronic hardware configuration and outputs a first delayed spike stream by inserting a first delay into the first spike stream, wherein the first delay is generated by the first delay unit and has a lower limit of zero seconds; a third subsystem that, upon receiving the first delayed spike from the first delayed spike stream, compares the first accumulated value with the second accumulated value to produce a first comparison result, at least in part by means of electronic hardware configuration; a fourth subsystem that increases the first delay at least in part by means of an electronic hardware configuration if the first comparison indicates that the first accumulated value is greater than the second accumulated value; a fifth subsystem that reduces the first delay at least in part by means of an electronic hardware configuration if the first comparison result indicates that the first accumulated value is less than the second accumulated value; a sixth subsystem that resets the first accumulated value and the second accumulated value at least in part by means of an electronic hardware configuration after generating the first comparison result; a seventh subsystem that, after generating the first comparison result, restarts, at least partially by means of the electronic hardware configuration, a first process for generating a first weighting function and a second weighting function, wherein the first weighting function is monotonically decreasing and the second weighting function is both monotonically increasing and symmetrically opposite to the first weighting function; an eighth subsystem that accumulates a first weighted value into a first accumulator at least in part by means of an electronic hardware configuration upon receiving a second spike from the second spike stream and in accordance with the first weighting function; and A ninth subsystem accumulates a second weighted value into a second accumulator at least in part by means of electronic hardware configuration upon receiving the same second spike from the second spike stream and according to the second weighting function.

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