A verification method, device, equipment and medium for a network-on-chip design example

Abstract

The present invention discloses a verification method, device, equipment and medium for a network-on-chip design instance, including: obtaining an interactive file corresponding to a network-on-chip NoC design instance to be tested, wherein the interactive file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner; obtaining a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interactive file, and generating configuration files and test cases corresponding to the target VIP core respectively; configuring the target VIP core according to the configuration file, and simulating the configured target VIP core in a preset verification platform framework by calling a test case to obtain a verification result corresponding to the NoC design instance to be tested. The technical solution of the embodiment of the present invention can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to a verification method, device, equipment and medium for an on-chip network design instance. Background Art

[0002] In chip design, especially in large-scale System on Chip (SoC), various functional intellectual property (IP) cores are widely used. The traditional on-chip bus interconnection architecture can no longer meet the interconnection and communication requirements between a large number of IP cores.

[0003] As a new type of on-chip bus interconnection structure, Network on a Chip (NoC) has been widely used in large-scale SoC chip design due to its high flexibility. However, in order to connect various types of IP cores, NoC needs to design different instances for different IP cores. Therefore, in the system architecture of the same SoC chip, there are often multiple NoC design instances of different types. Since the accuracy of the NoC design instance directly affects the operation results of the SoC chip, it is necessary to verify each NoC design instance in the SoC chip.

[0004] Different NoC design instances support different types, quantities, and interface characteristics of IP core interfaces. In the prior art, a dedicated verification system needs to be developed for each type of NoC design instance, resulting in low verification efficiency and high verification cost. Secondly, the NoC design instances involve many types of IP core interfaces and the interface protocols are relatively complex. Designers lack an effective description mechanism when delivering NoC design instances, which is not conducive to verifiers developing the corresponding verification environment quickly and accurately. Summary of the invention

[0005] The embodiments of the present invention provide a verification method, device, equipment and medium for a NoC design instance, which can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance.

[0006] In a first aspect, an embodiment of the present invention provides a method for verifying an on-chip network design instance, the method comprising:

[0007] Acquire an interaction file corresponding to a network on chip (NoC) design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner;

[0008] According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively;

[0009] The target VIP core is configured according to the configuration file, and the test case is called to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0010] In a second aspect, an embodiment of the present invention further provides a verification device for an on-chip network design example, the device comprising:

[0011] A file acquisition module, used to acquire an interactive file corresponding to a NoC design instance to be tested, wherein the interactive file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner;

[0012] A VIP core acquisition module, used to acquire a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and to generate a configuration file and a test case corresponding to the target VIP core respectively;

[0013] The simulation module is used to configure the target VIP core according to the configuration file, and call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0014] In a third aspect, an embodiment of the present invention further provides a computer device, the device comprising:

[0015] one or more processors;

[0016] A storage device for storing one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement a verification method for an on-chip network design example provided by any embodiment of the present invention.

[0018] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a verification method for an on-chip network design instance provided by any embodiment of the present invention.

[0019] The technical solution of the embodiment of the present invention obtains an interaction file corresponding to the on-chip network NoC design instance to be tested, obtains the target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and generates a configuration file and a test case corresponding to the target VIP core respectively, configures the target VIP core according to the configuration file, and calls the test case to simulate the configured target VIP core in the preset verification platform framework to obtain a technical means for obtaining a verification result corresponding to the NoC design instance to be tested, which can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a flow chart of a verification method of an on-chip network design example in Embodiment 1 of the present invention;

[0021] Figure 2 is a flow chart of a verification method of an on-chip network design example in Embodiment 2 of the present invention;

[0022] Figure 3 is a flow chart of a verification method of an on-chip network design example in Embodiment 3 of the present invention;

[0023] Figure 4 It is a structural diagram of a verification device of an on-chip network design example in Embodiment 4 of the present invention;

[0024] Figure 5 It is a structural diagram of a computer device in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific examples described herein are only used to explain the present invention, rather than to limit the present invention. It is also necessary to explain that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0026] Embodiment 1

[0027] Figure 1 This is a flowchart of a verification method for a network on chip design instance provided in the first embodiment of the present invention. This embodiment is applicable to the case of verifying a NoC design instance in a SoC chip system architecture. The method can be executed by a verification device for the network on chip design instance. The device can be implemented by software and / or hardware, and can generally be integrated in a terminal or server with a data processing function. Specifically, the method includes the following steps:

[0028] Step 110: Acquire an interaction file corresponding to the NoC design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner.

[0029] In this embodiment, after the designer develops the NoC design instance, he can describe the characteristic information of the NoC design instance to be tested in advance according to a unified standard information description method, obtain the interaction file, and upload the interaction file and the register transfer level (RTL) code of the NoC design instance to the terminal or server.

[0030] In this step, the interaction file may specifically include interface description information, internal feature description information, interface connectivity description information, address mapping description information, etc. of the NoC design instance to be tested.

[0031] Therefore, the designer can obtain an interactive file by describing the NoC design instance to be tested in a unified standard information description method, which is beneficial for the verifier to quickly and accurately develop a corresponding verification environment according to the characteristic information of the NoC design instance to be tested, thereby improving the verification efficiency of the NoC design instance.

[0032] Step 120: According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively.

[0033] In this embodiment, the verification platform framework can be developed based on the Universal Verification Methodology (UVM) platform using SystemVerilog language. The verification platform framework can include all types and defined Verification Intellectual Property (VIP) cores required by the NoC design instance.

[0034] In this step, the target VIP core corresponding to the NoC design instance to be tested can be obtained in the verification platform framework according to the interface description information in the interaction file, and then a configuration file corresponding to the target VIP core can be generated according to the interface description information and internal characteristic description information corresponding to the NoC design instance to be tested, so that the target VIP core can work normally under the configuration of the configuration file.

[0035] In this step, optionally, a test case corresponding to the target VIP core may be generated based on the interface connectivity description information and the address mapping description information in the interaction file.

[0036] In this embodiment, by developing a unified verification platform framework, it is possible to complete verification of multiple different NoC design instances at the same time, thereby avoiding the problem of low verification efficiency caused by the need to develop a special verification system for each type of NoC design instance in the prior art; secondly, the verification platform framework only needs to be maintained separately and can be applied to the verification system of the NoC design instance, thereby reducing the verification cost of the NoC design instance.

[0037] Step 130: configure the target VIP core according to the configuration file, and call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0038] In this step, the target VIP core can be functionally configured according to at least one configuration information in the configuration file, and then the test case is called to simulate the configured target VIP core through a simulation tool in the verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0039] The technical solution of the embodiment of the present invention obtains an interaction file corresponding to the on-chip network NoC design instance to be tested, obtains the target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and generates a configuration file and a test case corresponding to the target VIP core respectively, configures the target VIP core according to the configuration file, and calls the test case to simulate the configured target VIP core in the preset verification platform framework to obtain a technical means for obtaining a verification result corresponding to the NoC design instance to be tested, which can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance.

[0040] Embodiment 2

[0041] This embodiment is a further refinement of the above embodiment. The explanation of terms that are the same or corresponding to those in the above embodiment will not be repeated in this embodiment. Figure 2 This is a flow chart of a verification method for a network-on-chip design example provided in the second embodiment. In this embodiment, the technical solution of this embodiment can be combined with one or more methods in the solutions of the above embodiments, such as Figure 2 As shown, the method provided in this embodiment may also include:

[0042] Step 210: Acquire an interaction file corresponding to the NoC design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner.

[0043] Step 220: Generate a VIP core interface binding file corresponding to the NoC design instance to be tested according to the interface description information in the interaction file.

[0044] In this embodiment, specifically, the interface description information may include the interface name, the number of interfaces, the interface master-slave type (or input / output type), the interface read / write characteristics, the interface protocol type, the bit width of each group of signals of the protocol corresponding to the interface, the clock signal name and frequency, the reset signal name and characteristics, and the bit width and default value of other special signals, etc. The interface description information may be stored in the form of a file or a database, etc., which is not limited in this embodiment.

[0045] In this step, the interface description information can be obtained from an interface description information file or data, and the interface description information is analyzed by an analyzer to obtain an analysis result. Then, a generator is used to generate a VIP core interface binding file corresponding to the NoC design instance to be tested according to the analysis result and a preset output format.

[0046] The analyzer and generator may be implemented using a scripting language or a programming language, which is not limited in this embodiment.

[0047] Step 230: According to the VIP core interface binding file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework.

[0048] In this step, the target VIP core corresponding to the NoC design instance to be tested can be obtained in the preset verification platform framework according to the association information between the NoC design instance to be tested and the target VIP core in the VIP core interface binding file.

[0049] Step 240: Generate a configuration file corresponding to the target VIP core according to the internal characteristic description information of the NoC design instance to be tested and the interface description information in the interaction file.

[0050] In this embodiment, specifically, the internal characteristic description information may include information such as internal cache size and whether memory storage is supported, etc. The internal characteristic description information may be stored in a file form or a database form, etc., which is not limited in this embodiment.

[0051] In this step, the internal feature description information can be obtained from an internal feature description information file or data, and the internal feature description information and the interface description information can be analyzed by an analyzer to obtain an analysis result. Then, a generator can generate a configuration file corresponding to the target VIP core according to the analysis result and a preset output format.

[0052] In this embodiment, the configuration file may include the following configuration information: the type of VIP core, the number of VIP cores, the bit width of each signal of the interface protocol, the control of whether VIP is enabled, the control of VIP internal characteristics, etc. Taking the VIP core of the Advanced eXtensible Interface (AXI) protocol as an example, it is necessary to set the outstanding value of AXI-VIP to implement the characteristic test of the AXI interface protocol in the NoC design example.

[0053] Step 250: Generate a test case corresponding to the target VIP core according to the interface connectivity description information and the address mapping description information of the NoC design instance to be tested in the interaction file.

[0054] In a specific embodiment, the interface connectivity description information may include: the name of the input interface, which must be consistent with the interface name in the interface description information; the name of the output interface, which must be consistent with the interface name in the interface description information; and an identifier of whether the input interface and the output interface are connected, etc. The interface connectivity description information may be stored in a file form or a database form, etc., which is not limited in this embodiment.

[0055] In this embodiment, specifically, the address mapping description information may include: the starting address and the ending address of the address segment, and different address segments are stored in different records; the name of the output interface corresponding to each address segment, and this interface name must be consistent with the interface name in the interface description information; if there is a reserved address, it needs to be stored in a separate record; if the allocation of the address segment is subject to specific conditions, it needs to be explicitly specified. The address mapping description information can be stored in the form of a file or a database, etc., and this embodiment does not limit this.

[0056] In this step, the interface connectivity description information and the address mapping description information can be analyzed by an analyzer to obtain an analysis result, and then a generator can generate a test case corresponding to the target VIP core according to the analysis result and a preset output format.

[0057] In this embodiment, the test cases include three types of tests: read-only, write-only, and read-write. Since the test data must be output from the specified output port after entering from the input port specified in the NoC design instance, it is necessary to obtain the connectivity between interfaces by analyzing the interface connectivity description information, and determine the interface to which the transaction needs to be sent. At the same time, it is also necessary to generate the transaction data packet that needs to be sent during the simulation by analyzing the address mapping information.

[0058] Step 260: configure the target VIP core according to the configuration file, and call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0059] In one implementation of this embodiment, the configured target VIP core is simulated by calling the test case to obtain a verification result corresponding to the NoC design instance to be tested, including:

[0060] Step 261: Call the test case to simulate the configured target VIP core, and obtain the target transaction transmitted between the target VIP core and the NoC design instance to be tested during the simulation process;

[0061] In this step, when the target VIP core sends a target transaction to the NoC design instance under test, or receives a target transaction sent by the NoC design instance under test, the monitoring program in the target VIP core sends the detected target transaction to the transaction collector.

[0062] Step 262: predict and analyze the target transaction to obtain a transaction analysis result and a transaction response result;

[0063] In this step, the properties of the target transaction can be analyzed by the transaction collector, and the transaction analysis results can be output in a preset output format. The transaction properties that the transaction collector needs to analyze may include: the start and end time of the transaction request and response, the address of the transaction, the size of the transaction, and the name of the transaction's entry and exit interface in the NoC design instance to be tested.

[0064] In this embodiment, after the transaction collector collects the target transaction, it can also transmit the target transaction to the predictor, which predicts the target transaction through a built-in prediction model to obtain a transaction response result, and transmits the transaction response result to the scoreboard.

[0065] Step 263: Compare the transaction response result with the response transaction on the NoC design instance to be tested to obtain a transaction comparison result;

[0066] In this step, the transaction response result can be compared with the response transaction on the NoC design instance to be tested through the scoreboard to obtain a transaction comparison result.

[0067] Step 264: Use the transaction analysis result and the transaction comparison result together as a verification result corresponding to the NoC design instance to be tested.

[0068] In this embodiment, optionally, the target VIP core may also detect the protocol of the interface on the NoC design instance to be tested, obtain a protocol detection result, and use the protocol detection result as a verification result corresponding to the NoC design instance to be tested.

[0069] The technical solution of the embodiment of the present invention obtains an interaction file corresponding to a network on chip (NoC) design instance to be tested, generates a VIP core interface binding file according to the interface description information in the interaction file, obtains a target VIP core in a verification platform framework according to the VIP core interface binding file, generates a configuration file corresponding to the target VIP core according to the internal characteristic description information and interface description information of the NoC design instance to be tested in the interaction file, generates a test case corresponding to the target VIP core according to the interface connectivity description information and address mapping description information of the NoC design instance to be tested in the interaction file, configures the target VIP core according to the configuration file, and calls the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested. The technical means can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance.

[0070] Embodiment 3

[0071] This embodiment is a further refinement of the above embodiment. The explanation of terms that are the same or corresponding to those in the above embodiment will not be repeated in this embodiment. Figure 3 This is a flow chart of a verification method for a network-on-chip design example provided in the third embodiment. In this embodiment, the technical solution of this embodiment can be combined with one or more methods in the solutions of the above embodiments, such as Figure 3 As shown, the method provided in this embodiment may also include:

[0072] Step 310: Obtain an interaction file corresponding to the NoC design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner.

[0073] Step 320: According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively.

[0074] Step 330: configure the target VIP core according to the configuration file, and call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0075] In one implementation of the present embodiment, before configuring the target VIP core according to the configuration file and calling the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested, it also includes: compiling the RTL code of the NoC design instance to be tested, the verification platform framework, the VIP core interface binding file, the configuration file and the test case through a preset simulation tool.

[0076] Among them, if the RTL code of the NoC design instance to be tested, the verification platform framework, the VIP core interface binding file, the configuration file and the compilation results of the test case are all correct, the target VIP core can be configured according to the configuration file, and the configured target VIP core can be simulated by calling the test case in the preset verification platform framework.

[0077] Step 340: Generate a simulation result log according to the verification result, and extract transaction information in a preset format from the simulation result log to obtain a simulation result report corresponding to the NoC design instance to be tested.

[0078] In this step, the transaction information in a preset format may be extracted from the simulation result log by an analyzer, and then a simulation result report corresponding to the NoC design instance to be tested may be generated according to the transaction information by a generator.

[0079] Step 350: store the simulation result report in a preset database, and render the simulation result report in the database through a data renderer to obtain a visual report.

[0080] In this step, the simulation result report can be stored in a preset database by the generator. Since the database has a good processing capability for concurrent read and write requests, by storing the simulation result report in a preset database, the consistency and validity of the data acquisition results can be ensured during the simultaneous execution of the extraction of multiple simulation result reports.

[0081] In a specific embodiment, the visual report can be displayed via a local document or a web page. When the visual report is displayed via a local document, the user can view it using a corresponding viewer. For example, when the visual report is displayed in Excel format, the user can view it using Excel software. When the visual report is displayed via a web page, the user can view it using a browser.

[0082] In this embodiment, by generating a visual report corresponding to the NoC design instance to be tested, the simulation result of the NoC design instance can be intuitively presented to the user, which is convenient for the user to analyze and count the simulation result of the NoC design instance.

[0083] The technical solution of the embodiment of the present invention obtains an interaction file corresponding to an on-chip network NoC design instance to be tested, obtains a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and generates a configuration file and a test case corresponding to the target VIP core respectively, configures the target VIP core according to the configuration file, and simulates the configured target VIP core in the preset verification platform framework by calling the test case to obtain a verification result corresponding to the NoC design instance to be tested, generates a simulation result log according to the verification result, extracts transaction information in a preset format from the simulation result log, obtains a simulation result report corresponding to the NoC design instance to be tested, stores the simulation result report in a preset database, and renders the simulation result report in the database through a data renderer to obtain a visual report. The technical means can improve the verification efficiency of the NoC design instance, reduce the verification cost of the NoC design instance, and facilitate users to analyze and count the simulation results of the NoC design instance.

[0084] Embodiment 4

[0085] Figure 4 This is a structural diagram of a verification device for an on-chip network design example provided in Embodiment 4 of the present invention. The device includes: a file acquisition module 410, a VIP core acquisition module 420 and a simulation module 430.

[0086] The file acquisition module 410 is used to acquire an interactive file corresponding to the NoC design instance to be tested, wherein the interactive file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner;

[0087] A VIP core acquisition module 420 is used to acquire a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and to generate a configuration file and a test case corresponding to the target VIP core respectively;

[0088] The simulation module 430 is used to configure the target VIP core according to the configuration file, and call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0089] The technical solution of the embodiment of the present invention obtains an interaction file corresponding to the on-chip network NoC design instance to be tested, obtains the target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and generates a configuration file and a test case corresponding to the target VIP core respectively, configures the target VIP core according to the configuration file, and calls the test case to simulate the configured target VIP core in the preset verification platform framework to obtain a technical means for obtaining a verification result corresponding to the NoC design instance to be tested, which can improve the verification efficiency of the NoC design instance and reduce the verification cost of the NoC design instance.

[0090] Based on the above embodiments, the VIP core acquisition module 420 may include:

[0091] A binding file generating unit, configured to generate a VIP core interface binding file corresponding to the NoC design instance to be tested according to the interface description information in the interaction file;

[0092] A target VIP core acquisition unit, configured to acquire a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the VIP core interface binding file;

[0093] A configuration file generating unit, configured to generate a configuration file corresponding to the target VIP core according to the internal characteristic description information of the NoC design instance to be tested and the interface description information in the interaction file;

[0094] The test case generation unit is used to generate a test case corresponding to the target VIP core according to the interface connectivity description information and the address mapping description information of the NoC design instance to be tested in the interaction file.

[0095] The simulation module 430 may include:

[0096] A transaction acquisition unit, configured to call the test case to simulate the configured target VIP core, and acquire the target transaction transmitted between the target VIP core and the NoC design instance to be tested during the simulation process;

[0097] A transaction analysis unit, used to predict and analyze the target transaction to obtain a transaction analysis result and a transaction response result;

[0098] A transaction comparison unit, used for comparing the transaction response result with the response transaction on the NoC design instance to be tested, to obtain a transaction comparison result;

[0099] A verification result determination unit, configured to use the transaction analysis result and the transaction comparison result together as a verification result corresponding to the NoC design instance to be tested;

[0100] A result report generating unit, configured to generate a simulation result log according to the verification result, and extract transaction information in a preset format from the simulation result log to obtain a simulation result report corresponding to the NoC design instance to be tested;

[0101] A result report storage unit, used for storing the simulation result report in a preset database, and rendering the simulation result report in the database to obtain a visual report through a data renderer;

[0102] The compiling unit is used to compile the RTL code of the NoC design instance to be tested, the verification platform framework, the VIP core interface binding file, the configuration file and the test case through a preset simulation tool.

[0103] The verification device of the on-chip network design example provided in the embodiment of the present invention can execute the verification method of the on-chip network design example provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0104] Embodiment 5

[0105] Figure 5 A schematic diagram of the structure of a computer device provided in Embodiment 5 of the present invention is shown in FIG. Figure 5 As shown, the computer device includes a processor 510, a memory 520, an input device 530, and an output device 540; the number of the processor 510 in the computer device can be one or more. Figure 5 A processor 510 is taken as an example; the processor 510, the memory 520, the input device 530 and the output device 540 in the computer device can be connected via a bus or other means. Figure 5The example of connecting via a bus is taken. The memory 520, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to a verification method for an on-chip network design instance in any embodiment of the present invention (for example, a file acquisition module 410, a VIP core acquisition module 420 and a simulation module 430 in a verification device for an on-chip network design instance). The processor 510 executes various functional applications and data processing of the computer device by running the software programs, instructions and modules stored in the memory 520, that is, implements the above-mentioned verification method for an on-chip network design instance. That is, when the program is executed by the processor, it implements:

[0106] Acquire an interaction file corresponding to a network on chip (NoC) design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner;

[0107] According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively;

[0108] The target VIP core is configured according to the configuration file, and the test case is called to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0109] The computer device may be a large-scale SoC chip using a NoC design example, or a terminal or server with data processing functions, etc., which is not limited in this embodiment. Specifically, the processor 510 may be a central processing unit (CPU) or the like.

[0110] The memory 520 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 520 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 520 may further include a memory remotely arranged relative to the processor 510, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The input device 530 may be used to receive input digital or character information, and to generate key signal input related to user settings and function control of the computer device, and may include a keyboard and a mouse, etc. The output device 540 may include a display device such as a display screen.

[0111] Embodiment 6

[0112] Embodiment 6 of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the method described in any embodiment of the present invention is implemented. Of course, a computer-readable storage medium provided by an embodiment of the present invention can perform the relevant operations in a verification method of an on-chip network design example provided by any embodiment of the present invention. That is, when the program is executed by a processor, it implements:

[0113] Acquire an interaction file corresponding to a network on chip (NoC) design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner;

[0114] According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively;

[0115] The target VIP core is configured according to the configuration file, and the test case is called to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested.

[0116] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0117] It is worth noting that in the embodiment of the verification device of the above-mentioned on-chip network design example, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0118] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A verification method for a network-on-chip design example, characterized in that: The method comprises: Acquire an interaction file corresponding to a NoC design instance to be tested, wherein the interaction file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner; the interaction file includes interface description information, internal characteristic description information, interface connectivity description information, and address mapping description information of the NoC design instance to be tested; According to the characteristic information in the interaction file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework, and a configuration file and a test case corresponding to the target VIP core are generated respectively; The target VIP core is configured according to the configuration file, and the test case is called to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested; Wherein, obtaining a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file includes: Generate a VIP core interface binding file corresponding to the NoC design instance to be tested according to the interface description information in the interaction file; According to the VIP core interface binding file, a target VIP core corresponding to the NoC design instance to be tested is obtained in a preset verification platform framework.

2. The method according to claim 1, characterized in that Generating a configuration file corresponding to the target VIP core according to the characteristic information in the interaction file includes: A configuration file corresponding to the target VIP core is generated according to the internal characteristic description information of the NoC design instance to be tested and the interface description information in the interaction file.

3. The method according to claim 1, characterized in that Generate a test case corresponding to the target VIP core according to the characteristic information in the interaction file, including: A test case corresponding to the target VIP core is generated according to the interface connectivity description information and the address mapping description information of the NoC design instance to be tested in the interaction file.

4. The method according to claim 1, characterized in that: For the configured target VIP core, calling the test case to perform simulation, and obtaining a verification result corresponding to the NoC design instance to be tested, including: For the configured target VIP core, calling the test case to perform simulation, and obtaining the target transaction transmitted between the target VIP core and the NoC design instance to be tested during the simulation process; Predicting and analyzing the target transaction to obtain a transaction analysis result and a transaction response result; Comparing the transaction response result with the response transaction on the NoC design instance to be tested to obtain a transaction comparison result; The transaction analysis result and the transaction comparison result are used together as a verification result corresponding to the NoC design instance to be tested.

5. The method according to claim 1, characterized in that After obtaining the verification result corresponding to the NoC design instance to be tested, the method further includes: Generate a simulation result log according to the verification result, and extract transaction information in a preset format from the simulation result log to obtain a simulation result report corresponding to the NoC design instance to be tested; The simulation result report is stored in a preset database, and the simulation result report in the database is rendered by a data renderer to obtain a visual report.

6. The method according to any one of claims 1 to 5, characterized in that: Before configuring the target VIP core according to the configuration file and simulating the configured target VIP core in a preset verification platform framework by calling the test case to obtain a verification result corresponding to the NoC design instance to be tested, the method further includes: The RTL code of the NoC design instance to be tested, the verification platform framework, the VIP core interface binding file, the configuration file and the test case are compiled through a preset simulation tool.

7. A verification device for a network-on-chip design example, characterized in that: The device comprises: A file acquisition module is used to acquire an interactive file corresponding to a NoC design instance to be tested, wherein the interactive file includes characteristic information obtained by describing the NoC design instance to be tested in a standard information description manner; the interactive file includes interface description information, internal characteristic description information, interface connectivity description information, and address mapping description information of the NoC design instance to be tested; A VIP core acquisition module, used to acquire a target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the characteristic information in the interaction file, and to generate a configuration file and a test case corresponding to the target VIP core respectively; A simulation module, configured to configure the target VIP core according to the configuration file, and to call the test case to simulate the configured target VIP core in a preset verification platform framework to obtain a verification result corresponding to the NoC design instance to be tested; The VIP core acquisition module includes: A binding file generating unit, configured to generate a VIP core interface binding file corresponding to the NoC design instance to be tested according to the interface description information in the interaction file; The target VIP core acquisition unit is used to acquire the target VIP core corresponding to the NoC design instance to be tested in a preset verification platform framework according to the VIP core interface binding file.

8. A computer device, comprising: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the verification method of the on-chip network design example as claimed in any one of claims 1 to 6 when executing the programs.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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