Method for forming a pattern using a reverse pattern

Abstract

The present disclosure provides a method for forming a pattern using an inversion pattern. In the method for forming a pattern, a first upper inversion pattern and a second upper inversion pattern may be formed on a lower inversion layer. A buffer layer may be formed to fill a first opening portion provided by the first upper inversion pattern. A shielding pattern may be formed to cover a second region of the buffer layer. An etching process may be performed using the shielding pattern and the first upper inversion pattern as a first etching mask to form a first lower inversion pattern and a buffer layer pattern and a second lower inversion pattern overlapping the shielding pattern, the first lower inversion pattern providing a second opening portion overlapping the first opening portion. A hard mask layer may be formed and etched to separate a first pattern of a hard mask layer filling the first opening portion and the second opening portion. An etching process may be performed using the first hard mask layer pattern and the second upper inversion pattern as an etching mask to form a third lower inversion pattern overlapping the second upper inversion pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0081787, filed on Jul. 2, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method for forming a pattern using a reverse pattern. Background Art

[0004] When an integrated circuit is integrated into a semiconductor substrate, it is desirable to integrate a larger number of patterns in a limited area. As the integration of semiconductor devices increases, it is desirable to construct an integrated circuit with fine patterns of smaller size. Various processes have been tried to form dense fine patterns with nanometer critical dimensions (CD). Processes capable of patterning densely arranged fine patterns in one area and patterning patterns having shapes different from the fine patterns have been tried in adjacent areas. In order to pattern fine patterns of smaller size, a hard mask structure consisting of a composite layer including several material layers rather than a single layer is attempted as an etching mask. Summary of the invention

[0005] One aspect of the present disclosure provides a method for forming a pattern. The method for forming a pattern may include: sequentially forming a first hard mask layer, a lower inversion layer, and an upper inversion layer on a semiconductor substrate including a first region and a second region; patterning the upper inversion layer into: a first upper inversion pattern, which is located on the first region and provides a first opening portion; and a second upper inversion pattern, which is located on the second region; forming a buffer layer, which covers the first upper inversion pattern and the second upper inversion pattern; forming a shielding pattern, which opens a first portion of the buffer layer located on the first region and covers a second portion of the buffer layer located on the second region; patterning the lower inversion layer and the buffer layer into A first lower inversion pattern and a buffer layer pattern and a second lower inversion pattern overlapping the shielding pattern, wherein the first lower inversion pattern provides a second opening portion overlapping the first opening portion respectively; forming a second hard mask layer covering the first upper inversion pattern and the buffer layer pattern; etching the second hard mask layer to form a second hard mask layer first pattern and a second hard mask layer second pattern, wherein the second hard mask layer first pattern fills the first opening portion and the second opening portion, and the second hard mask layer second pattern fills the space between the first upper inversion pattern and the buffer layer pattern; and selectively removing the first upper inversion pattern.

[0006] According to another aspect of the present disclosure, a method for forming a pattern may include: sequentially forming an upper inversion layer including a first region and a second region on a lower inversion layer; patterning the upper inversion layer into: a first upper inversion pattern providing a first opening portion and being located on the first region; and a second upper inversion pattern being located on the second region; forming a buffer layer filling the first opening portion and covering the first upper inversion pattern and the second upper inversion pattern; forming a shielding pattern opening a first portion of the buffer layer located on the first region and covering a second portion of the buffer layer located on the second region; using the shielding pattern and the first upper inversion pattern as a first etching mask to sequentially remove the first portion of the buffer layer and some portions of the lower inversion layer to form a first lower inversion pattern and a buffer layer pattern and a second lower inversion pattern overlapping the shielding pattern, wherein the first lower inversion pattern provides a first opening portion overlapping the first opening portion A second opening portion overlapping the first opening portion; forming a hard mask layer, which fills the first opening portion and the second opening portion and covers the first upper inversion pattern and the buffer layer pattern; removing some portions of the hard mask layer to expose the first upper inversion pattern, thereby separating the hard mask layer first pattern and the hard mask layer second pattern from the hard mask layer, wherein the hard mask layer first pattern fills the first opening portion and the second opening portion, and the hard mask layer second pattern fills the space between the first upper inversion pattern and the buffer layer pattern; selectively removing the first upper inversion pattern; and using the hard mask layer first pattern, the hard mask layer second pattern and the second upper inversion pattern as a second etching mask to remove some portions of the first lower inversion pattern, the buffer layer pattern and the second lower inversion pattern, so as to pattern a third lower inversion pattern overlapping the second upper inversion pattern from the second lower inversion pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view schematically illustrating a layout of a target pattern according to an embodiment of the present disclosure.

[0008] Figures 2 to 18 is a view schematically illustrating a method of forming a pattern according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] The meaning of the terms used in various embodiments can be interpreted by those skilled in the art to which the embodiments belong according to the commonly understood meaning. Unless otherwise defined, the terms used in this article have the same meaning as those generally understood by those skilled in the art to which the embodiments belong.

[0010] In the description of the examples of the present disclosure, terms such as "first" and "second", "top" and "bottom or lower" are intended to distinguish elements, but are not used to limit elements or indicate a specific order. These terms indicate relative positional relationships, but do not limit specific circumstances in which another element is further introduced or directly contacts the element. The same interpretation can be applied to other expressions describing the relationship between elements.

[0011] Hereinafter, various examples of the embodiments will be described below with reference to the accompanying drawings. Various examples of the embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of various examples of the embodiments and intermediate structures. In this way, changes in the illustrated shapes, for example, due to manufacturing technology and / or tolerances, can be expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but can be interpreted as including shape deviations, for example, due to manufacturing. In the accompanying drawings, the lengths and sizes of the layers and regions may be exaggerated for clarity. The same reference numerals in the accompanying drawings may represent the same elements. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to another element or layer, or there may be an intermediate element or layer. On the contrary, when an element is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer.

[0012] For ease of description, spatially relative terms, such as "below," "under," "lower," "on," "upper," etc., may be used herein to describe the relationship of one element or feature to other (another) elements or features as shown in the accompanying drawings. It will be understood that in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "under" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, examples of the term "under" can include both upper and lower orientations. The device can be oriented in other ways (rotated 90 degrees or other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] It will be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, without departing from the teaching of the present disclosure, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0014] Embodiments of the present disclosure can be applied to the technical field for implementing integrated circuits such as dynamic random access memory (DRAM) devices, phase change random access memory (PcRAM) devices, or resistive random access memory (ReRAM) devices. Additionally, embodiments of the present disclosure can be applied to the technical field for implementing memory devices such as static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FeRAM) devices, or to the technical field for implementing logic devices in which logic integrated circuits are integrated. Embodiments of the present disclosure can be applied to the technical field for implementing various products that require fine patterns.

[0015] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not mentioned or described with reference to one drawing, the reference numeral can be mentioned or described with reference to another drawing. Additionally, even if a reference numeral is not shown in one drawing, it can be mentioned or described with reference to another drawing.

[0016] Figure 1 is a plan view schematically showing a layout 100T of target patterns 210T, 220T, and 230T according to an embodiment.

[0017] Reference Figure 1 , in a method of forming a pattern according to an embodiment, a first target pattern 210T can be formed as a fine-sized pattern in a first region 101T, and a second target pattern 220T having a shape different from that of the first target pattern 210T can be formed in a second region 102T adjacent to the first region 101T.

[0018] The first target patterns 210T can be formed to have the same shape and line width as each other. Each first target pattern 210T can be formed in a columnar shape. The first target patterns 210T can be arranged in a more dense arrangement than the second target patterns 220T. The first target pattern 210T can be a pattern for forming a memory cell of a DRAM device. The first region 101T can be understood as a cell region of a DRAM device. The second target pattern 220T can be a pattern for configuring a peripheral circuit of a DRAM device. When viewed from a plane such as a pad, each second target pattern 220T can be formed as a pattern having a rectangular planar shape. The second region 102T can be understood as a peripheral region of a DRAM device. Each first target pattern 210T can be formed to have a smaller line width than each second target pattern 220T.

[0019] The third target pattern 230T may be formed to have a stripe-shaped pattern extending along the boundary between the first region 101T and the second region 102T. The third target pattern 230T may be understood as a cell protection pattern that protects the arrangement of the first target pattern 210T from the outside. The third target pattern 230T may be formed to have a larger line width size than the first target pattern 210T.

[0020] Figures 2 to 18 is a schematic diagram showing the implementation according to Figure 1 FIG. 2 is a view of a process of a method for forming a pattern according to an embodiment of target patterns 210T, 220T, and 230T.

[0021] Figure 2 is a cross-sectional view schematically illustrating a process of forming an inversion layer 400 in a method for forming a pattern according to an embodiment of the present disclosure.

[0022] refer to Figure 2 , a semiconductor substrate 100 may be introduced as a base for performing the method of forming a pattern. For example, the semiconductor substrate 100 may be a silicon wafer. The semiconductor substrate 100 may include a first region 101 and a second region 102 adjacent to the first region 101. Various layers to be formed on the semiconductor substrate 100 may include a portion corresponding to the first region 101 and another portion corresponding to the second region 102. For example, an upper inversion layer 420 to be formed on the semiconductor substrate 100 may be introduced as a layer including the first region and the second region.

[0023] A target layer 200 and a first hard mask layer 300 may be sequentially formed on a semiconductor substrate 100. The target layer 200 may be formed as a layer to be patterned as Figure 1 The target layer 200 may include an insulating material layer or a silicon oxide (SiO 2 ) dielectric material layer. In another embodiment, the target layer 200 may include a conductive layer. The target layer 200 may be formed to have hundreds of To thousands Thickness.

[0024] A first hard mask layer 300 may be formed on the target layer 200. The first hard mask layer 300 may be formed as a layer to be patterned into a first hard mask layer pattern. In the process of patterning the target layer 200 into the target patterns 210T, 220T, and 230T, the first hard mask layer pattern may be used as an etching mask for selective etching. The first hard mask layer 300 may include a material that can have an etching selectivity relative to the target layer 200 in the etching process. The first hard mask layer 300 may include a material that can have a different etching rate from the target layer 200 in the etching process. The first hard mask layer 300 may include a material that can have a relatively lower etching rate than the target layer 200 in the etching process.

[0025] The first hard mask layer 300 may include a composite layer in which different material layers are stacked. The first hard mask layer 300 may be provided as a structure in which a first sublayer 310, a second sublayer 320, and a third sublayer 330 of the first hard mask layer are stacked. The first sublayer 310 of the first hard mask layer may be composed of lower silicon nitride (Si 3 N 4 ) layer is made of or includes a lower silicon nitride (Si 3 N 4 ) layer. The third sublayer 330 of the first hard mask layer may be composed of an upper silicon nitride (Si 3 N 4 ) layer or includes a silicon nitride (Si 3 N 4 The second sublayer 320 of the first hard mask layer may be located between the first sublayer 310 and the third sublayer 330 of the first hard mask layer. The second sublayer 320 of the first hard mask layer may include a dielectric material different from the first sublayer 310 and the third sublayer 330 of the first hard mask layer. The second sublayer 320 of the first hard mask layer may include, for example, an amorphous carbon layer.

[0026] The first sublayer 310 and the third sublayer 330 of the first hard mask layer may be formed of the same material and may have substantially the same thickness. The first sublayer 310 and the third sublayer 330 of the first hard mask layer may be formed to have several hundred The first sublayer 310 of the first hard mask layer may be formed to have a thickness of about The third sublayer 330 of the first hard mask layer may be formed to have a thickness of about The second sublayer 320 of the first hard mask layer may be formed to have a thickness greater than that of the first sublayer 310 and the third sublayer 330 of the first hard mask layer. The second sublayer 320 of the first hard mask layer may be formed to have a thickness of several thousand For example, the second sublayer 320 of the first hard mask layer may be formed to have a thickness of about to Thickness.

[0027] The inversion layer 400 may be formed on the first hard mask layer 300. The inversion layer 400 may be formed as a composite layer in which at least two or more material layers are stacked. A lower inversion layer 410 and an upper inversion layer 420 may be sequentially formed on the first hard mask layer 300. As will be described in more detail later, the inversion layer 400 may be introduced as a layer to be patterned to have a relative Figure 1 The shape of the first target pattern 210T is a reverse pattern of a shape in which the shape is reversed.

[0028] The lower inversion layer 410 and the upper inversion layer 420 may include dielectric materials having different etching rates. Depending on the etching process to be performed, the lower inversion layer 410 may have a lower etching rate than the upper inversion layer 420, or conversely, the upper inversion layer 420 may have a lower etching rate than the lower inversion layer 410. The upper inversion layer 420 may be made of or include, for example, a silicon oxynitride (SiON) layer, and the lower inversion layer 410 may include a spin on coating (SOC) layer.

[0029] The lower inversion layer 410 may be formed to have a greater thickness than the upper inversion layer 420. The lower inversion layer 410 may be formed to have a thickness of several hundred To thousands The lower inversion layer 410 may be formed to have a thickness of about The upper inversion layer 420 may be formed to have a thickness of several hundred The upper inversion layer 420 may be formed to have a thickness of to Thickness.

[0030] Figure 3 is a cross-sectional view schematically illustrating a process of forming a photoresist pattern 500 in a method of forming a pattern according to an embodiment of the present disclosure.

[0031] refer to Figure 3 , a photoresist material may be coated on the upper inversion layer 420 to form a photoresist layer. A photolithography process may be performed on the photoresist layer to form a photoresist pattern 500. The photolithography process may be performed by an ultraviolet lithography process using extreme ultraviolet light (EUV) as an exposure light source. Some portions of the photoresist layer may be exposed and developed to form a photoresist pattern 500 from the photoresist layer. In order to form the first photoresist pattern 510 as a pattern having a smaller line width than the second photoresist pattern 520, that is, in order to form the first photoresist pattern 510 as a nanometer-scale pattern, an ultraviolet lithography process may be introduced.

[0032] The photoresist pattern 500 may include a first photoresist pattern 510 located in the first region 101 and a second photoresist pattern 520 located in the second region 102. The first photoresist pattern 510 may be formed as a reverse pattern having a pattern shape reversed with respect to the first target pattern 210T. Figure 1 Each of the first target patterns 210T may be a pattern having a solid columnar shape, and the first photoresist pattern 510 may be formed to provide a pattern of opening portions 511 whose shape follows the shape of the first target pattern 210T. The opening portions 511 of the first photoresist pattern 510 may each have a hole shape that substantially vertically penetrates the photoresist layer.

[0033] The second photoresist pattern 520 may be formed to have a Figure 1 The solid shape of the second target pattern 220T is substantially the same as the solid shape of the second target pattern 220T. In the subsequent process, Figure 1 The third target pattern 230T may be introduced to be formed along the edge of the first photoresist pattern 510 while being attached to the sidewall of the first photoresist pattern 510. Therefore, the photoresist pattern 500 may not have a separate solid pattern reflecting the shape of the third target pattern 230T.

[0034] Figure 4 and Figure 5 4 and 5. are a cross-sectional view and a plan view respectively schematically illustrating a process of forming a first upper reverse pattern 421 and a second upper reverse pattern 422 in a method of forming a pattern according to an embodiment of the present disclosure.

[0035] refer to Figure 4 and Figure 5 By performing an etching process using the photoresist pattern 500 as an etching mask, a portion of the upper inversion layer 420 exposed by the photoresist pattern 500 may be selectively removed to pattern the upper inversion layer 420. Therefore, a first upper inversion pattern 421 may be formed in the first region 101, the shape of which follows the shape of the first photoresist pattern 510. A second upper inversion pattern 422 may be formed in the second region 102, the shape of which follows the shape of the second photoresist pattern 520.

[0036] The first upper reverse pattern 421 may provide a first opening portion 421H whose shape follows the shape of the opening portion 511 of the first photoresist pattern 510. The first opening portions 421H of the first upper reverse pattern 421 may each be formed in a shape extending the opening portion 511 of the first photoresist pattern 510 and formed at a position overlapping the opening portion 511 of the first photoresist pattern 510. The first upper reverse pattern 421 may substantially provide a first opening portion 421H for the first photoresist pattern 510. Figure 1 The first target pattern 210T is inverted in the reverse pattern shape. The second upper reverse pattern 422 may substantially provide Figure 1 The second upper reverse pattern 422 may not reverse the pattern of the second target pattern 220T, and may be understood as a term used to distinguish from the first upper reverse pattern 421.

[0037] The opening portions 421H of the first upper reverse pattern 421 may each have a different planar shape from the second upper reverse pattern 422. The first opening portions 421H may each have a smaller line width than the second upper reverse pattern 422, and may be arranged in a relatively dense arrangement in the first region 101. The first opening portions 421H may have substantially the same hole shape. On the other hand, each second upper reverse pattern 422 may be a pattern having a rectangular planar shape when viewed in a plane.

[0038] In the etching process of selectively patterning the first upper inversion pattern 421 and the second upper inversion pattern 422, the photoresist pattern 500 may be used as an etching mask. The photoresist pattern 500 may be lost due to the etching process used in selectively patterning the first upper inversion pattern 421 and the second upper inversion pattern 422. Therefore, the selective patterning process using the photoresist pattern 500 may be performed so that the selective etching stops on the lower inversion layer 410. Depending on the etching degree of the photoresist pattern 500 and the thickness of the photoresist pattern 500, the thickness of the upper inversion layer 420 may be defined. However, the entire inversion layer ( Figure 3 The thickness required for the upper inversion layer ( Figure 3 The lower inversion layer 410 may be introduced below the upper inversion layer 420 to compensate for the thickness of the inversion layer 400 which needs to be thicker than the upper inversion layer 420.

[0039] Figure 6 is a cross-sectional view schematically illustrating a process of forming a buffer layer 600 in the method of forming a pattern according to an embodiment of the present disclosure.

[0040] refer to Figure 6, the buffer layer 600 may be formed to fill the first opening portion 421H and cover the first upper inversion pattern 421 and the second upper inversion pattern 422. The buffer layer 600 may be formed as a composite layer including two or more layers. The buffer layer 600 may include a first buffer layer 610 and a second buffer layer 620. The first buffer layer 610 may be formed as a layer that extends while filling the first opening portion 421H to cover the first upper inversion pattern 421 and the second upper inversion pattern 422. The first buffer layer 610 may be introduced as a layer that reduces or mitigates process variations or topography caused by the first upper inversion pattern 421 and the second upper inversion pattern 422. The first buffer layer 610 may be formed as a layer that provides a substantially smooth and flat surface.

[0041] The second buffer layer 620 may be a layer thinner than the first buffer layer 610 and may be formed on the first buffer layer 610. The second buffer layer 620 may be introduced as a layer that further reduces or mitigates process variations or topography caused by the first upper inversion pattern 421 and the second upper inversion pattern 422. Accordingly, the buffer layer 600 may provide a substantially flat surface state. The second buffer layer 620 may be formed of a dielectric material having an etching rate different from that of the first buffer layer 610. In a subsequent etching process, the second buffer layer 620 may exhibit an etching rate higher than that of the first buffer layer 610, such that the first buffer layer 610 may be used as a layer to terminate the etching process.

[0042] The second buffer layer 620 may be formed of a material substantially the same as that of the upper inversion layer 420 and the first upper inversion pattern 421 and the second upper inversion pattern 422. The second buffer layer 620 may be formed of or include a silicon oxynitride (SiON) layer, for example. The second buffer layer 620 may be formed to have a thickness of about several hundreds The second buffer layer 620 may be formed to have to The first buffer layer 610 may be formed of a material substantially the same as that of the lower inversion layer 410. The first buffer layer 610 may be formed as a layer including a spin-on coating (SOC) layer. The first buffer layer 610 may be formed to have a thickness of about several hundreds The first buffer layer 610 may be formed to have to The thickness.

[0043] Figure 7 is a cross-sectional view schematically showing a process of forming a masking pattern 700 in a method of forming a pattern according to an embodiment of the present disclosure.

[0044] Reference Figure 7, a shielding pattern 700 shielding the second region 102 may be formed on the buffer layer 600. The shielding pattern 700 may be formed to cover the buffer layer second portion 602 located in the second region 102, leaving the buffer layer first portion 601 located in the first region 101 exposed. The buffer layer first portion 601 may be a portion where the first portion 611 of the first buffer layer 610 overlaps with the first portion 621 of the second buffer layer 620. The buffer layer second portion 602 may be a portion where the second portion 612 of the first buffer layer 610 overlaps with the second portion 622 of the second buffer layer 620. The shielding pattern 700 may be formed as a pattern that substantially completely overlaps the second region 102. The shielding pattern 700 may include a material layer having an etching rate different from that of the second buffer layer 620. The shielding pattern 700 may be formed of a photoresist material. The shielding pattern 700 may be formed of a dielectric material substantially the same as that of the first buffer layer 610. The shielding pattern 700 may include a spin-on (SOC) layer.

[0045] Figures 8 to 10 2 is a schematic cross-sectional view sequentially illustrating detailed processes of forming a first lower reverse pattern 412P and a second lower reverse pattern 417P in a method of forming a pattern according to an embodiment of the present disclosure. Figure 8 is a cross-sectional view schematically illustrating a process of removing a first portion 621 of a second buffer layer 620 in a method of forming a pattern according to an embodiment of the present disclosure.

[0046] Reference together Figure 8 and Figure 7 , the second buffer layer first portion 621 of the buffer layer first portion 601 exposed by the shielding pattern 700 can be selectively etched and removed by using the shielding pattern 700 as an etching mask. Because the shielding pattern 700 opens the first region 101, the etching process can be selectively applied only to the second buffer layer first portion 621 located in the first region 101. As the second buffer layer first portion 621 is selectively removed, the second buffer layer second portion 622 located in the second region 102 can be patterned into a second buffer layer pattern 622P.

[0047] Fig. 9 is a cross-sectional view schematically illustrating a process of removing a first portion 611 of a first buffer layer 610 in a method of forming a pattern according to an embodiment of the present disclosure.

[0048] Reference together Fig. 9 and Figure 8, the first buffer layer first portion 611 exposed as the second buffer layer first portion 621 is removed can be selectively etched and removed. The shielding pattern 700 can continue to be used as an etching mask. Even in the process of selectively etching the first buffer layer first portion 611, the shielding pattern 700 can also shield the buffer layer second portion 602 located in the second region 102 to protect the buffer layer second portion 602 from etching. As the first buffer layer first portion 611 is selectively removed, the first upper inversion pattern 421 can be exposed. As the first buffer layer first portion 611 is selectively removed, the first buffer layer second portion 612 located in the second region 102 can be patterned into a first buffer layer pattern 612P. Therefore, the buffer layer pattern 602P located in the second region 102 and substantially overlapping with the second region 102 can be implemented as a first buffer layer pattern 612P and a second buffer layer pattern 622P. The buffer layer pattern 602P can be formed as a pattern that substantially completely overlaps with the shielding pattern 700.

[0049] The process of selectively etching the first buffer layer first portion 611 may be performed by an etching process having an etching selectivity with respect to the first upper reverse pattern 421. Because the first upper reverse pattern 421, the first buffer layer 610, and the first buffer layer first portion 611 are formed of different materials having different etching rates, the first upper reverse pattern 421 may resist the etching process and maintain its shape. In the process of selectively removing the buffer layer first portion 601 and the first buffer layer first portion 611 using the shielding pattern 700, the first upper reverse pattern 421 may be used as a first etching mask for selective etching.

[0050] As the first buffer layer first portion 611 is selectively removed, the first portion 411 of the lower inversion layer 410 overlapping with and located below the first opening portion 421H of the first upper inversion pattern 421 may be exposed by the first upper inversion pattern 421. The second portion 412 of the lower inversion layer 410 overlapping with and located below the first upper inversion pattern 421 may be covered and shielded by the first upper inversion pattern 421. The second portion 412 of the lower inversion layer 410 may be covered by the first upper inversion pattern 421 and protected from etching. Therefore, selective etching may be achieved. The etching process may be performed by an anisotropic etching process.

[0051] Fig.10 2 is a cross-sectional view schematically illustrating a process of forming a first lower reverse pattern 412P and a second lower reverse pattern 417P in a method of forming a pattern according to an embodiment of the present disclosure.

[0052] Reference together Fig.10 and Fig. 9As the etching process continues, the first portion 411 of the lower inversion layer 410 may be exposed relative to the first upper inversion pattern 421 and the shielding pattern 700. The etching process using the first upper inversion pattern 421 and the shielding pattern 700 as a first etching mask may be continued to selectively remove the exposed first portion 411 of the lower inversion layer 410. Thus, a second opening portion 411H may be formed in a position where the first portion 411 of the lower inversion layer 410 is removed. The second opening portion 411H may overlap with the first opening portion 421H, and the second opening portions 411H may each have a shape in which the first opening portion 421H extends. The second opening portion 411H and the first opening portion 421H may each have a through-hole shape.

[0053] As the first portion 411 of the lower inversion layer 410 is selectively removed, the third portion ( Fig. 9 Thus, the third portion (417) of the lower inversion layer 410 can be protected from selective etching. Fig. 9 The second lower reverse pattern 417P may have a shape overlapping the shielding pattern 700.

[0054] As in Figures 8 to 10 In the detailed process depicted in FIG. 7 , a selective etching process substantially using the shielding pattern 700 and the first upper reverse pattern 421 as a first etching mask may be performed. The first portion 601 of the buffer layer 600 and the first portion 411 of the lower reverse layer 410 may be sequentially removed to pattern the first lower reverse pattern 412P, thereby providing a second opening portion 411H overlapping the first opening portion 421H. In addition, the buffer layer pattern 602P and the second lower reverse pattern 417P overlapping the shielding pattern 700 may be patterned.

[0055] Fig.11 is a cross-sectional view schematically illustrating a process of forming a second hard mask layer 800 in the method of forming a pattern according to an embodiment of the present disclosure.

[0056] refer to Fig.11 , the second hard mask layer 800 may be formed to fill the first opening portion 421H and the second opening portion 411H and extend to cover the first upper inversion pattern 421 and the buffer layer pattern 602P. The second hard mask layer 800 may be formed as a layer including an upper inversion layer and a lower inversion layer ( Figure 2The second hard mask layer 800 may be made of a material different from the buffer layer pattern 602P, the upper inversion layer and the lower inversion layer ( Figure 2 The first lower reverse pattern 412P and the second lower reverse pattern 417P may be formed of a dielectric material different from that of the first hard mask layer 300. The second hard mask layer 800 may be formed of a material different from that of the material constituting the first hard mask layer 300.

[0057] The second hard mask layer 800 may be formed of an ultra-low temperature oxide layer. The second hard mask layer 800 may be made of or include a silicon oxide layer. The second hard mask layer 800 may be formed to have a process difference D between the first region 101 and the second region 102. The process difference D may be caused by the buffer layer pattern 602P and the second lower reverse pattern 417P.

[0058] Fig.12 2 is a cross-sectional view schematically illustrating a process of forming a second hard mask layer first pattern 810 and a second pattern 820 in a method of forming a pattern according to an embodiment of the present disclosure.

[0059] Reference together Fig.12 and Fig.11 , a portion of the second hard mask layer 800 may be removed, so that the first upper reverse pattern 421 may be exposed. A portion of the thickness of the second hard mask layer 800 may be removed, so that the upper surface of the second buffer layer pattern 622P and the first upper reverse pattern 421 of the buffer layer pattern 602P may be exposed. The process of removing a portion of the thickness of the second hard mask layer 800 may be performed by a full etching process or an etch-back process. Through the etching process, the second hard mask layer 800 may be separated into a second hard mask layer first pattern 810 and a second pattern 820. In this way, in the process of separating the second hard mask layer into the second hard mask layer first pattern 810 and the second pattern 820, a chemical mechanical polishing (CMP) process may be excluded, and a full etching process may be applied. When the CMP process is applied, a defect that separation cannot be achieved may occur due to the process difference D of the second hard mask layer 800. Since the CMP process is excluded, the process defects accompanying the CMP process can be fundamentally prevented.

[0060] The second hard mask layer first pattern 810 may be separated into a pattern filling the first opening portion 421H and the second opening portion 411H. The second hard mask layer second pattern 820 may be separated into a pattern filling the gap between the first upper reverse pattern 421 and the buffer layer pattern 602P. The second hard mask layer first pattern 810 may be separated into a pattern having substantially the same column shape. The second hard mask layer first pattern 810 may have the same Figure 1 The second hard mask layer second pattern 820 may be formed to have substantially the same size, shape, and arrangement as the first target pattern 210T. Figure 1 The second hard mask layer second pattern 820 may be a pattern substantially the same as the third target pattern 230T of the embodiment of the present invention. The second hard mask layer second pattern 820 may be a pattern having a larger line width than the second hard mask layer first pattern 810 and having a strip shape extending long along the boundary between the first region 101 and the second region 102. Since the second hard mask layer second pattern 820 is disposed outside the relatively dense second hard mask layer first pattern 810, there may be a relatively high possibility of collapse in a subsequent etching process. More effectively, the second hard mask layer second pattern 820 has a larger line width than the second hard mask layer first pattern 810 so as to suppress or reduce the failure of the second hard mask layer second pattern 820 to collapse.

[0061] Fig.13 is a cross-sectional view schematically illustrating a process of selectively removing the first upper reverse pattern 421 in the method of forming a pattern according to an embodiment of the present disclosure.

[0062] Reference together Fig.13 and Fig.12 , an etching process may be performed to selectively remove the first upper reverse pattern 421. In the etching process, the second buffer layer pattern 622P of the buffer layer pattern 602P may be removed together with the first upper reverse pattern 421. Thus, the upper surfaces of the first lower reverse pattern 412P and the first buffer layer pattern 612P may be exposed.

[0063] Fig.14 and Fig.15 2 is a cross-sectional view schematically and sequentially illustrating a detailed process of forming a third lower reverse pattern 417P-E in the method of forming a pattern according to an embodiment of the present disclosure. Fig.14 is a cross-sectional view schematically illustrating a process of removing the first lower reverse pattern 412P and the first buffer layer pattern 612P in the method of forming a pattern according to an embodiment of the present disclosure.

[0064] Reference together Fig.14 and Fig.13 , the first lower reverse pattern 412P and the first buffer layer pattern 612P exposed by the second hard mask layer first pattern 810 and the second pattern 820 may be selectively etched. As the first lower reverse pattern 412P and the first buffer layer pattern 612P are gradually removed by such an etching process, the thickness of the etched first lower reverse pattern 412P-E and the etched buffer layer pattern 612P-E may be reduced. As the etching process continues, the etched first lower reverse pattern 412P-E and the etched first buffer layer pattern 612P-E may be removed.

[0065] Fig.15 is a cross-sectional view schematically illustrating a process of patterning the second lower reverse pattern 417P in the pattern forming method according to an embodiment of the present disclosure.

[0066] Reference together Fig.15 and Fig.14 , as the entirety of the etched first buffer layer pattern 612P-E is removed, some portions of the second upper inversion pattern 422 and the second lower inversion pattern 417P may be exposed. Some portions of the second lower inversion pattern 417P exposed by the second upper inversion pattern 422 may be continuously etched and selectively removed. Thus, the third lower inversion pattern 417P-E may be formed as a pattern overlapping the second upper inversion pattern 422, respectively. The third lower inversion pattern 417P-E may be a pattern separated from the second lower inversion pattern 417P. The third lower inversion pattern 417P-E may be formed as a pattern overlapping the second upper inversion pattern 422, respectively. Figure 1 The second target pattern 220T has substantially the same shape as the pattern.

[0067] like Fig.14 and Fig.15 As shown, in the etching process of removing some portions of the buffer layer pattern 602P and the second lower reverse pattern 417P while patterning the third lower reverse pattern 417P-E, the second hard mask layer first and second patterns 810 and 820 and the second upper reverse pattern 422 can be used as a second etching mask for selective etching.

[0068] Fig.16 is a cross-sectional view schematically illustrating a process of patterning the first hard mask layer patterns 301 and 302 in the method of forming a pattern according to an embodiment of the present disclosure.

[0069] Reference together Fig.16 and Fig.15 , an etching process may be performed by using the second hard mask layer first pattern 810 and the second pattern 820, the second upper reverse pattern 422, and the third lower reverse pattern 417P-E as an etching mask to pattern the first hard mask layer 300. Some portions of the first hard mask layer 300 exposed by the second hard mask layer first pattern 810 and the second pattern 820, the second upper reverse pattern 422, and the third lower reverse pattern 417P-E may be selectively removed. Therefore, a first hard mask layer first pattern 301 following the shape of the second hard mask layer first pattern 810 and the second pattern 820 may be formed in the first region 101, and a first hard mask layer second pattern 302 following the shape of the second upper reverse pattern 422 may be formed in the second region 102.

[0070] Fig.17 and Fig.182 is a cross-sectional view schematically illustrating a process of patterning target layer patterns 201 , 202 , and 203 in a pattern forming method according to an embodiment of the present disclosure.

[0071] Reference together Fig.17 and Fig.16 , the first hard mask layer patterns 301 and 302 may be pattern-transferred to the target layer 200. Portions of the target layer 200 exposed by the first hard mask layer patterns 301 and 302 may be selectively removed using the first hard mask layer patterns 301 and 302 as etching masks. Thus, target layer patterns 201, 202, and 203 that follow the shapes of the first hard mask layer patterns 301 and 302 may be formed. Thereafter, as shown in FIG. Fig.18 As shown, the first hard mask layer patterns 301 and 302 may be removed. The first target layer pattern 201 may be formed as Figure 1 The first target pattern 210T of the embodiment of the present invention may be formed, and the second target layer pattern 202 may be formed as a second target pattern 220T. The third target layer pattern 203 may be formed as a third target pattern 230T.

[0072] Various embodiments of the present disclosure have been described above. Those skilled in the art will appreciate that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive point of view but from an illustrative point of view. The scope of the present disclosure is not limited to the above description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be interpreted as being included in the concept.

[0073] While the present teachings have been shown and described with respect to the particular embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for forming a pattern, the method comprising: include: sequentially forming a first hard mask layer, a lower inversion layer, and an upper inversion layer on a semiconductor substrate including a first region and a second region; patterning the upper inversion layer into a first upper inversion pattern located on the first region and a second upper inversion pattern located on the second region, and providing a first opening portion between the first upper inversion patterns; forming a buffer layer, wherein the buffer layer covers the first upper inversion pattern and the second upper inversion pattern; forming a shielding pattern, the shielding pattern covering a second portion of the buffer layer located on the second region, while leaving a first portion of the buffer layer located on the first region exposed; patterning the lower inversion layer and the buffer layer into a first lower inversion pattern and a buffer layer pattern and a second lower inversion pattern overlapping the shielding pattern, wherein the first lower inversion pattern provides second opening portions respectively overlapping the first opening portions; forming a second hard mask layer, wherein the second hard mask layer covers the first upper inversion pattern and the buffer layer pattern; Etching the second hard mask layer to form a second hard mask layer first pattern and a second hard mask layer second pattern, wherein the second hard mask layer first pattern fills the first opening portion and the second opening portion, and the second hard mask layer second pattern fills a space between the first upper inversion pattern and the buffer layer pattern; as well as The first upper inversion pattern is selectively removed.

2. The method according to claim 1, in, Patterning the lower inversion layer and the buffer layer into the first lower inversion pattern, the buffer layer pattern, and the second lower inversion pattern includes sequentially removing the first portion of the buffer layer and portions of the lower inversion layer using the shielding pattern and the first upper inversion pattern as a first etch mask.

3. The method according to claim 1, further comprising: include: forming a target layer on the semiconductor substrate; removing portions of the first lower inversion pattern, the buffer layer pattern, and the second lower inversion pattern using the second hard mask layer first pattern, the second hard mask layer second pattern, and the second upper inversion pattern as a second etch mask to pattern the second lower inversion pattern into a third lower inversion pattern overlapping the second upper inversion pattern; selectively removing portions of the first hard mask layer exposed by the second hard mask layer first pattern, the second hard mask layer second pattern, and the third lower reverse pattern to pattern the first hard mask layer into a first hard mask layer pattern; as well as The pattern of the first hard mask layer pattern is transferred to the target layer.

4. The method according to claim 1, in, Each of the first opening portions has a different planar shape from that of the second upper reverse pattern.

5. The method according to claim 1, in, Each of the first opening portions has a line width smaller than that of the second upper reversal pattern.

6. The method according to claim 1, in, Each of the first opening portions has the same hole shape, and each of the second upper reverse patterns has a rectangular planar shape.

7. The method according to claim 1, in, The first patterns of the second hard mask layer have the same column shape, and The second pattern of the second hard mask layer has a line width greater than that of the first pattern of the second hard mask layer, and has a strip shape extending along a boundary between the first region and the second region.

8. The method according to claim 1, in, The thickness of the lower inversion layer is greater than the thickness of the upper inversion layer.

9. The method according to claim 1, in, The upper inversion layer and the lower inversion layer include dielectric materials having different etching rates from each other.

10. The method according to claim 9, in, The upper inversion layer includes a silicon oxynitride layer, and the lower inversion layer includes a spin-coated layer.

11. The method according to claim 1, in, The step of patterning the upper inversion layer into the first upper inversion pattern and the second upper inversion pattern comprises: forming a photoresist layer on the upper inversion layer; exposing portions of the photoresist layer to extreme ultraviolet light and developing to form a photoresist pattern from the photoresist layer; and The pattern of the photoresist pattern is transferred to the upper inversion layer.

12. The method according to claim 1, in, The buffer layer pattern comprises: a first buffer layer filling the first opening portion and covering the first upper inversion pattern and the second upper inversion pattern; and The etching rate of the dielectric material of the second buffer layer is different from that of the first buffer layer, and the thickness of the second buffer layer is thinner than that of the first buffer layer.

13. The method according to claim 12, in, The second buffer layer includes the same material as the upper inversion layer, and the first buffer layer includes the same material as the lower inversion layer.

14. The method according to claim 12, in, The second buffer layer includes a silicon oxynitride layer, and the first buffer layer includes a spin-coated layer.

15. The method according to claim 12, in, The shielding pattern includes a material having a different etching rate from that of the second buffer layer.

16. The method according to claim 12, in, The step of selectively removing the first upper inversion pattern includes removing the second buffer layer of the buffer layer pattern while removing the first upper inversion pattern.

17. The method according to claim 1, in, The second hard mask layer includes a material having a different etch rate from the buffer layer pattern and the upper and lower inversion layers.

18. The method according to claim 1, in, The first hard mask layer includes a material having a different etching rate from the second hard mask layer and the upper and lower inversion layers.

19. The method according to claim 1, in, The first hard mask layer includes: a composite layer including a lower silicon nitride layer, an amorphous carbon layer and an upper silicon nitride layer.

20. A method for forming a pattern, the method include: Form an upper inversion layer including a first region and a second region sequentially on a lower inversion layer; Pattern the upper inversion layer to provide a first upper inversion pattern located on the first region and providing a first opening portion and a second upper inversion pattern located on the second region; Form a buffer layer that fills the first opening portion and covers the first upper inversion pattern and the second upper inversion pattern; Form a masking pattern that covers a second portion of the buffer layer located on the second region, leaving an opening above a first portion of the buffer layer located on the first region; Use the masking pattern and the first upper inversion pattern as a first etching mask to sequentially remove the first portion of the buffer layer and some portions of the lower inversion layer to form a first lower inversion pattern, a buffer layer pattern, and a second lower inversion pattern overlapping with the masking pattern, wherein the first lower inversion pattern provides a second opening portion overlapping with the first opening portion; Form a hard mask layer that fills the first opening portion and the second opening portion and covers the first upper inversion pattern and the buffer layer pattern; Remove some portions of the hard mask layer to expose the first upper inversion pattern, thereby separating a first hard mask layer pattern and a second hard mask layer pattern from the hard mask layer, the first hard mask layer pattern filling the first opening portion and the second opening portion, and the second hard mask layer pattern filling the space between the first upper inversion pattern and the buffer layer pattern; Selectively remove the first upper inversion pattern; And Use the first hard mask layer pattern, the second hard mask layer pattern, and the second upper inversion pattern as a second etching mask to remove some portions of the first lower inversion pattern, the buffer layer pattern, and the second lower inversion pattern to pattern a third lower inversion pattern overlapping with the second upper inversion pattern from the second lower inversion pattern.

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