IC structure with sub-fin extension regions of different lateral dimensions

Abstract

The present invention relates to finned IC structures with sub-fin extension regions of different lateral dimensions. An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extension region and a second longitudinal extension region. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first and second longitudinal extension regions, a first sub-fin portion below the upper fin portion in the first longitudinal extension region and having a first lateral dimension, and a second sub-fin portion below the upper fin portion in the second longitudinal extension region and having a second lateral dimension different from the first lateral dimension. The second sub-fin can be used in a drain extension region of a lateral diffusion metal oxide semiconductor (LDMOS) device. The second sub-fin reduces sub-fin current and improves HCI reliability regardless of the type of LDMOS device.

Description

Technical Field

[0001] This disclosure relates to power amplifier devices, and more specifically to integrated circuit (IC) structures having semiconductor fins having different longitudinal extensions of sub-fins and different lateral dimensions. Background Technology

[0002] Radio frequency (RF) devices employ laterally diffused metal-oxide-semiconductor (LDMOS) devices. An LDMOS device includes a p-well with a source region and an n-well with a drain region within a semiconductor fin. A gate extends over both the p-well and the n-well, with a channel in the p-well and a drain extension region in the n-well. LDMOS devices come in various forms. For example, the LDMOS shallow trench isolation (LDMOS-STI) device includes shallow trench isolation (STI) within the drain extension region of the n-well, while the LDMOS dummy gate (LDMOS-DP) device does not have STI in the n-well but includes a second floating (dummy) gate above the drain extension region of the n-well.

[0003] For example, LDMOS FinFETs are used as power amplifiers for wireless networks with 3.3-5 volt power. One challenge these devices face is controlling hot carrier injection (HCI). HCI is a condition in electronic devices where electrons (holes) gain enough energy to break the interface state and overcome the potential barrier. In LDMOS FinFET devices, carriers can be trapped in a sub-fin region of the fin, located below the transistor gate and adjacent trench isolation between adjacent fins. The trapped charged carriers generate excessive current in the drain extension region and permanently alter the device's operating characteristics (e.g., switching characteristics). Therefore, HCI poses a challenge to device performance and reliability. Current approaches attempt to improve HCI reliability by providing various injection or local trench isolation to reduce sub-fin currents. These approaches are complex to implement and may not fully address the problems of all types of LDMOS FinFET devices. Summary of the Invention

[0004] One aspect of this disclosure relates to an integrated circuit (IC) structure, comprising: a semiconductor fin having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: an upper fin portion having a uniform lateral dimension in the first longitudinal extension region and the second longitudinal extension region; a first sub-fin portion located below the upper fin portion having a first lateral dimension in the first longitudinal extension region; and a second sub-fin portion located below the upper fin portion having a second lateral dimension different from the first lateral dimension in the second longitudinal extension region.

[0005] Another aspect of this disclosure includes a laterally diffused metal-oxide-semiconductor (LDMOS) device with a FinFET, comprising: a semiconductor fin having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: an upper fin having a uniform lateral dimension in the first and second longitudinal extension regions; a first sub-fin located below the upper fin, located in the first longitudinal extension region and having a first lateral dimension; and a second sub-fin located below the upper fin, located in the second longitudinal extension region and having a second lateral dimension different from the first lateral dimension; a p-well located in a portion of the first longitudinal extension region; an n-well located at least in the second longitudinal extension region; a source region located in the p-well; a drain region located in the n-well; a drain extension region located in the n-well, wherein the second sub-fin is located within the drain extension region; and a first gate structure extending over the p-well and the n-well.

[0006] Another aspect of this disclosure relates to a method comprising: forming a semiconductor fin having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: an upper fin portion having a uniform lateral dimension in the first longitudinal extension region and the second longitudinal extension region; a first sub-fin portion located below the upper fin portion having a first lateral dimension in the first longitudinal extension region; and a second sub-fin portion located below the upper fin portion having a second lateral dimension in the second longitudinal extension region that is different from the first lateral dimension; and forming a metal gate structure above the semiconductor fin.

[0007] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0008] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein like reference numerals denote like elements, and wherein:

[0009] Figure 1 A schematic plan view of the overall layout of the IC structure used to describe embodiments of the present disclosure is shown.

[0010] Figures 2A to 2B A cross-sectional view of trench pairs formed in a semiconductor substrate according to an embodiment of the present disclosure is shown.

[0011] Figures 3A to 3B A cross-sectional view is shown of a sub-fin formed in a first longitudinal extension region of a semiconductor fin according to an embodiment of the present disclosure.

[0012] Figures 4A to 4BA cross-sectional view is shown of a spacer layer formed in the first and second longitudinally extending regions of a semiconductor fin according to an embodiment of the present disclosure.

[0013] Figures 5A to 5B A cross-sectional view of a first etching for forming a second sub-fin portion within a second longitudinal extension region of a semiconductor fin, according to an embodiment of the present disclosure, is shown.

[0014] Figures 6A to 6B A cross-sectional view is shown of a second etching for forming a second sub-fin portion within a second longitudinal extension region of a semiconductor fin, according to an embodiment of the present disclosure.

[0015] Figures 7A to 7B A cross-sectional view is shown of a dielectric formed around a semiconductor fin within first and second longitudinally extending regions of the semiconductor fin according to an embodiment of the present disclosure.

[0016] Figures 8A to 8B A cross-sectional view showing a planarized and recessed semiconductor fin according to an embodiment of the present disclosure is shown.

[0017] Figure 9 Cross-sectional views of IC structures, FinFETs, and LDMOS devices according to embodiments of the present disclosure are shown.

[0018] Figure 10 Cross-sectional views of IC structures, FinFETs, and LDMOS devices according to other embodiments of this disclosure are shown.

[0019] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0020] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0021] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0022] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of any of the following, such as "A / B," "A and / or B," and "at least one of A and B," is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B and / or C” and “at least one of A, B and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0023] Embodiments of this disclosure provide an integrated circuit (IC) structure for use in, for example, a fin field-effect transistor (FinFET). This structure can be used in laterally diffused metal-oxide-semiconductor (LDMOS) devices, which have advantages suitable for radio frequency (RF) applications, such as wireless network power amplifiers. The IC structure includes a semiconductor fin having a first longitudinal extension region and a second longitudinal extension region. The semiconductor fin has an upper fin portion having a uniform lateral dimension in both the first and second longitudinal extension regions; a first sub-fin portion located below the upper fin portion, which is in the first longitudinal extension region and has the first lateral dimension; and a second sub-fin portion located below the upper fin portion, which is in the second longitudinal extension region and has a second lateral dimension different from (e.g., smaller than) the first lateral dimension. Thus, the semiconductor fin has two sub-fin portions with different lateral dimensions. The sub-fin portions are within a trench isolation having a bulbous cross-section adjacent to the second sub-fin portion. Regardless of the type of LDMOS device, the second sub-fin portion reduces the sub-fin current in the drain extension region of the LDMOS FinFET, thereby improving HCI reliability.

[0024] Figures 1 to 10 The integrated circuit (IC) structure 100 is formed according to various embodiments of the present disclosure. Figure 9 and Figure 10 ) and LDMOS devices 104, 204 ( Figure 9 and Figure 10 The diagram illustrates the method. For illustrative purposes, the IC structure 100 can be implemented using LDMOS devices 104 and 204 (respectively in...). Figure 9 and Figure 10 FinFET 102 in (i.e., fin-type LDMOS device) form Figure 9 and Figure 10 As will be described, embodiments of this disclosure are applicable to any of a variety of FinFET LDMOS devices, including FinFET LDMOS-STI devices and FinFET LDMOS-DP devices. It should be emphasized that the teachings of this disclosure are also applicable to other types of MOS devices.

[0025] Figure 1 A schematic plan view of the overall layout of the IC structure used to describe embodiments of the present disclosure is shown. Figure 1 Includes a set of view lines AA, BB and CC that will be mentioned for the purpose of describing this disclosure. Figure 1 A semiconductor fin 110 extending across the page is shown (actually four fins are shown), and a metal gate structure 112 extending across the semiconductor fin 110 (two parts in this example). View line AA spans region 114 (labeled by a rectangle), where the sub-fin portion of the longitudinally extending region 118 of the semiconductor fin 110 ( Figure 1 The lateral dimensions (not shown) of the semiconductor fin 110 are different from (i.e., smaller than) those of the sub-fins in another longitudinally extending region 116 of the semiconductor fin 110. View line BB spans the semiconductor fin 110 outside region 114, where the semiconductor fin 110 does not have sub-fins with varying lateral dimensions, i.e., where the sub-fins have regular lateral dimensions. View line CC is a cross-sectional view across the semiconductor fin 110, see [reference needed]. Figure 9 For any particular stage of the method, the figure number indicates the particular stage; the figure with the symbol "A" spans the view line AA, which shows the longitudinal extension area 118; the figure with the symbol "B" spans the view line BB, which shows any longitudinal extension area 116. Note that, as Figure 1 As shown, the figure marked with the symbol "B" illustrating the longitudinal extension region 116 can be a structure of the semiconductor fin 110 on either side of the longitudinal extension region 118. The symbol "C" is not used in these figures as it is not necessary.

[0026] Figures 2A to 8B A cross-sectional view of a semiconductor fin 110 formed according to an embodiment of the present disclosure is shown. The semiconductor fin 110 has a first longitudinal extension region 116 (in the figure marked "A") and a second longitudinal extension region 118 (in the figure marked "B"). As will be described, the semiconductor fin 110 will ultimately have: an upper fin portion having a uniform lateral dimension in the first and second longitudinal extension regions 116, 118; a first sub-fin portion located below the upper fin portion, located in the first longitudinal extension region 116 and having the first lateral dimension; and a second sub-fin portion located below the upper fin portion, located in the second longitudinal extension region 118 and having a second lateral dimension different from (e.g., smaller than) the first lateral dimension. As used herein, "lateral" dimension refers to a dimension in a non-vertical vertical direction relative to the longitudinal axis or major axis of the fin. As used herein, "sub-fin portion" refers to the lower portion of the semiconductor fin that will be positioned within a trench isolation.

[0027] refer to Figures 2A to 2B A hard mask 120 is formed over a (bulk) semiconductor substrate 122. The hard mask 120 may comprise any mask material layer now known or developed later, such as intermediate-temperature oxide (MTO) and silicon nitride. The hard mask 120 is patterned to form one or more semiconductor fins 110. Figures 8A to 8B That is, the hard mask includes openings to guide the etching of the semiconductor substrate 122 to form fins. The semiconductor substrate 122 may include, but is not limited to, silicon, germanium, silicon-germanium, silicon carbide, and other materials substantially composed of one or more materials having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4Materials composed of group III-V compound semiconductors with defined compositions, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, part or all of the semiconductor substrate may be strained.

[0028] Figures 2A to 2B A cross-sectional view is also shown of a pair of trenches 124 formed in a semiconductor substrate 122 to a first depth D1. Semiconductor fins 110 are formed therebetween in the trenches 124. It should be understood that any number of trenches 124 can be formed to form any number of semiconductor fins 110. In contrast to conventional processes, the first depth D1 does not extend to the depth of a complete semiconductor fin 110. As will be described herein, the first depth D1 is chosen such that the upper portions of sub-fins with different lateral dimensions will be positioned at this depth. The trenches 124 can be formed by etching. Optionally, a hard mask 120 can be patterned and the trenches 124 etched to define an upper fin 126 having a uniform lateral dimension ULD in the first and second longitudinal extension regions 116, 118. That is, the semiconductor fin 110 ( Figure 1 The upper fin 126 of the fin has a consistent lateral dimension regardless of its position along its length.

[0029] Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate), and is typically performed using a mask at appropriate locations to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid), which allows the solvent to selectively dissolve a given material (e.g., oxide) while leaving another material (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged, high-energy free radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching uses high-energy ions of a rare gas to bombard the wafer. The high-energy ions of the rare gas approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to produce deep, narrow features, such as trench 124.

[0030] Figures 3A to 3B A cross-sectional view is shown, showing a first mask 130 formed over the second longitudinal extension region 118, exposing the first longitudinal extension region 116. The first mask 130 may comprise any mask material now known or later developed, such as spin-coated hard mask (SOH). Figures 3A to 3B It also shows the etching of the trenches 124 in the first longitudinal extension region 116 to a depth greater than the first depth D1. Figures 2A to 2B A deeper second depth D2 is formed, thereby creating a first sub-fin 132 with a first lateral dimension LD1. The second depth D2 is chosen as the depth to which the "regular" sub-fin will extend. The first lateral dimension LD1 is dimensionally equivalent to the upper fin 126, i.e., similar to the fin etching expected to be completed in one step.

[0031] Figures 4A to 4B A cross-sectional view is shown with the first mask 130 removed above the second longitudinal extension region 118. The first mask 130 can be removed using any suitable ashing and wet stripping process. Figures 4A to 4BIt is also shown that a spacer layer 134 is formed over the first and second longitudinally extending regions 116, 118. The spacer layer 134 may include any spacer material now known or later developed, such as, but not limited to, silicon nitride. The spacer layer 134 may be formed by deposition. “Deposition” may include any technique now known or later developed suitable for the material to be deposited, including but not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sub-atmospheric pressure CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), finite reaction process CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. Here, the spacer layer 134 may be deposited, for example, by ALD. As will be described, spacer layer 134 will also be used to form collar 136. Figure 5A ).

[0032] Figures 5A to 5B A cross-sectional view is shown showing a second mask 140 formed over a first longitudinal extension region 116, exposing the second longitudinal extension region 118. The second mask 140 may comprise any mask material now known or developed later, such as spin-coated hard masks (SOH). Figure 5A This shows the alignment of the trench 124 in the etched second longitudinal extension region 118 with the first depth D1 ( Figures 2A to 2B A deeper third depth, D3. The third depth D3 can be deeper than the second depth D2. Figure 3B (Deeper or shallower.) The etching forms a collar 136 from the spacer layer 134, which then protects the upper fin 126 in the second longitudinal extension region 118. The etching may include any suitable anisotropic etching chemistry.

[0033] Figure 6A This illustrates further etching of the pair of trenches 124 in the second longitudinal extension region 118 to widen the pair of trenches 124 and form a shape smaller than the first lateral dimension LD1. Figure 3B A cross-sectional view of the second sub-fin 142 with a second lateral dimension LD2. The second lateral dimension is also smaller than the uniform lateral dimension ULD of the upper fin 126. (See figure) Figure 6BAs shown, during this process, the semiconductor fins 110 in the first longitudinal extension region 116 remain unchanged. Therefore, the semiconductor fins 110 in the first longitudinal extension region 116 have a regular semiconductor fin shape, while the semiconductor fins 110 in the second longitudinal extension region 118 have different lateral dimensions (LD2) in their sub-fin portions 142. Figure 6A The trench 124, enlarged by additional etching, has a lower portion with a bulbous cross-sectional shape, which forms a narrow sub-fin 142. The etching can include any isotropic etching chemical action and can be controlled, for example, in terms of chemical action, duration, operating parameters, etc., thereby controlling the size of the sub-fin 142.

[0034] Figures 7A to 7B The removal of the second mask 140 (and spacer layer 134) is illustrated, for example, by any suitable ashing process and wet stripping process. Figure 5B , 6B The cross-sectional view after that. Figures 7A to 7B Also shown is a pair of trenches 124, at least adjacent to the first and second sub-fins 132, 142, filled with dielectric 144. As will be described, dielectric 144 ultimately forms trench isolation 146. Figures 8A to 8B For example, shallow trench isolation (STI) between semiconductor fins 110. Dielectric 144 may include any interlayer dielectric now known or developed later. Suitable dielectric materials may include, but are not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymer thermosetting materials; silicon carbide; SiCOH dielectrics; fluorine-doped silicon oxide; spin-coated glass; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics; and any silicon-containing low-k dielectric. Examples of spin-coated low-k films with a SiCOH-type composition using silsesquioxane chemistry include HOSP. TM (Available from Honeywell), JSR 5109 and 5108 (Available from Japan Synthetic Rubber), Zirkon TM (Available from Shipley Microelectronics' Rohm and Haas division), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond. TM (Available from Applied Materials) and Coral TM (Available from Lam Research). An example of HSQ material is FOX. TM(Available from Dow Corning). In a non-limiting example, the formation of dielectric 144 may include performing in-situ vapor generation (ISSG) oxidation, polycrystalline silicon liner deposition, flowable chemical vapor deposition (FCVD) of dielectric 144, and annealing to improve the quality of the dielectric material. Figure 7A As shown, the dielectric 144 adjacent to the second sub-fin 142 has a bulbous cross-sectional shape, that is, it adopts the shape of the lower part of the groove 124 in the second longitudinal extension region 118. In contrast, as is generally expected, the dielectric 144 in the first longitudinal extension region 116 would be a straight-walled first sub-fin 132.

[0035] Figures 8A to 8B The cross-sectional views taken along view lines AA and BB are shown respectively. Figure 9 It shows along Figure 1 The cross-sectional view captured by the view line CC in the image. Figures 8A to 8B The diagram partially illustrates stages following conventional processing, such as, but not limited to, planarization, active region patterning, well implantation, semiconductor fin recessing, and junction annealing. Figures 8A to 8B (Not all shown). More specifically, the method may include (in Figure 9(Seen in final form) A p-well 152 is formed in a portion of a first longitudinal extension region 116, an n-well 154 is formed in at least a second longitudinal extension region 118, a source region 160 is formed in the p-well 152, a drain region 162 is formed in the n-well 154, and a drain extension region 164 is formed in the n-well. A second sub-fin 142 (shown by a dashed box) is located within the drain extension region 164. The p-well 152 may include a p-type dopant, which may include, but is not limited to, boron (B), indium (In), and gallium (Ga); the n-well 154 may include an n-type dopant, which may include, but is not limited to, phosphorus (P), arsenic (As), or antimony (Sb). Wells 152 and 154 may be formed using any now-known or later-developed semiconductor doping techniques, such as ion implantation, in-situ doping, etc. The source / drain regions 160 and 162 may be formed using any now-known or later-developed semiconductor doping techniques. For example, source / drain regions 160, 162 can be formed by mask-directed doping, wherein ion implantation is performed, followed by annealing to drive in the dopant. Source / drain regions 160, 162 can be doped with n-type dopant, for example, an n-type dopant concentration higher than that of n-well 154. Since these implantation steps are well known in the art, no further details are provided. In another example, source / drain regions 160, 162 can be formed by epitaxial growth on semiconductor fin 110, for example, after the formation of semiconductor fin 110 and the polysilicon gate but before the formation of the alternative metal gate (RMG). Drain extension region 164 extends from interface 153 between p-well 152 and n-well 154 to drain region 162. Figures 8A to 8B As shown, after the fins are recessed, the dielectric 144 creates a trench isolation 146 between the semiconductor fins 110. The cross-section of the trench isolation 146 is bulbous in the second longitudinal extension region 118, but is generally straight-walled in the first longitudinal extension region 116.

[0036] Figure 9 The stage is shown after an additional metal gate structure 112 is formed above the semiconductor fin 110 (e.g., using an alternative metal gate (RMG) process). Figure 9 In this configuration, the metal gate structure 112 includes a first active gate structure 166 located above a channel 168 in the p-well 152, and a second floating (virtual) gate structure 170 spaced apart from the first gate structure 166 and located above a drain extension region 164. Each metal gate structure 112 may be made of any gate material now known or developed hereafter, including, for example, gate dielectrics, work function metals, and gate conductors (not all shown). It should be understood that additional processing may also be performed, such as, but not limited to, mid-process and back-process interconnect processing.

[0037] Figure 9An IC structure 100, a FinFET 102, and an LDMOS device 104 according to embodiments of the present disclosure are also shown. Figure 10 A cross-sectional view of another embodiment of the IC structure 100, FinFET 102, and LDMOS device 204 is shown (similar to...). Figure 1 (See view line CC in the image). In this embodiment, the formed gate structure 212 has a single active gate 266 located above the channel 168 and the drain extension region 164. Furthermore, the method may further include forming a trench isolation 180 within the drain extension region 164 and adjacent to the drain region 162 in the semiconductor fin 110, i.e., prior to the formation of the gate structure, well, and source / drain regions. The trench isolation 180 can take any form of trench isolation structure to electrically isolate the active region. Any semiconductor fabrication technique now known or developed later can be used to form the trench isolation 180. Typically, the trench 182 is etched in the semiconductor fin 110 and filled with an insulating material such as an oxide to isolate one region of the semiconductor fin 110 from adjacent regions. The trench isolation 180 can be formed of any material now known or later developed for providing electrical insulation, such as silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon carbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) containing silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or multilayers thereof.

[0038] refer to Figure 9 and Figure 10 The IC structure 100 may include a semiconductor fin 110 having a first longitudinal extension region 116 and a second longitudinal extension region 118. The semiconductor fin 110 may include a single fin or multiple fins. The semiconductor fin 110 also has an upper fin portion 126 having a uniform lateral dimension ULD in the first longitudinal extension region 116 and the second longitudinal extension region 118. Figures 8A to 8B The semiconductor fin 110 also includes a first sub-fin 132 located below the upper fin 126, situated in the first longitudinal extension region 116 and having a first lateral dimension LD1; and a second sub-fin 142 located below the upper fin 126, situated in the second longitudinal extension region 118 and having a second lateral dimension LD2 different from the first lateral dimension LD1. For example, the second lateral dimension LD2 may be smaller than the first lateral dimension LD1. Figure 8A As shown, the second sub-fin 142 may have an inwardly curved outer surface 184, that is, due to the groove 124 ( Figure 6AThe lower part is bulbous. Each sub-fin 132, 142 is within the groove isolation 146. For example... Figure 8A As shown, the groove isolation 146 may have a bulbous cross-sectional shape adjacent to the second sub-fin 142.

[0039] IC structure 100 can be advantageously used for FinFET LDMOS devices 104 and 204 (respectively in...). Figure 9 and Figure 10 (As shown in the diagram). LDMOS devices 104, 204 may include a p-well 152 located in a portion of a first longitudinal extension region 116, an n-well 154 located in at least a second longitudinal extension region 118, a source region 160 in the p-well 152, a drain region 162 in the n-well 154, and a drain extension region 164 in the n-well 154. A second sub-fin 142 is located within the drain extension region 164. It should be noted that the second longitudinal extension region 118 and therefore the second sub-fin 142 are located within the drain extension region 164, but the drain extension region 164 may extend beyond the second longitudinal extension region 118 and partially enter the first longitudinal extension region 116 (in the diagram). Figure 9 and Figure 10 (Left side). That is, the second sub-fin 142 may be located only within a portion of the drain extension region 164, but a portion of the first sub-fin 132 may be located within the drain extension region 164 (see...). Figure 9 and Figure 10 (The edge of the drain extension region not covered by the dashed box). Figure 9 and Figure 10 In the middle, the first gate structures 166 and 266 extend above the p-well 152 and the n-well 154. Figure 9 The LDMOS device 104 includes a first gate structure 166 and a second floating gate structure 170 located above the drain extension region 164, meaning that device 104 is an LDMOS-DP device. In contrast, Figure 10 The LDMOS device 204 includes only a first gate structure 266, but includes a trench isolation 180 located in an n-well 154 within a drain extension region 164 and adjacent to the drain region 162. Each longitudinal extension region 116, 118 can be located at any desired location along the length of the semiconductor fin 110. However, in the LDMOS devices 104, 204, a second longitudinal extension region 118 can be located within the drain extension region 164.

[0040] During operation of FinFET LDMOS devices 104 and 204, the narrower sub-fin 142 within the drain extension region 164 reduces the current in the second sub-fin 142, thereby improving LDMOS HCI, for example, for wireless network power amplifier applications. Specifically, the current through the second sub-fin 142 is less than the sub-fin current in a conventional LDMOS device designed with a single lateral dimension (i.e., the first sub-fin 132 is within the drain extension region 164), because the second lateral dimension LD2 ( Figure 8A () smaller than the first lateral dimension LD1 () Figure 8B Therefore, IC structure 100 provides a 20%-30% lower impact ionization rate with a smaller depletion region and a larger potential drop through n-well 154. Thus, IC structure 100 with narrower sub-fins 142 improves HCI reliability regardless of the type of LDMOS device.

[0041] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0043] The approximate language used throughout the specification and claims can be used to modify any quantitative expression, which can be varied without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximately,” and “substantially” are not limited to the specified precise values. In at least some cases, approximate language can correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. An “approximate” term applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0044] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. An integrated circuit (IC) structure, comprising: A semiconductor fin having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: The upper fin has a uniform lateral dimension in both the first and second longitudinal extension regions. A first sub-fin located below the upper fin, which is in the first longitudinal extension region and has a first lateral dimension, and The second sub-fin is located below the upper fin and is in the second longitudinal extension region and has a second lateral dimension smaller than the first lateral dimension, wherein the second sub-fin is located in the drain extension region of the fin-type lateral diffused metal-oxide-semiconductor LDMOS device.

2. The IC structure according to claim 1, wherein, The second sub-fin has an inwardly curved outer surface.

3. The IC structure according to claim 1, wherein, Each sub-fin is located within a grooved isolation, wherein the grooved isolation has a bulbous cross-sectional shape adjacent to the second sub-fin.

4. The IC structure according to claim 1, wherein, A portion of the first sub-fin is located within the drain extension region.

5. The IC structure according to claim 1, wherein, The LDMOS device includes a first gate structure and a second floating gate structure, wherein the second floating gate structure is located above the drain extension region.

6. The IC structure according to claim 1, wherein, The LDMOS device includes trench isolation located in an n-well within the drain extension region and adjacent to the drain region.

7. The IC structure according to claim 1, wherein, The semiconductor fin includes multiple fins.

8. A FinFET (Fin Field-Effect Transistor) laterally diffused metal-oxide-semiconductor (LDMOS) device, comprising: A semiconductor fin having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: The upper fin has a uniform lateral dimension in both the first and second longitudinal extension regions. A first sub-fin located below the upper fin, which is in the first longitudinal extension region and has a first lateral dimension, and The second sub-fin is located below the upper fin and is in the second longitudinal extension region and has a second lateral dimension smaller than the first lateral dimension; The p-well is located in a portion of the first longitudinally extending region; At least n wells located in the second longitudinal extension region; The source region located in the p-well; The drain region located in the n-well; The drain extension region is located in the n-well, wherein the second sub-fin is located within the drain extension region; as well as A first gate structure extending above the p-well and the n-well.

9. The FinFET LDMOS device according to claim 8, wherein, The second sub-fin has an inwardly curved outer surface.

10. The FinFET LDMOS device of claim 8, wherein each sub-fin is located within a trench isolation, wherein, The groove isolation has a bulbous cross-sectional shape adjacent to the second fin.

11. The FinFET LDMOS device according to claim 8, wherein, A portion of the first sub-fin is located within the drain extension region.

12. The FinFET LDMOS device according to claim 8, further comprising a second floating gate structure spaced apart from the first gate structure, wherein, The second floating gate structure is located above the drain extension region.

13. The FinFET LDMOS device of claim 8, further comprising trench isolation located in the n-well within the drain extension region and adjacent to the drain region.

14. A method for forming an integrated circuit (IC) structure, comprising: A semiconductor fin is formed having a first longitudinal extension region and a second longitudinal extension region, the semiconductor fin having: The upper fin has a uniform lateral dimension in both the first and second longitudinal extension regions. A first sub-fin located below the upper fin, which is in the first longitudinal extension region and has a first lateral dimension, and A second sub-fin located below the upper fin, situated within the second longitudinal extension region and having a second lateral dimension smaller than the first lateral dimension, wherein the second sub-fin is located within the drain extension region of the fin-type laterally diffused metal-oxide-semiconductor (LDMOS) device; and A metal gate structure is formed above the semiconductor fin.

15. The method according to claim 14, wherein, Forming the semiconductor fin includes: A pair of trenches is formed in the substrate to a first depth, the trenches forming the semiconductor fins located therebetween; A first mask is formed above the second longitudinal extension region, exposing the first longitudinal extension region; The trenches in the first longitudinal extension region are etched to a second depth deeper than the first depth, thereby forming the first sub-fin having the first lateral dimension; Remove the first mask above the second longitudinal extension region; A spacer layer is formed above the first longitudinal extension region and the second longitudinal extension region; A second mask is formed above the first longitudinal extension region, exposing the second longitudinal extension region; The trenches in the second longitudinal extension region are etched to a third depth that is deeper than the first depth; The trench pairs in the second longitudinal extension region are etched to widen the trench pairs and form a second sub-fin having a second lateral dimension smaller than the first lateral dimension; Remove the second mask; and The groove pairs adjacent to the first and second sub-fins are filled with a dielectric.

16. The method of claim 15, wherein the dielectric adjacent to the second sub-fin has a bulbous cross-sectional shape.

17. The method of claim 14, further comprising, prior to forming the metal gate structure: A p-well is formed in a portion of the first longitudinally extending region; At least n-wells are formed in the second longitudinal extension region; A source region is formed in the p-well; A drain region is formed in the n-well; as well as A drain extension region is formed in the n-well.

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