Shielded gate trench semiconductor structure and shielded gate trench semiconductor device

Abstract

The present invention provides a shielded gate trench semiconductor structure, comprising a semiconductor layer, an interlayer insulating layer, a front metal layer and at least two contact terminals. A plurality of parallel deep trenches are also formed on the upper surface of the semiconductor layer; an oxide layer is formed on the inner surface of each deep trench, and each deep trench is filled with a source polysilicon layer extending along the depth direction and a gate polysilicon layer located on both sides of the source polysilicon layer. The interlayer insulating layer is formed on the semiconductor layer and covers the plurality of deep trenches. The front metal layer is formed on the interlayer insulating layer. At least two contact terminals are arranged in the interlayer insulating layer, one end of each contact terminal is connected to the front metal layer, and the other end is inserted into a deep trench to connect to the corresponding source polysilicon layer; wherein at least one deep trench without a contact terminal is spaced between the two contact terminals. The present invention improves the drain-source breakdown voltage of the semiconductor device and reduces the probability of the occurrence of the drain-source breakdown phenomenon in the semiconductor device.

Description

Technical Field

[0001] The invention relates to a semiconductor device, in particular to a shielded gate trench semiconductor structure and a shielded gate trench semiconductor device capable of improving a drain-source breakdown voltage. Background Art

[0002] SGT (shielded gate trench) MOSFET has the advantages of high power density and low switching loss, and is widely used in power devices. Although the existing shielded gate trench semiconductor devices have good characteristics of preventing drain-source breakdown compared to traditional trench MOSFETs. However, when a higher operating range is required, it is necessary to increase the trench depth and use more silicon volume to absorb energy. Therefore, if the drain-to-source breakdown voltage is to be increased based on the existing design, the overall manufacturing process and design must be changed, and the new operating range requirements cannot be met as quickly as possible. Summary of the invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is that the existing medium and low voltage SGT trench power devices are prone to drain-source breakdown, resulting in unstable operation of the power devices and a small operating range. In order to increase the drain-source breakdown voltage, the present invention proposes a shielded gate trench semiconductor structure, including a semiconductor layer, an interlayer insulating layer, a front metal layer and at least two contact terminals. A plurality of parallel deep trenches are also formed on the upper surface of the semiconductor layer; an oxide layer is formed on the inner surface of each deep trench, and each deep trench is filled with a source polysilicon layer extending along the depth direction and a gate polysilicon layer located on both sides of the source polysilicon layer. The interlayer insulating layer is formed on the semiconductor layer and covers the plurality of deep trenches. The front metal layer is formed on the interlayer insulating layer. At least two contact terminals are arranged in the interlayer insulating layer, one end of each contact terminal is connected to the front metal layer, and the other end is inserted into a deep trench to connect to the corresponding source polysilicon layer; wherein, at least one deep trench without a contact terminal is spaced between the two contact terminals.

[0004] Preferably, the semiconductor layer comprises: a semiconductor substrate layer of a first conductivity type; a first semiconductor layer of the first conductivity type formed on the semiconductor substrate layer; and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer.

[0005] Preferably, the doping concentration of the first semiconductor layer is less than the doping concentration of the semiconductor substrate layer.

[0006] Preferably, a plurality of deep trenches are formed on the semiconductor substrate layer, and openings of the plurality of deep trenches penetrate the first semiconductor layer and the second semiconductor layer.

[0007] Preferably, an interlayer insulating layer is formed on the second semiconductor layer.

[0008] Furthermore, the shielding gate trench semiconductor structure also includes a back metal layer, and the semiconductor layer is formed on the back metal layer.

[0009] The present invention also proposes a shielded gate trench semiconductor device, including a shielded gate trench semiconductor structure as described above, wherein: the back metal layer is divided into a source region and a gate region, a portion of the multiple deep trenches are located in the source region, and other deep trenches are located in the gate region; the front metal layer includes a source metal layer and a gate metal layer, the source metal layer is located in the source region, and the gate metal layer is located in the gate region, and the source metal layer and the gate metal layer are separated from each other on the interlayer insulating layer; the multiple contact terminals include two source contact terminals and a gate contact terminal, the two source contact terminals are located in the source region, and the gate contact terminal is located in the gate region; wherein one end of the two source contact terminals is connected to the source metal layer, and the other end is inserted into the corresponding deep trench located in the source region to connect to the corresponding source polysilicon layer, and a deep trench without a contact terminal is spaced between the two source contact terminals; and the two gate contact terminals are respectively inserted into the deep trenches located in the gate region, and are respectively connected to the corresponding two gate polysilicon layers.

[0010] Furthermore, the shielded gate trench semiconductor device also includes another source contact terminal inserted into the first semiconductor layer and the second semiconductor layer between two adjacent deep trenches to connect the source metal layer, the first semiconductor layer and the second semiconductor layer.

[0011] The beneficial effect of the present invention is that by configuring multiple contact terminals in the source region to connect the source polysilicon layer, the electric potential of the polysilicon is changed, so that the drain-source breakdown voltage can be increased, and the probability of drain-source breakdown occurring in the semiconductor device is reduced, thereby improving the stability of the device and the operating range of the semiconductor.

[0012] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the present invention is described in detail below with reference to preferred embodiments of the present invention and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a top view of a semiconductor device in a first embodiment of the present invention;

[0014] Figure 2 is a cross-sectional view of the semiconductor device AA' in the first embodiment of the present invention;

[0015] Figure 3 is a cross-sectional view of a semiconductor device AA′ in a second embodiment of the present invention;

[0016] Wherein, the reference numerals are:

[0017] 100 Shielded gate trench semiconductor structure

[0018] 110 Back metal layer

[0019] 120 semiconductor substrate layer

[0020] 130 first semiconductor layer

[0021] 140 Second semiconductor layer

[0022] 150 Interlayer insulation layer

[0023] 160 Front metal layer

[0024] 161 Source metal layer

[0025] 162 Gate metal layer

[0026] 171 Deep Groove

[0027] 171 Oxide layer

[0028] 173 source polysilicon layer

[0029] 174 Gate polysilicon layer

[0030] 181, 182 Source contact terminal

[0031] 183 Gate contact terminal

[0032] 200 Shielded Gate Trench Semiconductor Device DETAILED DESCRIPTION

[0033] The following is an explanation of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0034] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments. In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] It should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] See also Figure 1 and Figure 2 FIG. 1 is a shielded gate trench semiconductor structure 100 provided in accordance with a first embodiment of the present invention. The trench semiconductor structure can be used as a part of a power device and has a high drain-source breakdown voltage characteristic.

[0038] like Figure 1 and Figure 2 As shown, the shielded gate trench semiconductor structure 100 includes, from bottom to top, a back metal layer 110 , a semiconductor substrate layer 120 , a first semiconductor layer 130 , a second semiconductor layer 140 , an interlayer insulating layer 150 , a front metal layer 160 and at least two contact terminals 180 .

[0039] like Figure 2As shown, the semiconductor substrate layer 120 is formed on the back metal layer 110 at the outer edge, and the doping of the semiconductor substrate layer 120 is the first conductivity type, such as N+ heavy doping. The first semiconductor layer 130 and the second semiconductor layer 140 are formed on the semiconductor substrate layer 120 from bottom to top, so that the semiconductor substrate layer 120, the first semiconductor layer 130 and the second semiconductor layer 140 constitute a semiconductor layer formed on the back metal layer 110. Among them, the first semiconductor layer 130 is also the first conductivity type, and the doping concentration is less than the doping concentration of the semiconductor substrate layer 120; for example, the first semiconductor layer 130 can be formed on the semiconductor substrate layer 120 at the outer edge, so that its doping concentration is less than the doping concentration of the semiconductor substrate layer 120; or the first semiconductor layer 130 can be slightly implanted with the first type of ions, so that its doping concentration is less than the semiconductor substrate layer 120. On the contrary, the doping of the second semiconductor layer 140 is the second conductivity type, such as P doping. Specifically, through the above-mentioned doping configuration, the first semiconductor layer 130 and the second semiconductor layer 140 can be used as a well region and a source region respectively. The aforementioned NP doping is only an example and can be changed to different doping / ion implantation methods as long as the functions of the well region and the source region are achieved.

[0040] like Figure 1 As shown, a plurality of parallel deep trenches 171 are formed on the upper surface of the semiconductor layer. Specifically, the number of the deep trenches 171 is at least three, and the deep trenches 171 are formed on the semiconductor substrate layer 110, and the openings of the deep trenches 171 penetrate the first semiconductor layer 130 and the second semiconductor layer 140, so that the deep trenches 171 are not covered by the first semiconductor layer 130 and the second semiconductor layer 140. In other words, Figure 1 As shown, the deep trench 171 can cut the semiconductor substrate layer, the first semiconductor layer 130 and the second semiconductor layer 140 into a plurality of blocks in the top view direction. In addition, the deep trench 171 extends toward the back metal layer 110 in the depth direction. Specifically, the back metal layer 110 is suitable for being used as a drain of the semiconductor device, and the front metal layer 160 can be a corresponding source.

[0041] like Figure 1 As shown, an oxide layer 172 is formed on the inner surface of the deep trench 171, and the deep trench 171 is filled with a source polysilicon layer 173 extending along the depth direction and a gate polysilicon layer 174 located on both sides of the source polysilicon layer 173. Generally, the source polysilicon layer 173 and the gate polysilicon layer 174 are covered by the oxide layer 172, and the source polysilicon layer 173 forms a shielding gate.

[0042] like Figure 2As shown, the interlayer insulating layer 150 is formed on the second semiconductor layer 140 of the semiconductor layer and covers the deep trench 171, and the front metal layer 160 is formed on the interlayer insulating layer 150. At least two contact terminals 180 are arranged in the interlayer insulating layer 150, one end of the contact terminal 180 is connected to the front metal layer 160, and the other end penetrates the interlayer insulating layer 150 and is inserted into the deep trench 171 to connect to the source polysilicon layer 173. Specifically, the deep trenches 171 into which the two contact terminals 180 are inserted are not directly adjacent, but a deep trench 171 without a contact terminal 180 is spaced between the two contact terminals 180.

[0043] The newly added contact terminal 180 changes the potential of the polysilicon, so that the drain-source breakdown voltage of the shielded gate trench semiconductor structure 100 can be increased, thereby reducing the probability of the drain-source breakdown phenomenon occurring in the semiconductor device.

[0044] like Figure 3 2 is a shielded gate trench semiconductor device 200 according to a second embodiment of the present invention, which uses the aforementioned shielded gate trench semiconductor structure 100 and is described in detail as follows.

[0045] like Figure 3 As shown, the shielded gate trench semiconductor device 200 includes, from bottom to top, a back metal layer 110, a semiconductor substrate layer 120, a first semiconductor layer 130, a second semiconductor layer 140, an interlayer insulating layer 150, a source metal layer 161, a gate metal layer 162, source contact terminals 181, 182 and a gate contact terminal 183.

[0046] like Figure 3 As shown, the back metal layer 110 can be divided into a source region and a gate region; the outer edge of the semiconductor substrate layer 120 is formed on the back metal layer 110, and the first semiconductor layer 130 and the second semiconductor layer 140 are formed from bottom to top on the semiconductor substrate layer 120 to form a semiconductor layer. The conductivity type doped with the semiconductor substrate layer 120, the first semiconductor layer 130 and the second semiconductor layer 140 is substantially the same as that of the first embodiment, and will not be described again below.

[0047] like Figure 3As shown, a plurality of parallel deep trenches 171 are formed on the upper surface of the semiconductor substrate layer 120, some of the deep trenches 171 are located in the source region, and other deep trenches 171 are located in the gate region. Specifically, the source region of this embodiment is configured with three deep trenches 171, and the gate region is configured with one deep trench 171, but the number of configurations is not limited to this. Similarly, the deep trenches 171 penetrate the first semiconductor layer 130 and the second semiconductor layer 140, so that the deep trenches 171 are not covered by the first semiconductor layer 130 and the second semiconductor layer 140. Specifically, the back metal layer 110 is suitable for use as a drain of a semiconductor device.

[0048] like Figure 3 As shown, an oxide layer 172 is formed on the inner surface of the deep trench 171, and the deep trench 171 is filled with a source polysilicon layer 173 extending along the depth direction and a gate polysilicon layer 174 located on both sides of the source polysilicon layer 173. The interlayer insulating layer 150 is formed on the second semiconductor layer 140 of the semiconductor layer and covers the deep trench 171. The source metal layer 161 and the gate metal layer 162 are formed on the interlayer insulating layer 150, and together constitute the front metal layer 160 of the first embodiment. The source metal layer 161 is located in the source region, and the gate metal layer 162 is located in the gate region, and the source metal layer 161 and the gate metal layer 162 are separated from each other on the interlayer insulating layer 150 and do not constitute a direct electrical connection.

[0049] like Figure 3 As shown, source contact terminals 181, 182 and gate contact terminal 183 are arranged in the interlayer insulating layer 150, wherein the source contact terminals 181, 182 are located in the source region, and the gate contact terminal 183 is located in the gate region. There are at least two source contact terminals 181, one end of the two source contact terminals 181 is connected to the source metal layer 161, and the other end penetrates the interlayer insulating layer 150 and is inserted into the deep trench 171 located in the source region to connect to the corresponding source polysilicon layer 173. Taking the deep trench 171 close to the source region as the first deep trench 171 as an example, the two source contact terminals 181 are respectively inserted into the first and third deep trenches 171, so that the source polysilicon layer 173 connected to the two source contact terminals 181 are not directly adjacent, but the second deep trench 171 without the contact terminal 180 is separated between the two source contact terminals 181. Another source contact terminal 182 is inserted into the first semiconductor layer 130 and the second semiconductor layer 140 between two adjacent deep trenches 171, and connects the source metal layer 161, the first semiconductor layer 130 and the second semiconductor layer 140. There are at least two gate contact terminals 183, and the two gate contact terminals 183 are respectively inserted into the deep trenches 171 located in the gate region and respectively connected to the corresponding two gate polysilicon layers 174.

[0050] By configuring a plurality of contact terminals 180, 181 in the source region to connect the source polysilicon layer 173, the electric potential of the polysilicon is changed, so that the drain-source breakdown voltage can be increased, and the probability of the occurrence of the drain-source breakdown phenomenon of the semiconductor device is reduced, thereby improving the stability of the device and the operating range of the semiconductor device. In addition, the production of the newly added contact terminals 180, 181 does not require an increase in the number of photomasks, and only the photomasks related to the production of the contact terminals 180, 181 need to be adjusted and modified. Therefore, the present invention does not change the complexity of the device production process.

[0051] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A shielded gate trench semiconductor structure, characterized in that: include: A semiconductor layer, wherein a plurality of parallel deep trenches are formed on the upper surface of the semiconductor layer; An oxide layer is formed on the inner surface of each of the deep trenches, and each of the deep trenches is filled with a source polysilicon layer extending along a depth direction and a gate polysilicon layer located on both sides of the source polysilicon layer; an interlayer insulating layer formed on the semiconductor layer and covering the plurality of deep trenches; A front metal layer formed on the interlayer insulating layer; At least two contact terminals are arranged in the interlayer insulating layer, one end of each contact terminal is connected to the front metal layer, and the other end is inserted into one of the deep trenches to connect to the corresponding source polysilicon layer; wherein, at least one deep trench without the contact terminal is spaced between the two contact terminals.

2. The shielded gate trench semiconductor structure according to claim 1, wherein: The semiconductor layer comprises: a semiconductor substrate layer of a first conductivity type; A first semiconductor layer of a first conductivity type, the first semiconductor layer being formed on the semiconductor substrate layer; and A second semiconductor layer of a second conductivity type is formed on the first semiconductor layer.

3. The shielded gate trench semiconductor structure according to claim 2, wherein: The doping concentration of the first semiconductor layer is lower than the doping concentration of the semiconductor substrate layer.

4. The shielded gate trench semiconductor structure according to claim 2, wherein: The plurality of deep trenches are formed on the semiconductor substrate layer, and the openings of the plurality of deep trenches penetrate the first semiconductor layer and the second semiconductor layer.

5. The shielded gate trench semiconductor structure according to claim 2, wherein: The interlayer insulating layer is formed on the second semiconductor layer.

6. The shielded gate trench semiconductor structure according to claim 1, wherein: The invention also includes a back metal layer, and the semiconductor layer is formed on the back metal layer.

7. A shielded gate trench semiconductor device, characterized in that: A shielded gate trench semiconductor structure comprising any one of claims 1 to 6, wherein: The back metal layer is divided into a source region and a gate region, part of the plurality of deep trenches are located in the source region, and the other deep trenches are located in the gate region; The front metal layer includes a source metal layer and a gate metal layer, the source metal layer is located in the source region, the gate metal layer is located in the gate region, and the source metal layer and the gate metal layer are separated from each other on the interlayer insulating layer; The plurality of contact terminals include two source contact terminals and a gate contact terminal, the two source contact terminals are located in the source region, and the gate contact terminal is located in the gate region; wherein one end of the two source contact terminals is connected to the source metal layer, and the other end is inserted into the corresponding deep trench located in the source region to be connected to the corresponding source polysilicon layer, and the deep trench where the contact terminal is not configured is spaced between the two source contact terminals; and The two gate contact terminals are respectively inserted into the deep trenches located in the gate region and are respectively connected to the corresponding two gate polysilicon layers.

8. The shielded gate trench semiconductor device according to claim 7, wherein: The invention also includes another source contact terminal, which is inserted into the first semiconductor layer and the second semiconductor layer between two adjacent deep trenches to connect the source metal layer, the first semiconductor layer and the second semiconductor layer.

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