Resistive random access memory and manufacturing method thereof

Abstract

The present invention provides a resistance random access memory (RRAM) and a method for manufacturing the same. The RRAM includes a stacked structure and a bitline structure. The stacked structure is disposed on a substrate. The stacked structure includes a lower electrode, an upper electrode, and a variable resistance layer. The lower electrode is disposed on the substrate. The upper electrode is disposed on the lower electrode. The variable resistance layer is disposed between the lower electrode and the upper electrode. The bitline structure covers the top surface of the stacked structure and extends to a portion of the sidewalls of the stacked structure. The bitline structure is electrically connected to the stacked structure.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory and a manufacturing method thereof, and in particular to a resistance random access memory and a manufacturing method thereof. Background Art

[0002] Resistive random access memory (RRAM) has the advantages of simple structure, small area, low operating voltage, fast operation speed, long storage time, multi-state storage, and low power consumption, and has gradually become a trend.

[0003] Generally speaking, any structure in a resistance random access memory (RRAM) affects its resistance value and electrical performance. Therefore, how to design a resistance random access memory (RRAM) to achieve better electrical performance during operation becomes a very important topic. Summary of the Invention

[0004] The present invention is directed to a resistance random access memory and a manufacturing method thereof, which can obtain better electrical performance during operation and can comply with the trend of miniaturization.

[0005] According to an embodiment of the present invention, a resistance random access memory (RRAM) includes a stacked structure and a bitline structure. The stacked structure is disposed on a substrate. The stacked structure includes a lower electrode, an upper electrode, and a variable resistance layer. The lower electrode is disposed on the substrate. The upper electrode is disposed on the lower electrode. The variable resistance layer is disposed between the lower electrode and the upper electrode. The bitline structure covers the top surface of the stacked structure and extends to a portion of the sidewalls of the stacked structure. The bitline structure is electrically connected to the stacked structure.

[0006] According to an embodiment of the present invention, a method for manufacturing a resistive random access memory includes at least the following steps: forming a stacked structure on a substrate, wherein the stacked structure includes a lower electrode, a variable resistance layer, and an upper electrode formed in sequence; forming an insulating layer on the stacked structure, wherein the insulating layer has an opening; forming a dielectric material in the opening; removing a portion of the insulating layer and the dielectric material to form a trench in the stacked structure, wherein the trench exposes a top surface of the stacked structure and a portion of a sidewall of the stacked structure; and forming a bitline structure in the trench, wherein the bitline structure is electrically connected to the stacked structure.

[0007] Based on the above, the bit line structure of the resistance random access memory of the present invention covers the top surface of the stacked structure and also covers a portion of the sidewalls of the stacked structure. Thus, the area of ​​electrical connection between the bit line structure and the upper electrode can be increased, enabling direct contact between the bit line structure and the upper electrode, thereby enlarging the contact window. This eliminates the need for additional components to connect the bit line structure and the upper electrode, thereby effectively achieving better electrical performance during operation and complying with the trend of miniaturization.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1G It is a cross-sectional schematic diagram of a manufacturing process of a resistance random access memory according to an embodiment of the present invention.

[0010] Description of Reference Numerals

[0011] 10, 12, 14: Insulation material

[0012] 20:Mask material

[0013] 100: Resistive Random Access Memory

[0014] 101: Insulation layer

[0015] 102: Plug

[0016] 110: substrate

[0017] 112: lower electrode

[0018] 114: variable resistance layer

[0019] 116: oxygen exchange layer

[0020] 117: Oxygen-rich layer

[0021] 118: Upper electrode

[0022] 116a, 118a, 120a, 140a: top surface

[0023] 118b: bottom

[0024] 118s, 120s: sidewall

[0025] 120: stacked structure

[0026] 130, 132, 134: Dielectric materials

[0027] 1321, 1341: groove

[0028] 1341b: bottom

[0029] 140: coating

[0030] 150: bit line structure

[0031] 150b: bottom

[0032] 1501: Ditch

[0033] OP: Opening

[0034] P: Area

[0035] R1: First Zone

[0036] R2: Second Zone DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0039] Figures 1A to 1G FIG is a cross-sectional diagram of a manufacturing process of a resistance random access memory according to an embodiment of the present invention. Figure 1A This embodiment provides a method for manufacturing a resistance random access memory 100, and the steps are as follows: First, a substrate 110 is provided, and the substrate 110 is, for example, a silicon substrate.

[0040] Next, a lower electrode 112 is formed on the substrate 110. The material of the lower electrode 112 is, for example, titanium nitride (TiN) or indium tin oxide (ITO). The lower electrode 112 can be formed by, for example, physical vapor deposition (PVD) or atomic layer deposition (ALD), but the present invention is not limited thereto. In one embodiment, the lower electrode 112 is electrically connected to the drain region of a transistor (not shown) through, for example, the plug 102 in the substrate 110.

[0041] After forming the lower electrode 112, a variable resistance layer 114 is formed on the lower electrode 112. Here, the variable resistance layer 114 can be, for example, a film layer that can adjust its resistance value by changing the electric field, thereby controlling the switch (SET and RESET) state in the resistance random access memory 100, and the material of the variable resistance layer 114 can be a material whose crystalline state does not change due to heat. For example, the material of the variable resistance layer 114 can be a transition metal oxide, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), or other suitable metal oxides. The variable resistance layer 114 can be formed by, for example, physical vapor deposition or atomic layer deposition, but the present invention is not limited thereto.

[0042] After forming the variable resistor layer 114, an oxygen exchange layer 116 is formed on the variable resistor layer 114. The material of the oxygen exchange layer 116 is, for example, titanium, tantalum, hafnium, zirconium, platinum, or aluminum. The oxygen exchange layer 116 can be formed by, for example, physical vapor deposition or atomic layer deposition, but the present invention is not limited thereto.

[0043] After forming the oxygen exchange layer 116, an upper electrode 118 is formed on the oxygen exchange layer 116. The material of the upper electrode 118 includes a conductive material, such as titanium nitride or indium tin oxide. The upper electrode 118 is formed by, for example, physical vapor deposition or atomic layer deposition. Figure 1A As shown, the lower electrode 112, the variable resistance layer 114, the oxygen exchange layer 116, and the upper electrode 118 may form a stacked structure 120. For example, the stacked structure 120 may be configured such that the upper electrode 118 is disposed on the lower electrode 112, the variable resistance layer 114 is disposed between the lower electrode 112 and the upper electrode 118, and the oxygen exchange layer 116 is disposed between the variable resistance layer 114 and the upper electrode 118.

[0044] Furthermore, to prevent current dispersion and increase current density, thereby enhancing high-temperature data retention, an oxygen-rich layer 117 may be selectively formed between the oxygen exchange layer 116 and the upper electrode 118. Specifically, the stacked structure 120 may further include the oxygen-rich layer 117. The material of the oxygen-rich layer 117 is, for example, aluminum oxide. The oxygen-rich layer 117 may be formed, for example, by physical vapor deposition or atomic layer deposition. However, the present invention is not limited thereto. In embodiments not shown, the oxygen-rich layer 117 may not be formed between the oxygen exchange layer 116 and the upper electrode 118.

[0045] Please also refer to Figure 1A and Figure 1B After forming the stacked structure 120, an insulating material 10 may be formed on the substrate 110, wherein the insulating material 10 may cover the stacked structure 120. In this embodiment, the insulating material 10 may be formed by the following steps. First, as shown in FIG. Figure 1AAs shown, a first insulating material 12 may be formed on the substrate 110, wherein the first insulating material 12 is stacked on the stack structure 120. The first insulating material 12 is, for example, formed only on the upper electrode 118 of the stack structure 120. Figure 1B As shown, a second insulating material 14 may be formed on the substrate 110. The second insulating material 14 is, for example, formed entirely on the substrate 110 to cover the stacked structure 120 and the first insulating material 12. In one embodiment, a portion of the second insulating material 14 may be in direct contact with the substrate 110, but the present invention is not limited thereto.

[0046] In this embodiment, the stacked structure 120 and the first insulating material 12 stacked thereon are formed, for example, by the following steps. First, a lower electrode material, a variable resistance layer material, an oxygen exchange layer material, an oxygen-rich layer material, an upper electrode material, and a first insulating material can be sequentially and comprehensively formed on the substrate 110. Next, a patterning process (photolithography and etching process) is performed on the aforementioned materials to form the stacked structure 120 and the first insulating material 12 stacked thereon, and a portion of the substrate 110 is exposed. However, the present invention is not limited thereto, and the stacked structure 120 and the first insulating material 12 can be formed by other suitable methods.

[0047] Please also refer to Figure 1B and Figure 1C After forming the insulating material 10, a portion of the insulating material 10 is removed to form an insulating layer 101 having an opening OP, wherein the insulating layer 101 may surround the stacked structure 120. For example, a portion of the first insulating material 12 and a portion of the second insulating material 14 are removed to form the insulating layer 101 having the opening OP.

[0048] In this embodiment, if Figure 1C As shown, the substrate 110 includes a first region R1 and second regions R2 located on both sides of the first region R1. For example, the area exposed by the opening OP of the insulating layer 101 can be defined as the first region R1 of the substrate 110, and the area where the insulating layer 101 is located can be defined as the second region R2 of the substrate 110. Therefore, the film layer subsequently formed in the opening OP of the insulating layer 101 can be located only on the first region R1.

[0049] In one embodiment, in order to remove a portion of the insulating material 10 (the first insulating material 12 and a portion of the second insulating material 14) on the substrate 110 through an etching selectivity ratio to form the insulating layer 101 having the opening OP, the material of the first insulating material 12 can be different from the material of the second insulating material 14. The material of the first insulating material 12 is, for example, silicon nitride or silicon oxynitride. The material of the second insulating material 14 is, for example, silicon dioxide. However, the present invention is not limited thereto, and the method of removing the insulating material 10 can be determined according to design requirements. The method of forming the first insulating material 12 and the second insulating material 14 can include chemical vapor deposition.

[0050] Please also refer to Figure 1C and Figure 1D After forming the insulating layer 101 with the opening OP, a dielectric material 130 may be formed in the opening OP. The dielectric material 130 may be formed by the following steps. First, Figure 1C As shown, a first dielectric material 132 may be formed in the opening OP, wherein the first dielectric material 132 has a first groove 1321. The first dielectric material 132 is, for example, conformally formed on the opening OP so that the first dielectric material 132 has the first groove 1321. Figure 1D As shown, a second dielectric material 134 is formed on the first dielectric material 132 , wherein the second dielectric material 134 has a second groove 1341 .

[0051] In one embodiment, the first dielectric material 132 can be made of the same material as the second dielectric material 134. For example, the first dielectric material 132 can be made of hafnium dioxide, aluminum oxide, or zirconium oxide. For example, the second dielectric material 134 can be made of hafnium dioxide, aluminum oxide, or zirconium oxide, but the present invention is not limited thereto. The first dielectric material 132 and the second dielectric material 134 can be formed by chemical vapor deposition.

[0052] In one embodiment, if Figure 1D As shown, the second groove 1341 may have a rectangular profile, but the present invention is not limited thereto. In some embodiments not shown, the second groove 1341 may have a U-shaped profile or other suitable profiles.

[0053] In this embodiment, a portion of the second dielectric material 134 may be sandwiched between the second groove 1341 and the stacked structure 120. For example, the bottom 1341b of the second groove 1341 may be at a distance from the top surface 120a of the stacked structure 120, so that a portion of the dielectric material 130 may be sandwiched between the bottom 1341b of the second groove 1341 and the top surface 120a of the stacked structure 120. Here, the top surface 120a of the stacked structure 120 may be the top surface 118a of the upper electrode 118.

[0054] Please refer to Figure 1E Then, a mask material 20 may be formed in the second groove 1341. The mask material 20 may be, for example, spin-on carbon (SOC) or silicon dioxide, and may be formed by, for example, chemical vapor deposition.

[0055] Please refer to Figure 1F Then, a portion of the insulating layer 101 and the dielectric material 130 is removed through the mask material 20 to form a trench 1501 on the stacked structure 120, wherein the remaining dielectric material can form the cladding layer 140. In other words, by patterning the insulating layer 101 and the dielectric material 130, the cladding layer 140 can be formed on the sidewalls of the stacked structure 120, and the trench 1501 can be extended from the first region R1 to the second region R2.

[0056] Since the dielectric material constituting the cladding layer 140 is a film layer (the first dielectric material 132 and the second dielectric material 134) formed in the opening OP of the insulating layer 101, the cladding layer 140 can be located only on the first region R1, so as to reduce the resistance-capacitance delay (RC Delay) problem that may be caused by the cladding layer 140 extending to the second region R2, and can also effectively improve the phenomenon of wafer warpage that may be caused by the cladding layer 140 extending to the second region R2. In addition, in an embodiment not shown, Figure 1C The first region R1 and the second region R2 may be a unit cell region in the RRAM 100 , and the cladding layer 140 does not extend to the peripheral region outside the unit cell region, thereby further improving the wafer warpage phenomenon, but the present invention is not limited thereto.

[0057] In this embodiment, the trench 1501 may expose a portion of the stacked structure 120. For example, the trench 1501 may expose a portion of the top surface 120a of the stacked structure 120 and a portion of the sidewall 120s of the stacked structure 120, thereby increasing the area for electrical connection between a device subsequently formed in the trench 1501 and the stacked structure 120. For example, the trench 1501 may expose a portion of the top surface 118a of the upper electrode 118 and a portion of the sidewall 118s of the upper electrode 118, thereby increasing the area for electrical connection between a device subsequently formed in the trench 1501 and the upper electrode 118.

[0058] Furthermore, the trench 1501 may also expose a portion of the cladding layer 140. For example, the trench 1501 may also expose the top surface 140a of the cladding layer 140. In other words, the cladding layer 140 may cover a portion of the sidewall 120s of the stacked structure 120 that is close to the substrate 110, and expose another portion of the sidewall 120s of the stacked structure 120 that is away from the substrate 110. For example, the cladding layer 140 covers a portion of the sidewall 118s of the upper electrode 118 that is close to the substrate 110, and exposes another portion of the sidewall 118s of the upper electrode 118 that is away from the substrate 110.

[0059] Please refer to Figure 1G A bitline structure 150 is formed on the substrate 110. The bitline structure 150 covers the top surface 120a of the stacked structure 120 and a portion of the sidewall 120s of the stacked structure 120. The bitline structure 150 is electrically connected to the stacked structure 120. This increases the area of ​​electrical connection between the bitline structure 150 and the upper electrode 118, allowing direct contact between the bitline structure 150 and the upper electrode 118. This increases the contact window and eliminates the need for other components to connect the bitline structure 150 and the upper electrode 118. This effectively enables the resistance random access memory 100 to achieve better electrical performance during operation and meet the trend of miniaturization.

[0060] Furthermore, since the area of ​​electrical connection between the electrode and the conductive element affects the size of the filament region, in this embodiment, the bit line structure 150 covers the top surface 120a of the stacked structure 120 and covers a portion of the sidewall 120s of the stacked structure 120. This can expand the area P within the RRAM 100 where filaments can be formed, allowing filaments to be randomly formed within the area P, thereby further improving the electrical performance of the RRAM 100.

[0061] Furthermore, when the bitline structure within the RRAM is electrically connected to an electrode through, for example, a via, additional resistance is generated within the RRAM 100. Therefore, in this embodiment, the bitline structure 150 may cover a portion of the sidewall 118s of the upper electrode 118, the bottom surface 150b of the bitline structure 150 may be higher than the bottom surface 118b of the upper electrode 118, and the bitline structure 150 may be in direct contact with the upper electrode 118. In other words, there may not be a via between the bitline structure 150 and the upper electrode 118, thereby further ensuring better electrical performance of the RRAM 100 during operation.

[0062] In this embodiment, the bit line structure 150 may be formed by forming a conductive material within the trench 1501, and the conductive material fills the trench 1501. Therefore, the bit line structure 150 formed in the trench 1501 can increase the area of ​​electrical connection between the bit line structure 150 and the stacked structure 120. In addition, the bit line structure 150 formed in the trench 1501 may extend over the first region R1 and the second region R2, wherein the extension direction of the bit line structure 150 may be perpendicular to the stacking direction of the stacked structure 120.

[0063] It should be noted that the present invention does not limit the method for forming the bit line structure 150 . As long as the bit line structure 150 covers the top surface 120 a of the stack structure 120 and a portion of the sidewall 120 s of the stack structure 120 , it falls within the scope of protection of the present invention.

[0064] On the other hand, the cladding layer 140 may be sandwiched between the bitline structure 150 and the substrate 110. The cladding layer 140 may cover another portion of the sidewall 120s of the stacked structure 120. For example, the bitline structure 150 may cover a portion of the sidewall 118s of the upper electrode 118 away from the substrate 110, and the cladding layer 140 may cover another portion of the sidewall 118s of the upper electrode 118 closer to the substrate 110.

[0065] In one embodiment, the top surface 140a of the cladding layer 140 may be higher than the top surface 116a of the oxygen exchange layer 116 to prevent the resistance random access memory from becoming inoperable due to oxygen evaporation. The top surface 140a of the cladding layer 140 and the bottom surface 150b of the bit line structure 150 may be substantially coplanar.

[0066] In summary, the bitline structure of the RRAM of the present invention covers the top surface of the stacked structure and extends to a portion of the sidewalls of the stacked structure. This increases the area of ​​electrical connection between the bitline structure and the upper electrode, enabling direct contact between the bitline structure and the upper electrode, thereby enlarging the contact window and eliminating the need for additional resistance created by other components. This effectively achieves better electrical performance during operation and complies with the trend of miniaturization. Furthermore, the cladding layer is located only on the first region, reducing the resistance-capacitance delay that may occur if the cladding layer extends onto the second regions located on both sides. This also effectively mitigates the wafer warpage that may be caused by the cladding layer extending onto the second regions.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resistance random access memory, characterized in that: include: A stacking structure is provided on a substrate, wherein the stacking structure comprises: a lower electrode disposed on the substrate; an upper electrode disposed on the lower electrode; and a variable resistance layer disposed between the lower electrode and the upper electrode; and an insulating layer surrounding and not directly contacting the stack structure; a bit line structure covering a top surface of the stack structure and covering a portion of a sidewall of the stack structure, wherein the bit line structure is electrically connected to the stack structure; and The cladding layer is disposed on the sidewall of the stacked structure and in the opening of the insulating layer.

2. The resistance random access memory according to claim 1, wherein: The bit line structure covers a portion of a sidewall of the upper electrode, and the bit line structure is in direct contact with the upper electrode.

3. The resistance random access memory according to claim 1, wherein: There is no through hole between the bit line structure and the upper electrode.

4. The resistance random access memory according to claim 1, wherein: A bottom surface of the bit line structure is higher than a bottom surface of the upper electrode.

5. The resistance random access memory according to claim 1, wherein: The cladding layer is sandwiched between the bit line structure and the substrate, and covers another portion of the sidewall of the stacked structure. The stacked structure further includes an oxygen exchange layer disposed between the variable resistance layer and the upper electrode.

6. The resistance random access memory according to claim 5, wherein: The substrate includes a first region and second regions located on both sides of the first region, and the cladding layer is only located on the first region.

7. A method for manufacturing a resistance random access memory, characterized in that: include: forming a stacked structure on a substrate, wherein the stacked structure comprises a lower electrode, a variable resistance layer, and an upper electrode formed in sequence; forming an insulating layer on the substrate, wherein the insulating layer has an opening, wherein the opening exposes a portion of the stacked structure, and after the opening is formed, the insulating layer does not directly contact the stacked structure; forming a dielectric material in the opening; removing a portion of the insulating layer and the dielectric material to form a trench on the stack structure, wherein the trench exposes a top surface of the stack structure and a portion of a sidewall of the stack structure; as well as A bit line structure is formed in the trench, wherein the bit line structure is electrically connected to the stack structure.

8. The method for manufacturing a resistance random access memory according to claim 7, wherein: Forming the insulating layer includes: forming an insulating material on the substrate, wherein the insulating material covers the stacked structure, wherein forming the insulating material comprises: forming a first insulating material on the substrate, wherein the first insulating material is stacked on the stacked structure; forming a second insulating material on the substrate, wherein the second insulating material covers the stacked structure and the first insulating material; and A portion of the insulating material is removed to form the opening.

9. The method for manufacturing a resistance random access memory according to claim 7, wherein: Forming the dielectric material includes: forming a first dielectric material in the opening, wherein the first dielectric material has a first groove; and A second dielectric material is formed on the first dielectric material, wherein the second dielectric material has a second groove.

10. The method for manufacturing a resistance random access memory according to claim 9, wherein: The first dielectric material is conformally formed on the opening so that the first dielectric material has the first groove.

11. The method for manufacturing a resistance random access memory according to claim 9, wherein: The ditches include: forming a mask material in the second groove; and A portion of the dielectric material is removed through the mask material.

12. The method for manufacturing a resistance random access memory according to claim 9, wherein: A portion of the second dielectric material is sandwiched between the second groove and the stack structure.

13. The method for manufacturing a resistance random access memory according to claim 7, wherein: After removing a portion of the insulating layer and the dielectric material, the remaining dielectric material forms a cladding layer. The cladding layer is located on the sidewall of the stack structure and sandwiched between the bit line structure and the substrate.

14. The method for manufacturing a resistance random access memory according to claim 13, wherein: Forming the stacked structure includes: An oxygen exchange layer is formed between the variable resistance layer and the upper electrode, and a top surface of the coating layer is higher than a top surface of the oxygen exchange layer.

Images